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URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

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Rev 149 → Rev 150

/sdhc-sc-core/trunk/src/grpSd/unitSdCardModel/src/SdData.sv File deleted
/sdhc-sc-core/trunk/src/grpSd/unitSdCardModel/src/SdBusTrans.sv
1,17 → 1,24
`ifndef SDBUSTRANS_SV
`define SDBUSTRANS_SV
 
`include "SdDataBlock.sv"
 
const logic cSdStartbit = 0;
const logic cSdEndbit = 1;
 
typedef logic SdBusTransData[$];
 
virtual class SdBusTrans;
class SdBusTrans;
 
SdDataBlock DataBlocks[];
bit SendBusy = 0;
 
virtual function SdBusTransData packToData();
endfunction
 
virtual function void unpackFromData(ref SdBusTransData data);
endfunction
 
endclass
 
class SdBusTransToken extends SdBusTrans;
/sdhc-sc-core/trunk/src/grpSd/unitSdCardModel/src/SdBFM-impl.sv
1,7 → 1,7
`ifndef SDBFMIMPL_SV
`define SDBFMIMPL_SV
 
function SdBFM::new(virtual ISdCard card);
function SdBFM::new(virtual ISdBus card);
this.ICard = card;
this.Log = new;
this.Sem = new(1);
15,9 → 15,7
StopAfter = AfterCount;
endfunction
 
task SdBFM::send(input SdBusTrans token);
this.Sem.get(1);
task SdBFM::sendCmd(inout SdBusTransData data);
// startbit
@ICard.cb;
ICard.cb.Cmd <= cSdStartbit;
24,7 → 22,6
 
// data
begin
SdBusTransData data = token.packToData();
 
foreach(data[i]) begin
@ICard.cb;
39,7 → 36,95
 
@ICard.cb;
ICard.cb.Cmd <= 'z;
waitUntilReady();
endtask
 
task SdBFM::sendAllDataBlocks(SdDataBlock blocks[]);
foreach(blocks[i]) begin
sendDataBlock(blocks[i]);
waitUntilReady();
end
endtask
 
task SdBFM::waitUntilReady();
repeat (8) @ICard.cb;
endtask
 
task SdBFM::sendDataBlock(SdDataBlock block);
if (Mode == standard) sendStandardDataBlock(block.data);
else sendWideDataBlock(block.data);
endtask
 
task SdBFM::sendStandardDataBlock(logic data[$]);
data.push_front(0); // startbit
CrcOnContainer(data);
data.push_back(1); // endbit
 
foreach(data[i]) begin
@ICard.cb;
ICard.cb.Data[0] <= data[i];
end
 
@ICard.cb;
ICard.cb.Data <= 'z;
endtask
 
task SdBFM::sendWideDataBlock(logic data[$]);
logic dat0[$];
logic dat1[$];
logic dat2[$];
logic dat3[$];
 
for (int i = 0; i < data.size(); i+=4) begin
dat3.push_back(data[i]);
dat2.push_back(data[i+1]);
dat1.push_back(data[i+2]);
dat0.push_back(data[i+3]);
end
CrcOnContainer(dat0);
CrcOnContainer(dat1);
CrcOnContainer(dat2);
CrcOnContainer(dat3);
 
@ICard.cb;
ICard.cb.Data <= 0;
 
for(int i = 0; i < dat0.size(); i++) begin
@ICard.cb;
ICard.cb.Data <= (dat3[i]<<3) + (dat2[i] <<2) + (dat1[i] <<1) + dat0[i];
end
@ICard.cb;
ICard.cb.Data <= 0;
 
@ICard.cb;
ICard.cb.Data <= 'z;
endtask
 
task SdBFM::sendBusy();
@ICard.cb;
// 10 busy cycles
ICard.cb.Data[0] <= 0;
repeat (10) @ICard.cb;
ICard.cb.Data[0] <= 1;
 
@ICard.cb;
ICard.cb.Data <= 'z;
endtask
 
task SdBFM::send(input SdBusTrans token);
SdBusTransData data;
this.Sem.get(1);
data = token.packToData();
if (data.size() > 0) sendCmd(data);
if (token.DataBlocks.size() > 0) sendAllDataBlocks(token.DataBlocks);
else if (token.SendBusy == 1) sendBusy();
this.Sem.put(1);
endtask
 
73,9 → 158,54
begin
this.Log.error("Received invalid endbit during SdBFM.receive.\n");
end
endtask
 
task SdBFM::receiveDataBlock(output SdDataBlock block);
ICard.cb.Data <= 'bzzzz;
 
if (Mode == wide) wait (ICard.cb.Data == 'b0000);
else wait (ICard.cb.Data[0] == '0);
 
recvDataBlock(block);
endtask
 
task SdBFM::recvDataBlock(output SdDataBlock block);
if (Mode == standard) recvStandardDataBlock(block);
else recvWideDataBlock(block);
endtask
 
task SdBFM::recvStandardDataBlock(output SdDataBlock block);
Log.error("recvStandardDataBlock not implemented");
endtask
 
task SdBFM::recvWideDataBlock(output SdDataBlock block);
aCrc16 crc[4];
block = new();
 
$display("Startbits: %t", $time);
for (int j = 0; j <= 512*2; j++) begin
@ICard.cb;
for(int i = 0; i < 4; i++) begin
block.data.push_back(ICard.cb.Data[i]);
end
end
 
// crc
for (int j = 0; j < 16; j++) begin
@ICard.cb;
for(int i = 0; i < 4; i++) begin
crc[i] = ICard.cb.Data[i];
end
end
 
// TODO: check crc
 
// end bits
@ICard.cb;
$display("Endbits: %h, %t", ICard.cb.Data, $time);
assert(ICard.cb.Data == 'b1111);
endtask
 
task SdBFM::receiveOrSend();
if(ICard.cb.Cmd == cSdStartbit) begin
SdBusTransToken token;
/sdhc-sc-core/trunk/src/grpSd/unitSdCardModel/src/SdBFM.sv
8,7 → 8,7
`ifndef SDBFM_SV
`define SDBFM_SV
 
`include "SdCmdInterface.sv"
`include "SdBusInterface.sv"
`include "Crc.sv"
`include "Logger.sv"
`include "SDCommandArg.sv"
15,28 → 15,44
`include "SdBusTrans.sv"
 
typedef mailbox #(SdBusTrans) SdBfmMb;
typedef enum {
standard,
wide
} Mode_t;
 
class SdBFM;
 
virtual ISdCard.card ICard;
virtual ISdBus.card ICard;
SdBfmMb ReceivedTransMb;
SdBfmMb SendTransMb;
local semaphore Sem;
local Logger Log;
local int StopAfter = -1;
Mode_t Mode;
extern function new(virtual ISdBus card);
 
extern function new(virtual ISdCard card);
 
extern task start(); // starts a thread for receiving and sending via mailboxes
extern function stop(int AfterCount); // stop the thread
 
extern task send(input SdBusTrans token);
extern task sendBusy();
extern task receive(output SdBusTransToken token);
extern task receiveDataBlock(output SdDataBlock block);
extern task waitUntilReady();
 
extern local task sendCmd(inout SdBusTransData data);
extern local task sendAllDataBlocks(SdDataBlock blocks[]);
extern local task sendDataBlock(SdDataBlock block);
extern local task sendStandardDataBlock(logic data[$]);
extern local task sendWideDataBlock(logic data[$]);
extern local task recvDataBlock(output SdDataBlock block);
extern local task recvStandardDataBlock(output SdDataBlock block);
extern local task recvWideDataBlock(output SdDataBlock block);
extern local task recv(output SdBusTransToken token);
extern local task receiveOrSend();
extern local task run();
 
local semaphore Sem;
local Logger Log;
local int StopAfter = -1;
endclass
 
`include "SdBFM-impl.sv";
/sdhc-sc-core/trunk/src/grpSd/unitSdCardModel/src/SdDataBlock.sv
0,0 → 1,29
//
// file: SdData.sv
// author: Rainer Kastl
//
// Class for sending and receiving data (SD spec 2.00)
//
 
`ifndef SDDATA
`define SDDATA
typedef enum {
usual,
widewidth
} DataMode_t;
 
function automatic void CrcOnContainer(ref logic data[$]);
aCrc16 crc = 0;
crc = calcCrc16(data);
 
for (int i = 15; i >= 0; i--)
data.push_back(crc[i]);
endfunction
 
class SdDataBlock;
DataMode_t Mode;
logic data[$];
endclass
 
`endif
/sdhc-sc-core/trunk/src/grpSd/unitSdCardModel/src/SdCardModel.sv
13,13 → 13,11
 
`include "Crc.sv";
`include "SdCommand.sv";
`include "SdData.sv";
`include "SdBFM.sv";
`include "Logger.sv";
 
class SDCard;
local SdBFM bfm;
local virtual ISdCard.card ICard;
local SDCardState state;
local RCA_t rca;
local logic CCS;
27,8 → 25,6
local DataMode_t datamode;
local Logger log;
 
local event CmdReceived, InitDone;
 
local rand int datasize; // ram addresses = 2^datasize - 1; 512 byte blocks
constraint cdatasize {datasize > 1; datasize <= 32;}
 
38,12 → 34,9
this.ram = new[2^(datasize-1)];
endfunction
 
function new(virtual ISdCard CardInterface, event CmdReceived, event InitDone);
ICard = CardInterface;
bfm = new(CardInterface);
function new(SdBFM bfm);
this.bfm = bfm;
state = new();
this.CmdReceived = CmdReceived;
this.InitDone = InitDone;
this.CCS = 1;
rca = 0;
mode = standard;
61,7 → 54,6
SDOCR ocr;
SDCommandR6 rcaresponse;
logic data[$];
SdData sddata;
SdBusTransToken token;
 
log.note("Expecting CMD0");
156,21 → 148,19
this.bfm.receive(token);
assert(token.id == cSdCmdSendSCR);
 
// respond with R1
// respond with R1 and dummy SCR
response = new(cSdCmdSendSCR, state);
this.bfm.send(response);
 
repeat(2) @ICard.cb;
 
response.DataBlocks = new[1];
response.DataBlocks[0] = new();
// send dummy SCR
for (int i = 0; i < 64; i++)
data.push_back(0);
response.DataBlocks[0].data.push_back(0);
data[63-50] = 1;
data[63-48] = 1;
response.DataBlocks[0].data[63-50] = 1;
response.DataBlocks[0].data[63-48] = 1;
 
sddata = new(standard, widewidth);
sddata.send(ICard, data);
this.bfm.send(response);
 
// expect ACMD6
recvCMD55(rca);
182,7 → 172,7
response = new(cSdCmdSetBusWidth, state);
this.bfm.send(response);
 
sddata.mode = wide;
this.bfm.Mode = wide;
mode = wide;
 
// expect CMD6
190,18 → 180,18
this.bfm.receive(token);
assert(token.id == cSdCmdSwitchFuntion);
assert(token.arg == 'h00FFFFF1);
this.bfm.send(response);
 
// send status data structure
data = {};
response.DataBlocks = new[1];
response.DataBlocks[0] = new();
for (int i = 0; i < 512; i++)
data.push_back(0);
response.DataBlocks[0].data.push_back(0);
 
data[511-401] = 1;
data[511-376] = 1;
sddata.send(ICard, data);
response.DataBlocks[0].data[511-401] = 1;
response.DataBlocks[0].data[511-376] = 1;
 
this.bfm.send(response);
 
// expect CMD6 with set
log.note("Expect CMD6 with set");
this.bfm.receive(token);
209,16 → 199,6
assert(token.arg == 'h80FFFFF1);
this.bfm.send(response);
 
// send status data structure
data = {};
for (int i = 0; i < 512; i++)
data.push_back(0);
 
data[511-401] = 1;
data[511-376] = 1;
sddata.send(ICard, data);
 
// switch to 50MHz
// expect CMD13
log.note("Expect CMD13");
228,8 → 208,6
response = new(cSdCmdSendStatus, state);
this.bfm.send(response);
 
-> InitDone;
 
endtask
 
task run();
253,9 → 231,7
 
task read(SdBusTransToken token);
SDCommandR1 response;
logic data[$];
logic[31:0] addr;
SdData sddata = new(mode, usual);
 
// expect Read
assert(token.id == cSdCmdReadSingleBlock);
262,48 → 238,48
addr = token.arg[0];
assert(addr < ram.size());
response = new(cSdCmdReadSingleBlock, state);
this.bfm.send(response);
 
data = {};
response.DataBlocks = new[1];
response.DataBlocks[0] = new();
for (int i = 0; i < 512; i++) begin
for (int j = 7; j >= 0; j--) begin
data.push_back(ram[addr][i*8 + j]);
response.DataBlocks[0].data.push_back(ram[addr][i*8 + j]);
end
end
 
sddata.send(ICard, data);
this.bfm.send(response);
endtask
 
task write(SdBusTransToken token);
SDCommandR1 response;
SdData sddata = new(this.mode, widewidth);
logic rddata[$];
SdDataBlock rdblock;
logic[31:0] addr;
 
// expect Write
assert(token.id == cSdCmdWriteSingleBlock);
addr = token.arg[0];
addr = token.arg;
assert(addr < ram.size());
response = new(cSdCmdWriteSingleBlock, state);
this.bfm.send(response);
 
// recv data
sddata.recv(ICard, rddata);
$display("rddata: %p", rddata);
this.bfm.receiveDataBlock(rdblock);
$display("rddata: %p", rdblock.data);
 
$display("datasize: %h", datasize);
$display("Address (token): %h", token.arg);
$display("Address: %h", addr);
 
// write into ram
for (int i = 0; i < 512; i++) begin
for (int j = 7; j >= 0; j--) begin
ram[addr][i * 8 + j] = rddata.pop_front();
ram[addr][i * 8 + j] = rdblock.data.pop_front();
end
end
 
repeat (8) @ICard.cb;
sddata.sendBusy(ICard);
 
this.bfm.waitUntilReady();
this.bfm.sendBusy();
$display("Ram at write address: %h", ram[addr]);
 
endtask
327,8 → 303,8
 
class NoSDCard extends SDCard;
 
function new(virtual ISdCard CardInterface, event CmdReceived, event InitDone);
super.new(CardInterface, CmdReceived, InitDone);
function new(SdBFM bfm);
super.new(bfm);
endfunction
 
task automatic init();
/sdhc-sc-core/trunk/src/grpSd/unitSdCardModel/src/SdBusInterface.sv
0,0 → 1,26
//
// file: ../../unitSdVerificationTestbench/src/SdCmdInterface.sv
// author: Rainer Kastl
//
// Interface for the SdCmd entity
//
 
`ifndef SDBUSINTERFACE_SV
`define SDBUSINTERFACE_SV
 
interface ISdBus;
wire Cmd;
logic SClk;
wire[3:0] Data;
 
clocking cb @(posedge SClk);
inout Cmd;
inout Data;
endclocking
 
modport card (clocking cb);
 
endinterface
 
`endif
 
/sdhc-sc-core/trunk/src/grpSd/unitTestWbMaster/src/TestWbMaster-e.vhdl
0,0 → 1,41
--
-- Title: Wishbone master for test purpose
-- File: TestWbMaster-e.vhdl
-- Author: Copyright 2010: Rainer Kastl
-- Standard: VHDL'93
--
-- Description: Writes a block on the card and reads it back
--
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity TestWbMaster is
port (
-- Wishbone interface
CLK_I : in std_ulogic;
RST_I : in std_ulogic;
 
-- Wishbone master
ERR_I : in std_ulogic;
RTY_I : in std_ulogic;
ACK_I : in std_ulogic;
DAT_I : in std_ulogic_vector(31 downto 0);
 
CYC_O : out std_ulogic;
STB_O : out std_ulogic;
WE_O : out std_ulogic;
CTI_O : out std_ulogic_vector(2 downto 0);
BTE_O : out std_ulogic_vector(1 downto 0);
 
ADR_O : out std_ulogic_vector(6 downto 4);
DAT_O : out std_ulogic_vector(31 downto 0);
SEL_O : out std_ulogic_vector(0 downto 0);
 
-- status signal
ERR_O : out std_ulogic;
DON_O : out std_ulogic
);
end entity TestWbMaster;
 
/sdhc-sc-core/trunk/src/grpSd/unitTestWbMaster/src/TestWbMaster-Rtl-a.vhdl
0,0 → 1,175
--
-- Title: Architecture of TestWbMaster
-- File: TestWbMaster-Rtl-a.vhdl
-- Author: Copyright 2010: Rainer Kastl
-- Standard: VHDL'93
--
-- Description:
--
 
architecture Rtl of TestWbMaster is
 
type aState is (startAddr, writeBuffer, write, readbuffer, read, done);
subtype aCounter is unsigned(7 downto 0); -- 128 * 32 bit = 512 byte
 
type aWbState is (idle, write, read);
 
type aReg is record
 
State : aState;
Counter : aCounter;
WbState : aWbState;
Err : std_ulogic;
 
end record aReg;
 
signal R, NxR : aReg;
 
begin
 
Regs : process (CLK_I)
begin
if (rising_edge(CLK_I)) then
 
if (RST_I = '1') then
-- sync. reset
R.State <= startAddr;
R.Counter <= (others => '0');
R.WbState <= write;
R.Err <= '0';
 
else
R <= NxR;
 
end if;
 
end if;
end process Regs;
 
StateMachine : process (R, ERR_I, RTY_I, ACK_I, DAT_I)
begin
 
-- default assignment
NxR <= R;
ERR_O <= R.Err;
CTI_O <= "000";
CYC_O <= '0';
WE_O <= '0';
SEL_O <= "0";
STB_O <= '0';
ADR_O <= "000";
DAT_O <= (others => '0');
BTE_O <= "00";
DON_O <= '0';
 
-- we don´t care for errors or retrys
if (ERR_I = '1' or RTY_I = '1') then
NxR.Err <= '1';
end if;
 
case R.WbState is
when idle =>
null;
 
when write =>
-- write data
CTI_O <= "000";
CYC_O <= '1';
WE_O <= '1';
SEL_O <= "1";
STB_O <= '1';
 
if (ACK_I = '1') then
if (R.Counter = 128) then
NxR.Counter <= (others => '0');
else
NxR.Counter <= R.Counter + 1;
end if;
end if;
 
when read =>
-- read data
CTI_O <= "000";
CYC_O <= '1';
WE_O <= '0';
SEL_O <= "1";
STB_O <= '1';
 
if (ACK_I = '1') then
-- check data
--if to_unsigned(to_integer(DAT_I),32) /= to_unsigned(R.Counter, 32) then
-- NxR.Err <= '1';
--end if;
 
if (R.Counter = 128) then
NxR.Counter <= (others => '0');
NxR.WbState <= idle;
else
NxR.Counter <= R.Counter + 1;
end if;
end if;
 
when others =>
report "Invalid wbState" severity error;
end case;
case R.State is
when startAddr =>
ADR_O <= "001";
DAT_O <= X"00000004";
 
if (ACK_I = '1') then
NxR.State <= writeBuffer;
NxR.Counter <= (others => '0');
NxR.WbState <= write;
end if;
 
when writeBuffer =>
ADR_O <= "100"; -- write data
DAT_O <= std_ulogic_vector(R.Counter) & std_ulogic_vector(R.Counter) &
std_ulogic_vector(R.Counter) & std_ulogic_vector(R.Counter);
 
if (R.Counter = 128) then
NxR.State <= write;
NxR.Counter <= to_unsigned(128, aCounter'length);
NxR.WbState <= write;
end if;
 
when write =>
ADR_O <= "000";
DAT_O <= X"00000010"; -- start write operation
 
if (ACK_I = '1') then
NxR.State <= done;
NxR.WbState <= idle;
end if;
 
when read =>
ADR_O <= "000";
DAT_O <= X"00000001"; -- start read operation
 
if (ACK_I = '1') then
NxR.State <= readBuffer;
NxR.WbState <= read;
end if;
when readBuffer =>
ADR_O <= "011"; -- read data
if (R.Counter = 128) then
NxR.Counter <= (others => '0');
NxR.State <= done;
NxR.WbState <= idle;
end if;
 
when done =>
DON_O <= '1';
 
when others =>
report "Invalid state" severity error;
end case;
end process StateMachine;
 
 
end architecture Rtl;
/sdhc-sc-core/trunk/src/grpSd/unitSdTop/src/SdTop-Rtl-ea.vhdl
67,6 → 67,7
signal iSdWbSync, oSdControllerSync : aSdWbSlaveToSdController;
signal iSdControllerSync, oSdWbSync : aSdControllerToSdWbSlave;
signal SdStrobe : std_ulogic;
signal SdInStrobe : std_ulogic;
signal HighSpeed : std_ulogic;
signal iCmd : aiSdCmd;
signal oCmd : aoSdCmd;
209,6 → 210,7
iHighSpeed => HighSpeed,
iDisable => DisableSdClk,
oSdStrobe => SdStrobe,
oSdInStrobe => SdInStrobe,
oSdCardClk => oSClk
);
 
217,6 → 219,7
 
iClk => iSdClk,
iRstSync => iRstSync,
iStrobe => SdInStrobe,
iCmd => ioCmd,
iData => ioData,
oCmdSync => iCmd.Cmd,
/sdhc-sc-core/trunk/src/grpSd/unitSdClockMaster/src/SdClockMaster-Rtl-a.vhdl
15,6 → 15,7
Counter : aCounter;
Clk : std_ulogic;
Strobe : std_ulogic;
InStrobe : std_ulogic;
HighSpeed : std_ulogic;
end record aRegSet;
 
25,6 → 26,7
-- connect outputs with registers
oSdCardClk <= R.Clk;
oSdStrobe <= R.Strobe;
oSdInStrobe <= R.InStrobe;
 
Regs : process (iClk, iRstSync)
begin
36,6 → 38,7
R.Counter <= to_unsigned(0, R.Counter'length);
R.Clk <= cInactivated;
R.Strobe <= cInactivated;
R.InStrobe <= cInactivated;
R.HighSpeed <= cInactivated;
 
else
62,19 → 65,27
NxR.Clk <= R.Counter(1);
 
case R.Counter is
when "00" | "01" | "11" =>
when "00" | "11" =>
NxR.Strobe <= cInactivated;
NxR.InStrobe <= cInactivated;
 
when "10" =>
NxR.Strobe <= cActivated;
NxR.InStrobe <= cInactivated;
 
when "01" =>
NxR.InStrobe <= cActivated;
NxR.Strobe <= cInactivated;
 
when others =>
NxR.Strobe <= 'X';
NxR.InStrobe <= 'X';
end case;
 
when cActivated => -- High-Speed mode
NxR.Clk <= R.Counter(0);
NxR.Strobe <= R.Counter(0);
NxR.InStrobe <= not R.Counter(0);
 
when others =>
NxR.Clk <= 'X';
100,10 → 111,12
when cActivated =>
-- disable strobes and do not increment the counter
NxR.Strobe <= cInactivated;
NxR.InStrobe <= cInactivated;
 
when others =>
NxR.Clk <= 'X';
NxR.Strobe <= 'X';
NxR.InStrobe <= 'X';
 
end case;
 
/sdhc-sc-core/trunk/src/grpSd/unitSdClockMaster/src/SdClockMaster-e.vhdl
25,6 → 25,7
iDisable : in std_ulogic; -- Disables the clock output
 
oSdStrobe : out std_ulogic; -- strobe signal to enable SdCmd and SdData
oSdInStrobe : out std_ulogic; -- strobe signal to capture the input cmd and data
oSdCardClk : out std_ulogic -- clock output to SD card
);
 
/sdhc-sc-core/trunk/src/grpSd/unitSdData/src/SdData-Rtl-a.vhdl
334,7 → 334,7
case R.Mode is
when wide =>
for i in 0 to 3 loop
temp(i) := R.Word(to_integer(RBitInWordC) - i);
temp(3 - i) := R.Word(to_integer(RBitInWordC) - i);
end loop;
 
when standard =>
/sdhc-sc-core/trunk/src/grpSd/unitTbdSd/Files.tcl
29,6 → 29,11
Sd SdTop {Rtl}
Sd TbdSd {Rtl}}
 
set tb {Sd TbdSd {Bhv}}
set svunits {Sd TbdSd}
 
set sysvlogparams [list +incdir+../../unitSdCardModel/src+../src+../../unitSdWbSlave/src+../../../grpVerification/unitLogger/src/]
 
#set tb
set top Testbed
 
 
/sdhc-sc-core/trunk/src/grpSd/unitTbdSd/src/TbdSd.sv
0,0 → 1,60
//
// file: ../../unitSdVerificationTestbench/src/SdVerificationTestbench.sv
// author: Rainer Kastl
//
// SystemVerilog Testbench testing SdCmd and SdController
//
 
`ifndef SDVERIFICATIONTESTBENCH
`define SDVERIFICATIONTESTBENCH
 
`include "SdCardModel.sv";
 
program Test(ISdBus SdBus);
initial begin
SdBusTransToken token;
SdBFM SdBfm = new(SdBus);
SDCard card = new(SdBfm);
assert(card.randomize());
 
fork
begin // generator
end
 
begin // monitor
end
 
begin // driver for SdCardModel
card.run();
end
 
join;
 
$display("%t : Test completed.", $time);
end
endprogram
 
module Testbed();
logic Clk = 0;
logic nResetAsync = 0;
 
ISdBus CardInterface();
 
TbdSd top(
Clk,
nResetAsync,
CardInterface.Cmd,
CardInterface.SClk,
CardInterface.Data);
 
always #5 Clk <= ~Clk;
 
initial begin
#10 nResetAsync <= 1;
end
 
Test tb(CardInterface);
 
endmodule
 
`endif
/sdhc-sc-core/trunk/src/grpSd/unitTbdSd/src/TbdSd-Rtl-ea.vhdl
62,9 → 62,12
signal oRty : std_ulogic;
 
signal ErrorLed, DoneLed : std_ulogic;
signal LedBank : std_ulogic_vector(7 downto 0);
 
begin
 
oLedBank <= LedBank(7 downto 1) & DoneLed;
 
Reg : process (iClk) is
begin
if (rising_edge(iClk)) then
125,7 → 128,7
ioCmd => ioCmd,
oSclk => oSclk,
ioData => ioData,
oLedBank => oLedBank
oLedBank => LedBank
);
 
TestWbMaster_inst : entity work.TestWbMaster
/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/src/SdCmdInterface.sv File deleted
/sdhc-sc-core/trunk/src/grpSd/unitSdController/src/SdController-Rtl-a.vhdl
558,6 → 558,7
 
when read =>
NextR.ToSdData.DataMode <= usual;
oLedBank(0) <= cActivated;
 
case R.Region is
when send =>
604,6 → 605,7
 
when write =>
NextR.ToSdData.DataMode <= usual;
oLedBank(1) <= cActivated;
 
case R.Region is
when send =>
/sdhc-sc-core/trunk/src/grpSd/unitSdCardSynchronizer/src/SdCardSynchronizer-Rtl-ea.vhdl
21,6 → 21,7
 
iClk : in std_ulogic;
iRstSync : in std_ulogic;
iStrobe : in std_ulogic;
iCmd : in std_logic;
iData : in std_logic_vector(3 downto 0);
oCmdSync : out std_ulogic;
50,17 → 51,19
 
else
 
-- register input data
CmdSync(0) <= iCmd;
DataSync(0) <= std_ulogic_vector(iData);
if (iStrobe = cActivated) then
-- register input data
CmdSync(0) <= iCmd;
DataSync(0) <= std_ulogic_vector(iData);
 
-- additional synchronization FFs
for i in 1 to gSyncCount - 1 loop
-- additional synchronization FFs
for i in 1 to gSyncCount - 1 loop
 
CmdSync(i) <= CmdSync(i - 1);
DataSync(i) <= DataSync(i - 1);
CmdSync(i) <= CmdSync(i - 1);
DataSync(i) <= DataSync(i - 1);
 
end loop;
end loop;
end if;
end if;
end if;
end process Reg;

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