OpenCores
URL https://opencores.org/ocsvn/mdct/mdct/trunk

Subversion Repositories mdct

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    from Rev 15 to Rev 16
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Rev 15 → Rev 16

/trunk/source/testbench/wave.do
31,7 → 31,6
add wave -noupdate -format Literal -radix hexadecimal /tb_mdct/u_mdct/u_dct1d/row_reg
add wave -noupdate -format Logic -radix hexadecimal /tb_mdct/u_mdct/u_dbufctl/memswitchwr
add wave -noupdate -format Logic -radix hexadecimal /tb_mdct/u_mdct/u_dbufctl/memswitchrd
add wave -noupdate -format Logic /tb_mdct/u_mdct/u_dct2d/clk
add wave -noupdate -format Logic /tb_mdct/u_mdct/u_dct2d/rst
add wave -noupdate -format Logic -radix hexadecimal /tb_mdct/u_mdct/u_dct2d/odv
add wave -noupdate -format Literal -radix decimal /tb_mdct/u_mdct/u_dct2d/dcto
48,6 → 47,7
add wave -noupdate -format Literal -radix hexadecimal /tb_mdct/u_mdct/u_dct2d/col_reg
add wave -noupdate -format Literal -radix hexadecimal /tb_mdct/u_mdct/u_dct2d/row_reg
add wave -noupdate -format Logic -radix hexadecimal /tb_mdct/u_mdct/u_dbufctl/dataready
add wave -noupdate -format Logic /tb_mdct/u_mdct/u_dct2d/clk
add wave -noupdate -format Literal -radix hexadecimal /tb_mdct/u_mdct/u_dct1d/ramdatai_s
add wave -noupdate -format Logic -radix hexadecimal /tb_mdct/u_mdct/u_dct1d/ramwe_s
add wave -noupdate -format Literal /tb_mdct/u_inpimage/inpimage_proc/i
80,19 → 80,19
add wave -noupdate -format Literal /tb_mdct/u_inpimage/inpimage_proc/i
add wave -noupdate -format Literal /tb_mdct/u_inpimage/inpimage_proc/j
add wave -noupdate -format Literal /tb_mdct/u_inpimage/error_dcto1_matrix_s
add wave -noupdate -format Logic /tb_mdct/u_mdct/u1_ram/clk
add wave -noupdate -format Literal /tb_mdct/u_mdct/u1_ram/d
add wave -noupdate -format Literal /tb_mdct/u_mdct/u1_ram/waddr
add wave -noupdate -format Literal /tb_mdct/u_mdct/u1_ram/raddr
add wave -noupdate -format Logic -radix decimal /tb_mdct/u_mdct/u1_ram/clk
add wave -noupdate -format Literal -radix decimal /tb_mdct/u_mdct/u1_ram/d
add wave -noupdate -format Literal -radix unsigned /tb_mdct/u_mdct/u1_ram/raddr
add wave -noupdate -format Literal -radix decimal /tb_mdct/u_mdct/u1_ram/waddr
add wave -noupdate -format Logic /tb_mdct/u_mdct/u1_ram/we
add wave -noupdate -format Logic /tb_mdct/u_mdct/u1_ram/clk
add wave -noupdate -format Literal /tb_mdct/u_mdct/u1_ram/q
add wave -noupdate -format Literal -radix decimal /tb_mdct/u_mdct/u1_ram/q
add wave -noupdate -format Literal /tb_mdct/u_mdct/u1_ram/mem
add wave -noupdate -format Literal /tb_mdct/u_mdct/u1_ram/read_addr
add wave -noupdate -format Literal /tb_mdct/u_inpimage/final_outimage_proc/i
add wave -noupdate -format Literal /tb_mdct/u_inpimage/final_outimage_proc/j
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {220350000 ps} 0}
WaveRestoreCursors {{Cursor 1} {7596588 ps} 0}
configure wave -namecolwidth 155
configure wave -valuecolwidth 103
configure wave -justifyvalue left
106,4 → 106,4
configure wave -griddelta 40
configure wave -timeline 0
update
WaveRestoreZoom {218222050 ps} {222338850 ps}
WaveRestoreZoom {6158584 ps} {9141416 ps}
/trunk/source/testbench/INPIMAGE.VHD
34,7 → 34,6
entity INPIMAGE is
port (
clk : in STD_LOGIC;
ready : in STD_LOGIC;
odv1 : in STD_LOGIC;
dcto1 : in STD_LOGIC_VECTOR(OP_W-1 downto 0);
odv : in STD_LOGIC;
/trunk/source/testbench/MDCT_TB.VHD
45,7 → 45,6
dcti : in std_logic_vector(IP_W-1 downto 0);
idv : in STD_LOGIC;
 
fiforead : out STD_LOGIC; -- ready for input data
odv : out STD_LOGIC;
dcto : out std_logic_vector(COE_W-1 downto 0);
-- debug
69,7 → 68,6
component INPIMAGE is
port (
clk : in STD_LOGIC;
ready : in STD_LOGIC;
odv1 : in STD_LOGIC;
dcto1 : in STD_LOGIC_VECTOR(OP_W-1 downto 0);
odv : in STD_LOGIC;
89,7 → 87,6
signal dcti_s : STD_LOGIC_VECTOR(IP_W-1 downto 0);
signal idv_s : STD_LOGIC;
 
signal fiforead_s : STD_LOGIC;
signal odv_s : STD_LOGIC;
signal dcto_s : STD_LOGIC_VECTOR(COE_W-1 downto 0);
signal odv1_s : STD_LOGIC;
109,8 → 106,7
rst => rst_s,
dcti => dcti_s,
idv => idv_s,
 
fiforead => fiforead_s,
odv => odv_s,
dcto => dcto_s,
odv1 => odv1_s,
134,7 → 130,6
U_INPIMAGE : INPIMAGE
port map (
clk => clk_s,
ready => fiforead_s,
odv1 => odv1_s,
dcto1 => dcto1_s,
odv => odv_s,
/trunk/source/testbench/MDCTTB_PKG.vhd
77,7 → 77,7
constant ENABLE_QUANTIZATION_C : BOOLEAN := FALSE;
constant HEX_BASE : INTEGER := 16;
constant DEC_BASE : INTEGER := 10;
constant RUN_FULL_IMAGE : BOOLEAN := FALSE;
constant RUN_FULL_IMAGE : BOOLEAN := TRUE;
constant FILEIN_NAME_C : STRING := "SOURCE\TESTBENCH\lena512.txt";
constant FILEERROR_NAME_C : STRING := "SOURCE\TESTBENCH\imagee.txt";
constant FILEIMAGEO_NAME_C : STRING := "SOURCE\TESTBENCH\imageo.txt";
/trunk/source/MDCT.VHD
36,7 → 36,6
dcti : in std_logic_vector(IP_W-1 downto 0);
idv : in STD_LOGIC;
 
fiforead : out STD_LOGIC; -- ready for input data
odv : out STD_LOGIC;
dcto : out std_logic_vector(COE_W-1 downto 0);
-- debug
/trunk/DOC/mdct_spec.doc Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/DOC/mdct_spec.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/DOC/mdct_spec.pdf
trunk/DOC/mdct_spec.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/mdct.mpf =================================================================== --- trunk/mdct.mpf (revision 15) +++ trunk/mdct.mpf (revision 16) @@ -556,28 +556,28 @@ Project_File_P_10 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder XILINX last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 16 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_11 = C:/elektronika/dct/mdct/source/testbench/MDCT_TB.VHD Project_File_P_11 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder TESTBENCH last_compile 1144881653 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 6 cover_nosub 0 dont_compile 0 vhdl_use93 93 -Project_File_12 = C:/elektronika/dct/mdct/source/ROMO.VHD -Project_File_P_12 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder SOURCE last_compile 1145568090 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 1 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 9 dont_compile 0 cover_nosub 0 vhdl_use93 93 +Project_File_12 = C:/elektronika/dct/MDCT/synthesis/mdct_temp_2/MDCT_out.vhd +Project_File_P_12 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder PAR last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 12 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_13 = C:/elektronika/dct/MDCT/source/testbench/RUNSIM_TIMING.DO Project_File_P_13 = vhdl_novitalcheck 0 file_type tcl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder MODELSIM last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order -1 dont_compile 1 cover_nosub 0 vhdl_use93 2002 -Project_File_14 = C:/elektronika/dct/MDCT/synthesis/mdct_temp_2/MDCT_out.vhd -Project_File_P_14 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder PAR last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 12 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_14 = C:/elektronika/dct/mdct/source/ROMO.VHD +Project_File_P_14 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder SOURCE last_compile 1145568090 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 1 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 9 dont_compile 0 cover_nosub 0 vhdl_use93 93 Project_File_15 = C:/elektronika/dct/mdct/source/testbench/MDCTTB_PKG.vhd Project_File_P_15 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder TESTBENCH last_compile 1143976585 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 7 cover_nosub 0 dont_compile 0 vhdl_use93 93 Project_File_16 = C:/elektronika/dct/MDCT/source/xilinx/ram_xil.vhd Project_File_P_16 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder XILINX last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 18 dont_compile 0 cover_nosub 0 vhdl_use93 2002 -Project_File_17 = C:/elektronika/dct/mdct/source/DCT1D.vhd -Project_File_P_17 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder SOURCE last_compile 1145135163 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 1 cover_nosub 0 dont_compile 0 vhdl_use93 93 +Project_File_17 = C:/elektronika/dct/MDCT/source/xilinx/ROMO.VHD +Project_File_P_17 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder XILINX last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 15 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_18 = C:/elektronika/dct/mdct/source/MDCT.VHD Project_File_P_18 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder SOURCE last_compile 1143931873 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 0 cover_nosub 0 dont_compile 0 vhdl_use93 93 -Project_File_19 = C:/elektronika/dct/MDCT/source/xilinx/ROMO.VHD -Project_File_P_19 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder XILINX last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 15 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_20 = C:/elektronika/dct/MDCT/source/testbench/random1.vhd -Project_File_P_20 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder TESTBENCH last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 19 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_19 = C:/elektronika/dct/mdct/source/DCT1D.vhd +Project_File_P_19 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder SOURCE last_compile 1145135163 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 1 cover_nosub 0 dont_compile 0 vhdl_use93 93 +Project_File_20 = C:/elektronika/dct/mdct/source/testbench/INPIMAGE.VHD +Project_File_P_20 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder TESTBENCH last_compile 1143979283 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 5 cover_nosub 0 dont_compile 0 vhdl_use93 93 Project_File_21 = C:/elektronika/dct/mdct/source/MDCT_PKG.vhd Project_File_P_21 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder SOURCE last_compile 1144447956 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 2 cover_nosub 0 dont_compile 0 vhdl_use93 93 -Project_File_22 = C:/elektronika/dct/mdct/source/testbench/INPIMAGE.VHD -Project_File_P_22 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder TESTBENCH last_compile 1143979283 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vlog_vopt {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 5 cover_nosub 0 dont_compile 0 vhdl_use93 93 +Project_File_22 = C:/elektronika/dct/MDCT/source/testbench/random1.vhd +Project_File_P_22 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder TESTBENCH last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 19 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_23 = C:/elektronika/dct/MDCT/source/xilinx/rome_xil.vhd Project_File_P_23 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder XILINX last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 1 compile_to work compile_order 14 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_Sim_Count = 0 @@ -619,6 +619,6 @@ XML_CustomDoubleClick = LOGFILE_DoubleClick = Edit LOGFILE_CustomDoubleClick = -EditorState = {tabbed horizontal 1} {C:/elektronika/dct/MDCT/source/testbench/INPIMAGE.VHD 0 0} {C:/elektronika/dct/MDCT/source/testbench/MDCTTB_PKG.vhd 0 1} +EditorState = {tabbed horizontal 1} {C:/elektronika/dct/MDCT/source/testbench/INPIMAGE.VHD 0 0} {C:/elektronika/dct/MDCT/source/testbench/MDCTTB_PKG.vhd 0 0} {C:/elektronika/dct/MDCT/source/MDCT.VHD 0 0} {C:/elektronika/dct/MDCT/source/testbench/MDCT_TB.VHD 0 1} Project_Major_Version = 6 Project_Minor_Version = 1

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