OpenCores
URL https://opencores.org/ocsvn/sgmii/sgmii/trunk

Subversion Repositories sgmii

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    from Rev 15 to Rev 16
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Rev 15 → Rev 16

/sgmii/trunk/src/mXcver.v
32,11 → 32,11
 
 
generate
if(pXcverName=="AltCycIV")
if(pXcverName=="AltCycIV")
begin:AltCycIVXcver
wire [04:00] w5_ReconfigFromGxb;
wire [03:00] w4_ReconfigToGxb;
wire w_Reconfiguring;
begin:AltCycIVXcver
mAltGX u0AltGX (
.cal_blk_clk (i_CalClk),
.gxb_powerdown (i_GxBPwrDwn),
75,7 → 75,60
endgenerate
generate
if(pXcverName=="AltArriaV")
begin:AltArriaVXcver
wire [091:00] w92_ReconfigFromGxb;
wire [139:00] w140_ReconfigToGxb;
wire w_Reconfiguring;
mAltAvgxXcver uAltXCver(
.phy_mgmt_clk (i_RefClk125M), // phy_mgmt_clk.clk
.phy_mgmt_clk_reset (1'b0), // phy_mgmt_clk_reset.reset
.phy_mgmt_address (8'h0), // phy_mgmt.address
.phy_mgmt_read (1'b0), // .read
.phy_mgmt_readdata (), // .readdata
.phy_mgmt_waitrequest (), // .waitrequest
.phy_mgmt_write (1'b0), // .write
.phy_mgmt_writedata (32'h0), // .writedata
.tx_ready (), // tx_ready.export
.rx_ready (), // rx_ready.export
.pll_ref_clk (i_RefClk125M), // pll_ref_clk.clk
.tx_serial_data (o_SerTx), // tx_serial_data.export
.pll_locked (o_PllLocked), // pll_locked.export
.rx_serial_data (i_SerRx), // rx_serial_data.export
.rx_runningdisp (o_RunningDisparity), // rx_runningdisp.export
.rx_patterndetect (w_PatternDtec), // rx_patterndetect.export
.rx_disperr (w_DispErr), // rx_disperr.export
.rx_errdetect (w_ErrDtec), // rx_errdetect.export
.rx_syncstatus (w_SyncStatus), // rx_syncstatus.export
.tx_clkout (o_TxClk), // tx_clkout.export
.rx_clkout (), // rx_clkout.export
.tx_parallel_data (i8_TxCodeGroup), // tx_parallel_data.export
.tx_datak (i_TxCodeCtrl), // tx_datak.export
.rx_parallel_data (o8_RxCodeGroup), // rx_parallel_data.export
.rx_datak (o_RxCodeCtrl), // rx_datak.export
.reconfig_from_xcvr (w92_ReconfigFromGxb), // reconfig_from_xcvr.reconfig_from_xcvr
.reconfig_to_xcvr (w140_ReconfigToGxb) // reconfig_to_xcvr.reconfig_to_xcvr
);
assign o_SignalDetect = ~(w_ErrDtec|w_DispErr);
assign o_RxCodeInvalid = w_ErrDtec;
mAltAvgxReconfig uReconfig(
.reconfig_busy (w_Reconfiguring), // reconfig_busy.reconfig_busy
.mgmt_clk_clk (i_CalClk), // mgmt_clk_clk.clk
.mgmt_rst_reset (i_XcverDigitalRst), // mgmt_rst_reset.reset
.reconfig_mgmt_address (8'h0), // reconfig_mgmt.address
.reconfig_mgmt_read (1'b0), // .read
.reconfig_mgmt_readdata (), // .readdata
.reconfig_mgmt_waitrequest (), // .waitrequest
.reconfig_mgmt_write (1'b0), // .write
.reconfig_mgmt_writedata (32'h0), // .writedata
.reconfig_to_xcvr (w140_ReconfigToGxb),// reconfig_to_xcvr.reconfig_to_xcvr
.reconfig_from_xcvr (w92_ReconfigFromGxb)// reconfig_from_xcvr.reconfig_from_xcvr
);
end
endgenerate
 
/sgmii/trunk/src/mSGMII.v
1,5 → 1,5
/*
Copyright � 2012 JeffLieu-lieumychuong@gmail.com
Copyright � 2012 JeffLieu-jefflieu@fpga-ipcores.com
 
This file is part of SGMII-IP-Core.
SGMII-IP-Core is free software: you can redistribute it and/or modify
361,7 → 361,7
assign w_SignalDetect=~w_RxCodeInvalid;
/*mXcver u0Xcver(
/*mXcver #(.pXcverName("AltArriaV"))u0Xcver(
 
.i_SerRx (i_SerRx ),
.o_SerTx (o_SerTx ),
368,7 → 368,7
.i_RefClk125M (i_RefClk125M ),
.o_TxClk (w_ClkSys ),
.i_CalClk (i_CalClk ),
.i_CalClk (i_RefClk125M ),
.i_GxBPwrDwn (w_GxBPowerDown ),
.i_XcverDigitalRst (~w_ARstLogic_L ),
.o_PllLocked (w_PllLocked ),
/sgmii/trunk/src/mAltGX/mAltArriaVlvdsRx.v
14,7 → 14,7
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.0 Build 263 08/02/2012 SP 2 SJ Full Version
// 12.0 Build 263 08/02/2012 SP 2.dp9 SJ Full Version
// ************************************************************
 
 
37,19 → 37,21
`timescale 1 ps / 1 ps
// synopsys translate_on
module mAltArriaVlvdsRx (
pll_areset,
rx_cda_reset,
rx_channel_data_align,
rx_in,
rx_inclock,
rx_reset,
rx_divfwdclk,
rx_locked,
rx_out,
rx_outclock);
 
input pll_areset;
input [0:0] rx_cda_reset;
input [0:0] rx_channel_data_align;
input [0:0] rx_in;
input rx_inclock;
input [0:0] rx_reset;
output [0:0] rx_divfwdclk;
output rx_locked;
output [9:0] rx_out;
67,7 → 69,8
altlvds_rx ALTLVDS_RX_component (
.rx_in (rx_in),
.rx_inclock (rx_inclock),
.pll_areset (pll_areset),
.rx_reset (rx_reset),
.rx_cda_reset (rx_cda_reset),
.rx_channel_data_align (rx_channel_data_align),
.rx_divfwdclk (sub_wire0),
.rx_locked (sub_wire1),
75,6 → 78,7
.rx_outclock (sub_wire3),
.dpa_pll_cal_busy (),
.dpa_pll_recal (1'b0),
.pll_areset (1'b0),
.pll_phasecounterselect (),
.pll_phasedone (1'b1),
.pll_phasestep (),
81,7 → 85,6
.pll_phaseupdown (),
.pll_scanclk (),
.rx_cda_max (),
.rx_cda_reset (1'b0),
.rx_coreclk (1'b1),
.rx_data_align (1'b0),
.rx_data_align_reset (1'b0),
97,12 → 100,11
.rx_fifo_reset (1'b0),
.rx_pll_enable (1'b1),
.rx_readclock (1'b0),
.rx_reset (1'b0),
.rx_syncclock (1'b0));
defparam
ALTLVDS_RX_component.buffer_implementation = "RAM",
ALTLVDS_RX_component.cds_mode = "UNUSED",
ALTLVDS_RX_component.common_rx_tx_pll = "ON",
ALTLVDS_RX_component.common_rx_tx_pll = "OFF",
ALTLVDS_RX_component.data_align_rollover = 10,
ALTLVDS_RX_component.data_rate = "1250.0 Mbps",
ALTLVDS_RX_component.deserialization_factor = 10,
176,17 → 178,17
// Retrieval info: PRIVATE: PLL_Period STRING "8.000"
// Retrieval info: PRIVATE: pOUTCLOCK_PHASE_SHIFT NUMERIC "0"
// Retrieval info: PRIVATE: Reg_InOut NUMERIC "1"
// Retrieval info: PRIVATE: Use_Cda_Reset NUMERIC "0"
// Retrieval info: PRIVATE: Use_Cda_Reset NUMERIC "1"
// Retrieval info: PRIVATE: Use_Clock_Resc STRING "Dual-Regional clock"
// Retrieval info: PRIVATE: Use_Common_Rx_Tx_Plls NUMERIC "1"
// Retrieval info: PRIVATE: Use_Common_Rx_Tx_Plls NUMERIC "0"
// Retrieval info: PRIVATE: Use_Data_Align NUMERIC "1"
// Retrieval info: PRIVATE: Use_Lock NUMERIC "1"
// Retrieval info: PRIVATE: Use_Pll_Areset NUMERIC "1"
// Retrieval info: PRIVATE: Use_Pll_Areset NUMERIC "0"
// Retrieval info: PRIVATE: Use_Rawperror NUMERIC "0"
// Retrieval info: PRIVATE: Use_Tx_Out_Phase NUMERIC "0"
// Retrieval info: CONSTANT: BUFFER_IMPLEMENTATION STRING "RAM"
// Retrieval info: CONSTANT: CDS_MODE STRING "UNUSED"
// Retrieval info: CONSTANT: COMMON_RX_TX_PLL STRING "ON"
// Retrieval info: CONSTANT: COMMON_RX_TX_PLL STRING "OFF"
// Retrieval info: CONSTANT: clk_src_is_pll STRING "off"
// Retrieval info: CONSTANT: DATA_ALIGN_ROLLOVER NUMERIC "10"
// Retrieval info: CONSTANT: DATA_RATE STRING "1250.0 Mbps"
231,8 → 233,8
// Retrieval info: CONSTANT: USE_EXTERNAL_PLL STRING "OFF"
// Retrieval info: CONSTANT: USE_NO_PHASE_SHIFT STRING "ON"
// Retrieval info: CONSTANT: X_ON_BITSLIP STRING "ON"
// Retrieval info: USED_PORT: pll_areset 0 0 0 0 INPUT NODEFVAL "pll_areset"
// Retrieval info: CONNECT: @pll_areset 0 0 0 0 pll_areset 0 0 0 0
// Retrieval info: USED_PORT: rx_cda_reset 0 0 1 0 INPUT NODEFVAL "rx_cda_reset[0..0]"
// Retrieval info: CONNECT: @rx_cda_reset 0 0 1 0 rx_cda_reset 0 0 1 0
// Retrieval info: USED_PORT: rx_channel_data_align 0 0 1 0 INPUT NODEFVAL "rx_channel_data_align[0..0]"
// Retrieval info: CONNECT: @rx_channel_data_align 0 0 1 0 rx_channel_data_align 0 0 1 0
// Retrieval info: USED_PORT: rx_divfwdclk 0 0 1 0 OUTPUT NODEFVAL "rx_divfwdclk[0..0]"
247,6 → 249,8
// Retrieval info: CONNECT: rx_out 0 0 10 0 @rx_out 0 0 10 0
// Retrieval info: USED_PORT: rx_outclock 0 0 0 0 OUTPUT NODEFVAL "rx_outclock"
// Retrieval info: CONNECT: rx_outclock 0 0 0 0 @rx_outclock 0 0 0 0
// Retrieval info: USED_PORT: rx_reset 0 0 1 0 INPUT NODEFVAL "rx_reset[0..0]"
// Retrieval info: CONNECT: @rx_reset 0 0 1 0 rx_reset 0 0 1 0
// Retrieval info: GEN_FILE: TYPE_NORMAL mAltArriaVlvdsRx.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mAltArriaVlvdsRx.qip TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mAltArriaVlvdsRx.bsf FALSE TRUE
/sgmii/trunk/src/mAltGX/mAltArriaVlvdsTx.v
14,7 → 14,7
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.0 Build 263 08/02/2012 SP 2 SJ Full Version
// 12.0 Build 263 08/02/2012 SP 2.dp9 SJ Full Version
// ************************************************************
 
 
37,12 → 37,12
`timescale 1 ps / 1 ps
// synopsys translate_on
module mAltArriaVlvdsTx (
pll_areset,
tx_enable,
tx_in,
tx_inclock,
tx_out);
 
input pll_areset;
input tx_enable;
input [9:0] tx_in;
input tx_inclock;
output [0:0] tx_out;
51,14 → 51,14
wire [0:0] tx_out = sub_wire0[0:0];
 
altlvds_tx ALTLVDS_TX_component (
.pll_areset (pll_areset),
.tx_enable (tx_enable),
.tx_in (tx_in),
.tx_inclock (tx_inclock),
.tx_out (sub_wire0),
.pll_areset (1'b0),
.sync_inclock (1'b0),
.tx_coreclock (),
.tx_data_reset (1'b0),
.tx_enable (1'b1),
.tx_locked (),
.tx_outclock (),
.tx_pll_enable (1'b1),
91,8 → 91,8
ALTLVDS_TX_component.pll_self_reset_on_loss_lock = "OFF",
ALTLVDS_TX_component.preemphasis_setting = 0,
ALTLVDS_TX_component.refclk_frequency = "125.000000 MHz",
ALTLVDS_TX_component.registered_input = "TX_CLKIN",
ALTLVDS_TX_component.use_external_pll = "OFF",
ALTLVDS_TX_component.registered_input = "OFF",
ALTLVDS_TX_component.use_external_pll = "ON",
ALTLVDS_TX_component.use_no_phase_shift = "ON",
ALTLVDS_TX_component.vod_setting = 0,
ALTLVDS_TX_component.clk_src_is_pll = "off";
109,11 → 109,11
// Retrieval info: PRIVATE: CNX_COMMON_PLL NUMERIC "0"
// Retrieval info: PRIVATE: CNX_DATA_RATE STRING "1250.0"
// Retrieval info: PRIVATE: CNX_DESER_FACTOR NUMERIC "10"
// Retrieval info: PRIVATE: CNX_EXT_PLL STRING "OFF"
// Retrieval info: PRIVATE: CNX_EXT_PLL STRING "ON"
// Retrieval info: PRIVATE: CNX_LE_SERDES STRING "OFF"
// Retrieval info: PRIVATE: CNX_NUM_CHANNEL NUMERIC "1"
// Retrieval info: PRIVATE: CNX_OUTCLOCK_DIVIDE_BY NUMERIC "1"
// Retrieval info: PRIVATE: CNX_PLL_ARESET NUMERIC "1"
// Retrieval info: PRIVATE: CNX_PLL_ARESET NUMERIC "0"
// Retrieval info: PRIVATE: CNX_PLL_FREQ STRING "125.000000"
// Retrieval info: PRIVATE: CNX_PLL_PERIOD STRING "8.000"
// Retrieval info: PRIVATE: CNX_REG_INOUT NUMERIC "1"
124,9 → 124,9
// Retrieval info: PRIVATE: CNX_USE_PLL_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: CNX_USE_TX_OUT_PHASE NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria V"
// Retrieval info: PRIVATE: pCNX_OUTCLK_ALIGN STRING "UNUSED"
// Retrieval info: PRIVATE: pCNX_OUTCLK_ALIGN STRING "EDGE_ALIGNED"
// Retrieval info: PRIVATE: pINCLOCK_PHASE_SHIFT STRING "0.00"
// Retrieval info: PRIVATE: pOUTCLOCK_PHASE_SHIFT STRING "0.00"
// Retrieval info: PRIVATE: pOUTCLOCK_PHASE_SHIFT NUMERIC "0"
// Retrieval info: CONSTANT: CENTER_ALIGN_MSB STRING "UNUSED"
// Retrieval info: CONSTANT: COMMON_RX_TX_PLL STRING "OFF"
// Retrieval info: CONSTANT: CORECLOCK_DIVIDE_BY NUMERIC "1"
155,12 → 155,12
// Retrieval info: CONSTANT: PLL_SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: PREEMPHASIS_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: REFCLK_FREQUENCY STRING "125.000000 MHz"
// Retrieval info: CONSTANT: REGISTERED_INPUT STRING "TX_CLKIN"
// Retrieval info: CONSTANT: USE_EXTERNAL_PLL STRING "OFF"
// Retrieval info: CONSTANT: REGISTERED_INPUT STRING "OFF"
// Retrieval info: CONSTANT: USE_EXTERNAL_PLL STRING "ON"
// Retrieval info: CONSTANT: USE_NO_PHASE_SHIFT STRING "ON"
// Retrieval info: CONSTANT: VOD_SETTING NUMERIC "0"
// Retrieval info: USED_PORT: pll_areset 0 0 0 0 INPUT NODEFVAL "pll_areset"
// Retrieval info: CONNECT: @pll_areset 0 0 0 0 pll_areset 0 0 0 0
// Retrieval info: USED_PORT: tx_enable 0 0 0 0 INPUT NODEFVAL "tx_enable"
// Retrieval info: CONNECT: @tx_enable 0 0 0 0 tx_enable 0 0 0 0
// Retrieval info: USED_PORT: tx_in 0 0 10 0 INPUT NODEFVAL "tx_in[9..0]"
// Retrieval info: CONNECT: @tx_in 0 0 10 0 tx_in 0 0 10 0
// Retrieval info: USED_PORT: tx_inclock 0 0 0 0 INPUT NODEFVAL "tx_inclock"
/sgmii/trunk/src/mAltGX/mAltA5GXlvds.v
27,49 → 27,21
wire [9:0] w10_txdatalocal;
wire [9:0] w10_rxdatalocal;
wire w_RxKErr,w_RxRdErr;
wire w_TxClk;
wire w_TxClk,w_RxClk;
wire w_BitSlip;
/*mAlt8b10benc u8b10bEnc(
.clk (o_CoreClk),
.reset_n (~i_XcverDigitalRst),
.idle_ins (~i_TxCodeValid),
.kin (i_TxCodeCtrl),
.ena (1'b1),
.datain (i8_TxCodeGroup),
.rdin (1'b0),
.rdforce (i_TxForceNegDisp),
.kerr (),
.dataout (w10_txdatalocal),
.valid (),
.rdout (o_RunningDisparity),
.rdcascade ());*/
mEnc8b10bMem u8b10bEnc(
.i8_Din (i8_TxCodeGroup), //HGFEDCBA
.i_Kin (i_TxCodeCtrl),
.i_ForceDisparity (i_TxForceNegDisp),
.i_Disparity (~i_TxForceNegDisp), //1 Is negative, 0 is positive
.o10_Dout (w10_txdata), //abcdeifghj
.i_Disparity (~i_TxForceNegDisp), //1 is positive, 0 is negative
.o10_Dout (w10_txdata), //abcdeifghj
.o_Rd (o_RunningDisparity),
.o_KErr (),
.i_Clk (o_CoreClk),
.i_ARst_L (~i_XcverDigitalRst));
.i_Clk (w_RxClk),
.i_ARst_L (~i_XcverDigitalRst));
/*mAlt8b10bdec u8b10bDec(
.clk (o_CoreClk),
.reset_n (~i_XcverDigitalRst),
.idle_del (),
.ena (1'b1),
.datain (w10_rxdatalocal),
.rdforce (1'b0),
.rdin (1'b0),
.valid (w_RxDataValid),
.dataout (o8_RxCodeGroup),
.kout (o_RxCodeCtrl),
.kerr (w_RxKErr),
.rdcascade (),
.rdout (),
.rderr (w_RxRdErr));*/
mDec8b10bMem u8b10bDec(
.o8_Dout (o8_RxCodeGroup), //HGFEDCBA
.o_Kout (o_RxCodeCtrl),
78,9 → 50,9
.o_DpErr (w_RxRdErr),
.i_ForceDisparity (1'b0),
.i_Disparity (1'b0),
.i10_Din (w10_rxdata), //abcdeifghj
.i10_Din (w10_rxdata), //abcdeifghj
.o_Rd (),
.i_Clk (o_CoreClk),
.i_Clk (w_RxClk),
.i_ARst_L (~i_XcverDigitalRst));
assign o_RxCodeInvalid = w_RxKErr|w_RxRdErr;
87,42 → 59,57
assign o_SignalDetect = (~o_RxCodeInvalid)|o_RxCodeCtrl;
mAltArriaVlvdsRx ulvdsrx (
.rx_channel_data_align (i_RxBitSlip),
.rx_in (i_SerRx),
.rx_inclock (i_RefClk125M),
.rx_out (w10_rxdata),
.rx_locked (o_PllLocked),
//.rx_outclock (o_CoreClk),
.rx_divfwdclk (o_CoreClk),
.pll_areset (i_XcverDigitalRst));
.rx_cda_reset (w_RxCdaReset),
.rx_channel_data_align (i_RxBitSlip),
.rx_in (i_SerRx),
.rx_inclock (i_RefClk125M),
.rx_out (w10_rxdata),
.rx_locked (o_PllLocked),
.rx_reset (w_RxReset),
.rx_divfwdclk (w_RxClk));
/////////////////////////////////////////////////
//Hold In Reset Until Stable
/////////////////////////////////////////////////
reg [11:0] r12_LockCnt;
always@(posedge i_RefClk125M or negedge o_PllLocked)
if((~o_PllLocked))
r12_LockCnt<=12'h0;
else begin
if(~(&r12_LockCnt))
r12_LockCnt<=r12_LockCnt+12'h1;
end
assign w_RxReset = ~r12_LockCnt[11];
assign w_RxCdaReset = (r12_LockCnt[11:10]==2'b11)?1'b0:1'b1;
reg [9:0] r10_txdata;
mAltArriaVlvdsTx ulvdstx(
.tx_in (w10_txdata),
.tx_inclock (o_CoreClk),
//.tx_coreclock (w_TxClk),
.tx_out (o_SerTx),
.pll_areset(i_XcverDigitalRst));
.tx_in (r10_txdata),
.tx_inclock (w_TxSerClk),
.tx_enable (w_TxEnClk),
.tx_out (o_SerTx));
mAltLvdsPll uAltTxPll(
.refclk (w_RxClk), // refclk.clk
.rst (w_PorRst), // reset.reset
.outclk_0 (w_TxSerClk), // outclk0.clk
.outclk_1 (w_TxEnClk), // outclk1.clk
.outclk_2 (w_TxClk), // outclk2.clk
.locked (w_TxLocked) // locked.export
);
function [9:0] bitreverse ;
input [9:0] in;
integer I;
begin
for(I=0;I<10;I=I+1)
bitreverse[I]=in[9-I];
end
endfunction
always@(posedge w_TxClk)
r10_txdata <= w10_txdata;
//assign w10_txdata = bitreverse(w10_txdatalocal);
//assign w10_rxdatalocal = bitreverse(w10_rxdata);
// mAltRateAdapter uRxAdapter(
// .data (w10_txdatalocal),
// .rdclk (w_TxClk),
// .rdempty(rdempty),
// .rdreq (~rdempty),
// .wrclk (o_CoreClk),
// .wrreq (1'b1),
// .q(w10_txdata));
assign o_CoreClk = w_RxClk;
reg [7:0] r8_PorTmr;
assign w_PorRst = ~(&r8_PorTmr);
always@(posedge i_RefClk125M)
begin
if(w_PorRst)
r8_PorTmr <= r8_PorTmr+8'h1;
end
 
 
endmodule
/sgmii/trunk/src/mAltGX/mAltArriaVlvdsRx.ppf
2,10 → 2,11
<!DOCTYPE pinplan>
<pinplan intended_family="Arria V" variation_name="mAltArriaVlvdsRx" megafunction_name="ALTLVDS_RX" specifies="all_ports">
<global>
<pin name="pll_areset" direction="input" scope="external" />
<pin name="rx_cda_reset[0..0]" direction="input" scope="external" />
<pin name="rx_channel_data_align[0..0]" direction="input" scope="external" />
<pin name="rx_in[0..0]" direction="input" scope="external" />
<pin name="rx_inclock" direction="input" scope="external" />
<pin name="rx_reset[0..0]" direction="input" scope="external" />
<pin name="rx_divfwdclk[0..0]" direction="output" scope="external" />
<pin name="rx_locked" direction="output" scope="external" />
<pin name="rx_out[9..0]" direction="output" scope="external" />
/sgmii/trunk/src/mAltGX/mAltArriaVlvdsTx.ppf
2,7 → 2,7
<!DOCTYPE pinplan>
<pinplan intended_family="Arria V" variation_name="mAltArriaVlvdsTx" megafunction_name="ALTLVDS_TX" specifies="all_ports">
<global>
<pin name="pll_areset" direction="input" scope="external" />
<pin name="tx_enable" direction="input" scope="external" />
<pin name="tx_in[9..0]" direction="input" scope="external" />
<pin name="tx_inclock" direction="input" scope="external" />
<pin name="tx_out[0..0]" direction="output" scope="external" />
/sgmii/trunk/src/SGMIIDefs.v
1,5 → 1,5
/*
 
Copyright � 2012 JeffLieu-lieumychuong@gmail.com
This file is part of SGMII-IP-Core.
SGMII-IP-Core is free software: you can redistribute it and/or modify
45,8 → 45,8
`define K30_7 8'hFE //V/
 
`define cReg4Default 16'h0000
`define cReg0Default 16'h0000
`define cRegXDefault 16'h0000
`define cReg0Default 16'h1000
`define cRegXDefault 16'h0003
`define cRegLinkTimerDefault (10_000_000/8)
 
`define cLcAbility_FD 16'h0020

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