OpenCores

/trunk/syn/Altera/CycloneII/slib_clock_div.bsf

0,0 → 1,63

trunk/syn/Altera/CycloneII/slib_clock_div.bsf Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/syn/Altera/CycloneII/uart_16750.bsf =================================================================== --- trunk/syn/Altera/CycloneII/uart_16750.bsf (nonexistent) +++ trunk/syn/Altera/CycloneII/uart_16750.bsf (revision 16) @@ -0,0 +1,190 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 16 16 176 304) + (text "uart_16750" (rect 5 0 59 12)(font "Arial" )) + (text "inst" (rect 8 272 25 284)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "CLK" (rect 0 0 21 12)(font "Arial" )) + (text "CLK" (rect 21 27 42 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 0 48) + (input) + (text "RST" (rect 0 0 21 12)(font "Arial" )) + (text "RST" (rect 21 43 42 55)(font "Arial" )) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 0 64) + (input) + (text "BAUDCE" (rect 0 0 46 12)(font "Arial" )) + (text "BAUDCE" (rect 21 59 67 71)(font "Arial" )) + (line (pt 0 64)(pt 16 64)(line_width 1)) + ) + (port + (pt 0 80) + (input) + (text "CS" (rect 0 0 15 12)(font "Arial" )) + (text "CS" (rect 21 75 36 87)(font "Arial" )) + (line (pt 0 80)(pt 16 80)(line_width 1)) + ) + (port + (pt 0 96) + (input) + (text "WR" (rect 0 0 18 12)(font "Arial" )) + (text "WR" (rect 21 91 39 103)(font "Arial" )) + (line (pt 0 96)(pt 16 96)(line_width 1)) + ) + (port + (pt 0 112) + (input) + (text "RD" (rect 0 0 16 12)(font "Arial" )) + (text "RD" (rect 21 107 37 119)(font "Arial" )) + (line (pt 0 112)(pt 16 112)(line_width 1)) + ) + (port + (pt 0 128) + (input) + (text "A[2..0]" (rect 0 0 33 12)(font "Arial" )) + (text "A[2..0]" (rect 21 123 54 135)(font "Arial" )) + (line (pt 0 128)(pt 16 128)(line_width 3)) + ) + (port + (pt 0 144) + (input) + (text "DIN[7..0]" (rect 0 0 46 12)(font "Arial" )) + (text "DIN[7..0]" (rect 21 139 67 151)(font "Arial" )) + (line (pt 0 144)(pt 16 144)(line_width 3)) + ) + (port + (pt 0 160) + (input) + (text "RCLK" (rect 0 0 29 12)(font "Arial" )) + (text "RCLK" (rect 21 155 50 167)(font "Arial" )) + (line (pt 0 160)(pt 16 160)(line_width 1)) + ) + (port + (pt 0 176) + (input) + (text "CTSN" (rect 0 0 29 12)(font "Arial" )) + (text "CTSN" (rect 21 171 50 183)(font "Arial" )) + (line (pt 0 176)(pt 16 176)(line_width 1)) + ) + (port + (pt 0 192) + (input) + (text "DSRN" (rect 0 0 31 12)(font "Arial" )) + (text "DSRN" (rect 21 187 52 199)(font "Arial" )) + (line (pt 0 192)(pt 16 192)(line_width 1)) + ) + (port + (pt 0 208) + (input) + (text "DCDN" (rect 0 0 33 12)(font "Arial" )) + (text "DCDN" (rect 21 203 54 215)(font "Arial" )) + (line (pt 0 208)(pt 16 208)(line_width 1)) + ) + (port + (pt 0 224) + (input) + (text "RIN" (rect 0 0 20 12)(font "Arial" )) + (text "RIN" (rect 21 219 41 231)(font "Arial" )) + (line (pt 0 224)(pt 16 224)(line_width 1)) + ) + (port + (pt 0 240) + (input) + (text "SIN" (rect 0 0 18 12)(font "Arial" )) + (text "SIN" (rect 21 235 39 247)(font "Arial" )) + (line (pt 0 240)(pt 16 240)(line_width 1)) + ) + (port + (pt 160 32) + (output) + (text "DOUT[7..0]" (rect 0 0 56 12)(font "Arial" )) + (text "DOUT[7..0]" (rect 83 27 139 39)(font "Arial" )) + (line (pt 160 32)(pt 144 32)(line_width 3)) + ) + (port + (pt 160 48) + (output) + (text "DDIS" (rect 0 0 27 12)(font "Arial" )) + (text "DDIS" (rect 112 43 139 55)(font "Arial" )) + (line (pt 160 48)(pt 144 48)(line_width 1)) + ) + (port + (pt 160 64) + (output) + (text "INT" (rect 0 0 17 12)(font "Arial" )) + (text "INT" (rect 122 59 139 71)(font "Arial" )) + (line (pt 160 64)(pt 144 64)(line_width 1)) + ) + (port + (pt 160 80) + (output) + (text "OUT1N" (rect 0 0 36 12)(font "Arial" )) + (text "OUT1N" (rect 103 75 139 87)(font "Arial" )) + (line (pt 160 80)(pt 144 80)(line_width 1)) + ) + (port + (pt 160 96) + (output) + (text "OUT2N" (rect 0 0 36 12)(font "Arial" )) + (text "OUT2N" (rect 103 91 139 103)(font "Arial" )) + (line (pt 160 96)(pt 144 96)(line_width 1)) + ) + (port + (pt 160 112) + (output) + (text "BAUDOUTN" (rect 0 0 61 12)(font "Arial" )) + (text "BAUDOUTN" (rect 78 107 139 119)(font "Arial" )) + (line (pt 160 112)(pt 144 112)(line_width 1)) + ) + (port + (pt 160 128) + (output) + (text "RTSN" (rect 0 0 29 12)(font "Arial" )) + (text "RTSN" (rect 110 123 139 135)(font "Arial" )) + (line (pt 160 128)(pt 144 128)(line_width 1)) + ) + (port + (pt 160 144) + (output) + (text "DTRN" (rect 0 0 30 12)(font "Arial" )) + (text "DTRN" (rect 109 139 139 151)(font "Arial" )) + (line (pt 160 144)(pt 144 144)(line_width 1)) + ) + (port + (pt 160 160) + (output) + (text "SOUT" (rect 0 0 29 12)(font "Arial" )) + (text "SOUT" (rect 110 155 139 167)(font "Arial" )) + (line (pt 160 160)(pt 144 160)(line_width 1)) + ) + (drawing + (rectangle (rect 16 16 144 272)(line_width 1)) + ) +)

trunk/syn/Altera/CycloneII/uart_16750.bsf Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/syn/Altera/CycloneII/UART16750.dpf =================================================================== --- trunk/syn/Altera/CycloneII/UART16750.dpf (nonexistent) +++ trunk/syn/Altera/CycloneII/UART16750.dpf (revision 16) @@ -0,0 +1,12 @@ + + + + + + + + + + + +

trunk/syn/Altera/CycloneII/UART16750.dpf Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/syn/Altera/CycloneII/UART16750.map.summary =================================================================== --- trunk/syn/Altera/CycloneII/UART16750.map.summary (nonexistent) +++ trunk/syn/Altera/CycloneII/UART16750.map.summary (revision 16) @@ -0,0 +1,14 @@ +Analysis & Synthesis Status : Successful - Tue Feb 17 23:02:31 2009 +Quartus II Version : 8.0 Build 215 05/29/2008 SJ Full Version +Revision Name : UART16750 +Top-level Entity Name : UART16750 +Family : Cyclone II +Total logic elements : 417 + Total combinational functions : 417 + Dedicated logic registers : 293 +Total registers : 293 +Total pins : 36 +Total virtual pins : 0 +Total memory bits : 1,216 +Embedded Multiplier 9-bit elements : 0 +Total PLLs : 0

trunk/syn/Altera/CycloneII/UART16750.map.summary Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/syn/Altera/CycloneII/UART16750.sdc =================================================================== --- trunk/syn/Altera/CycloneII/UART16750.sdc (nonexistent) +++ trunk/syn/Altera/CycloneII/UART16750.sdc (revision 16) @@ -0,0 +1,73 @@ +########################################################################### +# +# Generated by : Version 8.0 Build 215 05/29/2008 SJ Full Version +# +# Project : UART16750 +# Revision : UART16750 +# +# Date : Fri Jan 16 10:46:32 Westeuropäische Normalzeit 2009 +# +########################################################################### + + +# WARNING: Expected ENABLE_CLOCK_LATENCY to be set to 'ON', but it is set to 'OFF' +# In SDC, create_generated_clock auto-generates clock latency +# +# ------------------------------------------ +# +# Create generated clocks based on PLLs +derive_pll_clocks -use_tan_name +# +# ------------------------------------------ +# WARNING: Global Fmax translated to derive_clocks. Behavior is not identical +if {![info exist ::qsta_message_posted]} { + post_message -type warning "Original Global Fmax translated from QSF using derive_clocks" + set ::qsta_message_posted 1 +} +derive_clocks -period "33 MHz" +# + + +# Original Clock Setting Name: CLK +create_clock -period "30.303 ns" \ + -name {CLK} {CLK} +# --------------------------------------------- + +# ** Clock Latency +# ------------- + +# ** Clock Uncertainty +# ----------------- + +# ** Multicycles +# ----------- +# ** Cuts +# ---- + +# ** Input/Output Delays +# ------------------- + + + + +# ** Tpd requirements +# ---------------- + +# ** Setup/Hold Relationships +# ------------------------ + +# ** Tsu/Th requirements +# ------------------- + + +# ** Tco/MinTco requirements +# ----------------------- + +# +# Entity Specific Timing Assignments found in +# the Timing Analyzer Settings report panel +# + + +# --------------------------------------------- +

trunk/syn/Altera/CycloneII/UART16750.sdc Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/syn/Altera/CycloneII/UART16750.qws =================================================================== --- trunk/syn/Altera/CycloneII/UART16750.qws (nonexistent) +++ trunk/syn/Altera/CycloneII/UART16750.qws (revision 16) @@ -0,0 +1,16 @@ +[ProjectWorkspace] +ptn_Child1=Frames +[ProjectWorkspace.Frames] +ptn_Child1=ChildFrames +[ProjectWorkspace.Frames.ChildFrames] +ptn_Child1=Document-0 +ptn_Child2=Document-1 +ptn_Child3=Document-2 +[ProjectWorkspace.Frames.ChildFrames.Document-1] +ptn_Child1=ViewFrame-0 +[ProjectWorkspace.Frames.ChildFrames.Document-1.ViewFrame-0] +DocPathName=UART16750.bdf +DocumentCLSID={7b19e8f2-2bbe-11d1-a082-0020affa5bde} +IsChildFrameDetached=False +IsActiveChildFrame=False +ptn_Child1=StateMap

trunk/syn/Altera/CycloneII/UART16750.qws Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/syn/Altera/CycloneII/UART16750.flow.rpt =================================================================== --- trunk/syn/Altera/CycloneII/UART16750.flow.rpt (nonexistent) +++ trunk/syn/Altera/CycloneII/UART16750.flow.rpt (revision 16) @@ -0,0 +1,113 @@ +Flow report for UART16750 +Tue Feb 17 23:02:41 2009 +Quartus II Version 8.0 Build 215 05/29/2008 SJ Full Version + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow Log + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-------------------------------------------------------------------------------+ +; Flow Summary ; ++------------------------------------+------------------------------------------+ +; Flow Status ; Analyzed - Tue Feb 17 23:02:41 2009 ; +; Quartus II Version ; 8.0 Build 215 05/29/2008 SJ Full Version ; +; Revision Name ; UART16750 ; +; Top-level Entity Name ; UART16750 ; +; Family ; Cyclone II ; +; Device ; EP2C5F256C6 ; +; Timing Models ; Final ; +; Met timing requirements ; Yes ; +; Total logic elements ; 448 / 4,608 ( 10 % ) ; +; Total combinational functions ; 418 / 4,608 ( 9 % ) ; +; Dedicated logic registers ; 285 / 4,608 ( 6 % ) ; +; Total registers ; 285 ; +; Total pins ; 36 / 158 ( 23 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 1,216 / 119,808 ( 1 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 26 ( 0 % ) ; +; Total PLLs ; 0 / 2 ( 0 % ) ; ++------------------------------------+------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 02/17/2009 23:02:25 ; +; Main task ; Compilation ; +; Revision Name ; UART16750 ; ++-------------------+---------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------+-------------+------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------+-------------+------------+ +; COMPILER_SIGNATURE_ID ; 18438518506.123490814503692 ; -- ; -- ; -- ; +; ENABLE_DA_RULE ; C101, C102, C103, C104, C105, C106, R101, R102, R103, R104, R105, T101, T102, A101, A102, A103, A104, A105, A106, A107, A108, A109, A110, S101, S102, S103, S104, D101, D102, D103, H101, H102, M101, M102, M103, M104, M105 ; -- ; -- ; -- ; +; ENABLE_DRC_SETTINGS ; On ; Off ; -- ; -- ; +; FMAX_REQUIREMENT ; 33.33 MHz ; -- ; -- ; -- ; +; IOBANK_VCCIO ; 3.3V ; -- ; -- ; 3 ; +; PARTITION_COLOR ; 14622752 ; -- ; -- ; Top ; +; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ; +; TCO_REQUIREMENT ; 15 ns ; -- ; -- ; -- ; +; TSU_REQUIREMENT ; 10 ns ; -- ; -- ; -- ; +; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_palace ; ++------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------+-------------+------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++-------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++-------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:05 ; 1.0 ; 182 MB ; 00:00:06 ; +; Fitter ; 00:00:04 ; 1.0 ; 190 MB ; 00:00:04 ; +; Assembler ; 00:00:01 ; 1.0 ; 146 MB ; 00:00:01 ; +; Classic Timing Analyzer ; 00:00:00 ; 1.0 ; 124 MB ; 00:00:01 ; +; Design Assistant ; 00:00:01 ; 1.0 ; 115 MB ; 00:00:01 ; +; Total ; 00:00:11 ; -- ; -- ; 00:00:13 ; ++-------------------------+--------------+-------------------------+---------------------+------------------------------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off UART16750 -c UART16750 +quartus_fit --read_settings_files=off --write_settings_files=off UART16750 -c UART16750 +quartus_asm --read_settings_files=off --write_settings_files=off UART16750 -c UART16750 +quartus_tan --read_settings_files=off --write_settings_files=off UART16750 -c UART16750 --timing_analysis_only +quartus_drc --read_settings_files=off --write_settings_files=off UART16750 -c UART16750 + + +

trunk/syn/Altera/CycloneII/UART16750.flow.rpt Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/syn/Altera/CycloneII/UART16750.drc.rpt =================================================================== --- trunk/syn/Altera/CycloneII/UART16750.drc.rpt (nonexistent) +++ trunk/syn/Altera/CycloneII/UART16750.drc.rpt (revision 16) @@ -0,0 +1,216 @@ +Design Assistant report for UART16750 +Tue Feb 17 23:02:41 2009 +Quartus II Version 8.0 Build 215 05/29/2008 SJ Full Version + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Design Assistant Summary + 3. Design Assistant Settings + 4. Information only Violations + 5. Design Assistant Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-------------------------------------------------------------------------+ +; Design Assistant Summary ; ++-----------------------------------+-------------------------------------+ +; Design Assistant Status ; Analyzed - Tue Feb 17 23:02:41 2009 ; +; Revision Name ; UART16750 ; +; Top-level Entity Name ; UART16750 ; +; Family ; Cyclone II ; +; Total Critical Violations ; 0 ; +; Total High Violations ; 0 ; +; Total Medium Violations ; 0 ; +; Total Information only Violations ; 55 ; ++-----------------------------------+-------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Design Assistant Settings ; ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+----+ +; Option ; Setting ; To ; ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+----+ +; Design Assistant mode ; Post-Fitting ; ; +; Threshold value for clock net not mapped to clock spines rule ; 25 ; ; +; Minimum number of clock port feed by gated clocks ; 30 ; ; +; Minimum number of node fan-out ; 30 ; ; +; Maximum number of nodes to report ; 50 ; ; +; Rule C101: Gated clock should be implemented according to the Altera standard scheme ; On ; ; +; Rule C102: Logic cell should not be used to generate inverted clock ; On ; ; +; Rule C103: Gated clock is not feeding at least a pre-defined number of clock port to effectively save power ; On ; ; +; Rule C104: Clock signal source should drive only input clock ports ; On ; ; +; Rule C105: Clock signal should be a global signal (Rule applies during post-fitting analysis. This rule applies during both post-fitting analysis and post-synthesis analysis if the design targets a MAX 3000 or MAX 7000 device. For more information, see the Help for the rule.) ; On ; ; +; Rule C106: Clock signal source should not drive registers that are triggered by different clock edges ; On ; ; +; Rule R101: Combinational logic used as a reset signal should be synchronized ; On ; ; +; Rule R102: External reset should be synchronized using two cascaded registers ; On ; ; +; Rule R103: External reset should be correctly synchronized ; On ; ; +; Rule R104: The reset signal that is generated in one clock domain and is used in the other clock domain, should be correctly synchronized ; On ; ; +; Rule R105: The reset signal that is generated in one clock domain and is used in the other clock domain, should be synchronized ; On ; ; +; Rule T101: Nodes with more than the specified number of fan-outs ; On ; ; +; Rule T102: Top nodes with the highest number of fan-outs ; On ; ; +; Rule A101: Design should not contain combinational loops ; On ; ; +; Rule A102: Register output should not drive its own control signal directly or through combinational logic ; On ; ; +; Rule A103: Design should not contain delay chains ; On ; ; +; Rule A104: Design should not contain ripple clock structures ; On ; ; +; Rule A105: Pulses should not be implemented asynchronously ; On ; ; +; Rule A106: Multiple pulses should not be generated in design ; On ; ; +; Rule A107: Design should not contain SR latches ; On ; ; +; Rule A108: Design should not contain latches ; On ; ; +; Rule A109: Combinational logic should not directly drive write enable signal of asynchronous RAM ; On ; ; +; Rule A110: Design should not contain asynchronous memory ; On ; ; +; Rule S101: Output enable and input of the same tri-state node should not be driven by same signal source ; On ; ; +; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source ; On ; ; +; Rule S103: More than one asynchronous signal port of the same register should not be driven by the same signal source ; On ; ; +; Rule S104: Clock port and any other signal port of same register should not be driven by the same signal source ; On ; ; +; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains ; On ; ; +; Rule D102: Multiple data bits that are transferred across asynchronous clock domains are synchronized, but not all bits may be aligned in the receiving clock domain ; On ; ; +; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains ; On ; ; +; Rule H101: Only one VREF pin should be assigned to the HardCopy test pin in an I/O bank (Rule does not apply to all HardCopy and HardCopy Stratix devices. This rule is used to analyze a design only when the rule applies to the design's target HardCopy or HardCopy Stratix device.) ; On ; ; +; Rule H102: PLL clock output drives multiple clock network types (Rule does not apply to all HardCopy and HardCopy Stratix devices. This rule is used to analyze a design only when the rule applies to the design's target HardCopy or HardCopy Stratix device.) ; On ; ; +; Rule M101: Data bits are not synchronized when transferred to the state machine of asynchronous clock domains ; On ; ; +; Rule M102: No reset signal defined to initialize the state machine ; On ; ; +; Rule M103: State machine should not contain an unreachable state ; On ; ; +; Rule M104: State machine should not contain a deadlock state ; On ; ; +; Rule M105: State machine should not contain a dead transition ; On ; ; ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+----+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Information only Violations ; ++------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------+---------+ +; Rule name ; Name ; Fan-Out ; ++------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------+---------+ +; Rule T101: Nodes with more than the specified number of fan-outs ; CLK~clkctrl ; 288 ; +; Rule T101: Nodes with more than the specified number of fan-outs ; inst1~clkctrl ; 224 ; +; Rule T101: Nodes with more than the specified number of fan-outs ; ~GND ; 34 ; +; Rule T101: Nodes with more than the specified number of fan-outs ; uart_16750:inst|iRXFIFOClear ; 41 ; +; Rule T101: Nodes with more than the specified number of fan-outs ; uart_16750:inst|iFCR_TXFIFOReset ; 33 ; +; Rule T102: Top nodes with the highest number of fan-outs ; CLK~clkctrl ; 288 ; +; Rule T102: Top nodes with the highest number of fan-outs ; inst1~clkctrl ; 224 ; +; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iRXFIFOClear ; 41 ; +; Rule T102: Top nodes with the highest number of fan-outs ; ~GND ; 34 ; +; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iFCR_TXFIFOReset ; 33 ; +; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|empty_dff ; 22 ; +; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|empty_dff ; 17 ; +; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|uart_baudgen:UART_BG16|Equal0~179 ; 17 ; +; Rule T102: Top nodes with the highest number of fan-outs ; A[1] ; 15 ; +; Rule T102: Top nodes with the highest number of fan-outs ; A[0] ; 15 ; +; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|Mux0~160 ; 14 ; +; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|slib_clock_div:UART_BG2|iQ ; 14 ; +; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iQ ; 14 ; +; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iFCR_FIFOEnable ; 13 ; +; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iRXFIFORead~50 ; 13 ; +; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|uart_receiver:UART_RX|iDataCountInit ; 12 ; +; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|State~57 ; 12 ; +; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iLCR[7] ; 12 ; +; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iA[1] ; 12 ; +; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|uart_receiver:UART_RX|slib_counter:RX_BRC|iCounter[4] ; 12 ; +; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|Mux5~105 ; 12 ; +; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|valid_wreq ; 12 ; +; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iMCR[4] ; 11 ; +; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|uart_receiver:UART_RX|CState.idle ; 11 ; +; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|uart_receiver:UART_RX|iDataCount[0] ; 11 ; +; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|valid_rreq ; 11 ; +; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|uart_receiver:UART_RX|iDataCount[1] ; 11 ; +; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|valid_wreq~186 ; 11 ; +; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|valid_rreq ; 10 ; +; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iLCR[1] ; 10 ; +; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|uart_receiver:UART_RX|iDataCount[2] ; 10 ; +; Rule T102: Top nodes with the highest number of fan-outs ; A[2] ; 10 ; +; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iDIN[0] ; 10 ; +; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iA[0] ; 10 ; +; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iTXFIFORead ; 10 ; +; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iDIN[1] ; 9 ; +; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iLCR[0] ; 9 ; +; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|uart_transmitter:UART_TX|CState~1612 ; 9 ; +; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|uart_receiver:UART_RX|RX_DATACOUNT~0 ; 9 ; +; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iSCRWrite~35 ; 8 ; +; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iDIN[2] ; 8 ; +; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|Mux5~104 ; 8 ; +; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iDLLWrite~31 ; 8 ; +; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iLCRWrite~28 ; 8 ; +; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iDLMWrite~32 ; 8 ; +; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|full_dff ; 8 ; +; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iRXFIFOWrite ; 8 ; +; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iDIN[5] ; 7 ; +; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iA[2] ; 7 ; +; Rule T102: Top nodes with the highest number of fan-outs ; uart_16750:inst|iLCR[3] ; 7 ; ++------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------+---------+ + + ++---------------------------+ +; Design Assistant Messages ; ++---------------------------+ +Info: ******************************************************************* +Info: Running Quartus II Design Assistant + Info: Version 8.0 Build 215 05/29/2008 SJ Full Version + Info: Processing started: Tue Feb 17 23:02:40 2009 +Info: Command: quartus_drc --read_settings_files=off --write_settings_files=off UART16750 -c UART16750 +Info: (Information) Rule T101: Nodes with more than the specified number of fan-outs. (Value defined:30). Found 5 node(s) with highest fan-out. + Info: Node "CLK~clkctrl" has 288 fan-out(s) + Info: Node "inst1~clkctrl" has 224 fan-out(s) + Info: Node "~GND" has 34 fan-out(s) + Info: Node "uart_16750:inst|iRXFIFOClear" has 41 fan-out(s) + Info: Node "uart_16750:inst|iFCR_TXFIFOReset" has 33 fan-out(s) +Info: (Information) Rule T102: Top nodes with the highest number of fan-outs. (Value defined:50). Found 50 node(s) with highest fan-out. + Info: Node "CLK~clkctrl" has 288 fan-out(s) + Info: Node "inst1~clkctrl" has 224 fan-out(s) + Info: Node "uart_16750:inst|iRXFIFOClear" has 41 fan-out(s) + Info: Node "~GND" has 34 fan-out(s) + Info: Node "uart_16750:inst|iFCR_TXFIFOReset" has 33 fan-out(s) + Info: Node "uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|empty_dff" has 22 fan-out(s) + Info: Node "uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|empty_dff" has 17 fan-out(s) + Info: Node "uart_16750:inst|uart_baudgen:UART_BG16|Equal0~179" has 17 fan-out(s) + Info: Node "A[1]" has 15 fan-out(s) + Info: Node "A[0]" has 15 fan-out(s) + Info: Node "uart_16750:inst|Mux0~160" has 14 fan-out(s) + Info: Node "uart_16750:inst|slib_clock_div:UART_BG2|iQ" has 14 fan-out(s) + Info: Node "uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iQ" has 14 fan-out(s) + Info: Node "uart_16750:inst|iFCR_FIFOEnable" has 13 fan-out(s) + Info: Node "uart_16750:inst|iRXFIFORead~50" has 13 fan-out(s) + Info: Node "uart_16750:inst|uart_receiver:UART_RX|iDataCountInit" has 12 fan-out(s) + Info: Node "uart_16750:inst|State~57" has 12 fan-out(s) + Info: Node "uart_16750:inst|iLCR[7]" has 12 fan-out(s) + Info: Node "uart_16750:inst|iA[1]" has 12 fan-out(s) + Info: Node "uart_16750:inst|uart_receiver:UART_RX|slib_counter:RX_BRC|iCounter[4]" has 12 fan-out(s) + Info: Node "uart_16750:inst|Mux5~105" has 12 fan-out(s) + Info: Node "uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|valid_wreq" has 12 fan-out(s) + Info: Node "uart_16750:inst|iMCR[4]" has 11 fan-out(s) + Info: Node "uart_16750:inst|uart_receiver:UART_RX|CState.idle" has 11 fan-out(s) + Info: Node "uart_16750:inst|uart_receiver:UART_RX|iDataCount[0]" has 11 fan-out(s) + Info: Node "uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|valid_rreq" has 11 fan-out(s) + Info: Node "uart_16750:inst|uart_receiver:UART_RX|iDataCount[1]" has 11 fan-out(s) + Info: Node "uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|valid_wreq~186" has 11 fan-out(s) + Info: Node "uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|valid_rreq" has 10 fan-out(s) + Info: Node "uart_16750:inst|iLCR[1]" has 10 fan-out(s) + Info: Truncated list of Design Assistant messages to 30 messages. Go to sections under Design Assistant section of Compilation Report for complete lists of Design Assistant messages generated. +Info: Design Assistant information: finished post-fitting analysis of current design -- generated 55 information messages and 0 warning messages +Info: Quartus II Design Assistant was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 115 megabytes + Info: Processing ended: Tue Feb 17 23:02:41 2009 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:01 + +

trunk/syn/Altera/CycloneII/UART16750.drc.rpt Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/syn/Altera/CycloneII/UART16750.tan.summary =================================================================== --- trunk/syn/Altera/CycloneII/UART16750.tan.summary (nonexistent) +++ trunk/syn/Altera/CycloneII/UART16750.tan.summary (revision 16) @@ -0,0 +1,76 @@ +-------------------------------------------------------------------------------------- +Timing Analyzer Summary +-------------------------------------------------------------------------------------- + +Type : Worst-case tsu +Slack : 2.580 ns +Required Time : 10.000 ns +Actual Time : 7.420 ns +From : WR +To : uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|empty_dff +From Clock : -- +To Clock : CLK +Failed Paths : 0 + +Type : Worst-case tco +Slack : 2.856 ns +Required Time : 15.000 ns +Actual Time : 12.144 ns +From : uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg5 +To : DOUT[3] +From Clock : CLK +To Clock : -- +Failed Paths : 0 + +Type : Worst-case tpd +Slack : N/A +Required Time : None +Actual Time : 14.563 ns +From : A[1] +To : DOUT[3] +From Clock : -- +To Clock : -- +Failed Paths : 0 + +Type : Worst-case th +Slack : N/A +Required Time : None +Actual Time : -2.602 ns +From : WR +To : uart_16750:inst|slib_edge_detect:UART_ED_WRITE|iDd +From Clock : -- +To Clock : CLK +Failed Paths : 0 + +Type : Clock Setup: 'CLK' +Slack : 22.036 ns +Required Time : 33.33 MHz ( period = 30.003 ns ) +Actual Time : 125.52 MHz ( period = 7.967 ns ) +From : uart_16750:inst|iTSR[3] +To : uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4] +From Clock : CLK +To Clock : CLK +Failed Paths : 0 + +Type : Clock Hold: 'CLK' +Slack : 0.391 ns +Required Time : 33.33 MHz ( period = 30.003 ns ) +Actual Time : N/A +From : uart_16750:inst|iLSR_FIFOERR +To : uart_16750:inst|iLSR_FIFOERR +From Clock : CLK +To Clock : CLK +Failed Paths : 0 + +Type : Total number of failed paths +Slack : +Required Time : +Actual Time : +From : +To : +From Clock : +To Clock : +Failed Paths : 0 + +-------------------------------------------------------------------------------------- +

trunk/syn/Altera/CycloneII/UART16750.tan.summary Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/syn/Altera/CycloneII/UART16750.fit.summary =================================================================== --- trunk/syn/Altera/CycloneII/UART16750.fit.summary (nonexistent) +++ trunk/syn/Altera/CycloneII/UART16750.fit.summary (revision 16) @@ -0,0 +1,16 @@ +Fitter Status : Successful - Tue Feb 17 23:02:36 2009 +Quartus II Version : 8.0 Build 215 05/29/2008 SJ Full Version +Revision Name : UART16750 +Top-level Entity Name : UART16750 +Family : Cyclone II +Device : EP2C5F256C6 +Timing Models : Final +Total logic elements : 448 / 4,608 ( 10 % ) + Total combinational functions : 418 / 4,608 ( 9 % ) + Dedicated logic registers : 285 / 4,608 ( 6 % ) +Total registers : 285 +Total pins : 36 / 158 ( 23 % ) +Total virtual pins : 0 +Total memory bits : 1,216 / 119,808 ( 1 % ) +Embedded Multiplier 9-bit elements : 0 / 26 ( 0 % ) +Total PLLs : 0 / 2 ( 0 % )

trunk/syn/Altera/CycloneII/UART16750.fit.summary Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/syn/Altera/CycloneII/UART16750.map.rpt =================================================================== --- trunk/syn/Altera/CycloneII/UART16750.map.rpt (nonexistent) +++ trunk/syn/Altera/CycloneII/UART16750.map.rpt (revision 16) @@ -0,0 +1,769 @@ +Analysis & Synthesis report for UART16750 +Tue Feb 17 23:02:31 2009 +Quartus II Version 8.0 Build 215 05/29/2008 SJ Full Version + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Analysis & Synthesis Source Files Read + 5. Analysis & Synthesis Resource Usage Summary + 6. Analysis & Synthesis Resource Utilization by Entity + 7. Analysis & Synthesis RAM Summary + 8. State Machine - |UART16750|uart_16750:inst|\UART_TXPROC:State + 9. State Machine - |UART16750|uart_16750:inst|uart_receiver:UART_RX|CState + 10. State Machine - |UART16750|uart_16750:inst|uart_transmitter:UART_TX|CState + 11. General Register Statistics + 12. Inverted Register Statistics + 13. Multiplexer Restructuring Statistics (Restructuring Performed) + 14. Source assignments for uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|altsyncram_t681:FIFOram + 15. Source assignments for uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram + 16. Parameter Settings for User Entity Instance: uart_16750:inst|slib_input_filter:UART_IF_CTS + 17. Parameter Settings for User Entity Instance: uart_16750:inst|slib_input_filter:UART_IF_DSR + 18. Parameter Settings for User Entity Instance: uart_16750:inst|slib_input_filter:UART_IF_DCD + 19. Parameter Settings for User Entity Instance: uart_16750:inst|slib_input_filter:UART_IF_RI + 20. Parameter Settings for User Entity Instance: uart_16750:inst|slib_clock_div:UART_BG2 + 21. Parameter Settings for User Entity Instance: uart_16750:inst|slib_fifo:UART_TXFF + 22. Parameter Settings for User Entity Instance: uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component + 23. Parameter Settings for User Entity Instance: uart_16750:inst|slib_fifo:UART_RXFF + 24. Parameter Settings for User Entity Instance: uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component + 25. Parameter Settings for User Entity Instance: uart_16750:inst|uart_receiver:UART_RX|slib_counter:RX_BRC + 26. Parameter Settings for User Entity Instance: uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF + 27. Parameter Settings for User Entity Instance: slib_clock_div:inst2 + 28. scfifo Parameter Settings by Entity Instance + 29. Analysis & Synthesis Messages + 30. Analysis & Synthesis Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++------------------------------------+------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Tue Feb 17 23:02:31 2009 ; +; Quartus II Version ; 8.0 Build 215 05/29/2008 SJ Full Version ; +; Revision Name ; UART16750 ; +; Top-level Entity Name ; UART16750 ; +; Family ; Cyclone II ; +; Total logic elements ; 417 ; +; Total combinational functions ; 417 ; +; Dedicated logic registers ; 293 ; +; Total registers ; 293 ; +; Total pins ; 36 ; +; Total virtual pins ; 0 ; +; Total memory bits ; 1,216 ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Total PLLs ; 0 ; ++------------------------------------+------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++--------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++--------------------------------------------------------------+--------------------+--------------------+ +; Device ; EP2C5F256C6 ; ; +; Top-level entity name ; UART16750 ; UART16750 ; +; Family name ; Cyclone II ; Stratix II ; +; Use Generated Physical Constraints File ; Off ; ; +; Use smart compilation ; Off ; Off ; +; Maximum processors allowed for parallel compilation ; 1 ; 1 ; +; Restructure Multiplexers ; Auto ; Auto ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; Disable OpenCore Plus hardware evaluation ; Off ; Off ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL93 ; VHDL93 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Parallel Synthesis ; Off ; Off ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Perform gate-level register retiming ; Off ; Off ; +; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto RAM to Logic Cell Conversion ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Show Parameter Settings Tables in Synthesis Report ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 2 ; 2 ; +; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Block Design Naming ; Auto ; Auto ; +; SDC constraint protection ; Off ; Off ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; ++--------------------------------------------------------------+--------------------+--------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++------------------------------------------+-----------------+------------------------------------+------------------------------------------------------------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; ++------------------------------------------+-----------------+------------------------------------+------------------------------------------------------------+ +; ../../../rtl/vhdl/uart_transmitter.vhd ; yes ; User VHDL File ; R:/uart16750/rtl/vhdl/uart_transmitter.vhd ; +; ../../../rtl/vhdl/slib_clock_div.vhd ; yes ; User VHDL File ; R:/uart16750/rtl/vhdl/slib_clock_div.vhd ; +; ../../../rtl/vhdl/slib_counter.vhd ; yes ; User VHDL File ; R:/uart16750/rtl/vhdl/slib_counter.vhd ; +; ../../../rtl/vhdl/slib_edge_detect.vhd ; yes ; User VHDL File ; R:/uart16750/rtl/vhdl/slib_edge_detect.vhd ; +; ../../../rtl/vhdl/slib_fifo_cyclone2.vhd ; yes ; User VHDL File ; R:/uart16750/rtl/vhdl/slib_fifo_cyclone2.vhd ; +; ../../../rtl/vhdl/slib_input_filter.vhd ; yes ; User VHDL File ; R:/uart16750/rtl/vhdl/slib_input_filter.vhd ; +; ../../../rtl/vhdl/slib_input_sync.vhd ; yes ; User VHDL File ; R:/uart16750/rtl/vhdl/slib_input_sync.vhd ; +; ../../../rtl/vhdl/slib_mv_filter.vhd ; yes ; User VHDL File ; R:/uart16750/rtl/vhdl/slib_mv_filter.vhd ; +; ../../../rtl/vhdl/uart_16750.vhd ; yes ; User VHDL File ; R:/uart16750/rtl/vhdl/uart_16750.vhd ; +; ../../../rtl/vhdl/uart_baudgen.vhd ; yes ; User VHDL File ; R:/uart16750/rtl/vhdl/uart_baudgen.vhd ; +; ../../../rtl/vhdl/uart_interrupt.vhd ; yes ; User VHDL File ; R:/uart16750/rtl/vhdl/uart_interrupt.vhd ; +; ../../../rtl/vhdl/uart_receiver.vhd ; yes ; User VHDL File ; R:/uart16750/rtl/vhdl/uart_receiver.vhd ; +; UART16750.bdf ; yes ; User Block Diagram/Schematic File ; R:/uart16750/syn/Altera/CycloneII/UART16750.bdf ; +; scfifo.tdf ; yes ; Megafunction ; r:/altera/80/quartus/libraries/megafunctions/scfifo.tdf ; +; a_regfifo.inc ; yes ; Megafunction ; r:/altera/80/quartus/libraries/megafunctions/a_regfifo.inc ; +; a_dpfifo.inc ; yes ; Megafunction ; r:/altera/80/quartus/libraries/megafunctions/a_dpfifo.inc ; +; a_i2fifo.inc ; yes ; Megafunction ; r:/altera/80/quartus/libraries/megafunctions/a_i2fifo.inc ; +; a_fffifo.inc ; yes ; Megafunction ; r:/altera/80/quartus/libraries/megafunctions/a_fffifo.inc ; +; a_f2fifo.inc ; yes ; Megafunction ; r:/altera/80/quartus/libraries/megafunctions/a_f2fifo.inc ; +; aglobal80.inc ; yes ; Megafunction ; r:/altera/80/quartus/libraries/megafunctions/aglobal80.inc ; +; db/scfifo_an31.tdf ; yes ; Auto-Generated Megafunction ; R:/uart16750/syn/Altera/CycloneII/db/scfifo_an31.tdf ; +; db/a_dpfifo_te31.tdf ; yes ; Auto-Generated Megafunction ; R:/uart16750/syn/Altera/CycloneII/db/a_dpfifo_te31.tdf ; +; db/altsyncram_t681.tdf ; yes ; Auto-Generated Megafunction ; R:/uart16750/syn/Altera/CycloneII/db/altsyncram_t681.tdf ; +; db/cntr_c5b.tdf ; yes ; Auto-Generated Megafunction ; R:/uart16750/syn/Altera/CycloneII/db/cntr_c5b.tdf ; +; db/cntr_p57.tdf ; yes ; Auto-Generated Megafunction ; R:/uart16750/syn/Altera/CycloneII/db/cntr_p57.tdf ; +; db/cntr_d5b.tdf ; yes ; Auto-Generated Megafunction ; R:/uart16750/syn/Altera/CycloneII/db/cntr_d5b.tdf ; +; db/scfifo_ko31.tdf ; yes ; Auto-Generated Megafunction ; R:/uart16750/syn/Altera/CycloneII/db/scfifo_ko31.tdf ; +; db/a_dpfifo_7g31.tdf ; yes ; Auto-Generated Megafunction ; R:/uart16750/syn/Altera/CycloneII/db/a_dpfifo_7g31.tdf ; +; db/altsyncram_h981.tdf ; yes ; Auto-Generated Megafunction ; R:/uart16750/syn/Altera/CycloneII/db/altsyncram_h981.tdf ; ++------------------------------------------+-----------------+------------------------------------+------------------------------------------------------------+ + + ++-----------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+-------+ +; Resource ; Usage ; ++---------------------------------------------+-------+ +; Estimated Total logic elements ; 417 ; +; ; ; +; Total combinational functions ; 417 ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 223 ; +; -- 3 input functions ; 72 ; +; -- <=2 input functions ; 122 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 348 ; +; -- arithmetic mode ; 69 ; +; ; ; +; Total registers ; 293 ; +; -- Dedicated logic registers ; 293 ; +; -- I/O registers ; 0 ; +; ; ; +; I/O pins ; 36 ; +; Total memory bits ; 1216 ; +; Maximum fan-out node ; CLK ; +; Maximum fan-out ; 312 ; +; Total fan-out ; 2682 ; +; Average fan-out ; 3.51 ; ++---------------------------------------------+-------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++---------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ +; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ; ++---------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ +; |UART16750 ; 417 (1) ; 293 (3) ; 1216 ; 0 ; 0 ; 0 ; 36 ; 0 ; |UART16750 ; work ; +; |slib_clock_div:inst2| ; 9 (9) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|slib_clock_div:inst2 ; work ; +; |uart_16750:inst| ; 407 (150) ; 284 (120) ; 1216 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst ; work ; +; |slib_clock_div:UART_BG2| ; 4 (4) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_clock_div:UART_BG2 ; work ; +; |slib_edge_detect:UART_BIDET| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_edge_detect:UART_BIDET ; work ; +; |slib_edge_detect:UART_ED_CTS| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_edge_detect:UART_ED_CTS ; work ; +; |slib_edge_detect:UART_ED_DCD| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_edge_detect:UART_ED_DCD ; work ; +; |slib_edge_detect:UART_ED_DSR| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_edge_detect:UART_ED_DSR ; work ; +; |slib_edge_detect:UART_ED_READ| ; 1 (1) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_edge_detect:UART_ED_READ ; work ; +; |slib_edge_detect:UART_ED_RI| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_edge_detect:UART_ED_RI ; work ; +; |slib_edge_detect:UART_ED_WRITE| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_edge_detect:UART_ED_WRITE ; work ; +; |slib_edge_detect:UART_FEDET| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_edge_detect:UART_FEDET ; work ; +; |slib_edge_detect:UART_IIC_THRE_ED| ; 1 (1) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_edge_detect:UART_IIC_THRE_ED ; work ; +; |slib_edge_detect:UART_PEDET| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_edge_detect:UART_PEDET ; work ; +; |slib_edge_detect:UART_RCLK| ; 1 (1) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_edge_detect:UART_RCLK ; work ; +; |slib_fifo:UART_RXFF| ; 49 (0) ; 29 (0) ; 704 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_fifo:UART_RXFF ; work ; +; |scfifo:scfifo_component| ; 49 (0) ; 29 (0) ; 704 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component ; work ; +; |scfifo_ko31:auto_generated| ; 49 (0) ; 29 (0) ; 704 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated ; work ; +; |a_dpfifo_7g31:dpfifo| ; 49 (29) ; 29 (12) ; 704 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo ; work ; +; |altsyncram_h981:FIFOram| ; 0 (0) ; 0 (0) ; 704 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram ; work ; +; |cntr_c5b:rd_ptr_msb| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_c5b:rd_ptr_msb ; work ; +; |cntr_d5b:wr_ptr| ; 7 (7) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_d5b:wr_ptr ; work ; +; |cntr_p57:usedw_counter| ; 7 (7) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_p57:usedw_counter ; work ; +; |slib_fifo:UART_TXFF| ; 50 (0) ; 29 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_fifo:UART_TXFF ; work ; +; |scfifo:scfifo_component| ; 50 (0) ; 29 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component ; work ; +; |scfifo_an31:auto_generated| ; 50 (0) ; 29 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated ; work ; +; |a_dpfifo_te31:dpfifo| ; 50 (30) ; 29 (12) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo ; work ; +; |altsyncram_t681:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|altsyncram_t681:FIFOram ; work ; +; |cntr_c5b:rd_ptr_msb| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_c5b:rd_ptr_msb ; work ; +; |cntr_d5b:wr_ptr| ; 7 (7) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_d5b:wr_ptr ; work ; +; |cntr_p57:usedw_counter| ; 7 (7) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_p57:usedw_counter ; work ; +; |slib_input_filter:UART_IF_CTS| ; 3 (3) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_input_filter:UART_IF_CTS ; work ; +; |slib_input_filter:UART_IF_DCD| ; 3 (3) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_input_filter:UART_IF_DCD ; work ; +; |slib_input_filter:UART_IF_DSR| ; 3 (3) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_input_filter:UART_IF_DSR ; work ; +; |slib_input_filter:UART_IF_RI| ; 3 (3) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_input_filter:UART_IF_RI ; work ; +; |slib_input_sync:UART_IS_CTS| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_input_sync:UART_IS_CTS ; work ; +; |slib_input_sync:UART_IS_DCD| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_input_sync:UART_IS_DCD ; work ; +; |slib_input_sync:UART_IS_DSR| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_input_sync:UART_IS_DSR ; work ; +; |slib_input_sync:UART_IS_RI| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_input_sync:UART_IS_RI ; work ; +; |slib_input_sync:UART_IS_SIN| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|slib_input_sync:UART_IS_SIN ; work ; +; |uart_baudgen:UART_BG16| ; 27 (27) ; 17 (17) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|uart_baudgen:UART_BG16 ; work ; +; |uart_interrupt:UART_IIC| ; 12 (12) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|uart_interrupt:UART_IIC ; work ; +; |uart_receiver:UART_RX| ; 66 (47) ; 32 (21) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|uart_receiver:UART_RX ; work ; +; |slib_counter:RX_BRC| ; 10 (10) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|uart_receiver:UART_RX|slib_counter:RX_BRC ; work ; +; |slib_mv_filter:RX_MVF| ; 9 (9) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF ; work ; +; |uart_transmitter:UART_TX| ; 34 (34) ; 16 (16) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |UART16750|uart_16750:inst|uart_transmitter:UART_TX ; work ; ++---------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis RAM Summary ; ++------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+ +; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ; ++------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+ +; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 64 ; 11 ; 64 ; 11 ; 704 ; None ; +; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|altsyncram_t681:FIFOram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 64 ; 8 ; 64 ; 8 ; 512 ; None ; ++------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+ + + +Encoding Type: One-Hot ++-----------------------------------------------------------------------------------------------------------------------------------------+ +; State Machine - |UART16750|uart_16750:inst|\UART_TXPROC:State ; ++----------------------------+--------------------------+--------------------------+----------------------------+-------------------------+ +; Name ; \UART_TXPROC:State.txend ; \UART_TXPROC:State.txrun ; \UART_TXPROC:State.txstart ; \UART_TXPROC:State.idle ; ++----------------------------+--------------------------+--------------------------+----------------------------+-------------------------+ +; \UART_TXPROC:State.idle ; 0 ; 0 ; 0 ; 0 ; +; \UART_TXPROC:State.txstart ; 0 ; 0 ; 1 ; 1 ; +; \UART_TXPROC:State.txrun ; 0 ; 1 ; 0 ; 1 ; +; \UART_TXPROC:State.txend ; 1 ; 0 ; 0 ; 1 ; ++----------------------------+--------------------------+--------------------------+----------------------------+-------------------------+ + + +Encoding Type: One-Hot ++---------------------------------------------------------------------------------------------------+ +; State Machine - |UART16750|uart_16750:inst|uart_receiver:UART_RX|CState ; ++--------------+--------------+-------------+------------+-------------+--------------+-------------+ +; Name ; CState.mwait ; CState.stop ; CState.par ; CState.data ; CState.start ; CState.idle ; ++--------------+--------------+-------------+------------+-------------+--------------+-------------+ +; CState.idle ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; CState.start ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ; +; CState.data ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ; +; CState.par ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ; +; CState.stop ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ; +; CState.mwait ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ; ++--------------+--------------+-------------+------------+-------------+--------------+-------------+ + + +Encoding Type: One-Hot ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; State Machine - |UART16750|uart_16750:inst|uart_transmitter:UART_TX|CState ; ++--------------+--------------+-------------+------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+--------------+-------------+ +; Name ; CState.stop2 ; CState.stop ; CState.par ; CState.bit7 ; CState.bit6 ; CState.bit5 ; CState.bit4 ; CState.bit3 ; CState.bit2 ; CState.bit1 ; CState.bit0 ; CState.start ; CState.idle ; ++--------------+--------------+-------------+------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+--------------+-------------+ +; CState.idle ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; CState.start ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ; +; CState.bit0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ; +; CState.bit1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ; +; CState.bit2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ; +; CState.bit3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CState.bit4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CState.bit5 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CState.bit6 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CState.bit7 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CState.par ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CState.stop ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CState.stop2 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; ++--------------+--------------+-------------+------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+--------------+-------------+ + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 293 ; +; Number of registers using Synchronous Clear ; 42 ; +; Number of registers using Synchronous Load ; 34 ; +; Number of registers using Asynchronous Clear ; 232 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 120 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++-----------------------------------------------------------+ +; Inverted Register Statistics ; ++-------------------------------------------------+---------+ +; Inverted Register ; Fan out ; ++-------------------------------------------------+---------+ +; uart_16750:inst|uart_interrupt:UART_IIC|iIIR[0] ; 2 ; +; Total number of inverted registers = 1 ; ; ++-------------------------------------------------+---------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Multiplexer Restructuring Statistics (Restructuring Performed) ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------+ +; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------+ +; 3:1 ; 2 bits ; 4 LEs ; 0 LEs ; 4 LEs ; Yes ; |UART16750|uart_16750:inst|slib_input_filter:UART_IF_DCD|iCount[1] ; +; 3:1 ; 2 bits ; 4 LEs ; 0 LEs ; 4 LEs ; Yes ; |UART16750|uart_16750:inst|slib_input_filter:UART_IF_RI|iCount[0] ; +; 3:1 ; 2 bits ; 4 LEs ; 0 LEs ; 4 LEs ; Yes ; |UART16750|uart_16750:inst|slib_input_filter:UART_IF_DSR|iCount[1] ; +; 3:1 ; 2 bits ; 4 LEs ; 0 LEs ; 4 LEs ; Yes ; |UART16750|uart_16750:inst|slib_input_filter:UART_IF_CTS|iCount[1] ; +; 3:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |UART16750|uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[3] ; +; 3:1 ; 7 bits ; 14 LEs ; 7 LEs ; 7 LEs ; Yes ; |UART16750|uart_16750:inst|iFECounter[5] ; +; 4:1 ; 6 bits ; 12 LEs ; 6 LEs ; 6 LEs ; No ; |UART16750|uart_16750:inst|uart_transmitter:UART_TX|CState~29 ; +; 10:1 ; 2 bits ; 12 LEs ; 12 LEs ; 0 LEs ; No ; |UART16750|uart_16750:inst|Mux0 ; +; 10:1 ; 4 bits ; 24 LEs ; 24 LEs ; 0 LEs ; No ; |UART16750|uart_16750:inst|Mux5 ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|altsyncram_t681:FIFOram ; ++---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------+ +; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; ++---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram ; ++---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------+ +; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; ++---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: uart_16750:inst|slib_input_filter:UART_IF_CTS ; ++----------------+-------+-------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-------------------------------------------------------------------+ +; size ; 2 ; Signed Integer ; ++----------------+-------+-------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: uart_16750:inst|slib_input_filter:UART_IF_DSR ; ++----------------+-------+-------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-------------------------------------------------------------------+ +; size ; 2 ; Signed Integer ; ++----------------+-------+-------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: uart_16750:inst|slib_input_filter:UART_IF_DCD ; ++----------------+-------+-------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-------------------------------------------------------------------+ +; size ; 2 ; Signed Integer ; ++----------------+-------+-------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: uart_16750:inst|slib_input_filter:UART_IF_RI ; ++----------------+-------+------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+------------------------------------------------------------------+ +; size ; 2 ; Signed Integer ; ++----------------+-------+------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: uart_16750:inst|slib_clock_div:UART_BG2 ; ++----------------+-------+-------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-------------------------------------------------------------+ +; ratio ; 8 ; Signed Integer ; ++----------------+-------+-------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++----------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: uart_16750:inst|slib_fifo:UART_TXFF ; ++----------------+-------+---------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+---------------------------------------------------------+ +; width ; 8 ; Signed Integer ; +; size_e ; 6 ; Signed Integer ; ++----------------+-------+---------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++----------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component ; ++-------------------------+-------------+------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++-------------------------+-------------+------------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; lpm_width ; 8 ; Signed Integer ; +; LPM_NUMWORDS ; 64 ; Signed Integer ; +; LPM_WIDTHU ; 6 ; Signed Integer ; +; LPM_SHOWAHEAD ; ON ; Untyped ; +; UNDERFLOW_CHECKING ; ON ; Untyped ; +; OVERFLOW_CHECKING ; ON ; Untyped ; +; ALLOW_RWCYCLE_WHEN_FULL ; OFF ; Untyped ; +; ADD_RAM_OUTPUT_REGISTER ; OFF ; Untyped ; +; ALMOST_FULL_VALUE ; 0 ; Untyped ; +; ALMOST_EMPTY_VALUE ; 0 ; Untyped ; +; USE_EAB ; ON ; Untyped ; +; MAXIMIZE_SPEED ; 5 ; Untyped ; +; DEVICE_FAMILY ; Cyclone II ; Untyped ; +; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ; +; CBXI_PARAMETER ; scfifo_an31 ; Untyped ; ++-------------------------+-------------+------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++----------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: uart_16750:inst|slib_fifo:UART_RXFF ; ++----------------+-------+---------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+---------------------------------------------------------+ +; width ; 11 ; Signed Integer ; +; size_e ; 6 ; Signed Integer ; ++----------------+-------+---------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++----------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component ; ++-------------------------+-------------+------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++-------------------------+-------------+------------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; lpm_width ; 11 ; Signed Integer ; +; LPM_NUMWORDS ; 64 ; Signed Integer ; +; LPM_WIDTHU ; 6 ; Signed Integer ; +; LPM_SHOWAHEAD ; ON ; Untyped ; +; UNDERFLOW_CHECKING ; ON ; Untyped ; +; OVERFLOW_CHECKING ; ON ; Untyped ; +; ALLOW_RWCYCLE_WHEN_FULL ; OFF ; Untyped ; +; ADD_RAM_OUTPUT_REGISTER ; OFF ; Untyped ; +; ALMOST_FULL_VALUE ; 0 ; Untyped ; +; ALMOST_EMPTY_VALUE ; 0 ; Untyped ; +; USE_EAB ; ON ; Untyped ; +; MAXIMIZE_SPEED ; 5 ; Untyped ; +; DEVICE_FAMILY ; Cyclone II ; Untyped ; +; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ; +; CBXI_PARAMETER ; scfifo_ko31 ; Untyped ; ++-------------------------+-------------+------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: uart_16750:inst|uart_receiver:UART_RX|slib_counter:RX_BRC ; ++----------------+-------+-------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-------------------------------------------------------------------------------+ +; width ; 4 ; Signed Integer ; ++----------------+-------+-------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++----------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF ; ++----------------+-------+---------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+---------------------------------------------------------------------------------+ +; width ; 4 ; Signed Integer ; +; threshold ; 10 ; Signed Integer ; ++----------------+-------+---------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: slib_clock_div:inst2 ; ++----------------+-------+------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+------------------------------------------+ +; ratio ; 18 ; Untyped ; ++----------------+-------+------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------+ +; scfifo Parameter Settings by Entity Instance ; ++----------------------------+-------------------------------------------------------------+ +; Name ; Value ; ++----------------------------+-------------------------------------------------------------+ +; Number of entity instances ; 2 ; +; Entity Instance ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component ; +; -- FIFO Type ; Single Clock ; +; -- lpm_width ; 8 ; +; -- LPM_NUMWORDS ; 64 ; +; -- LPM_SHOWAHEAD ; ON ; +; -- USE_EAB ; ON ; +; Entity Instance ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component ; +; -- FIFO Type ; Single Clock ; +; -- lpm_width ; 11 ; +; -- LPM_NUMWORDS ; 64 ; +; -- LPM_SHOWAHEAD ; ON ; +; -- USE_EAB ; ON ; ++----------------------------+-------------------------------------------------------------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus II Analysis & Synthesis + Info: Version 8.0 Build 215 05/29/2008 SJ Full Version + Info: Processing started: Tue Feb 17 23:02:25 2009 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off UART16750 -c UART16750 +Info: Found 2 design units, including 1 entities, in source file ../../../rtl/vhdl/uart_transmitter.vhd + Info: Found design unit 1: uart_transmitter-rtl + Info: Found entity 1: uart_transmitter +Info: Found 2 design units, including 1 entities, in source file ../../../rtl/vhdl/slib_clock_div.vhd + Info: Found design unit 1: slib_clock_div-rtl + Info: Found entity 1: slib_clock_div +Info: Found 2 design units, including 1 entities, in source file ../../../rtl/vhdl/slib_counter.vhd + Info: Found design unit 1: slib_counter-rtl + Info: Found entity 1: slib_counter +Info: Found 2 design units, including 1 entities, in source file ../../../rtl/vhdl/slib_edge_detect.vhd + Info: Found design unit 1: slib_edge_detect-rtl + Info: Found entity 1: slib_edge_detect +Info: Found 2 design units, including 1 entities, in source file ../../../rtl/vhdl/slib_fifo_cyclone2.vhd + Info: Found design unit 1: slib_fifo-altera + Info: Found entity 1: slib_fifo +Info: Found 2 design units, including 1 entities, in source file ../../../rtl/vhdl/slib_input_filter.vhd + Info: Found design unit 1: slib_input_filter-rtl + Info: Found entity 1: slib_input_filter +Info: Found 2 design units, including 1 entities, in source file ../../../rtl/vhdl/slib_input_sync.vhd + Info: Found design unit 1: slib_input_sync-rtl + Info: Found entity 1: slib_input_sync +Info: Found 2 design units, including 1 entities, in source file ../../../rtl/vhdl/slib_mv_filter.vhd + Info: Found design unit 1: slib_mv_filter-rtl + Info: Found entity 1: slib_mv_filter +Info: Found 2 design units, including 1 entities, in source file ../../../rtl/vhdl/uart_16750.vhd + Info: Found design unit 1: uart_16750-rtl + Info: Found entity 1: uart_16750 +Info: Found 2 design units, including 1 entities, in source file ../../../rtl/vhdl/uart_baudgen.vhd + Info: Found design unit 1: uart_baudgen-rtl + Info: Found entity 1: uart_baudgen +Info: Found 2 design units, including 1 entities, in source file ../../../rtl/vhdl/uart_interrupt.vhd + Info: Found design unit 1: uart_interrupt-rtl + Info: Found entity 1: uart_interrupt +Info: Found 2 design units, including 1 entities, in source file ../../../rtl/vhdl/uart_receiver.vhd + Info: Found design unit 1: uart_receiver-rtl + Info: Found entity 1: uart_receiver +Info: Found 1 design units, including 1 entities, in source file UART16750.bdf + Info: Found entity 1: UART16750 +Info: Elaborating entity "UART16750" for the top level hierarchy +Info: Elaborating entity "uart_16750" for hierarchy "uart_16750:inst" +Info: Elaborating entity "slib_edge_detect" for hierarchy "uart_16750:inst|slib_edge_detect:UART_ED_WRITE" +Info: Elaborating entity "slib_input_sync" for hierarchy "uart_16750:inst|slib_input_sync:UART_IS_SIN" +Info: Elaborating entity "slib_input_filter" for hierarchy "uart_16750:inst|slib_input_filter:UART_IF_CTS" +Info: Elaborating entity "uart_interrupt" for hierarchy "uart_16750:inst|uart_interrupt:UART_IIC" +Info: Elaborating entity "uart_baudgen" for hierarchy "uart_16750:inst|uart_baudgen:UART_BG16" +Info: Elaborating entity "slib_clock_div" for hierarchy "uart_16750:inst|slib_clock_div:UART_BG2" +Info: Elaborating entity "slib_fifo" for hierarchy "uart_16750:inst|slib_fifo:UART_TXFF" +Info: Elaborating entity "scfifo" for hierarchy "uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component" +Info: Elaborated megafunction instantiation "uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component" +Info: Instantiated megafunction "uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component" with the following parameter: + Info: Parameter "add_ram_output_register" = "OFF" + Info: Parameter "intended_device_family" = "Cyclone II" + Info: Parameter "lpm_numwords" = "64" + Info: Parameter "lpm_showahead" = "ON" + Info: Parameter "lpm_type" = "scfifo" + Info: Parameter "lpm_width" = "8" + Info: Parameter "lpm_widthu" = "6" + Info: Parameter "overflow_checking" = "ON" + Info: Parameter "underflow_checking" = "ON" + Info: Parameter "use_eab" = "ON" +Info: Found 1 design units, including 1 entities, in source file db/scfifo_an31.tdf + Info: Found entity 1: scfifo_an31 +Info: Elaborating entity "scfifo_an31" for hierarchy "uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated" +Info: Found 1 design units, including 1 entities, in source file db/a_dpfifo_te31.tdf + Info: Found entity 1: a_dpfifo_te31 +Info: Elaborating entity "a_dpfifo_te31" for hierarchy "uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo" +Info: Found 1 design units, including 1 entities, in source file db/altsyncram_t681.tdf + Info: Found entity 1: altsyncram_t681 +Info: Elaborating entity "altsyncram_t681" for hierarchy "uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|altsyncram_t681:FIFOram" +Info: Found 1 design units, including 1 entities, in source file db/cntr_c5b.tdf + Info: Found entity 1: cntr_c5b +Info: Elaborating entity "cntr_c5b" for hierarchy "uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_c5b:rd_ptr_msb" +Info: Found 1 design units, including 1 entities, in source file db/cntr_p57.tdf + Info: Found entity 1: cntr_p57 +Info: Elaborating entity "cntr_p57" for hierarchy "uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_p57:usedw_counter" +Info: Found 1 design units, including 1 entities, in source file db/cntr_d5b.tdf + Info: Found entity 1: cntr_d5b +Info: Elaborating entity "cntr_d5b" for hierarchy "uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_d5b:wr_ptr" +Info: Elaborating entity "slib_fifo" for hierarchy "uart_16750:inst|slib_fifo:UART_RXFF" +Info: Elaborating entity "scfifo" for hierarchy "uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component" +Info: Elaborated megafunction instantiation "uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component" +Info: Instantiated megafunction "uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component" with the following parameter: + Info: Parameter "add_ram_output_register" = "OFF" + Info: Parameter "intended_device_family" = "Cyclone II" + Info: Parameter "lpm_numwords" = "64" + Info: Parameter "lpm_showahead" = "ON" + Info: Parameter "lpm_type" = "scfifo" + Info: Parameter "lpm_width" = "11" + Info: Parameter "lpm_widthu" = "6" + Info: Parameter "overflow_checking" = "ON" + Info: Parameter "underflow_checking" = "ON" + Info: Parameter "use_eab" = "ON" +Info: Found 1 design units, including 1 entities, in source file db/scfifo_ko31.tdf + Info: Found entity 1: scfifo_ko31 +Info: Elaborating entity "scfifo_ko31" for hierarchy "uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated" +Info: Found 1 design units, including 1 entities, in source file db/a_dpfifo_7g31.tdf + Info: Found entity 1: a_dpfifo_7g31 +Info: Elaborating entity "a_dpfifo_7g31" for hierarchy "uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo" +Info: Found 1 design units, including 1 entities, in source file db/altsyncram_h981.tdf + Info: Found entity 1: altsyncram_h981 +Info: Elaborating entity "altsyncram_h981" for hierarchy "uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram" +Info: Elaborating entity "uart_transmitter" for hierarchy "uart_16750:inst|uart_transmitter:UART_TX" +Info: Elaborating entity "uart_receiver" for hierarchy "uart_16750:inst|uart_receiver:UART_RX" +Info: Elaborating entity "slib_counter" for hierarchy "uart_16750:inst|uart_receiver:UART_RX|slib_counter:RX_BRC" +Info: Elaborating entity "slib_mv_filter" for hierarchy "uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF" +Info: Elaborating entity "slib_clock_div" for hierarchy "slib_clock_div:inst2" +Info: State machine "|UART16750|uart_16750:inst|\UART_TXPROC:State" contains 4 states +Info: State machine "|UART16750|uart_16750:inst|uart_receiver:UART_RX|CState" contains 6 states +Info: State machine "|UART16750|uart_16750:inst|uart_transmitter:UART_TX|CState" contains 13 states +Info: Selected Auto state machine encoding method for state machine "|UART16750|uart_16750:inst|\UART_TXPROC:State" +Info: Encoding result for state machine "|UART16750|uart_16750:inst|\UART_TXPROC:State" + Info: Completed encoding using 4 state bits + Info: Encoded state bit "uart_16750:inst|\UART_TXPROC:State.txend" + Info: Encoded state bit "uart_16750:inst|\UART_TXPROC:State.txrun" + Info: Encoded state bit "uart_16750:inst|\UART_TXPROC:State.txstart" + Info: Encoded state bit "uart_16750:inst|\UART_TXPROC:State.idle" + Info: State "|UART16750|uart_16750:inst|\UART_TXPROC:State.idle" uses code string "0000" + Info: State "|UART16750|uart_16750:inst|\UART_TXPROC:State.txstart" uses code string "0011" + Info: State "|UART16750|uart_16750:inst|\UART_TXPROC:State.txrun" uses code string "0101" + Info: State "|UART16750|uart_16750:inst|\UART_TXPROC:State.txend" uses code string "1001" +Info: Selected Auto state machine encoding method for state machine "|UART16750|uart_16750:inst|uart_receiver:UART_RX|CState" +Info: Encoding result for state machine "|UART16750|uart_16750:inst|uart_receiver:UART_RX|CState" + Info: Completed encoding using 6 state bits + Info: Encoded state bit "uart_16750:inst|uart_receiver:UART_RX|CState.mwait" + Info: Encoded state bit "uart_16750:inst|uart_receiver:UART_RX|CState.stop" + Info: Encoded state bit "uart_16750:inst|uart_receiver:UART_RX|CState.par" + Info: Encoded state bit "uart_16750:inst|uart_receiver:UART_RX|CState.data" + Info: Encoded state bit "uart_16750:inst|uart_receiver:UART_RX|CState.start" + Info: Encoded state bit "uart_16750:inst|uart_receiver:UART_RX|CState.idle" + Info: State "|UART16750|uart_16750:inst|uart_receiver:UART_RX|CState.idle" uses code string "000000" + Info: State "|UART16750|uart_16750:inst|uart_receiver:UART_RX|CState.start" uses code string "000011" + Info: State "|UART16750|uart_16750:inst|uart_receiver:UART_RX|CState.data" uses code string "000101" + Info: State "|UART16750|uart_16750:inst|uart_receiver:UART_RX|CState.par" uses code string "001001" + Info: State "|UART16750|uart_16750:inst|uart_receiver:UART_RX|CState.stop" uses code string "010001" + Info: State "|UART16750|uart_16750:inst|uart_receiver:UART_RX|CState.mwait" uses code string "100001" +Info: Selected Auto state machine encoding method for state machine "|UART16750|uart_16750:inst|uart_transmitter:UART_TX|CState" +Info: Encoding result for state machine "|UART16750|uart_16750:inst|uart_transmitter:UART_TX|CState" + Info: Completed encoding using 13 state bits + Info: Encoded state bit "uart_16750:inst|uart_transmitter:UART_TX|CState.stop2" + Info: Encoded state bit "uart_16750:inst|uart_transmitter:UART_TX|CState.stop" + Info: Encoded state bit "uart_16750:inst|uart_transmitter:UART_TX|CState.par" + Info: Encoded state bit "uart_16750:inst|uart_transmitter:UART_TX|CState.bit7" + Info: Encoded state bit "uart_16750:inst|uart_transmitter:UART_TX|CState.bit6" + Info: Encoded state bit "uart_16750:inst|uart_transmitter:UART_TX|CState.bit5" + Info: Encoded state bit "uart_16750:inst|uart_transmitter:UART_TX|CState.bit4" + Info: Encoded state bit "uart_16750:inst|uart_transmitter:UART_TX|CState.bit3" + Info: Encoded state bit "uart_16750:inst|uart_transmitter:UART_TX|CState.bit2" + Info: Encoded state bit "uart_16750:inst|uart_transmitter:UART_TX|CState.bit1" + Info: Encoded state bit "uart_16750:inst|uart_transmitter:UART_TX|CState.bit0" + Info: Encoded state bit "uart_16750:inst|uart_transmitter:UART_TX|CState.start" + Info: Encoded state bit "uart_16750:inst|uart_transmitter:UART_TX|CState.idle" + Info: State "|UART16750|uart_16750:inst|uart_transmitter:UART_TX|CState.idle" uses code string "0000000000000" + Info: State "|UART16750|uart_16750:inst|uart_transmitter:UART_TX|CState.start" uses code string "0000000000011" + Info: State "|UART16750|uart_16750:inst|uart_transmitter:UART_TX|CState.bit0" uses code string "0000000000101" + Info: State "|UART16750|uart_16750:inst|uart_transmitter:UART_TX|CState.bit1" uses code string "0000000001001" + Info: State "|UART16750|uart_16750:inst|uart_transmitter:UART_TX|CState.bit2" uses code string "0000000010001" + Info: State "|UART16750|uart_16750:inst|uart_transmitter:UART_TX|CState.bit3" uses code string "0000000100001" + Info: State "|UART16750|uart_16750:inst|uart_transmitter:UART_TX|CState.bit4" uses code string "0000001000001" + Info: State "|UART16750|uart_16750:inst|uart_transmitter:UART_TX|CState.bit5" uses code string "0000010000001" + Info: State "|UART16750|uart_16750:inst|uart_transmitter:UART_TX|CState.bit6" uses code string "0000100000001" + Info: State "|UART16750|uart_16750:inst|uart_transmitter:UART_TX|CState.bit7" uses code string "0001000000001" + Info: State "|UART16750|uart_16750:inst|uart_transmitter:UART_TX|CState.par" uses code string "0010000000001" + Info: State "|UART16750|uart_16750:inst|uart_transmitter:UART_TX|CState.stop" uses code string "0100000000001" + Info: State "|UART16750|uart_16750:inst|uart_transmitter:UART_TX|CState.stop2" uses code string "1000000000001" +Info: Registers with preset signals will power-up high +Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back +Info: Generated suppressed messages file R:/uart16750/syn/Altera/CycloneII/UART16750.map.smsg +Info: Implemented 584 device resources after synthesis - the final resource count might be different + Info: Implemented 21 input pins + Info: Implemented 15 output pins + Info: Implemented 529 logic cells + Info: Implemented 19 RAM segments +Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 182 megabytes + Info: Processing ended: Tue Feb 17 23:02:31 2009 + Info: Elapsed time: 00:00:06 + Info: Total CPU time (on all processors): 00:00:06 + + ++------------------------------------------+ +; Analysis & Synthesis Suppressed Messages ; ++------------------------------------------+ +The suppressed messages can be found in R:/uart16750/syn/Altera/CycloneII/UART16750.map.smsg. + +

trunk/syn/Altera/CycloneII/UART16750.map.rpt Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/syn/Altera/CycloneII/UART16750.asm.rpt =================================================================== --- trunk/syn/Altera/CycloneII/UART16750.asm.rpt (nonexistent) +++ trunk/syn/Altera/CycloneII/UART16750.asm.rpt (revision 16) @@ -0,0 +1,129 @@ +Assembler report for UART16750 +Tue Feb 17 23:02:38 2009 +Quartus II Version 8.0 Build 215 05/29/2008 SJ Full Version + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: R:/uart16750/syn/Altera/CycloneII/UART16750.sof + 6. Assembler Device Options: R:/uart16750/syn/Altera/CycloneII/UART16750.pof + 7. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Tue Feb 17 23:02:38 2009 ; +; Revision Name ; UART16750 ; +; Top-level Entity Name ; UART16750 ; +; Family ; Cyclone II ; +; Device ; EP2C5F256C6 ; ++-----------------------+---------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------+ +; Assembler Settings ; ++-----------------------------------------------------------------------------+----------+---------------+ +; Option ; Setting ; Default Value ; ++-----------------------------------------------------------------------------+----------+---------------+ +; Use smart compilation ; Off ; Off ; +; Maximum processors allowed for parallel compilation ; 1 ; 1 ; +; Generate compressed bitstreams ; On ; On ; +; Compression mode ; Off ; Off ; +; Clock source for configuration device ; Internal ; Internal ; +; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ; +; Divide clock frequency by ; 1 ; 1 ; +; Auto user code ; Off ; Off ; +; Use configuration device ; On ; On ; +; Configuration device ; Auto ; Auto ; +; Configuration device auto user code ; Off ; Off ; +; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ; +; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ; +; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ; +; Hexadecimal Output File start address ; 0 ; 0 ; +; Hexadecimal Output File count direction ; Up ; Up ; +; Release clears before tri-states ; Off ; Off ; +; Auto-restart configuration after error ; On ; On ; +; Maintain Compatibility with All Cyclone II M4K Versions ; On ; On ; +; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ; +; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ; ++-----------------------------------------------------------------------------+----------+---------------+ + + ++-------------------------------------------------+ +; Assembler Generated Files ; ++-------------------------------------------------+ +; File Name ; ++-------------------------------------------------+ +; R:/uart16750/syn/Altera/CycloneII/UART16750.sof ; +; R:/uart16750/syn/Altera/CycloneII/UART16750.pof ; ++-------------------------------------------------+ + + ++---------------------------------------------------------------------------+ +; Assembler Device Options: R:/uart16750/syn/Altera/CycloneII/UART16750.sof ; ++----------------+----------------------------------------------------------+ +; Option ; Setting ; ++----------------+----------------------------------------------------------+ +; Device ; EP2C5F256C6 ; +; JTAG usercode ; 0xFFFFFFFF ; +; Checksum ; 0x000BA009 ; ++----------------+----------------------------------------------------------+ + + ++---------------------------------------------------------------------------+ +; Assembler Device Options: R:/uart16750/syn/Altera/CycloneII/UART16750.pof ; ++--------------------+------------------------------------------------------+ +; Option ; Setting ; ++--------------------+------------------------------------------------------+ +; Device ; EPCS4 ; +; JTAG usercode ; 0x00000000 ; +; Checksum ; 0x074AABDE ; +; Compression Ratio ; 2 ; ++--------------------+------------------------------------------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus II Assembler + Info: Version 8.0 Build 215 05/29/2008 SJ Full Version + Info: Processing started: Tue Feb 17 23:02:37 2009 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off UART16750 -c UART16750 +Info: Writing out detailed assembly data for power analysis +Info: Assembler is generating device programming files +Info: Quartus II Assembler was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 146 megabytes + Info: Processing ended: Tue Feb 17 23:02:38 2009 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:01 + +

trunk/syn/Altera/CycloneII/UART16750.asm.rpt Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/syn/Altera/CycloneII/UART16750.done =================================================================== --- trunk/syn/Altera/CycloneII/UART16750.done (nonexistent) +++ trunk/syn/Altera/CycloneII/UART16750.done (revision 16) @@ -0,0 +1 @@ +Tue Feb 17 23:02:41 2009

trunk/syn/Altera/CycloneII/UART16750.done Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/syn/Altera/CycloneII/UART16750.map.smsg =================================================================== --- trunk/syn/Altera/CycloneII/UART16750.map.smsg (nonexistent) +++ trunk/syn/Altera/CycloneII/UART16750.map.smsg (revision 16) @@ -0,0 +1,11 @@ +Warning (10036): Verilog HDL or VHDL warning at uart_16750.vhd(226): object "iFCR" assigned a value but never read +Warning (10036): Verilog HDL or VHDL warning at uart_16750.vhd(234): object "iIER_ERBI" assigned a value but never read +Warning (10036): Verilog HDL or VHDL warning at uart_16750.vhd(235): object "iIER_ETBEI" assigned a value but never read +Warning (10036): Verilog HDL or VHDL warning at uart_16750.vhd(236): object "iIER_ELSI" assigned a value but never read +Warning (10036): Verilog HDL or VHDL warning at uart_16750.vhd(237): object "iIER_EDSSI" assigned a value but never read +Warning (10036): Verilog HDL or VHDL warning at uart_16750.vhd(240): object "iIIR_PI" assigned a value but never read +Warning (10036): Verilog HDL or VHDL warning at uart_16750.vhd(241): object "iIIR_ID0" assigned a value but never read +Warning (10036): Verilog HDL or VHDL warning at uart_16750.vhd(242): object "iIIR_ID1" assigned a value but never read +Warning (10036): Verilog HDL or VHDL warning at uart_16750.vhd(243): object "iIIR_ID2" assigned a value but never read +Warning (10036): Verilog HDL or VHDL warning at uart_16750.vhd(244): object "iIIR_FIFO64" assigned a value but never read +Warning (10036): Verilog HDL or VHDL warning at uart_16750.vhd(306): object "iRInRE" assigned a value but never read

trunk/syn/Altera/CycloneII/UART16750.map.smsg Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/syn/Altera/CycloneII/UART16750.fit.rpt =================================================================== --- trunk/syn/Altera/CycloneII/UART16750.fit.rpt (nonexistent) +++ trunk/syn/Altera/CycloneII/UART16750.fit.rpt (revision 16) @@ -0,0 +1,1145 @@ +Fitter report for UART16750 +Tue Feb 17 23:02:36 2009 +Quartus II Version 8.0 Build 215 05/29/2008 SJ Full Version + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Fitter Partition Preservation Settings + 5. Fitter Netlist Optimizations + 6. Pin-Out File + 7. Fitter Resource Usage Summary + 8. Input Pins + 9. Output Pins + 10. I/O Bank Usage + 11. All Package Pins + 12. Output Pin Default Load For Reported TCO + 13. Fitter Resource Utilization by Entity + 14. Delay Chain Summary + 15. Pad To Core Delay Chain Fanout + 16. Control Signals + 17. Global & Other Fast Signals + 18. Non-Global High Fan-Out Signals + 19. Fitter RAM Summary + 20. Interconnect Usage Summary + 21. LAB Logic Elements + 22. LAB-wide Signals + 23. LAB Signals Sourced + 24. LAB Signals Sourced Out + 25. LAB Distinct Inputs + 26. Fitter Device Options + 27. Operating Settings and Conditions + 28. Fitter Messages + 29. Fitter Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+------------------------------------------+ +; Fitter Status ; Successful - Tue Feb 17 23:02:36 2009 ; +; Quartus II Version ; 8.0 Build 215 05/29/2008 SJ Full Version ; +; Revision Name ; UART16750 ; +; Top-level Entity Name ; UART16750 ; +; Family ; Cyclone II ; +; Device ; EP2C5F256C6 ; +; Timing Models ; Final ; +; Total logic elements ; 448 / 4,608 ( 10 % ) ; +; Total combinational functions ; 418 / 4,608 ( 9 % ) ; +; Dedicated logic registers ; 285 / 4,608 ( 6 % ) ; +; Total registers ; 285 ; +; Total pins ; 36 / 158 ( 23 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 1,216 / 119,808 ( 1 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 26 ( 0 % ) ; +; Total PLLs ; 0 / 2 ( 0 % ) ; ++------------------------------------+------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++--------------------------------------------------------------------+--------------------------------+--------------------------------+ +; Option ; Setting ; Default Value ; ++--------------------------------------------------------------------+--------------------------------+--------------------------------+ +; Device ; EP2C5F256C6 ; ; +; Fit Attempts to Skip ; 0 ; 0.0 ; +; Device I/O Standard ; 3.3-V LVTTL ; ; +; Use smart compilation ; Off ; Off ; +; Maximum processors allowed for parallel compilation ; 1 ; 1 ; +; Use TimeQuest Timing Analyzer ; Off ; Off ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Router Effort Multiplier ; 1.0 ; 1.0 ; +; Always Enable Input Buffers ; Off ; Off ; +; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ; +; Optimize Fast-Corner Timing ; Off ; Off ; +; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize IOC Register Placement for Timing ; On ; On ; +; Limit to One Fitting Attempt ; Off ; Off ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; PCI I/O ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Global Memory Control Signals ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Auto Merge PLLs ; On ; On ; +; Ignore PLL Mode When Merging PLLs ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Stop After Congestion Map Generation ; Off ; Off ; +; Save Intermediate Fitting Results ; Off ; Off ; +; Maximum number of global clocks allowed ; -1 ; -1 ; ++--------------------------------------------------------------------+--------------------------------+--------------------------------+ + + ++--------------------------------------------------------------------------------------------------------+ +; Fitter Partition Preservation Settings ; ++------+-------------------+---------+------------------------------+------------------------+-----------+ +; Name ; # Preserved Nodes ; # Nodes ; Preservation Level Requested ; Netlist Type Used ; Hierarchy ; ++------+-------------------+---------+------------------------------+------------------------+-----------+ +; Top ; 0 ; 765 ; Placement and Routing ; Post-Synthesis Netlist ; ; ++------+-------------------+---------+------------------------------+------------------------+-----------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Netlist Optimizations ; ++-------------------------+-----------------+------------------+---------------------+-----------+----------------+--------------------------------------------------------------------------------------------------------------------------------------------+------------------+-----------------------+ +; Node ; Action ; Operation ; Reason ; Node Port ; Node Port Name ; Destination Node ; Destination Port ; Destination Port Name ; ++-------------------------+-----------------+------------------+---------------------+-----------+----------------+--------------------------------------------------------------------------------------------------------------------------------------------+------------------+-----------------------+ +; uart_16750:inst|iTSR[0] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|altsyncram_t681:FIFOram|q_b[0] ; PORTBDATAOUT ; ; +; uart_16750:inst|iTSR[1] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|altsyncram_t681:FIFOram|q_b[1] ; PORTBDATAOUT ; ; +; uart_16750:inst|iTSR[2] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|altsyncram_t681:FIFOram|q_b[2] ; PORTBDATAOUT ; ; +; uart_16750:inst|iTSR[3] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|altsyncram_t681:FIFOram|q_b[3] ; PORTBDATAOUT ; ; +; uart_16750:inst|iTSR[4] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|altsyncram_t681:FIFOram|q_b[4] ; PORTBDATAOUT ; ; +; uart_16750:inst|iTSR[5] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|altsyncram_t681:FIFOram|q_b[5] ; PORTBDATAOUT ; ; +; uart_16750:inst|iTSR[6] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|altsyncram_t681:FIFOram|q_b[6] ; PORTBDATAOUT ; ; +; uart_16750:inst|iTSR[7] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|altsyncram_t681:FIFOram|q_b[7] ; PORTBDATAOUT ; ; ++-------------------------+-----------------+------------------+---------------------+-----------+----------------+--------------------------------------------------------------------------------------------------------------------------------------------+------------------+-----------------------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in R:/uart16750/syn/Altera/CycloneII/UART16750.pin. + + ++----------------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++---------------------------------------------+------------------------------+ +; Resource ; Usage ; ++---------------------------------------------+------------------------------+ +; Total logic elements ; 448 / 4,608 ( 10 % ) ; +; -- Combinational with no register ; 163 ; +; -- Register only ; 30 ; +; -- Combinational with a register ; 255 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 223 ; +; -- 3 input functions ; 72 ; +; -- <=2 input functions ; 123 ; +; -- Register only ; 30 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 349 ; +; -- arithmetic mode ; 69 ; +; ; ; +; Total registers* ; 285 / 5,058 ( 6 % ) ; +; -- Dedicated logic registers ; 285 / 4,608 ( 6 % ) ; +; -- I/O registers ; 0 / 450 ( 0 % ) ; +; ; ; +; Total LABs: partially or completely used ; 40 / 288 ( 14 % ) ; +; User inserted logic elements ; 0 ; +; Virtual pins ; 0 ; +; I/O pins ; 36 / 158 ( 23 % ) ; +; -- Clock pins ; 1 / 4 ( 25 % ) ; +; Global signals ; 2 ; +; M4Ks ; 2 / 26 ( 8 % ) ; +; Total memory bits ; 1,216 / 119,808 ( 1 % ) ; +; Total RAM block bits ; 9,216 / 119,808 ( 8 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 26 ( 0 % ) ; +; PLLs ; 0 / 2 ( 0 % ) ; +; Global clocks ; 2 / 8 ( 25 % ) ; +; JTAGs ; 0 / 1 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 2% / 2% / 2% ; +; Peak interconnect usage (total/H/V) ; 4% / 3% / 4% ; +; Maximum fan-out node ; CLK~clkctrl ; +; Maximum fan-out ; 287 ; +; Highest non-global fan-out signal ; uart_16750:inst|iRXFIFOClear ; +; Highest non-global fan-out ; 41 ; +; Total fan-out ; 2428 ; +; Average fan-out ; 3.17 ; ++---------------------------------------------+------------------------------+ +* Register count does not include registers inside RAM blocks or DSP blocks. + + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++--------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ; ++--------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ +; A[0] ; G13 ; 3 ; 28 ; 11 ; 3 ; 15 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; +; A[1] ; F16 ; 3 ; 28 ; 10 ; 3 ; 15 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; +; A[2] ; F15 ; 3 ; 28 ; 9 ; 0 ; 10 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; +; CLK ; H15 ; 3 ; 28 ; 7 ; 1 ; 1 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; +; CS ; G12 ; 3 ; 28 ; 10 ; 0 ; 5 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; +; CTSN ; M15 ; 3 ; 28 ; 4 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; +; DCDN ; M16 ; 3 ; 28 ; 4 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; +; DIN[0] ; B11 ; 2 ; 24 ; 14 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; +; DIN[1] ; B12 ; 2 ; 21 ; 14 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; +; DIN[2] ; B13 ; 2 ; 24 ; 14 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; +; DIN[3] ; B14 ; 2 ; 26 ; 14 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; +; DIN[4] ; A11 ; 2 ; 21 ; 14 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; +; DIN[5] ; A12 ; 2 ; 21 ; 14 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; +; DIN[6] ; A13 ; 2 ; 24 ; 14 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; +; DIN[7] ; A14 ; 2 ; 26 ; 14 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; +; DSRN ; L14 ; 3 ; 28 ; 5 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; +; RD ; D15 ; 3 ; 28 ; 11 ; 1 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; +; RIN ; L16 ; 3 ; 28 ; 5 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; +; RSTN ; G16 ; 3 ; 28 ; 9 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; +; SIN ; G15 ; 3 ; 28 ; 9 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; +; WR ; E14 ; 3 ; 28 ; 12 ; 1 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; User ; ++--------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++---------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ; ++---------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------+ +; DDIS ; E16 ; 3 ; 28 ; 12 ; 4 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; DOUT[0] ; T14 ; 4 ; 26 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; DOUT[1] ; T13 ; 4 ; 24 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; DOUT[2] ; T12 ; 4 ; 21 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; DOUT[3] ; T11 ; 4 ; 14 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; DOUT[4] ; R14 ; 4 ; 26 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; DOUT[5] ; R13 ; 4 ; 24 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; DOUT[6] ; R12 ; 4 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; DOUT[7] ; R11 ; 4 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; DTRN ; L15 ; 3 ; 28 ; 5 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; INT ; D16 ; 3 ; 28 ; 11 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; OUT1N ; N16 ; 3 ; 28 ; 4 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; OUT2N ; N15 ; 3 ; 28 ; 3 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; RTSN ; K15 ; 3 ; 28 ; 6 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; +; SOUT ; K16 ; 3 ; 28 ; 6 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; User ; 10 pF ; ++---------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------+ + + ++------------------------------------------------------------+ +; I/O Bank Usage ; ++----------+------------------+---------------+--------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; ++----------+------------------+---------------+--------------+ +; 1 ; 2 / 35 ( 6 % ) ; 3.3V ; -- ; +; 2 ; 8 / 43 ( 19 % ) ; 3.3V ; -- ; +; 3 ; 21 / 39 ( 54 % ) ; 3.3V ; -- ; +; 4 ; 8 / 41 ( 20 % ) ; 3.3V ; -- ; ++----------+------------------+---------------+--------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; A1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A2 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; A3 ; 166 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A4 ; 165 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A5 ; 163 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A6 ; 155 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A7 ; 149 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A8 ; 148 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A9 ; 146 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A10 ; 141 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A11 ; 136 ; 2 ; DIN[4] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A12 ; 135 ; 2 ; DIN[5] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A13 ; 132 ; 2 ; DIN[6] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A14 ; 128 ; 2 ; DIN[7] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A15 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; A16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B1 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B3 ; 167 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B4 ; 164 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B5 ; 162 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B6 ; 154 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B7 ; 150 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; B9 ; 147 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B10 ; 140 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B11 ; 133 ; 2 ; DIN[0] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B12 ; 134 ; 2 ; DIN[1] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B13 ; 131 ; 2 ; DIN[2] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B14 ; 127 ; 2 ; DIN[3] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B16 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; C1 ; 2 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C2 ; 3 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C3 ; 0 ; 1 ; ~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; +; C4 ; 161 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C5 ; 160 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C6 ; 159 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C7 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; C8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C10 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; C11 ; 137 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C12 ; 130 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C13 ; 129 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C14 ; 123 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C15 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; C16 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; D1 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; D2 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; D3 ; 8 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D4 ; 9 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D5 ; 4 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D6 ; 158 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D7 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; D8 ; 153 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D9 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; D10 ; 145 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D11 ; 144 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D12 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; +; D13 ; 124 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D14 ; 126 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D15 ; 120 ; 3 ; RD ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; D16 ; 121 ; 3 ; INT ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; E1 ; 11 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E2 ; 12 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E3 ; 6 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E4 ; 7 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E5 ; 5 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E6 ; 168 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E7 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; E8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E10 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; E11 ; ; ; GNDA_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; +; E12 ; ; ; VCCA_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; E13 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; E14 ; 125 ; 3 ; WR ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; E15 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; E16 ; 122 ; 3 ; DDIS ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; F1 ; 17 ; 1 ; ^DATA0 ; input ; ; ; -- ; ; -- ; -- ; +; F2 ; 15 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; +; F3 ; 10 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F4 ; 1 ; 1 ; ~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; +; F5 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; F6 ; 169 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F7 ; 151 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F8 ; 152 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F9 ; 143 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F10 ; 142 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F11 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; F12 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; +; F13 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; F14 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; F15 ; 113 ; 3 ; A[2] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; F16 ; 114 ; 3 ; A[1] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; G1 ; 14 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; +; G2 ; 13 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; +; G3 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; G4 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; G5 ; 19 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ; +; G6 ; 156 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G7 ; 157 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G10 ; 138 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G11 ; 139 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; G12 ; 117 ; 3 ; CS ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; G13 ; 118 ; 3 ; A[0] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; G14 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; G15 ; 112 ; 3 ; SIN ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; G16 ; 111 ; 3 ; RSTN ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; H1 ; 21 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; H2 ; 20 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; H3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H4 ; 18 ; 1 ; ^DCLK ; ; ; ; -- ; ; -- ; -- ; +; H5 ; 16 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ; +; H6 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; H7 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; H8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; H11 ; 116 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H12 ; 109 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H13 ; 119 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H15 ; 107 ; 3 ; CLK ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; H16 ; 108 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; J1 ; 24 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; J2 ; 23 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; J3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J4 ; 32 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J5 ; 22 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; +; J6 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; J7 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J10 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; J11 ; 115 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J12 ; 110 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J13 ; 102 ; 3 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ; +; J14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J15 ; 106 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; J16 ; 105 ; 3 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; K1 ; 26 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K2 ; 25 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K3 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; K4 ; 27 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K5 ; 28 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K6 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; K7 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; K8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; K9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K10 ; 71 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; K11 ; 70 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; K12 ; 101 ; 3 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ; +; K13 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; K14 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; K15 ; 104 ; 3 ; RTSN ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; K16 ; 103 ; 3 ; SOUT ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; L1 ; 30 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L2 ; 31 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L3 ; 37 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L4 ; 41 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L5 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; +; L6 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L7 ; 55 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; L8 ; 56 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; L9 ; 66 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; L10 ; 67 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; L11 ; 83 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; L12 ; 77 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; L13 ; 100 ; 3 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ; +; L14 ; 96 ; 3 ; DSRN ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; L15 ; 97 ; 3 ; DTRN ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; L16 ; 98 ; 3 ; RIN ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; M1 ; 29 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M2 ; 33 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M3 ; 34 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M4 ; 42 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M5 ; ; ; VCCA_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M6 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; +; M7 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; M8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M10 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; M11 ; 82 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; M12 ; 85 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M13 ; 99 ; 3 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; +; M14 ; 95 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M15 ; 93 ; 3 ; CTSN ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; M16 ; 94 ; 3 ; DCDN ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; N1 ; 35 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N2 ; 36 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N3 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; N4 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; N5 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; +; N6 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; N7 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; N8 ; 52 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; N9 ; 61 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; N10 ; 62 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; N11 ; 72 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; N12 ; 84 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N13 ; 86 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N14 ; 87 ; 3 ; ~LVDS41p/nCEO~ ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; N15 ; 91 ; 3 ; OUT2N ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; N16 ; 92 ; 3 ; OUT1N ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; P1 ; 38 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P2 ; 39 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P3 ; 40 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P4 ; 46 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P5 ; 45 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P6 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; P7 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; P8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P10 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; P11 ; 65 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P12 ; 73 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P13 ; 74 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P14 ; 88 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P15 ; 89 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P16 ; 90 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R1 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; R2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R3 ; 43 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R4 ; 48 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R5 ; 50 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R6 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; R7 ; 54 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R8 ; 58 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R9 ; 60 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R10 ; 68 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R11 ; 64 ; 4 ; DOUT[7] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; R12 ; 76 ; 4 ; DOUT[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; R13 ; 79 ; 4 ; DOUT[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; R14 ; 81 ; 4 ; DOUT[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; R15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R16 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; T1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T2 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; T3 ; 44 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T4 ; 47 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T5 ; 49 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T6 ; 51 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T7 ; 53 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T8 ; 57 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T9 ; 59 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T10 ; 69 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T11 ; 63 ; 4 ; DOUT[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; T12 ; 75 ; 4 ; DOUT[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; T13 ; 78 ; 4 ; DOUT[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; T14 ; 80 ; 4 ; DOUT[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; T15 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; T16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++-------------------------------------------------------------------------------+ +; Output Pin Default Load For Reported TCO ; ++----------------------------------+-------+------------------------------------+ +; I/O Standard ; Load ; Termination Resistance ; ++----------------------------------+-------+------------------------------------+ +; 3.3-V LVTTL ; 0 pF ; Not Available ; +; 3.3-V LVCMOS ; 0 pF ; Not Available ; +; 2.5 V ; 0 pF ; Not Available ; +; 1.8 V ; 0 pF ; Not Available ; +; 1.5 V ; 0 pF ; Not Available ; +; 3.3-V PCI ; 10 pF ; 25 Ohm (Parallel) ; +; 3.3-V PCI-X ; 10 pF ; 25 Ohm (Parallel) ; +; SSTL-2 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; +; SSTL-2 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; +; SSTL-18 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; +; SSTL-18 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; +; 1.5-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ; +; 1.5-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ; +; 1.8-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ; +; 1.8-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ; +; Differential SSTL-2 ; 0 pF ; (See SSTL-2) ; +; Differential 2.5-V SSTL Class II ; 0 pF ; (See SSTL-2 Class II) ; +; Differential 1.8-V SSTL Class I ; 0 pF ; (See 1.8-V SSTL Class I) ; +; Differential 1.8-V SSTL Class II ; 0 pF ; (See 1.8-V SSTL Class II) ; +; Differential 1.5-V HSTL Class I ; 0 pF ; (See 1.5-V HSTL Class I) ; +; Differential 1.5-V HSTL Class II ; 0 pF ; (See 1.5-V HSTL Class II) ; +; Differential 1.8-V HSTL Class I ; 0 pF ; (See 1.8-V HSTL Class I) ; +; Differential 1.8-V HSTL Class II ; 0 pF ; (See 1.8-V HSTL Class II) ; +; LVDS ; 0 pF ; 100 Ohm (Differential) ; +; mini-LVDS ; 0 pF ; 100 Ohm (Differential) ; +; RSDS ; 0 pF ; 100 Ohm (Differential) ; +; Simple RSDS ; 0 pF ; Not Available ; +; Differential LVPECL ; 0 pF ; 100 Ohm (Differential) ; ++----------------------------------+-------+------------------------------------+ +Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables. + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++---------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ; ++---------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ +; |UART16750 ; 448 (4) ; 285 (3) ; 0 (0) ; 1216 ; 2 ; 0 ; 0 ; 0 ; 36 ; 0 ; 163 (1) ; 30 (2) ; 255 (1) ; |UART16750 ; work ; +; |slib_clock_div:inst2| ; 9 (9) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 6 (6) ; |UART16750|slib_clock_div:inst2 ; work ; +; |uart_16750:inst| ; 435 (172) ; 276 (112) ; 0 (0) ; 1216 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 159 (54) ; 28 (17) ; 248 (96) ; |UART16750|uart_16750:inst ; work ; +; |slib_clock_div:UART_BG2| ; 4 (4) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (4) ; |UART16750|uart_16750:inst|slib_clock_div:UART_BG2 ; work ; +; |slib_edge_detect:UART_BIDET| ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; |UART16750|uart_16750:inst|slib_edge_detect:UART_BIDET ; work ; +; |slib_edge_detect:UART_ED_CTS| ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; |UART16750|uart_16750:inst|slib_edge_detect:UART_ED_CTS ; work ; +; |slib_edge_detect:UART_ED_DCD| ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; |UART16750|uart_16750:inst|slib_edge_detect:UART_ED_DCD ; work ; +; |slib_edge_detect:UART_ED_DSR| ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 0 (0) ; |UART16750|uart_16750:inst|slib_edge_detect:UART_ED_DSR ; work ; +; |slib_edge_detect:UART_ED_READ| ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; |UART16750|uart_16750:inst|slib_edge_detect:UART_ED_READ ; work ; +; |slib_edge_detect:UART_ED_RI| ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; |UART16750|uart_16750:inst|slib_edge_detect:UART_ED_RI ; work ; +; |slib_edge_detect:UART_ED_WRITE| ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; |UART16750|uart_16750:inst|slib_edge_detect:UART_ED_WRITE ; work ; +; |slib_edge_detect:UART_FEDET| ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; |UART16750|uart_16750:inst|slib_edge_detect:UART_FEDET ; work ; +; |slib_edge_detect:UART_IIC_THRE_ED| ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; |UART16750|uart_16750:inst|slib_edge_detect:UART_IIC_THRE_ED ; work ; +; |slib_edge_detect:UART_PEDET| ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; |UART16750|uart_16750:inst|slib_edge_detect:UART_PEDET ; work ; +; |slib_edge_detect:UART_RCLK| ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; |UART16750|uart_16750:inst|slib_edge_detect:UART_RCLK ; work ; +; |slib_fifo:UART_RXFF| ; 49 (0) ; 29 (0) ; 0 (0) ; 704 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 20 (0) ; 0 (0) ; 29 (0) ; |UART16750|uart_16750:inst|slib_fifo:UART_RXFF ; work ; +; |scfifo:scfifo_component| ; 49 (0) ; 29 (0) ; 0 (0) ; 704 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 20 (0) ; 0 (0) ; 29 (0) ; |UART16750|uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component ; work ; +; |scfifo_ko31:auto_generated| ; 49 (0) ; 29 (0) ; 0 (0) ; 704 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 20 (0) ; 0 (0) ; 29 (0) ; |UART16750|uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated ; work ; +; |a_dpfifo_7g31:dpfifo| ; 49 (29) ; 29 (12) ; 0 (0) ; 704 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 20 (17) ; 0 (0) ; 29 (12) ; |UART16750|uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo ; work ; +; |altsyncram_h981:FIFOram| ; 0 (0) ; 0 (0) ; 0 (0) ; 704 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |UART16750|uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram ; work ; +; |cntr_c5b:rd_ptr_msb| ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 5 (5) ; |UART16750|uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_c5b:rd_ptr_msb ; work ; +; |cntr_d5b:wr_ptr| ; 7 (7) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 6 (6) ; |UART16750|uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_d5b:wr_ptr ; work ; +; |cntr_p57:usedw_counter| ; 7 (7) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 6 (6) ; |UART16750|uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_p57:usedw_counter ; work ; +; |slib_fifo:UART_TXFF| ; 50 (0) ; 29 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 20 (0) ; 0 (0) ; 30 (0) ; |UART16750|uart_16750:inst|slib_fifo:UART_TXFF ; work ; +; |scfifo:scfifo_component| ; 50 (0) ; 29 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 20 (0) ; 0 (0) ; 30 (0) ; |UART16750|uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component ; work ; +; |scfifo_an31:auto_generated| ; 50 (0) ; 29 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 20 (0) ; 0 (0) ; 30 (0) ; |UART16750|uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated ; work ; +; |a_dpfifo_te31:dpfifo| ; 50 (30) ; 29 (12) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 20 (17) ; 0 (0) ; 30 (13) ; |UART16750|uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo ; work ; +; |altsyncram_t681:FIFOram| ; 0 (0) ; 0 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |UART16750|uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|altsyncram_t681:FIFOram ; work ; +; |cntr_c5b:rd_ptr_msb| ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 5 (5) ; |UART16750|uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_c5b:rd_ptr_msb ; work ; +; |cntr_d5b:wr_ptr| ; 7 (7) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 6 (6) ; |UART16750|uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_d5b:wr_ptr ; work ; +; |cntr_p57:usedw_counter| ; 7 (7) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 6 (6) ; |UART16750|uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_p57:usedw_counter ; work ; +; |slib_input_filter:UART_IF_CTS| ; 3 (3) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 3 (3) ; |UART16750|uart_16750:inst|slib_input_filter:UART_IF_CTS ; work ; +; |slib_input_filter:UART_IF_DCD| ; 3 (3) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 3 (3) ; |UART16750|uart_16750:inst|slib_input_filter:UART_IF_DCD ; work ; +; |slib_input_filter:UART_IF_DSR| ; 3 (3) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 3 (3) ; |UART16750|uart_16750:inst|slib_input_filter:UART_IF_DSR ; work ; +; |slib_input_filter:UART_IF_RI| ; 3 (3) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 3 (3) ; |UART16750|uart_16750:inst|slib_input_filter:UART_IF_RI ; work ; +; |slib_input_sync:UART_IS_CTS| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 2 (2) ; 0 (0) ; |UART16750|uart_16750:inst|slib_input_sync:UART_IS_CTS ; work ; +; |slib_input_sync:UART_IS_DCD| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 2 (2) ; 0 (0) ; |UART16750|uart_16750:inst|slib_input_sync:UART_IS_DCD ; work ; +; |slib_input_sync:UART_IS_DSR| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 2 (2) ; 0 (0) ; |UART16750|uart_16750:inst|slib_input_sync:UART_IS_DSR ; work ; +; |slib_input_sync:UART_IS_RI| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 2 (2) ; 0 (0) ; |UART16750|uart_16750:inst|slib_input_sync:UART_IS_RI ; work ; +; |slib_input_sync:UART_IS_SIN| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 1 (1) ; |UART16750|uart_16750:inst|slib_input_sync:UART_IS_SIN ; work ; +; |uart_baudgen:UART_BG16| ; 27 (27) ; 17 (17) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 9 (9) ; 0 (0) ; 18 (18) ; |UART16750|uart_16750:inst|uart_baudgen:UART_BG16 ; work ; +; |uart_interrupt:UART_IIC| ; 12 (12) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 8 (8) ; 0 (0) ; 4 (4) ; |UART16750|uart_16750:inst|uart_interrupt:UART_IIC ; work ; +; |uart_receiver:UART_RX| ; 66 (48) ; 32 (21) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 31 (24) ; 0 (0) ; 35 (23) ; |UART16750|uart_16750:inst|uart_receiver:UART_RX ; work ; +; |slib_counter:RX_BRC| ; 10 (10) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (5) ; 0 (0) ; 5 (5) ; |UART16750|uart_16750:inst|uart_receiver:UART_RX|slib_counter:RX_BRC ; work ; +; |slib_mv_filter:RX_MVF| ; 9 (9) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 7 (7) ; |UART16750|uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF ; work ; +; |uart_transmitter:UART_TX| ; 35 (35) ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 17 (17) ; 1 (1) ; 17 (17) ; |UART16750|uart_16750:inst|uart_transmitter:UART_TX ; work ; ++---------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++----------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++---------+----------+---------------+---------------+-----------------------+-----+ +; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; ++---------+----------+---------------+---------------+-----------------------+-----+ +; DDIS ; Output ; -- ; -- ; -- ; -- ; +; INT ; Output ; -- ; -- ; -- ; -- ; +; OUT1N ; Output ; -- ; -- ; -- ; -- ; +; OUT2N ; Output ; -- ; -- ; -- ; -- ; +; RTSN ; Output ; -- ; -- ; -- ; -- ; +; DTRN ; Output ; -- ; -- ; -- ; -- ; +; SOUT ; Output ; -- ; -- ; -- ; -- ; +; DOUT[7] ; Output ; -- ; -- ; -- ; -- ; +; DOUT[6] ; Output ; -- ; -- ; -- ; -- ; +; DOUT[5] ; Output ; -- ; -- ; -- ; -- ; +; DOUT[4] ; Output ; -- ; -- ; -- ; -- ; +; DOUT[3] ; Output ; -- ; -- ; -- ; -- ; +; DOUT[2] ; Output ; -- ; -- ; -- ; -- ; +; DOUT[1] ; Output ; -- ; -- ; -- ; -- ; +; DOUT[0] ; Output ; -- ; -- ; -- ; -- ; +; A[1] ; Input ; 6 ; 6 ; -- ; -- ; +; A[2] ; Input ; 6 ; 6 ; -- ; -- ; +; A[0] ; Input ; 6 ; 6 ; -- ; -- ; +; CS ; Input ; 0 ; 4 ; -- ; -- ; +; RD ; Input ; 6 ; 0 ; -- ; -- ; +; CLK ; Input ; 0 ; 0 ; -- ; -- ; +; WR ; Input ; 0 ; 4 ; -- ; -- ; +; DIN[7] ; Input ; 6 ; 0 ; -- ; -- ; +; DIN[0] ; Input ; 6 ; 0 ; -- ; -- ; +; DIN[3] ; Input ; 6 ; 0 ; -- ; -- ; +; DIN[4] ; Input ; 6 ; 0 ; -- ; -- ; +; DIN[6] ; Input ; 6 ; 0 ; -- ; -- ; +; DIN[2] ; Input ; 6 ; 0 ; -- ; -- ; +; DIN[5] ; Input ; 6 ; 0 ; -- ; -- ; +; DIN[1] ; Input ; 6 ; 0 ; -- ; -- ; +; RSTN ; Input ; 6 ; 0 ; -- ; -- ; +; DCDN ; Input ; 0 ; 6 ; -- ; -- ; +; RIN ; Input ; 0 ; 6 ; -- ; -- ; +; DSRN ; Input ; 0 ; 6 ; -- ; -- ; +; CTSN ; Input ; 6 ; 0 ; -- ; -- ; +; SIN ; Input ; 6 ; 0 ; -- ; -- ; ++---------+----------+---------------+---------------+-----------------------+-----+ + + ++-----------------------------------------------------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++-----------------------------------------------------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++-----------------------------------------------------------------+-------------------+---------+ +; A[1] ; ; ; +; - uart_16750:inst|Mux0~160 ; 1 ; 6 ; +; - uart_16750:inst|Mux0~162 ; 1 ; 6 ; +; - uart_16750:inst|Mux0~163 ; 1 ; 6 ; +; - uart_16750:inst|Mux0~164 ; 1 ; 6 ; +; - uart_16750:inst|Mux0~166 ; 1 ; 6 ; +; - uart_16750:inst|Mux1~88 ; 1 ; 6 ; +; - uart_16750:inst|Mux1~89 ; 1 ; 6 ; +; - uart_16750:inst|Mux2~106 ; 1 ; 6 ; +; - uart_16750:inst|Mux2~108 ; 1 ; 6 ; +; - uart_16750:inst|Mux3~430 ; 1 ; 6 ; +; - uart_16750:inst|Mux3~431 ; 1 ; 6 ; +; - uart_16750:inst|Mux3~434 ; 1 ; 6 ; +; - uart_16750:inst|Mux5~104 ; 1 ; 6 ; +; - uart_16750:inst|Mux5~105 ; 1 ; 6 ; +; - uart_16750:inst|iA[1] ; 1 ; 6 ; +; A[2] ; ; ; +; - uart_16750:inst|Mux0~160 ; 0 ; 6 ; +; - uart_16750:inst|Mux0~161 ; 0 ; 6 ; +; - uart_16750:inst|Mux0~163 ; 0 ; 6 ; +; - uart_16750:inst|Mux0~166 ; 0 ; 6 ; +; - uart_16750:inst|Mux1~87 ; 0 ; 6 ; +; - uart_16750:inst|Mux2~110 ; 0 ; 6 ; +; - uart_16750:inst|Mux3~435 ; 0 ; 6 ; +; - uart_16750:inst|Mux5~104 ; 0 ; 6 ; +; - uart_16750:inst|Mux5~105 ; 0 ; 6 ; +; - uart_16750:inst|iA[2] ; 0 ; 6 ; +; A[0] ; ; ; +; - uart_16750:inst|Mux0~167 ; 0 ; 6 ; +; - uart_16750:inst|Mux1~91 ; 0 ; 6 ; +; - uart_16750:inst|Mux2~106 ; 0 ; 6 ; +; - uart_16750:inst|Mux2~107 ; 0 ; 6 ; +; - uart_16750:inst|Mux2~108 ; 0 ; 6 ; +; - uart_16750:inst|Mux2~109 ; 0 ; 6 ; +; - uart_16750:inst|Mux3~430 ; 0 ; 6 ; +; - uart_16750:inst|Mux3~432 ; 0 ; 6 ; +; - uart_16750:inst|Mux3~433 ; 0 ; 6 ; +; - uart_16750:inst|Mux3~434 ; 0 ; 6 ; +; - uart_16750:inst|Mux4~37 ; 0 ; 6 ; +; - uart_16750:inst|Mux5~110 ; 0 ; 6 ; +; - uart_16750:inst|Mux6~37 ; 0 ; 6 ; +; - uart_16750:inst|Mux7~37 ; 0 ; 6 ; +; - uart_16750:inst|iA[0] ; 0 ; 6 ; +; CS ; ; ; +; - uart_16750:inst|UART_OUTREGS~0 ; 1 ; 4 ; +; - uart_16750:inst|iLCRWrite~27 ; 1 ; 4 ; +; - uart_16750:inst|iLCRWrite~29 ; 1 ; 4 ; +; - uart_16750:inst|iMSRRead~26 ; 1 ; 4 ; +; - uart_16750:inst|iCSWR ; 1 ; 4 ; +; RD ; ; ; +; - uart_16750:inst|UART_OUTREGS~0 ; 0 ; 6 ; +; - uart_16750:inst|iMSRRead~26 ; 0 ; 6 ; +; CLK ; ; ; +; WR ; ; ; +; - uart_16750:inst|iLCRWrite~27 ; 1 ; 4 ; +; - uart_16750:inst|iLCRWrite~29 ; 1 ; 4 ; +; - uart_16750:inst|iCSWR ; 1 ; 4 ; +; DIN[7] ; ; ; +; - uart_16750:inst|iDIN[7]~feeder ; 0 ; 6 ; +; DIN[0] ; ; ; +; - uart_16750:inst|iDIN[0]~feeder ; 0 ; 6 ; +; DIN[3] ; ; ; +; - uart_16750:inst|iDIN[3]~feeder ; 0 ; 6 ; +; DIN[4] ; ; ; +; - uart_16750:inst|iDIN[4] ; 0 ; 6 ; +; DIN[6] ; ; ; +; - uart_16750:inst|iDIN[6] ; 0 ; 6 ; +; DIN[2] ; ; ; +; - uart_16750:inst|iDIN[2]~feeder ; 0 ; 6 ; +; DIN[5] ; ; ; +; - uart_16750:inst|iDIN[5]~feeder ; 0 ; 6 ; +; DIN[1] ; ; ; +; - uart_16750:inst|iDIN[1] ; 0 ; 6 ; +; RSTN ; ; ; +; - inst4~feeder ; 0 ; 6 ; +; DCDN ; ; ; +; - uart_16750:inst|slib_input_sync:UART_IS_DCD|iD[0]~feeder ; 1 ; 6 ; +; RIN ; ; ; +; - uart_16750:inst|slib_input_sync:UART_IS_RI|iD[0] ; 1 ; 6 ; +; DSRN ; ; ; +; - uart_16750:inst|slib_input_sync:UART_IS_DSR|iD[0] ; 1 ; 6 ; +; CTSN ; ; ; +; - uart_16750:inst|slib_input_sync:UART_IS_CTS|iD[0]~feeder ; 0 ; 6 ; +; SIN ; ; ; +; - uart_16750:inst|slib_input_sync:UART_IS_SIN|iD[0] ; 0 ; 6 ; ++-----------------------------------------------------------------+-------------------+---------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Control Signals ; ++----------------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+-------------------------+--------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++----------------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+-------------------------+--------+----------------------+------------------+---------------------------+ +; CLK ; PIN_H15 ; 287 ; Clock ; yes ; Global Clock ; GCLK6 ; -- ; +; inst1 ; LCFF_X27_Y9_N17 ; 224 ; Async. clear ; yes ; Global Clock ; GCLK7 ; -- ; +; inst1 ; LCFF_X27_Y9_N17 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; +; inst5 ; LCFF_X27_Y9_N3 ; 1 ; Async. clear ; no ; -- ; -- ; -- ; +; uart_16750:inst|State~57 ; LCCOMB_X18_Y3_N4 ; 12 ; Clock enable ; no ; -- ; -- ; -- ; +; uart_16750:inst|UART_CTI~1 ; LCCOMB_X26_Y3_N4 ; 6 ; Sync. clear ; no ; -- ; -- ; -- ; +; uart_16750:inst|\UART_TXPROC:State.txstart ; LCFF_X21_Y6_N15 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; uart_16750:inst|iDLLWrite~31 ; LCCOMB_X25_Y5_N12 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; uart_16750:inst|iDLMWrite~32 ; LCCOMB_X24_Y5_N4 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; uart_16750:inst|iFCRWrite~27 ; LCCOMB_X24_Y5_N12 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; uart_16750:inst|iFCR_TXFIFOReset ; LCFF_X21_Y5_N13 ; 33 ; Sync. clear, Sync. load ; no ; -- ; -- ; -- ; +; uart_16750:inst|iFECounter[5]~214 ; LCCOMB_X22_Y3_N20 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; uart_16750:inst|iIERWrite~26 ; LCCOMB_X24_Y5_N2 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; uart_16750:inst|iLCRWrite~28 ; LCCOMB_X24_Y5_N20 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; uart_16750:inst|iMCRWrite~23 ; LCCOMB_X24_Y5_N22 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; uart_16750:inst|iRXFIFOClear ; LCFF_X21_Y4_N5 ; 41 ; Sync. clear, Sync. load ; no ; -- ; -- ; -- ; +; uart_16750:inst|iSCRWrite~35 ; LCCOMB_X24_Y5_N16 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; uart_16750:inst|slib_clock_div:UART_BG2|iQ ; LCFF_X20_Y4_N27 ; 14 ; Clock enable ; no ; -- ; -- ; -- ; +; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_c5b:rd_ptr_msb|_~2 ; LCCOMB_X26_Y7_N14 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_d5b:wr_ptr|_~2 ; LCCOMB_X27_Y6_N2 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_p57:usedw_counter|_~2 ; LCCOMB_X26_Y7_N20 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|rd_ptr_lsb~2 ; LCCOMB_X26_Y6_N30 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; +; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|valid_wreq ; LCCOMB_X26_Y6_N6 ; 12 ; Write enable ; no ; -- ; -- ; -- ; +; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_c5b:rd_ptr_msb|_~2 ; LCCOMB_X21_Y6_N18 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_d5b:wr_ptr|_~2 ; LCCOMB_X25_Y5_N20 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_p57:usedw_counter|_~2 ; LCCOMB_X25_Y5_N10 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|rd_ptr_lsb~2 ; LCCOMB_X21_Y6_N0 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; +; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|valid_wreq~186 ; LCCOMB_X25_Y5_N18 ; 11 ; Write enable ; no ; -- ; -- ; -- ; +; uart_16750:inst|uart_baudgen:UART_BG16|Equal0~179 ; LCCOMB_X20_Y4_N30 ; 17 ; Sync. clear ; no ; -- ; -- ; -- ; +; uart_16750:inst|uart_receiver:UART_RX|iDataCountInit ; LCCOMB_X20_Y3_N10 ; 12 ; Sync. clear ; no ; -- ; -- ; -- ; +; uart_16750:inst|uart_receiver:UART_RX|iFilterClear ; LCCOMB_X19_Y4_N14 ; 5 ; Sync. clear ; no ; -- ; -- ; -- ; +; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[3]~214 ; LCCOMB_X19_Y4_N12 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; uart_16750:inst|uart_transmitter:UART_TX|CState~1612 ; LCCOMB_X20_Y4_N22 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; ++----------------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+-------------------------+--------+----------------------+------------------+---------------------------+ + + ++---------------------------------------------------------------------------------------------------------+ +; Global & Other Fast Signals ; ++-------+-----------------+---------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++-------+-----------------+---------+----------------------+------------------+---------------------------+ +; CLK ; PIN_H15 ; 287 ; Global Clock ; GCLK6 ; -- ; +; inst1 ; LCFF_X27_Y9_N17 ; 224 ; Global Clock ; GCLK7 ; -- ; ++-------+-----------------+---------+----------------------+------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------+ +; Non-Global High Fan-Out Signals ; ++----------------------------------------------------------------------------------------------------------------------------+---------+ +; Name ; Fan-Out ; ++----------------------------------------------------------------------------------------------------------------------------+---------+ +; uart_16750:inst|iRXFIFOClear ; 41 ; +; ~GND ; 34 ; +; uart_16750:inst|iFCR_TXFIFOReset ; 33 ; +; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|empty_dff ; 22 ; +; uart_16750:inst|uart_baudgen:UART_BG16|Equal0~179 ; 17 ; +; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|empty_dff ; 17 ; +; A[0] ; 15 ; +; A[1] ; 15 ; +; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iQ ; 14 ; +; uart_16750:inst|slib_clock_div:UART_BG2|iQ ; 14 ; +; uart_16750:inst|Mux0~160 ; 14 ; +; uart_16750:inst|iRXFIFORead~50 ; 13 ; +; uart_16750:inst|iFCR_FIFOEnable ; 13 ; +; uart_16750:inst|uart_receiver:UART_RX|iDataCountInit ; 12 ; +; uart_16750:inst|State~57 ; 12 ; +; uart_16750:inst|uart_receiver:UART_RX|slib_counter:RX_BRC|iCounter[4] ; 12 ; +; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|valid_wreq ; 12 ; +; uart_16750:inst|iA[1] ; 12 ; +; uart_16750:inst|Mux5~105 ; 12 ; +; uart_16750:inst|iLCR[7] ; 12 ; +; uart_16750:inst|uart_receiver:UART_RX|CState.idle ; 11 ; +; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|valid_rreq ; 11 ; +; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|valid_wreq~186 ; 11 ; +; uart_16750:inst|iMCR[4] ; 11 ; +; uart_16750:inst|uart_receiver:UART_RX|iDataCount[1] ; 11 ; +; uart_16750:inst|uart_receiver:UART_RX|iDataCount[0] ; 11 ; +; A[2] ; 10 ; +; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|valid_rreq ; 10 ; +; uart_16750:inst|iTXFIFORead ; 10 ; +; uart_16750:inst|iDIN[0] ; 10 ; +; uart_16750:inst|iA[0] ; 10 ; +; uart_16750:inst|iLCR[1] ; 10 ; +; uart_16750:inst|uart_receiver:UART_RX|iDataCount[2] ; 10 ; +; uart_16750:inst|uart_receiver:UART_RX|RX_DATACOUNT~0 ; 9 ; +; uart_16750:inst|uart_transmitter:UART_TX|CState~1612 ; 9 ; +; uart_16750:inst|iDIN[1] ; 9 ; +; uart_16750:inst|iLCR[0] ; 9 ; +; uart_16750:inst|iDLMWrite~32 ; 8 ; +; uart_16750:inst|iDIN[2] ; 8 ; +; uart_16750:inst|iDLLWrite~31 ; 8 ; +; uart_16750:inst|iSCRWrite~35 ; 8 ; +; uart_16750:inst|iLCRWrite~28 ; 8 ; +; uart_16750:inst|iRXFIFOWrite ; 8 ; +; uart_16750:inst|Mux5~104 ; 8 ; +; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|full_dff ; 8 ; +; uart_16750:inst|iFECounter[5]~214 ; 7 ; +; uart_16750:inst|iDIN[5] ; 7 ; +; uart_16750:inst|iDIN[3] ; 7 ; +; uart_16750:inst|iA[2] ; 7 ; +; uart_16750:inst|uart_transmitter:UART_TX|CState.stop ; 7 ; ++----------------------------------------------------------------------------------------------------------------------------+---------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter RAM Summary ; ++------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+------------+ +; Name ; Type ; Mode ; Clock Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M4Ks ; MIF ; Location ; ++------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+------------+ +; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 64 ; 11 ; 64 ; 11 ; yes ; no ; yes ; no ; 704 ; 64 ; 11 ; 64 ; 11 ; 704 ; 1 ; None ; M4K_X23_Y3 ; +; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|altsyncram_t681:FIFOram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 64 ; 8 ; 64 ; 8 ; yes ; no ; yes ; yes ; 512 ; 64 ; 8 ; 64 ; 8 ; 512 ; 1 ; None ; M4K_X23_Y5 ; ++------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+------------+ +Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section. + + ++-----------------------------------------------------+ +; Interconnect Usage Summary ; ++----------------------------+------------------------+ +; Interconnect Resource Type ; Usage ; ++----------------------------+------------------------+ +; Block interconnects ; 556 / 15,666 ( 4 % ) ; +; C16 interconnects ; 4 / 812 ( < 1 % ) ; +; C4 interconnects ; 269 / 11,424 ( 2 % ) ; +; Direct links ; 112 / 15,666 ( < 1 % ) ; +; Global clocks ; 2 / 8 ( 25 % ) ; +; Local interconnects ; 293 / 4,608 ( 6 % ) ; +; R24 interconnects ; 3 / 652 ( < 1 % ) ; +; R4 interconnects ; 304 / 13,328 ( 2 % ) ; ++----------------------------+------------------------+ + + ++----------------------------------------------------------------------------+ +; LAB Logic Elements ; ++---------------------------------------------+------------------------------+ +; Number of Logic Elements (Average = 11.20) ; Number of LABs (Total = 40) ; ++---------------------------------------------+------------------------------+ +; 1 ; 7 ; +; 2 ; 0 ; +; 3 ; 1 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 1 ; +; 7 ; 1 ; +; 8 ; 1 ; +; 9 ; 1 ; +; 10 ; 1 ; +; 11 ; 1 ; +; 12 ; 2 ; +; 13 ; 2 ; +; 14 ; 2 ; +; 15 ; 11 ; +; 16 ; 9 ; ++---------------------------------------------+------------------------------+ + + ++-------------------------------------------------------------------+ +; LAB-wide Signals ; ++------------------------------------+------------------------------+ +; LAB-wide Signals (Average = 2.40) ; Number of LABs (Total = 40) ; ++------------------------------------+------------------------------+ +; 1 Async. clear ; 33 ; +; 1 Clock ; 39 ; +; 1 Clock enable ; 11 ; +; 1 Sync. clear ; 2 ; +; 1 Sync. load ; 3 ; +; 2 Clock enables ; 8 ; ++------------------------------------+------------------------------+ + + ++-----------------------------------------------------------------------------+ +; LAB Signals Sourced ; ++----------------------------------------------+------------------------------+ +; Number of Signals Sourced (Average = 18.07) ; Number of LABs (Total = 40) ; ++----------------------------------------------+------------------------------+ +; 0 ; 0 ; +; 1 ; 3 ; +; 2 ; 4 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 1 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 2 ; +; 13 ; 0 ; +; 14 ; 1 ; +; 15 ; 1 ; +; 16 ; 0 ; +; 17 ; 2 ; +; 18 ; 3 ; +; 19 ; 2 ; +; 20 ; 2 ; +; 21 ; 2 ; +; 22 ; 0 ; +; 23 ; 3 ; +; 24 ; 1 ; +; 25 ; 3 ; +; 26 ; 3 ; +; 27 ; 1 ; +; 28 ; 5 ; +; 29 ; 0 ; +; 30 ; 0 ; +; 31 ; 0 ; +; 32 ; 1 ; ++----------------------------------------------+------------------------------+ + + ++--------------------------------------------------------------------------------+ +; LAB Signals Sourced Out ; ++-------------------------------------------------+------------------------------+ +; Number of Signals Sourced Out (Average = 6.92) ; Number of LABs (Total = 40) ; ++-------------------------------------------------+------------------------------+ +; 0 ; 0 ; +; 1 ; 10 ; +; 2 ; 1 ; +; 3 ; 1 ; +; 4 ; 3 ; +; 5 ; 1 ; +; 6 ; 2 ; +; 7 ; 3 ; +; 8 ; 3 ; +; 9 ; 3 ; +; 10 ; 2 ; +; 11 ; 3 ; +; 12 ; 1 ; +; 13 ; 4 ; +; 14 ; 2 ; +; 15 ; 0 ; +; 16 ; 1 ; ++-------------------------------------------------+------------------------------+ + + ++-----------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++----------------------------------------------+------------------------------+ +; Number of Distinct Inputs (Average = 12.30) ; Number of LABs (Total = 40) ; ++----------------------------------------------+------------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 2 ; +; 3 ; 6 ; +; 4 ; 1 ; +; 5 ; 1 ; +; 6 ; 2 ; +; 7 ; 5 ; +; 8 ; 0 ; +; 9 ; 1 ; +; 10 ; 1 ; +; 11 ; 3 ; +; 12 ; 1 ; +; 13 ; 2 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 1 ; +; 17 ; 1 ; +; 18 ; 0 ; +; 19 ; 3 ; +; 20 ; 1 ; +; 21 ; 2 ; +; 22 ; 0 ; +; 23 ; 0 ; +; 24 ; 0 ; +; 25 ; 0 ; +; 26 ; 1 ; +; 27 ; 1 ; +; 28 ; 0 ; +; 29 ; 2 ; +; 30 ; 1 ; +; 31 ; 1 ; ++----------------------------------------------+------------------------------+ + + ++--------------------------------------------------------------------------------------+ +; Fitter Device Options ; ++----------------------------------------------+---------------------------------------+ +; Option ; Setting ; ++----------------------------------------------+---------------------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Active Serial ; +; Error detection CRC ; Off ; +; nCEO ; As output driving ground ; +; ASDO,nCSO ; As input tri-stated ; +; Reserve all unused pins ; As input tri-stated with weak pull-up ; +; Base pin-out file on sameframe device ; Off ; ++----------------------------------------------+---------------------------------------+ + + ++------------------------------------+ +; Operating Settings and Conditions ; ++---------------------------+--------+ +; Setting ; Value ; ++---------------------------+--------+ +; Nominal Core Voltage ; 1.20 V ; +; Low Junction Temperature ; 0 �C ; +; High Junction Temperature ; 85 �C ; ++---------------------------+--------+ + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Info: ******************************************************************* +Info: Running Quartus II Fitter + Info: Version 8.0 Build 215 05/29/2008 SJ Full Version + Info: Processing started: Tue Feb 17 23:02:32 2009 +Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off UART16750 -c UART16750 +Info: Selected device EP2C5F256C6 for design "UART16750" +Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices + Info: Device EP2C8F256C6 is compatible +Info: Fitter converted 3 user pins into dedicated programming pins + Info: Pin ~ASDO~ is reserved at location C3 + Info: Pin ~nCSO~ is reserved at location F4 + Info: Pin ~LVDS41p/nCEO~ is reserved at location N14 +Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements. +Info: Fitter is using the Classic Timing Analyzer +Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements +Info: Automatically promoted node CLK (placed in PIN H15 (CLK5, LVDSCLK2n, Input)) + Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G6 +Info: Automatically promoted node inst1 + Info: Automatically promoted destinations to use location or clock signal Global Clock + Info: Following destination nodes may be non-global or may not use global or regional clocks + Info: Destination node uart_16750:inst|iLSR_FIFOERR +Info: Starting register packing +Info: Finished register packing + Extra Info: Packed 8 registers into blocks of type EC +Info: Fitter preparation operations ending: elapsed time is 00:00:00 +Info: Fitter placement preparation operations beginning +Info: Fitter placement preparation operations ending: elapsed time is 00:00:01 +Info: Fitter placement operations beginning +Info: Fitter placement was successful +Info: Fitter placement operations ending: elapsed time is 00:00:00 +Info: Estimated most critical path is memory to pin delay of 10.082 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X23_Y3; Fanout = 1; MEM Node = 'uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a3~portb_address_reg5' + Info: 2: + IC(0.000 ns) + CELL(2.991 ns) = 2.991 ns; Loc. = M4K_X23_Y3; Fanout = 1; MEM Node = 'uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|q_b[3]' + Info: 3: + IC(0.316 ns) + CELL(0.420 ns) = 3.727 ns; Loc. = LAB_X24_Y3; Fanout = 1; COMB Node = 'uart_16750:inst|Mux4~35' + Info: 4: + IC(0.481 ns) + CELL(0.271 ns) = 4.479 ns; Loc. = LAB_X25_Y3; Fanout = 1; COMB Node = 'uart_16750:inst|Mux4~36' + Info: 5: + IC(0.415 ns) + CELL(0.150 ns) = 5.044 ns; Loc. = LAB_X25_Y3; Fanout = 1; COMB Node = 'uart_16750:inst|Mux4~37' + Info: 6: + IC(0.290 ns) + CELL(0.271 ns) = 5.605 ns; Loc. = LAB_X25_Y3; Fanout = 1; COMB Node = 'uart_16750:inst|Mux4~38' + Info: 7: + IC(1.489 ns) + CELL(2.988 ns) = 10.082 ns; Loc. = PIN_T11; Fanout = 0; PIN Node = 'DOUT[3]' + Info: Total cell delay = 7.091 ns ( 70.33 % ) + Info: Total interconnect delay = 2.991 ns ( 29.67 % ) +Info: Fitter routing operations beginning +Info: Average interconnect usage is 1% of the available device resources + Info: Peak interconnect usage is 3% of the available device resources in the region that extends from location X14_Y0 to location X28_Y14 +Info: Fitter routing operations ending: elapsed time is 00:00:00 +Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info: Optimizations that may affect the design's routability were skipped + Info: Optimizations that may affect the design's timing were skipped +Info: Started post-fitting delay annotation +Info: Delay annotation completed successfully +Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements. +Info: Generated suppressed messages file R:/uart16750/syn/Altera/CycloneII/UART16750.fit.smsg +Info: Quartus II Fitter was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 190 megabytes + Info: Processing ended: Tue Feb 17 23:02:36 2009 + Info: Elapsed time: 00:00:04 + Info: Total CPU time (on all processors): 00:00:04 + + ++----------------------------+ +; Fitter Suppressed Messages ; ++----------------------------+ +The suppressed messages can be found in R:/uart16750/syn/Altera/CycloneII/UART16750.fit.smsg. + +

trunk/syn/Altera/CycloneII/UART16750.fit.rpt Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/syn/Altera/CycloneII/UART16750.qpf =================================================================== --- trunk/syn/Altera/CycloneII/UART16750.qpf (nonexistent) +++ trunk/syn/Altera/CycloneII/UART16750.qpf (revision 16) @@ -0,0 +1,23 @@ +# Copyright (C) 1991-2008 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + + + +QUARTUS_VERSION = "8.0" +DATE = "09:40:30 January 16, 2009" + + +# Revisions + +PROJECT_REVISION = "UART16750"

trunk/syn/Altera/CycloneII/UART16750.qpf Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/syn/Altera/CycloneII/UART16750.tan.rpt =================================================================== --- trunk/syn/Altera/CycloneII/UART16750.tan.rpt (nonexistent) +++ trunk/syn/Altera/CycloneII/UART16750.tan.rpt (revision 16) @@ -0,0 +1,1279 @@ +Classic Timing Analyzer report for UART16750 +Tue Feb 17 23:02:39 2009 +Quartus II Version 8.0 Build 215 05/29/2008 SJ Full Version + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Timing Analyzer Summary + 3. Timing Analyzer Settings + 4. Clock Settings Summary + 5. Clock Setup: 'CLK' + 6. Clock Hold: 'CLK' + 7. tsu + 8. tco + 9. tpd + 10. th + 11. Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Timing Analyzer Summary ; ++------------------------------+-----------+----------------------------------+----------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------+------------+----------+--------------+ +; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ; ++------------------------------+-----------+----------------------------------+----------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------+------------+----------+--------------+ +; Worst-case tsu ; 2.580 ns ; 10.000 ns ; 7.420 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|empty_dff ; -- ; CLK ; 0 ; +; Worst-case tco ; 2.856 ns ; 15.000 ns ; 12.144 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg5 ; DOUT[3] ; CLK ; -- ; 0 ; +; Worst-case tpd ; N/A ; None ; 14.563 ns ; A[1] ; DOUT[3] ; -- ; -- ; 0 ; +; Worst-case th ; N/A ; None ; -2.602 ns ; WR ; uart_16750:inst|slib_edge_detect:UART_ED_WRITE|iDd ; -- ; CLK ; 0 ; +; Clock Setup: 'CLK' ; 22.036 ns ; 33.33 MHz ( period = 30.003 ns ) ; 125.52 MHz ( period = 7.967 ns ) ; uart_16750:inst|iTSR[3] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4] ; CLK ; CLK ; 0 ; +; Clock Hold: 'CLK' ; 0.391 ns ; 33.33 MHz ( period = 30.003 ns ) ; N/A ; uart_16750:inst|iLSR_FIFOERR ; uart_16750:inst|iLSR_FIFOERR ; CLK ; CLK ; 0 ; +; Total number of failed paths ; ; ; ; ; ; ; ; 0 ; ++------------------------------+-----------+----------------------------------+----------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------+------------+----------+--------------+ + + ++-------------------------------------------------------------------------------------------------------------------------+ +; Timing Analyzer Settings ; ++---------------------------------------------------------------------+--------------------+------+---------+-------------+ +; Option ; Setting ; From ; To ; Entity Name ; ++---------------------------------------------------------------------+--------------------+------+---------+-------------+ +; Device Name ; EP2C5F256C6 ; ; ; ; +; Timing Models ; Final ; ; ; ; +; Default hold multicycle ; Same as Multicycle ; ; ; ; +; Cut paths between unrelated clock domains ; On ; ; ; ; +; Cut off read during write signal paths ; On ; ; ; ; +; Cut off feedback from I/O pins ; On ; ; ; ; +; Report Combined Fast/Slow Timing ; Off ; ; ; ; +; tsu Requirement ; 10 ns ; ; ; ; +; tco Requirement ; 15 ns ; ; ; ; +; fmax Requirement ; 33.33 MHz ; ; ; ; +; Ignore Clock Settings ; Off ; ; ; ; +; Analyze latches as synchronous elements ; On ; ; ; ; +; Enable Recovery/Removal analysis ; Off ; ; ; ; +; Enable Clock Latency ; Off ; ; ; ; +; Use TimeQuest Timing Analyzer ; Off ; ; ; ; +; Number of source nodes to report per destination node ; 10 ; ; ; ; +; Number of destination nodes to report ; 10 ; ; ; ; +; Number of paths to report ; 200 ; ; ; ; +; Report Minimum Timing Checks ; Off ; ; ; ; +; Use Fast Timing Models ; Off ; ; ; ; +; Report IO Paths Separately ; Off ; ; ; ; +; Perform Multicorner Analysis ; On ; ; ; ; +; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ; +; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ; +; Clock Settings ; CLK ; ; CLK ; ; +; Output Pin Load ; 10 ; ; DDIS ; ; +; Output Pin Load ; 10 ; ; INT ; ; +; Output Pin Load ; 10 ; ; OUT1N ; ; +; Output Pin Load ; 10 ; ; OUT2N ; ; +; Output Pin Load ; 10 ; ; RTSN ; ; +; Output Pin Load ; 10 ; ; DTRN ; ; +; Output Pin Load ; 10 ; ; SOUT ; ; +; Output Pin Load ; 10 ; ; DOUT[7] ; ; +; Output Pin Load ; 10 ; ; DOUT[6] ; ; +; Output Pin Load ; 10 ; ; DOUT[5] ; ; +; Output Pin Load ; 10 ; ; DOUT[4] ; ; +; Output Pin Load ; 10 ; ; DOUT[3] ; ; +; Output Pin Load ; 10 ; ; DOUT[2] ; ; +; Output Pin Load ; 10 ; ; DOUT[1] ; ; +; Output Pin Load ; 10 ; ; DOUT[0] ; ; ++---------------------------------------------------------------------+--------------------+------+---------+-------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Settings Summary ; ++-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+ +; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ; ++-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+ +; CLK ; CLK ; User Pin ; 33.33 MHz ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ; ++-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Setup: 'CLK' ; ++-----------------------------------------+-----------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+ +; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ; ++-----------------------------------------+-----------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+ +; 22.036 ns ; 125.52 MHz ( period = 7.967 ns ) ; uart_16750:inst|iTSR[3] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 7.752 ns ; +; 22.054 ns ; 125.80 MHz ( period = 7.949 ns ) ; uart_16750:inst|iTSR[4] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 7.734 ns ; +; 22.107 ns ; 126.65 MHz ( period = 7.896 ns ) ; uart_16750:inst|iTSR[3] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[3] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 7.681 ns ; +; 22.125 ns ; 126.94 MHz ( period = 7.878 ns ) ; uart_16750:inst|iTSR[4] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[3] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 7.663 ns ; +; 22.178 ns ; 127.80 MHz ( period = 7.825 ns ) ; uart_16750:inst|iTSR[3] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[2] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 7.610 ns ; +; 22.196 ns ; 128.09 MHz ( period = 7.807 ns ) ; uart_16750:inst|iTSR[4] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[2] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 7.592 ns ; +; 22.206 ns ; 128.25 MHz ( period = 7.797 ns ) ; uart_16750:inst|iTSR[2] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 7.582 ns ; +; 22.249 ns ; 128.97 MHz ( period = 7.754 ns ) ; uart_16750:inst|iTSR[3] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[1] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 7.539 ns ; +; 22.267 ns ; 129.27 MHz ( period = 7.736 ns ) ; uart_16750:inst|iTSR[4] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[1] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 7.521 ns ; +; 22.277 ns ; 129.43 MHz ( period = 7.726 ns ) ; uart_16750:inst|iTSR[2] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[3] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 7.511 ns ; +; 22.348 ns ; 130.63 MHz ( period = 7.655 ns ) ; uart_16750:inst|iTSR[2] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[2] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 7.440 ns ; +; 22.405 ns ; 131.61 MHz ( period = 7.598 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg5 ; uart_16750:inst|iFECounter[6] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.333 ns ; +; 22.405 ns ; 131.61 MHz ( period = 7.598 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg4 ; uart_16750:inst|iFECounter[6] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.333 ns ; +; 22.405 ns ; 131.61 MHz ( period = 7.598 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg3 ; uart_16750:inst|iFECounter[6] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.333 ns ; +; 22.405 ns ; 131.61 MHz ( period = 7.598 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg2 ; uart_16750:inst|iFECounter[6] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.333 ns ; +; 22.405 ns ; 131.61 MHz ( period = 7.598 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg1 ; uart_16750:inst|iFECounter[6] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.333 ns ; +; 22.405 ns ; 131.61 MHz ( period = 7.598 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg0 ; uart_16750:inst|iFECounter[6] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.333 ns ; +; 22.419 ns ; 131.86 MHz ( period = 7.584 ns ) ; uart_16750:inst|iTSR[2] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[1] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 7.369 ns ; +; 22.476 ns ; 132.86 MHz ( period = 7.527 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg5 ; uart_16750:inst|iFECounter[5] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.262 ns ; +; 22.476 ns ; 132.86 MHz ( period = 7.527 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg4 ; uart_16750:inst|iFECounter[5] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.262 ns ; +; 22.476 ns ; 132.86 MHz ( period = 7.527 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg3 ; uart_16750:inst|iFECounter[5] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.262 ns ; +; 22.476 ns ; 132.86 MHz ( period = 7.527 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg2 ; uart_16750:inst|iFECounter[5] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.262 ns ; +; 22.476 ns ; 132.86 MHz ( period = 7.527 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg1 ; uart_16750:inst|iFECounter[5] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.262 ns ; +; 22.476 ns ; 132.86 MHz ( period = 7.527 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg0 ; uart_16750:inst|iFECounter[5] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.262 ns ; +; 22.547 ns ; 134.12 MHz ( period = 7.456 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg5 ; uart_16750:inst|iFECounter[4] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.191 ns ; +; 22.547 ns ; 134.12 MHz ( period = 7.456 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg4 ; uart_16750:inst|iFECounter[4] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.191 ns ; +; 22.547 ns ; 134.12 MHz ( period = 7.456 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg3 ; uart_16750:inst|iFECounter[4] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.191 ns ; +; 22.547 ns ; 134.12 MHz ( period = 7.456 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg2 ; uart_16750:inst|iFECounter[4] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.191 ns ; +; 22.547 ns ; 134.12 MHz ( period = 7.456 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg1 ; uart_16750:inst|iFECounter[4] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.191 ns ; +; 22.547 ns ; 134.12 MHz ( period = 7.456 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg0 ; uart_16750:inst|iFECounter[4] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.191 ns ; +; 22.618 ns ; 135.41 MHz ( period = 7.385 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg5 ; uart_16750:inst|iFECounter[3] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.120 ns ; +; 22.618 ns ; 135.41 MHz ( period = 7.385 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg4 ; uart_16750:inst|iFECounter[3] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.120 ns ; +; 22.618 ns ; 135.41 MHz ( period = 7.385 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg3 ; uart_16750:inst|iFECounter[3] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.120 ns ; +; 22.618 ns ; 135.41 MHz ( period = 7.385 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg2 ; uart_16750:inst|iFECounter[3] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.120 ns ; +; 22.618 ns ; 135.41 MHz ( period = 7.385 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg1 ; uart_16750:inst|iFECounter[3] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.120 ns ; +; 22.618 ns ; 135.41 MHz ( period = 7.385 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg0 ; uart_16750:inst|iFECounter[3] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.120 ns ; +; 22.632 ns ; 135.67 MHz ( period = 7.371 ns ) ; uart_16750:inst|iTSR[3] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[0] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 7.156 ns ; +; 22.650 ns ; 136.00 MHz ( period = 7.353 ns ) ; uart_16750:inst|iTSR[4] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[0] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 7.138 ns ; +; 22.689 ns ; 136.72 MHz ( period = 7.314 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg5 ; uart_16750:inst|iFECounter[2] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.049 ns ; +; 22.689 ns ; 136.72 MHz ( period = 7.314 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg4 ; uart_16750:inst|iFECounter[2] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.049 ns ; +; 22.689 ns ; 136.72 MHz ( period = 7.314 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg3 ; uart_16750:inst|iFECounter[2] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.049 ns ; +; 22.689 ns ; 136.72 MHz ( period = 7.314 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg2 ; uart_16750:inst|iFECounter[2] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.049 ns ; +; 22.689 ns ; 136.72 MHz ( period = 7.314 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg1 ; uart_16750:inst|iFECounter[2] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.049 ns ; +; 22.689 ns ; 136.72 MHz ( period = 7.314 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg0 ; uart_16750:inst|iFECounter[2] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 7.049 ns ; +; 22.707 ns ; 137.06 MHz ( period = 7.296 ns ) ; uart_16750:inst|iTSR[0] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 7.081 ns ; +; 22.733 ns ; 137.55 MHz ( period = 7.270 ns ) ; uart_16750:inst|iLCR[0] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4] ; CLK ; CLK ; 30.003 ns ; 29.781 ns ; 7.048 ns ; +; 22.778 ns ; 138.41 MHz ( period = 7.225 ns ) ; uart_16750:inst|iTSR[0] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[3] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 7.010 ns ; +; 22.802 ns ; 138.87 MHz ( period = 7.201 ns ) ; uart_16750:inst|iTSR[2] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[0] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 6.986 ns ; +; 22.804 ns ; 138.91 MHz ( period = 7.199 ns ) ; uart_16750:inst|iLCR[0] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[3] ; CLK ; CLK ; 30.003 ns ; 29.781 ns ; 6.977 ns ; +; 22.820 ns ; 139.22 MHz ( period = 7.183 ns ) ; uart_16750:inst|iTSR[5] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 6.968 ns ; +; 22.840 ns ; 139.61 MHz ( period = 7.163 ns ) ; uart_16750:inst|iLCR[4] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4] ; CLK ; CLK ; 30.003 ns ; 29.783 ns ; 6.943 ns ; +; 22.849 ns ; 139.78 MHz ( period = 7.154 ns ) ; uart_16750:inst|iTSR[0] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[2] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 6.939 ns ; +; 22.875 ns ; 140.29 MHz ( period = 7.128 ns ) ; uart_16750:inst|iLCR[0] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[2] ; CLK ; CLK ; 30.003 ns ; 29.781 ns ; 6.906 ns ; +; 22.891 ns ; 140.61 MHz ( period = 7.112 ns ) ; uart_16750:inst|iTSR[5] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[3] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 6.897 ns ; +; 22.911 ns ; 141.00 MHz ( period = 7.092 ns ) ; uart_16750:inst|iLCR[4] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[3] ; CLK ; CLK ; 30.003 ns ; 29.783 ns ; 6.872 ns ; +; 22.920 ns ; 141.18 MHz ( period = 7.083 ns ) ; uart_16750:inst|iTSR[0] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[1] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 6.868 ns ; +; 22.946 ns ; 141.70 MHz ( period = 7.057 ns ) ; uart_16750:inst|iLCR[0] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[1] ; CLK ; CLK ; 30.003 ns ; 29.781 ns ; 6.835 ns ; +; 22.960 ns ; 141.98 MHz ( period = 7.043 ns ) ; uart_16750:inst|iTSR[1] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 6.828 ns ; +; 22.962 ns ; 142.03 MHz ( period = 7.041 ns ) ; uart_16750:inst|iTSR[5] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[2] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 6.826 ns ; +; 22.982 ns ; 142.43 MHz ( period = 7.021 ns ) ; uart_16750:inst|iLCR[4] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[2] ; CLK ; CLK ; 30.003 ns ; 29.783 ns ; 6.801 ns ; +; 23.031 ns ; 143.43 MHz ( period = 6.972 ns ) ; uart_16750:inst|iTSR[1] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[3] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 6.757 ns ; +; 23.033 ns ; 143.47 MHz ( period = 6.970 ns ) ; uart_16750:inst|iTSR[5] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[1] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 6.755 ns ; +; 23.053 ns ; 143.88 MHz ( period = 6.950 ns ) ; uart_16750:inst|iLCR[4] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[1] ; CLK ; CLK ; 30.003 ns ; 29.783 ns ; 6.730 ns ; +; 23.075 ns ; 144.34 MHz ( period = 6.928 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg5 ; uart_16750:inst|iFECounter[1] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 6.663 ns ; +; 23.075 ns ; 144.34 MHz ( period = 6.928 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg4 ; uart_16750:inst|iFECounter[1] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 6.663 ns ; +; 23.075 ns ; 144.34 MHz ( period = 6.928 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg3 ; uart_16750:inst|iFECounter[1] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 6.663 ns ; +; 23.075 ns ; 144.34 MHz ( period = 6.928 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg2 ; uart_16750:inst|iFECounter[1] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 6.663 ns ; +; 23.075 ns ; 144.34 MHz ( period = 6.928 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg1 ; uart_16750:inst|iFECounter[1] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 6.663 ns ; +; 23.075 ns ; 144.34 MHz ( period = 6.928 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg0 ; uart_16750:inst|iFECounter[1] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 6.663 ns ; +; 23.102 ns ; 144.91 MHz ( period = 6.901 ns ) ; uart_16750:inst|iTSR[1] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[2] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 6.686 ns ; +; 23.147 ns ; 145.86 MHz ( period = 6.856 ns ) ; uart_16750:inst|iTSR[7] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 6.641 ns ; +; 23.155 ns ; 146.03 MHz ( period = 6.848 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg5 ; uart_16750:inst|iFECounter[0] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 6.583 ns ; +; 23.155 ns ; 146.03 MHz ( period = 6.848 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg4 ; uart_16750:inst|iFECounter[0] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 6.583 ns ; +; 23.155 ns ; 146.03 MHz ( period = 6.848 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg3 ; uart_16750:inst|iFECounter[0] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 6.583 ns ; +; 23.155 ns ; 146.03 MHz ( period = 6.848 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg2 ; uart_16750:inst|iFECounter[0] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 6.583 ns ; +; 23.155 ns ; 146.03 MHz ( period = 6.848 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg1 ; uart_16750:inst|iFECounter[0] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 6.583 ns ; +; 23.155 ns ; 146.03 MHz ( period = 6.848 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg0 ; uart_16750:inst|iFECounter[0] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 6.583 ns ; +; 23.173 ns ; 146.41 MHz ( period = 6.830 ns ) ; uart_16750:inst|iTSR[1] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[1] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 6.615 ns ; +; 23.218 ns ; 147.38 MHz ( period = 6.785 ns ) ; uart_16750:inst|iTSR[7] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[3] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 6.570 ns ; +; 23.289 ns ; 148.94 MHz ( period = 6.714 ns ) ; uart_16750:inst|iTSR[7] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[2] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 6.499 ns ; +; 23.303 ns ; 149.25 MHz ( period = 6.700 ns ) ; uart_16750:inst|iTSR[0] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[0] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 6.485 ns ; +; 23.329 ns ; 149.84 MHz ( period = 6.674 ns ) ; uart_16750:inst|iLCR[0] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[0] ; CLK ; CLK ; 30.003 ns ; 29.781 ns ; 6.452 ns ; +; 23.360 ns ; 150.53 MHz ( period = 6.643 ns ) ; uart_16750:inst|iTSR[7] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[1] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 6.428 ns ; +; 23.416 ns ; 151.81 MHz ( period = 6.587 ns ) ; uart_16750:inst|iTSR[5] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[0] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 6.372 ns ; +; 23.436 ns ; 152.28 MHz ( period = 6.567 ns ) ; uart_16750:inst|iLCR[4] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[0] ; CLK ; CLK ; 30.003 ns ; 29.783 ns ; 6.347 ns ; +; 23.556 ns ; 155.11 MHz ( period = 6.447 ns ) ; uart_16750:inst|iTSR[1] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[0] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 6.232 ns ; +; 23.616 ns ; 156.57 MHz ( period = 6.387 ns ) ; uart_16750:inst|iLCR[5] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4] ; CLK ; CLK ; 30.003 ns ; 29.782 ns ; 6.166 ns ; +; 23.630 ns ; 156.91 MHz ( period = 6.373 ns ) ; uart_16750:inst|iTSR[3] ; uart_16750:inst|uart_receiver:UART_RX|CState.mwait ; CLK ; CLK ; 30.003 ns ; 29.792 ns ; 6.162 ns ; +; 23.648 ns ; 157.36 MHz ( period = 6.355 ns ) ; uart_16750:inst|iTSR[4] ; uart_16750:inst|uart_receiver:UART_RX|CState.mwait ; CLK ; CLK ; 30.003 ns ; 29.792 ns ; 6.144 ns ; +; 23.687 ns ; 158.33 MHz ( period = 6.316 ns ) ; uart_16750:inst|iLCR[5] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[3] ; CLK ; CLK ; 30.003 ns ; 29.782 ns ; 6.095 ns ; +; 23.695 ns ; 158.53 MHz ( period = 6.308 ns ) ; uart_16750:inst|iTSR[3] ; uart_16750:inst|SOUT ; CLK ; CLK ; 30.003 ns ; 29.803 ns ; 6.108 ns ; +; 23.704 ns ; 158.76 MHz ( period = 6.299 ns ) ; uart_16750:inst|iLCR[1] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4] ; CLK ; CLK ; 30.003 ns ; 29.783 ns ; 6.079 ns ; +; 23.713 ns ; 158.98 MHz ( period = 6.290 ns ) ; uart_16750:inst|iTSR[4] ; uart_16750:inst|SOUT ; CLK ; CLK ; 30.003 ns ; 29.803 ns ; 6.090 ns ; +; 23.743 ns ; 159.74 MHz ( period = 6.260 ns ) ; uart_16750:inst|iTSR[7] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[0] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 6.045 ns ; +; 23.758 ns ; 160.13 MHz ( period = 6.245 ns ) ; uart_16750:inst|iLCR[5] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[2] ; CLK ; CLK ; 30.003 ns ; 29.782 ns ; 6.024 ns ; +; 23.775 ns ; 160.57 MHz ( period = 6.228 ns ) ; uart_16750:inst|iLCR[1] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[3] ; CLK ; CLK ; 30.003 ns ; 29.783 ns ; 6.008 ns ; +; 23.796 ns ; 161.11 MHz ( period = 6.207 ns ) ; uart_16750:inst|iTSR[6] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 5.992 ns ; +; 23.800 ns ; 161.21 MHz ( period = 6.203 ns ) ; uart_16750:inst|iTSR[2] ; uart_16750:inst|uart_receiver:UART_RX|CState.mwait ; CLK ; CLK ; 30.003 ns ; 29.792 ns ; 5.992 ns ; +; 23.829 ns ; 161.97 MHz ( period = 6.174 ns ) ; uart_16750:inst|iLCR[5] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[1] ; CLK ; CLK ; 30.003 ns ; 29.782 ns ; 5.953 ns ; +; 23.846 ns ; 162.42 MHz ( period = 6.157 ns ) ; uart_16750:inst|iLCR[1] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[2] ; CLK ; CLK ; 30.003 ns ; 29.783 ns ; 5.937 ns ; +; 23.865 ns ; 162.92 MHz ( period = 6.138 ns ) ; uart_16750:inst|iTSR[2] ; uart_16750:inst|SOUT ; CLK ; CLK ; 30.003 ns ; 29.803 ns ; 5.938 ns ; +; 23.867 ns ; 162.97 MHz ( period = 6.136 ns ) ; uart_16750:inst|iTSR[6] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[3] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 5.921 ns ; +; 23.875 ns ; 163.19 MHz ( period = 6.128 ns ) ; uart_16750:inst|iTSR[3] ; uart_16750:inst|uart_receiver:UART_RX|CState.start ; CLK ; CLK ; 30.003 ns ; 29.792 ns ; 5.917 ns ; +; 23.875 ns ; 163.19 MHz ( period = 6.128 ns ) ; uart_16750:inst|iTSR[3] ; uart_16750:inst|uart_receiver:UART_RX|CState.idle ; CLK ; CLK ; 30.003 ns ; 29.792 ns ; 5.917 ns ; +; 23.893 ns ; 163.67 MHz ( period = 6.110 ns ) ; uart_16750:inst|iTSR[4] ; uart_16750:inst|uart_receiver:UART_RX|CState.start ; CLK ; CLK ; 30.003 ns ; 29.792 ns ; 5.899 ns ; +; 23.893 ns ; 163.67 MHz ( period = 6.110 ns ) ; uart_16750:inst|iTSR[4] ; uart_16750:inst|uart_receiver:UART_RX|CState.idle ; CLK ; CLK ; 30.003 ns ; 29.792 ns ; 5.899 ns ; +; 23.917 ns ; 164.31 MHz ( period = 6.086 ns ) ; uart_16750:inst|iLCR[1] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[1] ; CLK ; CLK ; 30.003 ns ; 29.783 ns ; 5.866 ns ; +; 23.938 ns ; 164.88 MHz ( period = 6.065 ns ) ; uart_16750:inst|iTSR[6] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[2] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 5.850 ns ; +; 23.942 ns ; 164.99 MHz ( period = 6.061 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.bit7 ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4] ; CLK ; CLK ; 30.003 ns ; 29.784 ns ; 5.842 ns ; +; 23.970 ns ; 165.76 MHz ( period = 6.033 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg5 ; uart_16750:inst|iLSR_BI ; CLK ; CLK ; 30.003 ns ; 29.739 ns ; 5.769 ns ; +; 23.970 ns ; 165.76 MHz ( period = 6.033 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg4 ; uart_16750:inst|iLSR_BI ; CLK ; CLK ; 30.003 ns ; 29.739 ns ; 5.769 ns ; +; 23.970 ns ; 165.76 MHz ( period = 6.033 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg3 ; uart_16750:inst|iLSR_BI ; CLK ; CLK ; 30.003 ns ; 29.739 ns ; 5.769 ns ; +; 23.970 ns ; 165.76 MHz ( period = 6.033 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg2 ; uart_16750:inst|iLSR_BI ; CLK ; CLK ; 30.003 ns ; 29.739 ns ; 5.769 ns ; +; 23.970 ns ; 165.76 MHz ( period = 6.033 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg1 ; uart_16750:inst|iLSR_BI ; CLK ; CLK ; 30.003 ns ; 29.739 ns ; 5.769 ns ; +; 23.970 ns ; 165.76 MHz ( period = 6.033 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg0 ; uart_16750:inst|iLSR_BI ; CLK ; CLK ; 30.003 ns ; 29.739 ns ; 5.769 ns ; +; 23.993 ns ; 166.39 MHz ( period = 6.010 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.par ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4] ; CLK ; CLK ; 30.003 ns ; 29.786 ns ; 5.793 ns ; +; 24.009 ns ; 166.83 MHz ( period = 5.994 ns ) ; uart_16750:inst|iTSR[6] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[1] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 5.779 ns ; +; 24.013 ns ; 166.94 MHz ( period = 5.990 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.bit7 ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[3] ; CLK ; CLK ; 30.003 ns ; 29.784 ns ; 5.771 ns ; +; 24.029 ns ; 167.39 MHz ( period = 5.974 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.stop2 ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4] ; CLK ; CLK ; 30.003 ns ; 29.786 ns ; 5.757 ns ; +; 24.045 ns ; 167.84 MHz ( period = 5.958 ns ) ; uart_16750:inst|iTSR[2] ; uart_16750:inst|uart_receiver:UART_RX|CState.start ; CLK ; CLK ; 30.003 ns ; 29.792 ns ; 5.747 ns ; +; 24.045 ns ; 167.84 MHz ( period = 5.958 ns ) ; uart_16750:inst|iTSR[2] ; uart_16750:inst|uart_receiver:UART_RX|CState.idle ; CLK ; CLK ; 30.003 ns ; 29.792 ns ; 5.747 ns ; +; 24.064 ns ; 168.38 MHz ( period = 5.939 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.par ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[3] ; CLK ; CLK ; 30.003 ns ; 29.786 ns ; 5.722 ns ; +; 24.084 ns ; 168.95 MHz ( period = 5.919 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.bit7 ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[2] ; CLK ; CLK ; 30.003 ns ; 29.784 ns ; 5.700 ns ; +; 24.099 ns ; 169.38 MHz ( period = 5.904 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.idle ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4] ; CLK ; CLK ; 30.003 ns ; 29.784 ns ; 5.685 ns ; +; 24.100 ns ; 169.41 MHz ( period = 5.903 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.stop2 ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[3] ; CLK ; CLK ; 30.003 ns ; 29.786 ns ; 5.686 ns ; +; 24.135 ns ; 170.42 MHz ( period = 5.868 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.par ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[2] ; CLK ; CLK ; 30.003 ns ; 29.786 ns ; 5.651 ns ; +; 24.143 ns ; 170.65 MHz ( period = 5.860 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_p57:usedw_counter|safe_q[3] ; uart_16750:inst|uart_interrupt:UART_IIC|iIIR[0] ; CLK ; CLK ; 30.003 ns ; 29.789 ns ; 5.646 ns ; +; 24.155 ns ; 171.00 MHz ( period = 5.848 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.bit7 ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[1] ; CLK ; CLK ; 30.003 ns ; 29.784 ns ; 5.629 ns ; +; 24.170 ns ; 171.44 MHz ( period = 5.833 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.idle ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[3] ; CLK ; CLK ; 30.003 ns ; 29.784 ns ; 5.614 ns ; +; 24.171 ns ; 171.47 MHz ( period = 5.832 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.stop2 ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[2] ; CLK ; CLK ; 30.003 ns ; 29.786 ns ; 5.615 ns ; +; 24.179 ns ; 171.70 MHz ( period = 5.824 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg5 ; uart_16750:inst|iLSR_PE ; CLK ; CLK ; 30.003 ns ; 29.739 ns ; 5.560 ns ; +; 24.179 ns ; 171.70 MHz ( period = 5.824 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg4 ; uart_16750:inst|iLSR_PE ; CLK ; CLK ; 30.003 ns ; 29.739 ns ; 5.560 ns ; +; 24.179 ns ; 171.70 MHz ( period = 5.824 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg3 ; uart_16750:inst|iLSR_PE ; CLK ; CLK ; 30.003 ns ; 29.739 ns ; 5.560 ns ; +; 24.179 ns ; 171.70 MHz ( period = 5.824 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg2 ; uart_16750:inst|iLSR_PE ; CLK ; CLK ; 30.003 ns ; 29.739 ns ; 5.560 ns ; +; 24.179 ns ; 171.70 MHz ( period = 5.824 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg1 ; uart_16750:inst|iLSR_PE ; CLK ; CLK ; 30.003 ns ; 29.739 ns ; 5.560 ns ; +; 24.179 ns ; 171.70 MHz ( period = 5.824 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg0 ; uart_16750:inst|iLSR_PE ; CLK ; CLK ; 30.003 ns ; 29.739 ns ; 5.560 ns ; +; 24.206 ns ; 172.50 MHz ( period = 5.797 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.par ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[1] ; CLK ; CLK ; 30.003 ns ; 29.786 ns ; 5.580 ns ; +; 24.212 ns ; 172.68 MHz ( period = 5.791 ns ) ; uart_16750:inst|iLCR[5] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[0] ; CLK ; CLK ; 30.003 ns ; 29.782 ns ; 5.570 ns ; +; 24.241 ns ; 173.55 MHz ( period = 5.762 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.idle ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[2] ; CLK ; CLK ; 30.003 ns ; 29.784 ns ; 5.543 ns ; +; 24.242 ns ; 173.58 MHz ( period = 5.761 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.stop2 ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[1] ; CLK ; CLK ; 30.003 ns ; 29.786 ns ; 5.544 ns ; +; 24.300 ns ; 175.35 MHz ( period = 5.703 ns ) ; uart_16750:inst|iLCR[1] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[0] ; CLK ; CLK ; 30.003 ns ; 29.783 ns ; 5.483 ns ; +; 24.301 ns ; 175.38 MHz ( period = 5.702 ns ) ; uart_16750:inst|iTSR[0] ; uart_16750:inst|uart_receiver:UART_RX|CState.mwait ; CLK ; CLK ; 30.003 ns ; 29.792 ns ; 5.491 ns ; +; 24.312 ns ; 175.72 MHz ( period = 5.691 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.idle ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[1] ; CLK ; CLK ; 30.003 ns ; 29.784 ns ; 5.472 ns ; +; 24.327 ns ; 176.18 MHz ( period = 5.676 ns ) ; uart_16750:inst|iLCR[0] ; uart_16750:inst|uart_receiver:UART_RX|CState.mwait ; CLK ; CLK ; 30.003 ns ; 29.785 ns ; 5.458 ns ; +; 24.338 ns ; 176.52 MHz ( period = 5.665 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.stop ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4] ; CLK ; CLK ; 30.003 ns ; 29.786 ns ; 5.448 ns ; +; 24.354 ns ; 177.02 MHz ( period = 5.649 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.bit4 ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4] ; CLK ; CLK ; 30.003 ns ; 29.784 ns ; 5.430 ns ; +; 24.366 ns ; 177.40 MHz ( period = 5.637 ns ) ; uart_16750:inst|iTSR[0] ; uart_16750:inst|SOUT ; CLK ; CLK ; 30.003 ns ; 29.803 ns ; 5.437 ns ; +; 24.392 ns ; 178.22 MHz ( period = 5.611 ns ) ; uart_16750:inst|iLCR[0] ; uart_16750:inst|SOUT ; CLK ; CLK ; 30.003 ns ; 29.796 ns ; 5.404 ns ; +; 24.392 ns ; 178.22 MHz ( period = 5.611 ns ) ; uart_16750:inst|iTSR[6] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[0] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 5.396 ns ; +; 24.409 ns ; 178.76 MHz ( period = 5.594 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.stop ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[3] ; CLK ; CLK ; 30.003 ns ; 29.786 ns ; 5.377 ns ; +; 24.414 ns ; 178.92 MHz ( period = 5.589 ns ) ; uart_16750:inst|iTSR[5] ; uart_16750:inst|uart_receiver:UART_RX|CState.mwait ; CLK ; CLK ; 30.003 ns ; 29.792 ns ; 5.378 ns ; +; 24.425 ns ; 179.28 MHz ( period = 5.578 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.bit4 ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[3] ; CLK ; CLK ; 30.003 ns ; 29.784 ns ; 5.359 ns ; +; 24.434 ns ; 179.57 MHz ( period = 5.569 ns ) ; uart_16750:inst|iLCR[4] ; uart_16750:inst|uart_receiver:UART_RX|CState.mwait ; CLK ; CLK ; 30.003 ns ; 29.787 ns ; 5.353 ns ; +; 24.440 ns ; 179.76 MHz ( period = 5.563 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_p57:usedw_counter|safe_q[1] ; uart_16750:inst|uart_interrupt:UART_IIC|iIIR[0] ; CLK ; CLK ; 30.003 ns ; 29.789 ns ; 5.349 ns ; +; 24.463 ns ; 180.51 MHz ( period = 5.540 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.bit5 ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4] ; CLK ; CLK ; 30.003 ns ; 29.784 ns ; 5.321 ns ; +; 24.479 ns ; 181.03 MHz ( period = 5.524 ns ) ; uart_16750:inst|iTSR[5] ; uart_16750:inst|SOUT ; CLK ; CLK ; 30.003 ns ; 29.803 ns ; 5.324 ns ; +; 24.480 ns ; 181.06 MHz ( period = 5.523 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.stop ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[2] ; CLK ; CLK ; 30.003 ns ; 29.786 ns ; 5.306 ns ; +; 24.496 ns ; 181.59 MHz ( period = 5.507 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.bit4 ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[2] ; CLK ; CLK ; 30.003 ns ; 29.784 ns ; 5.288 ns ; +; 24.499 ns ; 181.69 MHz ( period = 5.504 ns ) ; uart_16750:inst|iLCR[4] ; uart_16750:inst|SOUT ; CLK ; CLK ; 30.003 ns ; 29.798 ns ; 5.299 ns ; +; 24.534 ns ; 182.85 MHz ( period = 5.469 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.bit5 ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[3] ; CLK ; CLK ; 30.003 ns ; 29.784 ns ; 5.250 ns ; +; 24.538 ns ; 182.98 MHz ( period = 5.465 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.bit7 ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[0] ; CLK ; CLK ; 30.003 ns ; 29.784 ns ; 5.246 ns ; +; 24.546 ns ; 183.25 MHz ( period = 5.457 ns ) ; uart_16750:inst|iTSR[0] ; uart_16750:inst|uart_receiver:UART_RX|CState.start ; CLK ; CLK ; 30.003 ns ; 29.792 ns ; 5.246 ns ; +; 24.546 ns ; 183.25 MHz ( period = 5.457 ns ) ; uart_16750:inst|iTSR[0] ; uart_16750:inst|uart_receiver:UART_RX|CState.idle ; CLK ; CLK ; 30.003 ns ; 29.792 ns ; 5.246 ns ; +; 24.551 ns ; 183.42 MHz ( period = 5.452 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.stop ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[1] ; CLK ; CLK ; 30.003 ns ; 29.786 ns ; 5.235 ns ; +; 24.554 ns ; 183.52 MHz ( period = 5.449 ns ) ; uart_16750:inst|iTSR[1] ; uart_16750:inst|uart_receiver:UART_RX|CState.mwait ; CLK ; CLK ; 30.003 ns ; 29.792 ns ; 5.238 ns ; +; 24.567 ns ; 183.96 MHz ( period = 5.436 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.bit4 ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[1] ; CLK ; CLK ; 30.003 ns ; 29.784 ns ; 5.217 ns ; +; 24.568 ns ; 183.99 MHz ( period = 5.435 ns ) ; uart_16750:inst|iFCR_RXTrigger[0] ; uart_16750:inst|uart_interrupt:UART_IIC|iIIR[0] ; CLK ; CLK ; 30.003 ns ; 29.790 ns ; 5.222 ns ; +; 24.572 ns ; 184.13 MHz ( period = 5.431 ns ) ; uart_16750:inst|iLCR[0] ; uart_16750:inst|uart_receiver:UART_RX|CState.start ; CLK ; CLK ; 30.003 ns ; 29.785 ns ; 5.213 ns ; +; 24.572 ns ; 184.13 MHz ( period = 5.431 ns ) ; uart_16750:inst|iLCR[0] ; uart_16750:inst|uart_receiver:UART_RX|CState.idle ; CLK ; CLK ; 30.003 ns ; 29.785 ns ; 5.213 ns ; +; 24.589 ns ; 184.71 MHz ( period = 5.414 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.par ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[0] ; CLK ; CLK ; 30.003 ns ; 29.786 ns ; 5.197 ns ; +; 24.605 ns ; 185.25 MHz ( period = 5.398 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.bit5 ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[2] ; CLK ; CLK ; 30.003 ns ; 29.784 ns ; 5.179 ns ; +; 24.619 ns ; 185.74 MHz ( period = 5.384 ns ) ; uart_16750:inst|iTSR[1] ; uart_16750:inst|SOUT ; CLK ; CLK ; 30.003 ns ; 29.803 ns ; 5.184 ns ; +; 24.625 ns ; 185.94 MHz ( period = 5.378 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.stop2 ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[0] ; CLK ; CLK ; 30.003 ns ; 29.786 ns ; 5.161 ns ; +; 24.659 ns ; 187.13 MHz ( period = 5.344 ns ) ; uart_16750:inst|iTSR[5] ; uart_16750:inst|uart_receiver:UART_RX|CState.start ; CLK ; CLK ; 30.003 ns ; 29.792 ns ; 5.133 ns ; +; 24.659 ns ; 187.13 MHz ( period = 5.344 ns ) ; uart_16750:inst|iTSR[5] ; uart_16750:inst|uart_receiver:UART_RX|CState.idle ; CLK ; CLK ; 30.003 ns ; 29.792 ns ; 5.133 ns ; +; 24.671 ns ; 187.55 MHz ( period = 5.332 ns ) ; uart_16750:inst|slib_edge_detect:UART_ED_WRITE|iDd ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|empty_dff ; CLK ; CLK ; 30.003 ns ; 29.783 ns ; 5.112 ns ; +; 24.676 ns ; 187.72 MHz ( period = 5.327 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.bit5 ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[1] ; CLK ; CLK ; 30.003 ns ; 29.784 ns ; 5.108 ns ; +; 24.679 ns ; 187.83 MHz ( period = 5.324 ns ) ; uart_16750:inst|iLCR[4] ; uart_16750:inst|uart_receiver:UART_RX|CState.start ; CLK ; CLK ; 30.003 ns ; 29.787 ns ; 5.108 ns ; +; 24.679 ns ; 187.83 MHz ( period = 5.324 ns ) ; uart_16750:inst|iLCR[4] ; uart_16750:inst|uart_receiver:UART_RX|CState.idle ; CLK ; CLK ; 30.003 ns ; 29.787 ns ; 5.108 ns ; +; 24.691 ns ; 188.25 MHz ( period = 5.312 ns ) ; uart_16750:inst|iDLM[3] ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[15] ; CLK ; CLK ; 30.003 ns ; 29.776 ns ; 5.085 ns ; +; 24.691 ns ; 188.25 MHz ( period = 5.312 ns ) ; uart_16750:inst|iDLM[3] ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[3] ; CLK ; CLK ; 30.003 ns ; 29.776 ns ; 5.085 ns ; +; 24.691 ns ; 188.25 MHz ( period = 5.312 ns ) ; uart_16750:inst|iDLM[3] ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[12] ; CLK ; CLK ; 30.003 ns ; 29.776 ns ; 5.085 ns ; +; 24.691 ns ; 188.25 MHz ( period = 5.312 ns ) ; uart_16750:inst|iDLM[3] ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[10] ; CLK ; CLK ; 30.003 ns ; 29.776 ns ; 5.085 ns ; +; 24.691 ns ; 188.25 MHz ( period = 5.312 ns ) ; uart_16750:inst|iDLM[3] ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[11] ; CLK ; CLK ; 30.003 ns ; 29.776 ns ; 5.085 ns ; +; 24.691 ns ; 188.25 MHz ( period = 5.312 ns ) ; uart_16750:inst|iDLM[3] ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[1] ; CLK ; CLK ; 30.003 ns ; 29.776 ns ; 5.085 ns ; +; 24.691 ns ; 188.25 MHz ( period = 5.312 ns ) ; uart_16750:inst|iDLM[3] ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[4] ; CLK ; CLK ; 30.003 ns ; 29.776 ns ; 5.085 ns ; +; 24.691 ns ; 188.25 MHz ( period = 5.312 ns ) ; uart_16750:inst|iDLM[3] ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[9] ; CLK ; CLK ; 30.003 ns ; 29.776 ns ; 5.085 ns ; +; 24.691 ns ; 188.25 MHz ( period = 5.312 ns ) ; uart_16750:inst|iDLM[3] ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[8] ; CLK ; CLK ; 30.003 ns ; 29.776 ns ; 5.085 ns ; +; 24.691 ns ; 188.25 MHz ( period = 5.312 ns ) ; uart_16750:inst|iDLM[3] ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[2] ; CLK ; CLK ; 30.003 ns ; 29.776 ns ; 5.085 ns ; +; 24.691 ns ; 188.25 MHz ( period = 5.312 ns ) ; uart_16750:inst|iDLM[3] ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[0] ; CLK ; CLK ; 30.003 ns ; 29.776 ns ; 5.085 ns ; +; 24.691 ns ; 188.25 MHz ( period = 5.312 ns ) ; uart_16750:inst|iDLM[3] ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[5] ; CLK ; CLK ; 30.003 ns ; 29.776 ns ; 5.085 ns ; +; 24.691 ns ; 188.25 MHz ( period = 5.312 ns ) ; uart_16750:inst|iDLM[3] ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[6] ; CLK ; CLK ; 30.003 ns ; 29.776 ns ; 5.085 ns ; +; 24.691 ns ; 188.25 MHz ( period = 5.312 ns ) ; uart_16750:inst|iDLM[3] ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[14] ; CLK ; CLK ; 30.003 ns ; 29.776 ns ; 5.085 ns ; +; 24.691 ns ; 188.25 MHz ( period = 5.312 ns ) ; uart_16750:inst|iDLM[3] ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[7] ; CLK ; CLK ; 30.003 ns ; 29.776 ns ; 5.085 ns ; +; 24.691 ns ; 188.25 MHz ( period = 5.312 ns ) ; uart_16750:inst|iDLM[3] ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[13] ; CLK ; CLK ; 30.003 ns ; 29.776 ns ; 5.085 ns ; +; 24.695 ns ; 188.39 MHz ( period = 5.308 ns ) ; uart_16750:inst|uart_transmitter:UART_TX|CState.idle ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[0] ; CLK ; CLK ; 30.003 ns ; 29.784 ns ; 5.089 ns ; +; 24.721 ns ; 189.32 MHz ( period = 5.282 ns ) ; uart_16750:inst|iFCR_RXTrigger[1] ; uart_16750:inst|uart_interrupt:UART_IIC|iIIR[0] ; CLK ; CLK ; 30.003 ns ; 29.790 ns ; 5.069 ns ; +; 24.741 ns ; 190.04 MHz ( period = 5.262 ns ) ; uart_16750:inst|iTSR[7] ; uart_16750:inst|uart_receiver:UART_RX|CState.mwait ; CLK ; CLK ; 30.003 ns ; 29.792 ns ; 5.051 ns ; +; 24.770 ns ; 191.09 MHz ( period = 5.233 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_p57:usedw_counter|safe_q[3] ; uart_16750:inst|iRTS ; CLK ; CLK ; 30.003 ns ; 29.805 ns ; 5.035 ns ; +; 24.786 ns ; 191.68 MHz ( period = 5.217 ns ) ; uart_16750:inst|iDLL[3] ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[15] ; CLK ; CLK ; 30.003 ns ; 29.770 ns ; 4.984 ns ; +; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ; ++-----------------------------------------+-----------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Hold: 'CLK' ; ++-----------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+ +; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ; ++-----------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+ +; 0.391 ns ; uart_16750:inst|iLSR_FIFOERR ; uart_16750:inst|iLSR_FIFOERR ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|slib_input_filter:UART_IF_DSR|iCount[1] ; uart_16750:inst|slib_input_filter:UART_IF_DSR|iCount[1] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|slib_input_filter:UART_IF_DSR|iCount[0] ; uart_16750:inst|slib_input_filter:UART_IF_DSR|iCount[0] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|slib_input_filter:UART_IF_DCD|iCount[1] ; uart_16750:inst|slib_input_filter:UART_IF_DCD|iCount[1] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|slib_input_filter:UART_IF_DCD|iCount[0] ; uart_16750:inst|slib_input_filter:UART_IF_DCD|iCount[0] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|slib_input_filter:UART_IF_RI|iCount[0] ; uart_16750:inst|slib_input_filter:UART_IF_RI|iCount[0] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|slib_input_filter:UART_IF_RI|iCount[1] ; uart_16750:inst|slib_input_filter:UART_IF_RI|iCount[1] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|slib_input_filter:UART_IF_DSR|Q ; uart_16750:inst|slib_input_filter:UART_IF_DSR|Q ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|slib_input_filter:UART_IF_DCD|Q ; uart_16750:inst|slib_input_filter:UART_IF_DCD|Q ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|slib_input_filter:UART_IF_RI|Q ; uart_16750:inst|slib_input_filter:UART_IF_RI|Q ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|iLSR_BI ; uart_16750:inst|iLSR_BI ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|iLSR_FE ; uart_16750:inst|iLSR_FE ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|iMSR_dCTS ; uart_16750:inst|iMSR_dCTS ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|iLSR_PE ; uart_16750:inst|iLSR_PE ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|iLSR_OE ; uart_16750:inst|iLSR_OE ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|iMSR_dDSR ; uart_16750:inst|iMSR_dDSR ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|iMSR_dDCD ; uart_16750:inst|iMSR_dDCD ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|iMSR_TERI ; uart_16750:inst|iMSR_TERI ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|iCharTimeout ; uart_16750:inst|iCharTimeout ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|usedw_is_2_dff ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|usedw_is_2_dff ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|slib_input_filter:UART_IF_CTS|iCount[1] ; uart_16750:inst|slib_input_filter:UART_IF_CTS|iCount[1] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|slib_input_filter:UART_IF_CTS|iCount[0] ; uart_16750:inst|slib_input_filter:UART_IF_CTS|iCount[0] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|\UART_TXPROC:State.txrun ; uart_16750:inst|\UART_TXPROC:State.txrun ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|usedw_is_1_dff ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|usedw_is_1_dff ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|usedw_is_0_dff ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|usedw_is_0_dff ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|slib_clock_div:UART_BG2|iCounter[0] ; uart_16750:inst|slib_clock_div:UART_BG2|iCounter[0] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|slib_clock_div:UART_BG2|iCounter[2] ; uart_16750:inst|slib_clock_div:UART_BG2|iCounter[2] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|slib_clock_div:UART_BG2|iCounter[1] ; uart_16750:inst|slib_clock_div:UART_BG2|iCounter[1] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|slib_input_filter:UART_IF_CTS|Q ; uart_16750:inst|slib_input_filter:UART_IF_CTS|Q ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|\UART_TXPROC:State.idle ; uart_16750:inst|\UART_TXPROC:State.idle ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|uart_transmitter:UART_TX|iTx2 ; uart_16750:inst|uart_transmitter:UART_TX|iTx2 ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|low_addressa[5] ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|low_addressa[5] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|low_addressa[4] ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|low_addressa[4] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|low_addressa[3] ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|low_addressa[3] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|low_addressa[2] ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|low_addressa[2] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|low_addressa[1] ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|low_addressa[1] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|low_addressa[0] ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|low_addressa[0] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|rd_ptr_lsb ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|rd_ptr_lsb ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|full_dff ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|full_dff ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|uart_transmitter:UART_TX|CState.bit5 ; uart_16750:inst|uart_transmitter:UART_TX|CState.bit5 ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|uart_transmitter:UART_TX|CState.idle ; uart_16750:inst|uart_transmitter:UART_TX|CState.idle ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|uart_transmitter:UART_TX|CState.stop ; uart_16750:inst|uart_transmitter:UART_TX|CState.stop ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|uart_transmitter:UART_TX|CState.bit7 ; uart_16750:inst|uart_transmitter:UART_TX|CState.bit7 ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|uart_transmitter:UART_TX|CState.bit6 ; uart_16750:inst|uart_transmitter:UART_TX|CState.bit6 ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|uart_receiver:UART_RX|CState.mwait ; uart_16750:inst|uart_receiver:UART_RX|CState.mwait ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|uart_receiver:UART_RX|CState.data ; uart_16750:inst|uart_receiver:UART_RX|CState.data ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|uart_receiver:UART_RX|CState.start ; uart_16750:inst|uart_receiver:UART_RX|CState.start ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|uart_receiver:UART_RX|CState.idle ; uart_16750:inst|uart_receiver:UART_RX|CState.idle ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|iFCR_FIFO64E ; uart_16750:inst|iFCR_FIFO64E ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|uart_receiver:UART_RX|iParityReceived ; uart_16750:inst|uart_receiver:UART_RX|iParityReceived ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iQ ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iQ ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|uart_receiver:UART_RX|iDOUT[7] ; uart_16750:inst|uart_receiver:UART_RX|iDOUT[7] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|uart_receiver:UART_RX|iDOUT[5] ; uart_16750:inst|uart_receiver:UART_RX|iDOUT[5] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|uart_receiver:UART_RX|iDOUT[4] ; uart_16750:inst|uart_receiver:UART_RX|iDOUT[4] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|uart_receiver:UART_RX|iDOUT[3] ; uart_16750:inst|uart_receiver:UART_RX|iDOUT[3] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|uart_receiver:UART_RX|iDOUT[2] ; uart_16750:inst|uart_receiver:UART_RX|iDOUT[2] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|uart_receiver:UART_RX|iDOUT[1] ; uart_16750:inst|uart_receiver:UART_RX|iDOUT[1] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|\UART_RXPROC:State ; uart_16750:inst|\UART_RXPROC:State ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|uart_receiver:UART_RX|slib_counter:RX_BRC|iCounter[4] ; uart_16750:inst|uart_receiver:UART_RX|slib_counter:RX_BRC|iCounter[4] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|uart_receiver:UART_RX|iDOUT[6] ; uart_16750:inst|uart_receiver:UART_RX|iDOUT[6] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[5] ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[5] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[4] ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[4] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[3] ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[3] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[2] ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[2] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[1] ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[1] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|rd_ptr_lsb ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|rd_ptr_lsb ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[0] ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[0] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|uart_receiver:UART_RX|iDOUT[0] ; uart_16750:inst|uart_receiver:UART_RX|iDOUT[0] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.391 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|full_dff ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|full_dff ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.407 ns ; +; 0.516 ns ; uart_16750:inst|slib_input_sync:UART_IS_RI|iD[0] ; uart_16750:inst|slib_input_sync:UART_IS_RI|iD[1] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.532 ns ; +; 0.516 ns ; inst4 ; inst5 ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.532 ns ; +; 0.522 ns ; uart_16750:inst|slib_input_filter:UART_IF_DCD|iCount[0] ; uart_16750:inst|slib_input_filter:UART_IF_DCD|iCount[1] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.538 ns ; +; 0.523 ns ; uart_16750:inst|slib_input_sync:UART_IS_RI|iD[1] ; uart_16750:inst|slib_input_filter:UART_IF_RI|iCount[0] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.539 ns ; +; 0.524 ns ; uart_16750:inst|slib_input_sync:UART_IS_RI|iD[1] ; uart_16750:inst|slib_input_filter:UART_IF_RI|iCount[1] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.540 ns ; +; 0.525 ns ; uart_16750:inst|uart_transmitter:UART_TX|\TX_FIN:iLast ; uart_16750:inst|uart_transmitter:UART_TX|iFinished ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.541 ns ; +; 0.525 ns ; uart_16750:inst|iMCR[5] ; uart_16750:inst|iRTS ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.541 ns ; +; 0.526 ns ; uart_16750:inst|slib_input_sync:UART_IS_DSR|iD[0] ; uart_16750:inst|slib_input_sync:UART_IS_DSR|iD[1] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.542 ns ; +; 0.529 ns ; uart_16750:inst|iTimeoutCount[5] ; uart_16750:inst|iTimeoutCount[5] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.545 ns ; +; 0.529 ns ; uart_16750:inst|slib_input_filter:UART_IF_CTS|iCount[1] ; uart_16750:inst|slib_input_filter:UART_IF_CTS|iCount[0] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.545 ns ; +; 0.529 ns ; uart_16750:inst|uart_transmitter:UART_TX|iFinished ; uart_16750:inst|\UART_TXPROC:State.txend ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.545 ns ; +; 0.529 ns ; uart_16750:inst|slib_input_filter:UART_IF_CTS|iCount[1] ; uart_16750:inst|slib_input_filter:UART_IF_CTS|Q ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.545 ns ; +; 0.530 ns ; uart_16750:inst|slib_input_sync:UART_IS_CTS|iD[0] ; uart_16750:inst|slib_input_sync:UART_IS_CTS|iD[1] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.546 ns ; +; 0.531 ns ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[15] ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[15] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.547 ns ; +; 0.531 ns ; uart_16750:inst|\UART_TXPROC:State.txrun ; uart_16750:inst|iTXStart ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.547 ns ; +; 0.531 ns ; uart_16750:inst|uart_receiver:UART_RX|iBaudStepD ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iQ ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.547 ns ; +; 0.531 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_d5b:wr_ptr|safe_q[5] ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_d5b:wr_ptr|safe_q[5] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.547 ns ; +; 0.532 ns ; uart_16750:inst|slib_input_filter:UART_IF_DCD|iCount[1] ; uart_16750:inst|slib_input_filter:UART_IF_DCD|iCount[0] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.548 ns ; +; 0.533 ns ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[0] ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|low_addressa[1] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.549 ns ; +; 0.533 ns ; uart_16750:inst|uart_receiver:UART_RX|iDOUT[5] ; uart_16750:inst|iRXFIFOD[5] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.549 ns ; +; 0.533 ns ; uart_16750:inst|uart_receiver:UART_RX|iDOUT[1] ; uart_16750:inst|iRXFIFOD[1] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.549 ns ; +; 0.534 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[4] ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[4] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.550 ns ; +; 0.536 ns ; uart_16750:inst|slib_input_filter:UART_IF_DSR|iCount[1] ; uart_16750:inst|slib_input_filter:UART_IF_DSR|iCount[0] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.552 ns ; +; 0.537 ns ; uart_16750:inst|slib_input_filter:UART_IF_DSR|iCount[1] ; uart_16750:inst|slib_input_filter:UART_IF_DSR|Q ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.553 ns ; +; 0.537 ns ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_p57:usedw_counter|safe_q[5] ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_p57:usedw_counter|safe_q[5] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.553 ns ; +; 0.537 ns ; uart_16750:inst|slib_clock_div:UART_BG2|iCounter[0] ; uart_16750:inst|slib_clock_div:UART_BG2|iCounter[1] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.553 ns ; +; 0.538 ns ; uart_16750:inst|slib_input_filter:UART_IF_DCD|iCount[1] ; uart_16750:inst|slib_input_filter:UART_IF_DCD|Q ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.554 ns ; +; 0.538 ns ; uart_16750:inst|uart_receiver:UART_RX|iDOUT[7] ; uart_16750:inst|iRXFIFOD[7] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.554 ns ; +; 0.538 ns ; uart_16750:inst|uart_receiver:UART_RX|iDOUT[3] ; uart_16750:inst|iRXFIFOD[3] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.554 ns ; +; 0.538 ns ; uart_16750:inst|uart_receiver:UART_RX|iDOUT[2] ; uart_16750:inst|iRXFIFOD[2] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.554 ns ; +; 0.539 ns ; slib_clock_div:inst2|iCounter[0] ; slib_clock_div:inst2|iQ ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.555 ns ; +; 0.539 ns ; uart_16750:inst|slib_clock_div:UART_BG2|iCounter[0] ; uart_16750:inst|slib_clock_div:UART_BG2|iQ ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.555 ns ; +; 0.539 ns ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|rd_ptr_lsb ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|low_addressa[0] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.555 ns ; +; 0.540 ns ; uart_16750:inst|slib_clock_div:UART_BG2|iCounter[0] ; uart_16750:inst|slib_clock_div:UART_BG2|iCounter[2] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.556 ns ; +; 0.541 ns ; uart_16750:inst|slib_input_sync:UART_IS_CTS|iD[1] ; uart_16750:inst|slib_input_filter:UART_IF_CTS|iCount[1] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.557 ns ; +; 0.541 ns ; uart_16750:inst|uart_receiver:UART_RX|iDOUT[4] ; uart_16750:inst|iRXFIFOD[4] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.557 ns ; +; 0.552 ns ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[4] ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[4] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.568 ns ; +; 0.553 ns ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[2] ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|low_addressa[3] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.569 ns ; +; 0.555 ns ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[4] ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|low_addressa[5] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.571 ns ; +; 0.557 ns ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[3] ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|low_addressa[4] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.573 ns ; +; 0.559 ns ; uart_16750:inst|iMCR[4] ; uart_16750:inst|DTRN ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.575 ns ; +; 0.562 ns ; uart_16750:inst|iMCR[4] ; uart_16750:inst|RTSN ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.578 ns ; +; 0.562 ns ; uart_16750:inst|iMCR[4] ; uart_16750:inst|slib_edge_detect:UART_ED_CTS|iDd ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.578 ns ; +; 0.567 ns ; uart_16750:inst|uart_baudgen:UART_BG16|BAUDTICK ; uart_16750:inst|slib_clock_div:UART_BG2|iCounter[0] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.583 ns ; +; 0.568 ns ; uart_16750:inst|uart_baudgen:UART_BG16|BAUDTICK ; uart_16750:inst|BAUDOUTN ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.584 ns ; +; 0.638 ns ; uart_16750:inst|\UART_TXPROC:State.txstart ; uart_16750:inst|iTXStart ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.654 ns ; +; 0.656 ns ; uart_16750:inst|uart_transmitter:UART_TX|CState.bit0 ; uart_16750:inst|uart_transmitter:UART_TX|CState.bit1 ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.672 ns ; +; 0.657 ns ; uart_16750:inst|slib_clock_div:UART_BG2|iCounter[2] ; uart_16750:inst|slib_clock_div:UART_BG2|iQ ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.673 ns ; +; 0.660 ns ; uart_16750:inst|uart_transmitter:UART_TX|CState.bit3 ; uart_16750:inst|uart_transmitter:UART_TX|CState.bit4 ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.676 ns ; +; 0.660 ns ; uart_16750:inst|uart_transmitter:UART_TX|CState.bit2 ; uart_16750:inst|uart_transmitter:UART_TX|CState.bit3 ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.676 ns ; +; 0.662 ns ; uart_16750:inst|slib_input_sync:UART_IS_SIN|iD[0] ; uart_16750:inst|slib_input_sync:UART_IS_SIN|iD[1] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.678 ns ; +; 0.663 ns ; uart_16750:inst|iIER[3] ; uart_16750:inst|uart_interrupt:UART_IIC|iIIR[0] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.679 ns ; +; 0.664 ns ; uart_16750:inst|slib_input_sync:UART_IS_DCD|iD[0] ; uart_16750:inst|slib_input_sync:UART_IS_DCD|iD[1] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.680 ns ; +; 0.667 ns ; uart_16750:inst|uart_receiver:UART_RX|iDOUT[6] ; uart_16750:inst|iRXFIFOD[10] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.683 ns ; +; 0.670 ns ; uart_16750:inst|uart_receiver:UART_RX|PE ; uart_16750:inst|iRXFIFOD[8] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.686 ns ; +; 0.674 ns ; uart_16750:inst|uart_receiver:UART_RX|iDOUT[0] ; uart_16750:inst|iRXFIFOD[0] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.690 ns ; +; 0.677 ns ; uart_16750:inst|\UART_TXPROC:State.txstart ; uart_16750:inst|iTXFIFORead ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.693 ns ; +; 0.677 ns ; uart_16750:inst|uart_receiver:UART_RX|iDOUT[6] ; uart_16750:inst|iRXFIFOD[6] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.693 ns ; +; 0.696 ns ; uart_16750:inst|uart_receiver:UART_RX|slib_counter:RX_BRC|iCounter[4] ; uart_16750:inst|uart_receiver:UART_RX|iBaudStepD ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.712 ns ; +; 0.702 ns ; uart_16750:inst|uart_receiver:UART_RX|CState.stop ; uart_16750:inst|iRXFIFOD[9] ; CLK ; CLK ; 0.000 ns ; 0.018 ns ; 0.720 ns ; +; 0.755 ns ; slib_clock_div:inst2|iCounter[1] ; slib_clock_div:inst2|iQ ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.771 ns ; +; 0.759 ns ; uart_16750:inst|\UART_TXPROC:State.txend ; uart_16750:inst|\UART_TXPROC:State.idle ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.775 ns ; +; 0.765 ns ; uart_16750:inst|uart_receiver:UART_RX|iDOUT[7] ; uart_16750:inst|iRXFIFOD[10] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.781 ns ; +; 0.770 ns ; uart_16750:inst|\UART_TXPROC:State.idle ; uart_16750:inst|\UART_TXPROC:State.txstart ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.786 ns ; +; 0.778 ns ; uart_16750:inst|iTimeoutCount[5] ; uart_16750:inst|iCharTimeout ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.794 ns ; +; 0.780 ns ; uart_16750:inst|iRTS ; uart_16750:inst|RTSN ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.796 ns ; +; 0.795 ns ; uart_16750:inst|uart_receiver:UART_RX|iDataCount[2] ; uart_16750:inst|uart_receiver:UART_RX|iDataCount[2] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.811 ns ; +; 0.795 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_d5b:wr_ptr|safe_q[1] ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_d5b:wr_ptr|safe_q[1] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.811 ns ; +; 0.797 ns ; uart_16750:inst|slib_input_filter:UART_IF_CTS|iCount[0] ; uart_16750:inst|slib_input_filter:UART_IF_CTS|Q ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.813 ns ; +; 0.798 ns ; uart_16750:inst|slib_edge_detect:UART_ED_DSR|iDd ; uart_16750:inst|iMSR_dDSR ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.814 ns ; +; 0.799 ns ; uart_16750:inst|iTimeoutCount[0] ; uart_16750:inst|iTimeoutCount[0] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.815 ns ; +; 0.799 ns ; uart_16750:inst|iTimeoutCount[3] ; uart_16750:inst|iTimeoutCount[3] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.815 ns ; +; 0.799 ns ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[0] ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[0] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.815 ns ; +; 0.799 ns ; uart_16750:inst|slib_input_filter:UART_IF_CTS|iCount[0] ; uart_16750:inst|slib_input_filter:UART_IF_CTS|iCount[1] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.815 ns ; +; 0.800 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|usedw_is_2_dff ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|usedw_is_1_dff ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.816 ns ; +; 0.801 ns ; uart_16750:inst|slib_input_filter:UART_IF_DCD|iCount[0] ; uart_16750:inst|slib_input_filter:UART_IF_DCD|Q ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.817 ns ; +; 0.801 ns ; uart_16750:inst|uart_receiver:UART_RX|CState.data ; uart_16750:inst|uart_receiver:UART_RX|CState.par ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.817 ns ; +; 0.801 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[0] ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[0] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.817 ns ; +; 0.802 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[2] ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[2] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.818 ns ; +; 0.803 ns ; uart_16750:inst|iRTS ; uart_16750:inst|slib_edge_detect:UART_ED_CTS|iDd ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.819 ns ; +; 0.804 ns ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[0] ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[0] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.820 ns ; +; 0.804 ns ; uart_16750:inst|uart_receiver:UART_RX|CState.data ; uart_16750:inst|uart_receiver:UART_RX|CState.stop ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.820 ns ; +; 0.805 ns ; uart_16750:inst|slib_input_filter:UART_IF_RI|iCount[0] ; uart_16750:inst|slib_input_filter:UART_IF_RI|Q ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.821 ns ; +; 0.805 ns ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[1] ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[1] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.821 ns ; +; 0.805 ns ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.821 ns ; +; 0.805 ns ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[1] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[1] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.821 ns ; +; 0.806 ns ; uart_16750:inst|slib_input_filter:UART_IF_RI|iCount[0] ; uart_16750:inst|slib_input_filter:UART_IF_RI|iCount[1] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.822 ns ; +; 0.806 ns ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[11] ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[11] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.822 ns ; +; 0.806 ns ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[4] ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[4] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.822 ns ; +; 0.806 ns ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[9] ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[9] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.822 ns ; +; 0.806 ns ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[2] ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[2] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.822 ns ; +; 0.806 ns ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[14] ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[14] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.822 ns ; +; 0.806 ns ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[7] ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[7] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.822 ns ; +; 0.806 ns ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[13] ; uart_16750:inst|uart_baudgen:UART_BG16|iCounter[13] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.822 ns ; +; 0.806 ns ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_d5b:wr_ptr|safe_q[4] ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_d5b:wr_ptr|safe_q[4] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.822 ns ; +; 0.806 ns ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_d5b:wr_ptr|safe_q[1] ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_d5b:wr_ptr|safe_q[1] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.822 ns ; +; 0.806 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_d5b:wr_ptr|safe_q[4] ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_d5b:wr_ptr|safe_q[4] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.822 ns ; +; 0.806 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_d5b:wr_ptr|safe_q[3] ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_d5b:wr_ptr|safe_q[3] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.822 ns ; +; 0.807 ns ; uart_16750:inst|slib_input_filter:UART_IF_RI|Q ; uart_16750:inst|slib_edge_detect:UART_ED_RI|iDd ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.823 ns ; +; 0.808 ns ; slib_clock_div:inst2|iCounter[0] ; slib_clock_div:inst2|iCounter[0] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.824 ns ; +; 0.809 ns ; uart_16750:inst|slib_edge_detect:UART_FEDET|iDd ; uart_16750:inst|iLSR_FE ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.825 ns ; +; 0.809 ns ; uart_16750:inst|\UART_TXPROC:State.idle ; uart_16750:inst|iTXStart ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.825 ns ; +; 0.809 ns ; uart_16750:inst|uart_receiver:UART_RX|CState.mwait ; uart_16750:inst|uart_receiver:UART_RX|CState.idle ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.825 ns ; +; 0.810 ns ; uart_16750:inst|iMCR[0] ; uart_16750:inst|slib_edge_detect:UART_ED_DSR|iDd ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.826 ns ; +; 0.811 ns ; uart_16750:inst|uart_transmitter:UART_TX|CState.stop ; uart_16750:inst|uart_transmitter:UART_TX|CState.stop2 ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.827 ns ; +; 0.812 ns ; uart_16750:inst|uart_transmitter:UART_TX|CState.bit5 ; uart_16750:inst|uart_transmitter:UART_TX|CState.bit6 ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.828 ns ; +; 0.813 ns ; slib_clock_div:inst2|iCounter[2] ; slib_clock_div:inst2|iCounter[2] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.829 ns ; +; 0.813 ns ; uart_16750:inst|uart_baudgen:UART_BG16|BAUDTICK ; uart_16750:inst|slib_clock_div:UART_BG2|iQ ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.829 ns ; +; 0.814 ns ; uart_16750:inst|slib_input_filter:UART_IF_DSR|iCount[0] ; uart_16750:inst|slib_input_filter:UART_IF_DSR|Q ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.830 ns ; +; 0.814 ns ; uart_16750:inst|iFECounter[1] ; uart_16750:inst|iFECounter[1] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.830 ns ; +; 0.814 ns ; uart_16750:inst|iFECounter[3] ; uart_16750:inst|iFECounter[3] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.830 ns ; +; 0.814 ns ; uart_16750:inst|iFCR_TXFIFOReset ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|usedw_is_2_dff ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.830 ns ; +; 0.814 ns ; uart_16750:inst|\UART_TXPROC:State.txstart ; uart_16750:inst|\UART_TXPROC:State.txrun ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.830 ns ; +; 0.814 ns ; uart_16750:inst|iFCR_TXFIFOReset ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|full_dff ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.830 ns ; +; 0.815 ns ; uart_16750:inst|iFECounter[6] ; uart_16750:inst|iFECounter[6] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.831 ns ; +; 0.816 ns ; uart_16750:inst|slib_input_filter:UART_IF_DSR|iCount[0] ; uart_16750:inst|slib_input_filter:UART_IF_DSR|iCount[1] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.832 ns ; +; 0.816 ns ; uart_16750:inst|slib_input_sync:UART_IS_CTS|iD[1] ; uart_16750:inst|slib_input_filter:UART_IF_CTS|iCount[0] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.832 ns ; +; 0.816 ns ; uart_16750:inst|slib_clock_div:UART_BG2|iCounter[1] ; uart_16750:inst|slib_clock_div:UART_BG2|iQ ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.832 ns ; +; 0.817 ns ; uart_16750:inst|slib_input_sync:UART_IS_DCD|iD[1] ; uart_16750:inst|slib_input_filter:UART_IF_DCD|iCount[1] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.833 ns ; +; 0.817 ns ; uart_16750:inst|slib_input_sync:UART_IS_SIN|iD[1] ; uart_16750:inst|uart_receiver:UART_RX|CState.start ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.833 ns ; +; 0.817 ns ; uart_16750:inst|slib_input_sync:UART_IS_SIN|iD[1] ; uart_16750:inst|uart_receiver:UART_RX|CState.idle ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.833 ns ; +; 0.818 ns ; uart_16750:inst|slib_input_sync:UART_IS_DCD|iD[1] ; uart_16750:inst|slib_input_filter:UART_IF_DCD|iCount[0] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.834 ns ; +; 0.818 ns ; uart_16750:inst|iMCR[0] ; uart_16750:inst|iMSR_dDSR ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.834 ns ; +; 0.820 ns ; uart_16750:inst|iTimeoutCount[4] ; uart_16750:inst|iTimeoutCount[4] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.836 ns ; +; 0.820 ns ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iQ ; uart_16750:inst|uart_receiver:UART_RX|iParityReceived ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.836 ns ; +; 0.821 ns ; uart_16750:inst|iFECounter[0] ; uart_16750:inst|iFECounter[0] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.837 ns ; +; 0.821 ns ; uart_16750:inst|iFCR_TXFIFOReset ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|usedw_is_0_dff ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.837 ns ; +; 0.821 ns ; uart_16750:inst|uart_transmitter:UART_TX|CState.stop2 ; uart_16750:inst|uart_transmitter:UART_TX|iTx2 ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.837 ns ; +; 0.822 ns ; uart_16750:inst|iFCR_TXFIFOReset ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|usedw_is_1_dff ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.838 ns ; +; 0.825 ns ; uart_16750:inst|slib_edge_detect:UART_ED_CTS|iDd ; uart_16750:inst|iMSR_dCTS ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.841 ns ; +; 0.825 ns ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[3] ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[3] ; CLK ; CLK ; 0.000 ns ; 0.016 ns ; 0.841 ns ; +; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ++-----------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; tsu ; ++-----------------------------------------+-----------------------------------------------------+------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------+ +; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ; ++-----------------------------------------+-----------------------------------------------------+------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------+ +; 2.580 ns ; 10.000 ns ; 7.420 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|empty_dff ; CLK ; +; 2.743 ns ; 10.000 ns ; 7.257 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|empty_dff ; CLK ; +; 2.878 ns ; 10.000 ns ; 7.122 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|empty_dff ; CLK ; +; 3.167 ns ; 10.000 ns ; 6.833 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|usedw_is_2_dff ; CLK ; +; 3.196 ns ; 10.000 ns ; 6.804 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|empty_dff ; CLK ; +; 3.376 ns ; 10.000 ns ; 6.624 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|usedw_is_1_dff ; CLK ; +; 3.379 ns ; 10.000 ns ; 6.621 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg4 ; CLK ; +; 3.384 ns ; 10.000 ns ; 6.616 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|usedw_is_2_dff ; CLK ; +; 3.439 ns ; 10.000 ns ; 6.561 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|usedw_is_0_dff ; CLK ; +; 3.456 ns ; 10.000 ns ; 6.544 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_p57:usedw_counter|safe_q[5] ; CLK ; +; 3.457 ns ; 10.000 ns ; 6.543 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|usedw_is_0_dff ; CLK ; +; 3.466 ns ; 10.000 ns ; 6.534 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|usedw_is_1_dff ; CLK ; +; 3.527 ns ; 10.000 ns ; 6.473 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_p57:usedw_counter|safe_q[4] ; CLK ; +; 3.598 ns ; 10.000 ns ; 6.402 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_p57:usedw_counter|safe_q[3] ; CLK ; +; 3.620 ns ; 10.000 ns ; 6.380 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|usedw_is_2_dff ; CLK ; +; 3.643 ns ; 10.000 ns ; 6.357 ns ; RD ; uart_16750:inst|iMSR_dDSR ; CLK ; +; 3.651 ns ; 10.000 ns ; 6.349 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_p57:usedw_counter|safe_q[0] ; CLK ; +; 3.651 ns ; 10.000 ns ; 6.349 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_p57:usedw_counter|safe_q[1] ; CLK ; +; 3.651 ns ; 10.000 ns ; 6.349 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_p57:usedw_counter|safe_q[2] ; CLK ; +; 3.670 ns ; 10.000 ns ; 6.330 ns ; RD ; uart_16750:inst|iLSR_PE ; CLK ; +; 3.671 ns ; 10.000 ns ; 6.329 ns ; RD ; uart_16750:inst|iLSR_BI ; CLK ; +; 3.674 ns ; 10.000 ns ; 6.326 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|usedw_is_1_dff ; CLK ; +; 3.682 ns ; 10.000 ns ; 6.318 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|usedw_is_2_dff ; CLK ; +; 3.725 ns ; 10.000 ns ; 6.275 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|full_dff ; CLK ; +; 3.737 ns ; 10.000 ns ; 6.263 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|usedw_is_0_dff ; CLK ; +; 3.738 ns ; 10.000 ns ; 6.262 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg0 ; CLK ; +; 3.746 ns ; 10.000 ns ; 6.254 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg1 ; CLK ; +; 3.754 ns ; 10.000 ns ; 6.246 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_p57:usedw_counter|safe_q[5] ; CLK ; +; 3.768 ns ; 10.000 ns ; 6.232 ns ; RD ; uart_16750:inst|iTHRInterrupt ; CLK ; +; 3.775 ns ; 10.000 ns ; 6.225 ns ; RD ; uart_16750:inst|iMSR_dDCD ; CLK ; +; 3.777 ns ; 10.000 ns ; 6.223 ns ; RD ; uart_16750:inst|iMSR_TERI ; CLK ; +; 3.788 ns ; 10.000 ns ; 6.212 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_p57:usedw_counter|safe_q[3] ; CLK ; +; 3.788 ns ; 10.000 ns ; 6.212 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_p57:usedw_counter|safe_q[5] ; CLK ; +; 3.788 ns ; 10.000 ns ; 6.212 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_p57:usedw_counter|safe_q[2] ; CLK ; +; 3.788 ns ; 10.000 ns ; 6.212 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_p57:usedw_counter|safe_q[1] ; CLK ; +; 3.788 ns ; 10.000 ns ; 6.212 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_p57:usedw_counter|safe_q[0] ; CLK ; +; 3.788 ns ; 10.000 ns ; 6.212 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_p57:usedw_counter|safe_q[4] ; CLK ; +; 3.825 ns ; 10.000 ns ; 6.175 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_p57:usedw_counter|safe_q[4] ; CLK ; +; 3.832 ns ; 10.000 ns ; 6.168 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg4 ; CLK ; +; 3.881 ns ; 10.000 ns ; 6.119 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|full_dff ; CLK ; +; 3.882 ns ; 10.000 ns ; 6.118 ns ; RD ; uart_16750:inst|iLSR_OE ; CLK ; +; 3.885 ns ; 10.000 ns ; 6.115 ns ; RD ; uart_16750:inst|iLSR_FE ; CLK ; +; 3.890 ns ; 10.000 ns ; 6.110 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|rd_ptr_lsb ; CLK ; +; 3.896 ns ; 10.000 ns ; 6.104 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_p57:usedw_counter|safe_q[3] ; CLK ; +; 3.910 ns ; 10.000 ns ; 6.090 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|usedw_is_0_dff ; CLK ; +; 3.919 ns ; 10.000 ns ; 6.081 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|usedw_is_1_dff ; CLK ; +; 3.920 ns ; 10.000 ns ; 6.080 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[4] ; CLK ; +; 3.920 ns ; 10.000 ns ; 6.080 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[3] ; CLK ; +; 3.920 ns ; 10.000 ns ; 6.080 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[2] ; CLK ; +; 3.920 ns ; 10.000 ns ; 6.080 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[1] ; CLK ; +; 3.920 ns ; 10.000 ns ; 6.080 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[0] ; CLK ; +; 3.933 ns ; 10.000 ns ; 6.067 ns ; RD ; uart_16750:inst|iTimeoutCount[0] ; CLK ; +; 3.933 ns ; 10.000 ns ; 6.067 ns ; RD ; uart_16750:inst|iTimeoutCount[1] ; CLK ; +; 3.933 ns ; 10.000 ns ; 6.067 ns ; RD ; uart_16750:inst|iTimeoutCount[2] ; CLK ; +; 3.933 ns ; 10.000 ns ; 6.067 ns ; RD ; uart_16750:inst|iTimeoutCount[3] ; CLK ; +; 3.933 ns ; 10.000 ns ; 6.067 ns ; RD ; uart_16750:inst|iTimeoutCount[4] ; CLK ; +; 3.933 ns ; 10.000 ns ; 6.067 ns ; RD ; uart_16750:inst|iTimeoutCount[5] ; CLK ; +; 3.949 ns ; 10.000 ns ; 6.051 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_p57:usedw_counter|safe_q[0] ; CLK ; +; 3.949 ns ; 10.000 ns ; 6.051 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_p57:usedw_counter|safe_q[1] ; CLK ; +; 3.949 ns ; 10.000 ns ; 6.051 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_p57:usedw_counter|safe_q[2] ; CLK ; +; 3.953 ns ; 10.000 ns ; 6.047 ns ; RD ; uart_16750:inst|iMSR_dCTS ; CLK ; +; 3.995 ns ; 10.000 ns ; 6.005 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg2 ; CLK ; +; 4.008 ns ; 10.000 ns ; 5.992 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg3 ; CLK ; +; 4.028 ns ; 10.000 ns ; 5.972 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[2] ; CLK ; +; 4.035 ns ; 10.000 ns ; 5.965 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg5 ; CLK ; +; 4.039 ns ; 10.000 ns ; 5.961 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_d5b:wr_ptr|safe_q[5] ; CLK ; +; 4.039 ns ; 10.000 ns ; 5.961 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_d5b:wr_ptr|safe_q[4] ; CLK ; +; 4.039 ns ; 10.000 ns ; 5.961 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_d5b:wr_ptr|safe_q[3] ; CLK ; +; 4.039 ns ; 10.000 ns ; 5.961 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_d5b:wr_ptr|safe_q[2] ; CLK ; +; 4.039 ns ; 10.000 ns ; 5.961 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_d5b:wr_ptr|safe_q[1] ; CLK ; +; 4.039 ns ; 10.000 ns ; 5.961 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_d5b:wr_ptr|safe_q[0] ; CLK ; +; 4.096 ns ; 10.000 ns ; 5.904 ns ; CS ; uart_16750:inst|iMSR_dDSR ; CLK ; +; 4.117 ns ; 10.000 ns ; 5.883 ns ; WR ; uart_16750:inst|iTHRInterrupt ; CLK ; +; 4.131 ns ; 10.000 ns ; 5.869 ns ; WR ; uart_16750:inst|iLCR[2] ; CLK ; +; 4.131 ns ; 10.000 ns ; 5.869 ns ; WR ; uart_16750:inst|iLCR[6] ; CLK ; +; 4.131 ns ; 10.000 ns ; 5.869 ns ; WR ; uart_16750:inst|iLCR[1] ; CLK ; +; 4.131 ns ; 10.000 ns ; 5.869 ns ; WR ; uart_16750:inst|iLCR[4] ; CLK ; +; 4.141 ns ; 10.000 ns ; 5.859 ns ; WR ; uart_16750:inst|iLCR[0] ; CLK ; +; 4.141 ns ; 10.000 ns ; 5.859 ns ; WR ; uart_16750:inst|iLCR[3] ; CLK ; +; 4.149 ns ; 10.000 ns ; 5.851 ns ; WR ; uart_16750:inst|iDLM[3] ; CLK ; +; 4.178 ns ; 10.000 ns ; 5.822 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|full_dff ; CLK ; +; 4.179 ns ; 10.000 ns ; 5.821 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|full_dff ; CLK ; +; 4.187 ns ; 10.000 ns ; 5.813 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[4] ; CLK ; +; 4.187 ns ; 10.000 ns ; 5.813 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[3] ; CLK ; +; 4.188 ns ; 10.000 ns ; 5.812 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[1] ; CLK ; +; 4.188 ns ; 10.000 ns ; 5.812 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[0] ; CLK ; +; 4.189 ns ; 10.000 ns ; 5.811 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[5] ; CLK ; +; 4.191 ns ; 10.000 ns ; 5.809 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg0 ; CLK ; +; 4.199 ns ; 10.000 ns ; 5.801 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg1 ; CLK ; +; 4.206 ns ; 10.000 ns ; 5.794 ns ; WR ; uart_16750:inst|iDLM[2] ; CLK ; +; 4.206 ns ; 10.000 ns ; 5.794 ns ; WR ; uart_16750:inst|iDLM[0] ; CLK ; +; 4.206 ns ; 10.000 ns ; 5.794 ns ; WR ; uart_16750:inst|iDLM[1] ; CLK ; +; 4.221 ns ; 10.000 ns ; 5.779 ns ; CS ; uart_16750:inst|iTHRInterrupt ; CLK ; +; 4.228 ns ; 10.000 ns ; 5.772 ns ; CS ; uart_16750:inst|iMSR_dDCD ; CLK ; +; 4.230 ns ; 10.000 ns ; 5.770 ns ; CS ; uart_16750:inst|iMSR_TERI ; CLK ; +; 4.241 ns ; 10.000 ns ; 5.759 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_p57:usedw_counter|safe_q[3] ; CLK ; +; 4.241 ns ; 10.000 ns ; 5.759 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_p57:usedw_counter|safe_q[5] ; CLK ; +; 4.241 ns ; 10.000 ns ; 5.759 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_p57:usedw_counter|safe_q[2] ; CLK ; +; 4.241 ns ; 10.000 ns ; 5.759 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_p57:usedw_counter|safe_q[1] ; CLK ; +; 4.241 ns ; 10.000 ns ; 5.759 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_p57:usedw_counter|safe_q[0] ; CLK ; +; 4.241 ns ; 10.000 ns ; 5.759 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_p57:usedw_counter|safe_q[4] ; CLK ; +; 4.269 ns ; 10.000 ns ; 5.731 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|altsyncram_t681:FIFOram|ram_block1a0~porta_we_reg ; CLK ; +; 4.337 ns ; 10.000 ns ; 5.663 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_d5b:wr_ptr|safe_q[5] ; CLK ; +; 4.337 ns ; 10.000 ns ; 5.663 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_d5b:wr_ptr|safe_q[4] ; CLK ; +; 4.337 ns ; 10.000 ns ; 5.663 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_d5b:wr_ptr|safe_q[3] ; CLK ; +; 4.337 ns ; 10.000 ns ; 5.663 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_d5b:wr_ptr|safe_q[2] ; CLK ; +; 4.337 ns ; 10.000 ns ; 5.663 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_d5b:wr_ptr|safe_q[1] ; CLK ; +; 4.337 ns ; 10.000 ns ; 5.663 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_d5b:wr_ptr|safe_q[0] ; CLK ; +; 4.343 ns ; 10.000 ns ; 5.657 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|rd_ptr_lsb ; CLK ; +; 4.373 ns ; 10.000 ns ; 5.627 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[4] ; CLK ; +; 4.373 ns ; 10.000 ns ; 5.627 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[3] ; CLK ; +; 4.373 ns ; 10.000 ns ; 5.627 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[2] ; CLK ; +; 4.373 ns ; 10.000 ns ; 5.627 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[1] ; CLK ; +; 4.373 ns ; 10.000 ns ; 5.627 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[0] ; CLK ; +; 4.382 ns ; 10.000 ns ; 5.618 ns ; WR ; uart_16750:inst|iIER[3] ; CLK ; +; 4.386 ns ; 10.000 ns ; 5.614 ns ; CS ; uart_16750:inst|iTimeoutCount[0] ; CLK ; +; 4.386 ns ; 10.000 ns ; 5.614 ns ; CS ; uart_16750:inst|iTimeoutCount[1] ; CLK ; +; 4.386 ns ; 10.000 ns ; 5.614 ns ; CS ; uart_16750:inst|iTimeoutCount[2] ; CLK ; +; 4.386 ns ; 10.000 ns ; 5.614 ns ; CS ; uart_16750:inst|iTimeoutCount[3] ; CLK ; +; 4.386 ns ; 10.000 ns ; 5.614 ns ; CS ; uart_16750:inst|iTimeoutCount[4] ; CLK ; +; 4.386 ns ; 10.000 ns ; 5.614 ns ; CS ; uart_16750:inst|iTimeoutCount[5] ; CLK ; +; 4.387 ns ; 10.000 ns ; 5.613 ns ; WR ; uart_16750:inst|iFCR_RXTrigger[1] ; CLK ; +; 4.387 ns ; 10.000 ns ; 5.613 ns ; WR ; uart_16750:inst|iFCR_RXTrigger[0] ; CLK ; +; 4.387 ns ; 10.000 ns ; 5.613 ns ; WR ; uart_16750:inst|iFCR_FIFOEnable ; CLK ; +; 4.406 ns ; 10.000 ns ; 5.594 ns ; CS ; uart_16750:inst|iMSR_dCTS ; CLK ; +; 4.408 ns ; 10.000 ns ; 5.592 ns ; WR ; uart_16750:inst|iIER[2] ; CLK ; +; 4.408 ns ; 10.000 ns ; 5.592 ns ; WR ; uart_16750:inst|iIER[1] ; CLK ; +; 4.408 ns ; 10.000 ns ; 5.592 ns ; WR ; uart_16750:inst|iIER[0] ; CLK ; +; 4.409 ns ; 10.000 ns ; 5.591 ns ; WR ; uart_16750:inst|iDLM[7] ; CLK ; +; 4.409 ns ; 10.000 ns ; 5.591 ns ; WR ; uart_16750:inst|iDLM[4] ; CLK ; +; 4.409 ns ; 10.000 ns ; 5.591 ns ; WR ; uart_16750:inst|iDLM[6] ; CLK ; +; 4.409 ns ; 10.000 ns ; 5.591 ns ; WR ; uart_16750:inst|iDLM[5] ; CLK ; +; 4.426 ns ; 10.000 ns ; 5.574 ns ; RD ; uart_16750:inst|iCharTimeout ; CLK ; +; 4.429 ns ; 10.000 ns ; 5.571 ns ; CS ; uart_16750:inst|iLCR[2] ; CLK ; +; 4.429 ns ; 10.000 ns ; 5.571 ns ; CS ; uart_16750:inst|iLCR[6] ; CLK ; +; 4.429 ns ; 10.000 ns ; 5.571 ns ; CS ; uart_16750:inst|iLCR[1] ; CLK ; +; 4.429 ns ; 10.000 ns ; 5.571 ns ; CS ; uart_16750:inst|iLCR[4] ; CLK ; +; 4.439 ns ; 10.000 ns ; 5.561 ns ; CS ; uart_16750:inst|iLCR[0] ; CLK ; +; 4.439 ns ; 10.000 ns ; 5.561 ns ; CS ; uart_16750:inst|iLCR[3] ; CLK ; +; 4.445 ns ; 10.000 ns ; 5.555 ns ; CS ; uart_16750:inst|iSCR[1] ; CLK ; +; 4.445 ns ; 10.000 ns ; 5.555 ns ; CS ; uart_16750:inst|iSCR[2] ; CLK ; +; 4.445 ns ; 10.000 ns ; 5.555 ns ; CS ; uart_16750:inst|iSCR[3] ; CLK ; +; 4.447 ns ; 10.000 ns ; 5.553 ns ; CS ; uart_16750:inst|iDLM[3] ; CLK ; +; 4.448 ns ; 10.000 ns ; 5.552 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg2 ; CLK ; +; 4.461 ns ; 10.000 ns ; 5.539 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg3 ; CLK ; +; 4.481 ns ; 10.000 ns ; 5.519 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[2] ; CLK ; +; 4.488 ns ; 10.000 ns ; 5.512 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg5 ; CLK ; +; 4.504 ns ; 10.000 ns ; 5.496 ns ; CS ; uart_16750:inst|iDLM[2] ; CLK ; +; 4.504 ns ; 10.000 ns ; 5.496 ns ; CS ; uart_16750:inst|iDLM[0] ; CLK ; +; 4.504 ns ; 10.000 ns ; 5.496 ns ; CS ; uart_16750:inst|iDLM[1] ; CLK ; +; 4.518 ns ; 10.000 ns ; 5.482 ns ; WR ; uart_16750:inst|iFCR_FIFO64E ; CLK ; +; 4.561 ns ; 10.000 ns ; 5.439 ns ; WR ; uart_16750:inst|iSCR[1] ; CLK ; +; 4.561 ns ; 10.000 ns ; 5.439 ns ; WR ; uart_16750:inst|iSCR[2] ; CLK ; +; 4.561 ns ; 10.000 ns ; 5.439 ns ; WR ; uart_16750:inst|iSCR[3] ; CLK ; +; 4.567 ns ; 10.000 ns ; 5.433 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|altsyncram_t681:FIFOram|ram_block1a0~porta_we_reg ; CLK ; +; 4.640 ns ; 10.000 ns ; 5.360 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[4] ; CLK ; +; 4.640 ns ; 10.000 ns ; 5.360 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[3] ; CLK ; +; 4.641 ns ; 10.000 ns ; 5.359 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[1] ; CLK ; +; 4.641 ns ; 10.000 ns ; 5.359 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[0] ; CLK ; +; 4.642 ns ; 10.000 ns ; 5.358 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[5] ; CLK ; +; 4.680 ns ; 10.000 ns ; 5.320 ns ; CS ; uart_16750:inst|iIER[3] ; CLK ; +; 4.685 ns ; 10.000 ns ; 5.315 ns ; CS ; uart_16750:inst|iFCR_RXTrigger[1] ; CLK ; +; 4.685 ns ; 10.000 ns ; 5.315 ns ; CS ; uart_16750:inst|iFCR_RXTrigger[0] ; CLK ; +; 4.685 ns ; 10.000 ns ; 5.315 ns ; CS ; uart_16750:inst|iFCR_FIFOEnable ; CLK ; +; 4.705 ns ; 10.000 ns ; 5.295 ns ; CS ; uart_16750:inst|iLSR_PE ; CLK ; +; 4.706 ns ; 10.000 ns ; 5.294 ns ; CS ; uart_16750:inst|iLSR_BI ; CLK ; +; 4.706 ns ; 10.000 ns ; 5.294 ns ; CS ; uart_16750:inst|iIER[2] ; CLK ; +; 4.706 ns ; 10.000 ns ; 5.294 ns ; CS ; uart_16750:inst|iIER[1] ; CLK ; +; 4.706 ns ; 10.000 ns ; 5.294 ns ; CS ; uart_16750:inst|iIER[0] ; CLK ; +; 4.707 ns ; 10.000 ns ; 5.293 ns ; CS ; uart_16750:inst|iDLM[7] ; CLK ; +; 4.707 ns ; 10.000 ns ; 5.293 ns ; CS ; uart_16750:inst|iDLM[4] ; CLK ; +; 4.707 ns ; 10.000 ns ; 5.293 ns ; CS ; uart_16750:inst|iDLM[6] ; CLK ; +; 4.707 ns ; 10.000 ns ; 5.293 ns ; CS ; uart_16750:inst|iDLM[5] ; CLK ; +; 4.733 ns ; 10.000 ns ; 5.267 ns ; CS ; uart_16750:inst|iSCR[0] ; CLK ; +; 4.736 ns ; 10.000 ns ; 5.264 ns ; CS ; uart_16750:inst|iMCR[0] ; CLK ; +; 4.736 ns ; 10.000 ns ; 5.264 ns ; CS ; uart_16750:inst|iMCR[5] ; CLK ; +; 4.736 ns ; 10.000 ns ; 5.264 ns ; CS ; uart_16750:inst|iMCR[4] ; CLK ; +; 4.814 ns ; 10.000 ns ; 5.186 ns ; WR ; uart_16750:inst|iFCR_RXFIFOReset ; CLK ; +; 4.816 ns ; 10.000 ns ; 5.184 ns ; CS ; uart_16750:inst|iFCR_FIFO64E ; CLK ; +; 4.817 ns ; 10.000 ns ; 5.183 ns ; WR ; uart_16750:inst|iFCR_TXFIFOReset ; CLK ; +; 4.849 ns ; 10.000 ns ; 5.151 ns ; WR ; uart_16750:inst|iSCR[0] ; CLK ; +; 4.852 ns ; 10.000 ns ; 5.148 ns ; WR ; uart_16750:inst|iMCR[0] ; CLK ; +; 4.852 ns ; 10.000 ns ; 5.148 ns ; WR ; uart_16750:inst|iMCR[5] ; CLK ; +; 4.852 ns ; 10.000 ns ; 5.148 ns ; WR ; uart_16750:inst|iMCR[4] ; CLK ; +; 4.871 ns ; 10.000 ns ; 5.129 ns ; WR ; uart_16750:inst|iDLL[6] ; CLK ; +; 4.871 ns ; 10.000 ns ; 5.129 ns ; WR ; uart_16750:inst|iDLL[7] ; CLK ; +; 4.874 ns ; 10.000 ns ; 5.126 ns ; WR ; uart_16750:inst|iDLL[3] ; CLK ; +; 4.874 ns ; 10.000 ns ; 5.126 ns ; WR ; uart_16750:inst|iDLL[4] ; CLK ; +; 4.874 ns ; 10.000 ns ; 5.126 ns ; WR ; uart_16750:inst|iDLL[1] ; CLK ; +; 4.874 ns ; 10.000 ns ; 5.126 ns ; WR ; uart_16750:inst|iDLL[2] ; CLK ; +; 4.874 ns ; 10.000 ns ; 5.126 ns ; WR ; uart_16750:inst|iDLL[0] ; CLK ; +; 4.879 ns ; 10.000 ns ; 5.121 ns ; CS ; uart_16750:inst|iCharTimeout ; CLK ; +; 4.897 ns ; 10.000 ns ; 5.103 ns ; WR ; uart_16750:inst|iLCR[5] ; CLK ; +; 4.897 ns ; 10.000 ns ; 5.103 ns ; WR ; uart_16750:inst|iLCR[7] ; CLK ; +; 4.917 ns ; 10.000 ns ; 5.083 ns ; CS ; uart_16750:inst|iLSR_OE ; CLK ; +; 4.920 ns ; 10.000 ns ; 5.080 ns ; CS ; uart_16750:inst|iLSR_FE ; CLK ; +; 4.933 ns ; 10.000 ns ; 5.067 ns ; CS ; uart_16750:inst|iMCR[3] ; CLK ; +; 4.933 ns ; 10.000 ns ; 5.067 ns ; CS ; uart_16750:inst|iMCR[2] ; CLK ; +; 4.933 ns ; 10.000 ns ; 5.067 ns ; CS ; uart_16750:inst|iMCR[1] ; CLK ; +; 4.964 ns ; 10.000 ns ; 5.036 ns ; CS ; uart_16750:inst|iSCR[4] ; CLK ; +; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ++-----------------------------------------+-----------------------------------------------------+------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; tco ; ++----------+--------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+------------+ +; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ; ++----------+--------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+------------+ +; 2.856 ns ; 15.000 ns ; 12.144 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg5 ; DOUT[3] ; CLK ; +; 2.856 ns ; 15.000 ns ; 12.144 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg4 ; DOUT[3] ; CLK ; +; 2.856 ns ; 15.000 ns ; 12.144 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg3 ; DOUT[3] ; CLK ; +; 2.856 ns ; 15.000 ns ; 12.144 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg2 ; DOUT[3] ; CLK ; +; 2.856 ns ; 15.000 ns ; 12.144 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg1 ; DOUT[3] ; CLK ; +; 2.856 ns ; 15.000 ns ; 12.144 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg0 ; DOUT[3] ; CLK ; +; 3.224 ns ; 15.000 ns ; 11.776 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg5 ; DOUT[5] ; CLK ; +; 3.224 ns ; 15.000 ns ; 11.776 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg4 ; DOUT[5] ; CLK ; +; 3.224 ns ; 15.000 ns ; 11.776 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg3 ; DOUT[5] ; CLK ; +; 3.224 ns ; 15.000 ns ; 11.776 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg2 ; DOUT[5] ; CLK ; +; 3.224 ns ; 15.000 ns ; 11.776 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg1 ; DOUT[5] ; CLK ; +; 3.224 ns ; 15.000 ns ; 11.776 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg0 ; DOUT[5] ; CLK ; +; 3.265 ns ; 15.000 ns ; 11.735 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg5 ; DOUT[0] ; CLK ; +; 3.265 ns ; 15.000 ns ; 11.735 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg4 ; DOUT[0] ; CLK ; +; 3.265 ns ; 15.000 ns ; 11.735 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg3 ; DOUT[0] ; CLK ; +; 3.265 ns ; 15.000 ns ; 11.735 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg2 ; DOUT[0] ; CLK ; +; 3.265 ns ; 15.000 ns ; 11.735 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg1 ; DOUT[0] ; CLK ; +; 3.265 ns ; 15.000 ns ; 11.735 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg0 ; DOUT[0] ; CLK ; +; 3.443 ns ; 15.000 ns ; 11.557 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg5 ; DOUT[7] ; CLK ; +; 3.443 ns ; 15.000 ns ; 11.557 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg4 ; DOUT[7] ; CLK ; +; 3.443 ns ; 15.000 ns ; 11.557 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg3 ; DOUT[7] ; CLK ; +; 3.443 ns ; 15.000 ns ; 11.557 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg2 ; DOUT[7] ; CLK ; +; 3.443 ns ; 15.000 ns ; 11.557 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg1 ; DOUT[7] ; CLK ; +; 3.443 ns ; 15.000 ns ; 11.557 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg0 ; DOUT[7] ; CLK ; +; 3.447 ns ; 15.000 ns ; 11.553 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg5 ; DOUT[2] ; CLK ; +; 3.447 ns ; 15.000 ns ; 11.553 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg4 ; DOUT[2] ; CLK ; +; 3.447 ns ; 15.000 ns ; 11.553 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg3 ; DOUT[2] ; CLK ; +; 3.447 ns ; 15.000 ns ; 11.553 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg2 ; DOUT[2] ; CLK ; +; 3.447 ns ; 15.000 ns ; 11.553 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg1 ; DOUT[2] ; CLK ; +; 3.447 ns ; 15.000 ns ; 11.553 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg0 ; DOUT[2] ; CLK ; +; 3.639 ns ; 15.000 ns ; 11.361 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg5 ; DOUT[1] ; CLK ; +; 3.639 ns ; 15.000 ns ; 11.361 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg4 ; DOUT[1] ; CLK ; +; 3.639 ns ; 15.000 ns ; 11.361 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg3 ; DOUT[1] ; CLK ; +; 3.639 ns ; 15.000 ns ; 11.361 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg2 ; DOUT[1] ; CLK ; +; 3.639 ns ; 15.000 ns ; 11.361 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg1 ; DOUT[1] ; CLK ; +; 3.639 ns ; 15.000 ns ; 11.361 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg0 ; DOUT[1] ; CLK ; +; 3.800 ns ; 15.000 ns ; 11.200 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg5 ; DOUT[4] ; CLK ; +; 3.800 ns ; 15.000 ns ; 11.200 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg4 ; DOUT[4] ; CLK ; +; 3.800 ns ; 15.000 ns ; 11.200 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg3 ; DOUT[4] ; CLK ; +; 3.800 ns ; 15.000 ns ; 11.200 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg2 ; DOUT[4] ; CLK ; +; 3.800 ns ; 15.000 ns ; 11.200 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg1 ; DOUT[4] ; CLK ; +; 3.800 ns ; 15.000 ns ; 11.200 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg0 ; DOUT[4] ; CLK ; +; 3.944 ns ; 15.000 ns ; 11.056 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg5 ; DOUT[6] ; CLK ; +; 3.944 ns ; 15.000 ns ; 11.056 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg4 ; DOUT[6] ; CLK ; +; 3.944 ns ; 15.000 ns ; 11.056 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg3 ; DOUT[6] ; CLK ; +; 3.944 ns ; 15.000 ns ; 11.056 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg2 ; DOUT[6] ; CLK ; +; 3.944 ns ; 15.000 ns ; 11.056 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg1 ; DOUT[6] ; CLK ; +; 3.944 ns ; 15.000 ns ; 11.056 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg0 ; DOUT[6] ; CLK ; +; 4.127 ns ; 15.000 ns ; 10.873 ns ; uart_16750:inst|iLCR[7] ; DOUT[3] ; CLK ; +; 4.486 ns ; 15.000 ns ; 10.514 ns ; uart_16750:inst|iLCR[7] ; DOUT[0] ; CLK ; +; 4.550 ns ; 15.000 ns ; 10.450 ns ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|empty_dff ; DOUT[6] ; CLK ; +; 4.594 ns ; 15.000 ns ; 10.406 ns ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|empty_dff ; DOUT[0] ; CLK ; +; 4.722 ns ; 15.000 ns ; 10.278 ns ; uart_16750:inst|iLCR[7] ; DOUT[2] ; CLK ; +; 4.875 ns ; 15.000 ns ; 10.125 ns ; uart_16750:inst|iLSR_FE ; DOUT[3] ; CLK ; +; 4.894 ns ; 15.000 ns ; 10.106 ns ; uart_16750:inst|iRXFIFOWrite ; DOUT[0] ; CLK ; +; 4.913 ns ; 15.000 ns ; 10.087 ns ; uart_16750:inst|iLCR[7] ; DOUT[1] ; CLK ; +; 5.035 ns ; 15.000 ns ; 9.965 ns ; uart_16750:inst|iLCR[7] ; DOUT[6] ; CLK ; +; 5.047 ns ; 15.000 ns ; 9.953 ns ; uart_16750:inst|iFCR_FIFOEnable ; DOUT[5] ; CLK ; +; 5.084 ns ; 15.000 ns ; 9.916 ns ; uart_16750:inst|iLCR[7] ; DOUT[7] ; CLK ; +; 5.114 ns ; 15.000 ns ; 9.886 ns ; uart_16750:inst|iMCR[4] ; DOUT[7] ; CLK ; +; 5.228 ns ; 15.000 ns ; 9.772 ns ; uart_16750:inst|iLCR[0] ; DOUT[0] ; CLK ; +; 5.254 ns ; 15.000 ns ; 9.746 ns ; uart_16750:inst|iTXRunning ; DOUT[6] ; CLK ; +; 5.255 ns ; 15.000 ns ; 9.745 ns ; uart_16750:inst|iMCR[3] ; DOUT[7] ; CLK ; +; 5.260 ns ; 15.000 ns ; 9.740 ns ; uart_16750:inst|iMCR[4] ; DOUT[5] ; CLK ; +; 5.275 ns ; 15.000 ns ; 9.725 ns ; uart_16750:inst|iFCR_FIFO64E ; DOUT[5] ; CLK ; +; 5.295 ns ; 15.000 ns ; 9.705 ns ; uart_16750:inst|iLSR_FIFOERR ; DOUT[7] ; CLK ; +; 5.307 ns ; 15.000 ns ; 9.693 ns ; uart_16750:inst|iLCR[7] ; DOUT[5] ; CLK ; +; 5.413 ns ; 15.000 ns ; 9.587 ns ; uart_16750:inst|slib_input_filter:UART_IF_DSR|Q ; DOUT[5] ; CLK ; +; 5.487 ns ; 15.000 ns ; 9.513 ns ; uart_16750:inst|iDLM[3] ; DOUT[3] ; CLK ; +; 5.503 ns ; 15.000 ns ; 9.497 ns ; uart_16750:inst|iIER[3] ; DOUT[3] ; CLK ; +; 5.549 ns ; 15.000 ns ; 9.451 ns ; uart_16750:inst|iMCR[4] ; DOUT[6] ; CLK ; +; 5.571 ns ; 15.000 ns ; 9.429 ns ; uart_16750:inst|uart_interrupt:UART_IIC|iIIR[3] ; DOUT[3] ; CLK ; +; 5.612 ns ; 15.000 ns ; 9.388 ns ; uart_16750:inst|slib_input_filter:UART_IF_DCD|Q ; DOUT[7] ; CLK ; +; 5.711 ns ; 15.000 ns ; 9.289 ns ; uart_16750:inst|iDLM[4] ; DOUT[4] ; CLK ; +; 5.737 ns ; 15.000 ns ; 9.263 ns ; uart_16750:inst|iMCR[0] ; DOUT[5] ; CLK ; +; 5.798 ns ; 15.000 ns ; 9.202 ns ; uart_16750:inst|iMCR[2] ; DOUT[6] ; CLK ; +; 5.841 ns ; 15.000 ns ; 9.159 ns ; uart_16750:inst|iLSR_OE ; DOUT[1] ; CLK ; +; 5.899 ns ; 15.000 ns ; 9.101 ns ; uart_16750:inst|slib_input_filter:UART_IF_RI|Q ; DOUT[6] ; CLK ; +; 5.936 ns ; 15.000 ns ; 9.064 ns ; uart_16750:inst|slib_input_filter:UART_IF_CTS|Q ; DOUT[4] ; CLK ; +; 5.950 ns ; 15.000 ns ; 9.050 ns ; uart_16750:inst|iDLM[5] ; DOUT[5] ; CLK ; +; 5.956 ns ; 15.000 ns ; 9.044 ns ; uart_16750:inst|iDLM[0] ; DOUT[0] ; CLK ; +; 6.113 ns ; 15.000 ns ; 8.887 ns ; uart_16750:inst|iRTS ; DOUT[4] ; CLK ; +; 6.114 ns ; 15.000 ns ; 8.886 ns ; uart_16750:inst|iLCR[7] ; DOUT[4] ; CLK ; +; 6.123 ns ; 15.000 ns ; 8.877 ns ; uart_16750:inst|iLSR_BI ; DOUT[4] ; CLK ; +; 6.142 ns ; 15.000 ns ; 8.858 ns ; uart_16750:inst|iDLL[3] ; DOUT[3] ; CLK ; +; 6.145 ns ; 15.000 ns ; 8.855 ns ; uart_16750:inst|iLCR[2] ; DOUT[2] ; CLK ; +; 6.157 ns ; 15.000 ns ; 8.843 ns ; uart_16750:inst|iMCR[5] ; DOUT[5] ; CLK ; +; 6.185 ns ; 15.000 ns ; 8.815 ns ; uart_16750:inst|iFCR_FIFOEnable ; DOUT[7] ; CLK ; +; 6.218 ns ; 15.000 ns ; 8.782 ns ; uart_16750:inst|uart_interrupt:UART_IIC|iIIR[0] ; DOUT[0] ; CLK ; +; 6.240 ns ; 15.000 ns ; 8.760 ns ; uart_16750:inst|iMCR[0] ; DOUT[0] ; CLK ; +; 6.256 ns ; 15.000 ns ; 8.744 ns ; uart_16750:inst|iMCR[4] ; DOUT[4] ; CLK ; +; 6.266 ns ; 15.000 ns ; 8.734 ns ; uart_16750:inst|iFCR_FIFOEnable ; DOUT[6] ; CLK ; +; 6.278 ns ; 15.000 ns ; 8.722 ns ; uart_16750:inst|iLCR[1] ; DOUT[1] ; CLK ; +; 6.287 ns ; 15.000 ns ; 8.713 ns ; uart_16750:inst|iLSR_PE ; DOUT[2] ; CLK ; +; 6.326 ns ; 15.000 ns ; 8.674 ns ; uart_16750:inst|iDLL[4] ; DOUT[4] ; CLK ; +; 6.351 ns ; 15.000 ns ; 8.649 ns ; uart_16750:inst|iIER[0] ; DOUT[0] ; CLK ; +; 6.353 ns ; 15.000 ns ; 8.647 ns ; uart_16750:inst|iDLM[6] ; DOUT[6] ; CLK ; +; 6.386 ns ; 15.000 ns ; 8.614 ns ; uart_16750:inst|iLCR[3] ; DOUT[3] ; CLK ; +; 6.400 ns ; 15.000 ns ; 8.600 ns ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|empty_dff ; DOUT[5] ; CLK ; +; 6.408 ns ; 15.000 ns ; 8.592 ns ; uart_16750:inst|uart_interrupt:UART_IIC|iIIR[2] ; DOUT[2] ; CLK ; +; 6.528 ns ; 15.000 ns ; 8.472 ns ; uart_16750:inst|iLCR[6] ; DOUT[6] ; CLK ; +; 6.571 ns ; 15.000 ns ; 8.429 ns ; uart_16750:inst|iDLL[0] ; DOUT[0] ; CLK ; +; 6.575 ns ; 15.000 ns ; 8.425 ns ; uart_16750:inst|iDLM[7] ; DOUT[7] ; CLK ; +; 6.580 ns ; 15.000 ns ; 8.420 ns ; uart_16750:inst|uart_interrupt:UART_IIC|iIIR[1] ; DOUT[1] ; CLK ; +; 6.607 ns ; 15.000 ns ; 8.393 ns ; uart_16750:inst|iDLM[2] ; DOUT[2] ; CLK ; +; 6.723 ns ; 15.000 ns ; 8.277 ns ; uart_16750:inst|iDLM[1] ; DOUT[1] ; CLK ; +; 6.731 ns ; 15.000 ns ; 8.269 ns ; uart_16750:inst|iMCR[3] ; DOUT[3] ; CLK ; +; 6.732 ns ; 15.000 ns ; 8.268 ns ; uart_16750:inst|iDLL[2] ; DOUT[2] ; CLK ; +; 6.780 ns ; 15.000 ns ; 8.220 ns ; uart_16750:inst|iMSR_dDCD ; DOUT[3] ; CLK ; +; 6.806 ns ; 15.000 ns ; 8.194 ns ; uart_16750:inst|iDLL[5] ; DOUT[5] ; CLK ; +; 6.885 ns ; 15.000 ns ; 8.115 ns ; uart_16750:inst|iDLL[6] ; DOUT[6] ; CLK ; +; 6.924 ns ; 15.000 ns ; 8.076 ns ; uart_16750:inst|iDLL[1] ; DOUT[1] ; CLK ; +; 6.927 ns ; 15.000 ns ; 8.073 ns ; uart_16750:inst|iDLL[7] ; DOUT[7] ; CLK ; +; 6.998 ns ; 15.000 ns ; 8.002 ns ; uart_16750:inst|iIER[2] ; DOUT[2] ; CLK ; +; 7.115 ns ; 15.000 ns ; 7.885 ns ; uart_16750:inst|iIER[1] ; DOUT[1] ; CLK ; +; 7.262 ns ; 15.000 ns ; 7.738 ns ; uart_16750:inst|iSCR[5] ; DOUT[5] ; CLK ; +; 7.263 ns ; 15.000 ns ; 7.737 ns ; uart_16750:inst|iMSR_TERI ; DOUT[2] ; CLK ; +; 7.317 ns ; 15.000 ns ; 7.683 ns ; uart_16750:inst|iMSR_dCTS ; DOUT[0] ; CLK ; +; 7.319 ns ; 15.000 ns ; 7.681 ns ; uart_16750:inst|iMCR[2] ; DOUT[2] ; CLK ; +; 7.390 ns ; 15.000 ns ; 7.610 ns ; uart_16750:inst|iSCR[4] ; DOUT[4] ; CLK ; +; 7.451 ns ; 15.000 ns ; 7.549 ns ; uart_16750:inst|iSCR[7] ; DOUT[7] ; CLK ; +; 7.462 ns ; 15.000 ns ; 7.538 ns ; uart_16750:inst|iMCR[1] ; DOUT[1] ; CLK ; +; 7.474 ns ; 15.000 ns ; 7.526 ns ; uart_16750:inst|iMSR_dDSR ; DOUT[1] ; CLK ; +; 7.600 ns ; 15.000 ns ; 7.400 ns ; uart_16750:inst|iLCR[5] ; DOUT[5] ; CLK ; +; 7.654 ns ; 15.000 ns ; 7.346 ns ; uart_16750:inst|iSCR[3] ; DOUT[3] ; CLK ; +; 7.704 ns ; 15.000 ns ; 7.296 ns ; uart_16750:inst|iLCR[4] ; DOUT[4] ; CLK ; +; 7.711 ns ; 15.000 ns ; 7.289 ns ; uart_16750:inst|iSCR[6] ; DOUT[6] ; CLK ; +; 8.115 ns ; 15.000 ns ; 6.885 ns ; uart_16750:inst|iSCR[2] ; DOUT[2] ; CLK ; +; 8.167 ns ; 15.000 ns ; 6.833 ns ; uart_16750:inst|iSCR[0] ; DOUT[0] ; CLK ; +; 8.198 ns ; 15.000 ns ; 6.802 ns ; uart_16750:inst|uart_interrupt:UART_IIC|iIIR[0] ; INT ; CLK ; +; 8.201 ns ; 15.000 ns ; 6.799 ns ; uart_16750:inst|DDIS ; DDIS ; CLK ; +; 8.386 ns ; 15.000 ns ; 6.614 ns ; uart_16750:inst|iSCR[1] ; DOUT[1] ; CLK ; +; 8.486 ns ; 15.000 ns ; 6.514 ns ; uart_16750:inst|RTSN ; RTSN ; CLK ; +; 8.509 ns ; 15.000 ns ; 6.491 ns ; uart_16750:inst|DTRN ; DTRN ; CLK ; +; 8.711 ns ; 15.000 ns ; 6.289 ns ; uart_16750:inst|SOUT ; SOUT ; CLK ; +; 8.844 ns ; 15.000 ns ; 6.156 ns ; uart_16750:inst|OUT1N ; OUT1N ; CLK ; +; 8.977 ns ; 15.000 ns ; 6.023 ns ; uart_16750:inst|OUT2N ; OUT2N ; CLK ; ++----------+--------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+------------+ + + ++--------------------------------------------------------------+ +; tpd ; ++-------+-------------------+-----------------+------+---------+ +; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ; ++-------+-------------------+-----------------+------+---------+ +; N/A ; None ; 14.563 ns ; A[1] ; DOUT[3] ; +; N/A ; None ; 14.343 ns ; A[2] ; DOUT[3] ; +; N/A ; None ; 14.204 ns ; A[1] ; DOUT[0] ; +; N/A ; None ; 13.968 ns ; A[1] ; DOUT[2] ; +; N/A ; None ; 13.938 ns ; A[2] ; DOUT[0] ; +; N/A ; None ; 13.777 ns ; A[1] ; DOUT[1] ; +; N/A ; None ; 13.702 ns ; A[2] ; DOUT[2] ; +; N/A ; None ; 13.511 ns ; A[2] ; DOUT[1] ; +; N/A ; None ; 13.266 ns ; A[1] ; DOUT[6] ; +; N/A ; None ; 13.217 ns ; A[1] ; DOUT[7] ; +; N/A ; None ; 13.057 ns ; A[0] ; DOUT[5] ; +; N/A ; None ; 12.967 ns ; A[2] ; DOUT[6] ; +; N/A ; None ; 12.958 ns ; A[0] ; DOUT[4] ; +; N/A ; None ; 12.797 ns ; A[1] ; DOUT[5] ; +; N/A ; None ; 12.778 ns ; A[2] ; DOUT[7] ; +; N/A ; None ; 12.697 ns ; A[1] ; DOUT[4] ; +; N/A ; None ; 11.717 ns ; A[0] ; DOUT[3] ; +; N/A ; None ; 11.264 ns ; A[0] ; DOUT[2] ; +; N/A ; None ; 11.071 ns ; A[0] ; DOUT[0] ; +; N/A ; None ; 10.987 ns ; A[0] ; DOUT[1] ; +; N/A ; None ; 10.837 ns ; A[0] ; DOUT[7] ; +; N/A ; None ; 10.686 ns ; A[2] ; DOUT[4] ; +; N/A ; None ; 10.584 ns ; A[0] ; DOUT[6] ; +; N/A ; None ; 10.286 ns ; A[2] ; DOUT[5] ; ++-------+-------------------+-----------------+------+---------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; th ; ++-----------------------------------------+-----------------------------------------------------+-----------+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------+ +; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ; ++-----------------------------------------+-----------------------------------------------------+-----------+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------+ +; N/A ; None ; -2.602 ns ; WR ; uart_16750:inst|slib_edge_detect:UART_ED_WRITE|iDd ; CLK ; +; N/A ; None ; -2.855 ns ; CS ; uart_16750:inst|slib_edge_detect:UART_ED_WRITE|iDd ; CLK ; +; N/A ; None ; -2.879 ns ; CS ; uart_16750:inst|DDIS ; CLK ; +; N/A ; None ; -2.910 ns ; RSTN ; inst4 ; CLK ; +; N/A ; None ; -2.916 ns ; DCDN ; uart_16750:inst|slib_input_sync:UART_IS_DCD|iD[0] ; CLK ; +; N/A ; None ; -2.920 ns ; CTSN ; uart_16750:inst|slib_input_sync:UART_IS_CTS|iD[0] ; CLK ; +; N/A ; None ; -3.212 ns ; DIN[3] ; uart_16750:inst|iDIN[3] ; CLK ; +; N/A ; None ; -3.215 ns ; DIN[7] ; uart_16750:inst|iDIN[7] ; CLK ; +; N/A ; None ; -3.218 ns ; DIN[5] ; uart_16750:inst|iDIN[5] ; CLK ; +; N/A ; None ; -3.333 ns ; DSRN ; uart_16750:inst|slib_input_sync:UART_IS_DSR|iD[0] ; CLK ; +; N/A ; None ; -3.351 ns ; RIN ; uart_16750:inst|slib_input_sync:UART_IS_RI|iD[0] ; CLK ; +; N/A ; None ; -3.355 ns ; DIN[6] ; uart_16750:inst|iDIN[6] ; CLK ; +; N/A ; None ; -3.362 ns ; DIN[4] ; uart_16750:inst|iDIN[4] ; CLK ; +; N/A ; None ; -3.410 ns ; CS ; uart_16750:inst|slib_edge_detect:UART_ED_READ|iDd ; CLK ; +; N/A ; None ; -3.536 ns ; DIN[2] ; uart_16750:inst|iDIN[2] ; CLK ; +; N/A ; None ; -3.599 ns ; A[0] ; uart_16750:inst|iA[0] ; CLK ; +; N/A ; None ; -3.613 ns ; A[1] ; uart_16750:inst|iA[1] ; CLK ; +; N/A ; None ; -3.626 ns ; DIN[0] ; uart_16750:inst|iDIN[0] ; CLK ; +; N/A ; None ; -3.629 ns ; A[2] ; uart_16750:inst|iA[2] ; CLK ; +; N/A ; None ; -3.914 ns ; RD ; uart_16750:inst|DDIS ; CLK ; +; N/A ; None ; -4.038 ns ; SIN ; uart_16750:inst|slib_input_sync:UART_IS_SIN|iD[0] ; CLK ; +; N/A ; None ; -4.040 ns ; DIN[1] ; uart_16750:inst|iDIN[1] ; CLK ; +; N/A ; None ; -4.183 ns ; CS ; uart_16750:inst|iTHRInterrupt ; CLK ; +; N/A ; None ; -4.323 ns ; CS ; uart_16750:inst|iDLL[5] ; CLK ; +; N/A ; None ; -4.410 ns ; WR ; uart_16750:inst|iSCR[7] ; CLK ; +; N/A ; None ; -4.410 ns ; WR ; uart_16750:inst|iSCR[6] ; CLK ; +; N/A ; None ; -4.410 ns ; WR ; uart_16750:inst|iSCR[5] ; CLK ; +; N/A ; None ; -4.445 ns ; RD ; uart_16750:inst|slib_edge_detect:UART_ED_READ|iDd ; CLK ; +; N/A ; None ; -4.481 ns ; WR ; uart_16750:inst|iTHRInterrupt ; CLK ; +; N/A ; None ; -4.526 ns ; CS ; uart_16750:inst|iSCR[7] ; CLK ; +; N/A ; None ; -4.526 ns ; CS ; uart_16750:inst|iSCR[6] ; CLK ; +; N/A ; None ; -4.526 ns ; CS ; uart_16750:inst|iSCR[5] ; CLK ; +; N/A ; None ; -4.575 ns ; CS ; uart_16750:inst|iLCR[7] ; CLK ; +; N/A ; None ; -4.575 ns ; CS ; uart_16750:inst|iLCR[5] ; CLK ; +; N/A ; None ; -4.598 ns ; CS ; uart_16750:inst|iDLL[0] ; CLK ; +; N/A ; None ; -4.598 ns ; CS ; uart_16750:inst|iDLL[2] ; CLK ; +; N/A ; None ; -4.598 ns ; CS ; uart_16750:inst|iDLL[1] ; CLK ; +; N/A ; None ; -4.598 ns ; CS ; uart_16750:inst|iDLL[4] ; CLK ; +; N/A ; None ; -4.598 ns ; CS ; uart_16750:inst|iDLL[3] ; CLK ; +; N/A ; None ; -4.601 ns ; CS ; uart_16750:inst|iDLL[7] ; CLK ; +; N/A ; None ; -4.601 ns ; CS ; uart_16750:inst|iDLL[6] ; CLK ; +; N/A ; None ; -4.621 ns ; WR ; uart_16750:inst|iDLL[5] ; CLK ; +; N/A ; None ; -4.655 ns ; CS ; uart_16750:inst|iFCR_TXFIFOReset ; CLK ; +; N/A ; None ; -4.658 ns ; CS ; uart_16750:inst|iFCR_RXFIFOReset ; CLK ; +; N/A ; None ; -4.690 ns ; WR ; uart_16750:inst|iSCR[4] ; CLK ; +; N/A ; None ; -4.721 ns ; WR ; uart_16750:inst|iMCR[1] ; CLK ; +; N/A ; None ; -4.721 ns ; WR ; uart_16750:inst|iMCR[2] ; CLK ; +; N/A ; None ; -4.721 ns ; WR ; uart_16750:inst|iMCR[3] ; CLK ; +; N/A ; None ; -4.806 ns ; CS ; uart_16750:inst|iSCR[4] ; CLK ; +; N/A ; None ; -4.837 ns ; CS ; uart_16750:inst|iMCR[1] ; CLK ; +; N/A ; None ; -4.837 ns ; CS ; uart_16750:inst|iMCR[2] ; CLK ; +; N/A ; None ; -4.837 ns ; CS ; uart_16750:inst|iMCR[3] ; CLK ; +; N/A ; None ; -4.850 ns ; CS ; uart_16750:inst|iLSR_FE ; CLK ; +; N/A ; None ; -4.853 ns ; CS ; uart_16750:inst|iLSR_OE ; CLK ; +; N/A ; None ; -4.873 ns ; WR ; uart_16750:inst|iLCR[7] ; CLK ; +; N/A ; None ; -4.873 ns ; WR ; uart_16750:inst|iLCR[5] ; CLK ; +; N/A ; None ; -4.891 ns ; CS ; uart_16750:inst|iCharTimeout ; CLK ; +; N/A ; None ; -4.896 ns ; WR ; uart_16750:inst|iDLL[0] ; CLK ; +; N/A ; None ; -4.896 ns ; WR ; uart_16750:inst|iDLL[2] ; CLK ; +; N/A ; None ; -4.896 ns ; WR ; uart_16750:inst|iDLL[1] ; CLK ; +; N/A ; None ; -4.896 ns ; WR ; uart_16750:inst|iDLL[4] ; CLK ; +; N/A ; None ; -4.896 ns ; WR ; uart_16750:inst|iDLL[3] ; CLK ; +; N/A ; None ; -4.899 ns ; WR ; uart_16750:inst|iDLL[7] ; CLK ; +; N/A ; None ; -4.899 ns ; WR ; uart_16750:inst|iDLL[6] ; CLK ; +; N/A ; None ; -4.918 ns ; WR ; uart_16750:inst|iMCR[4] ; CLK ; +; N/A ; None ; -4.918 ns ; WR ; uart_16750:inst|iMCR[5] ; CLK ; +; N/A ; None ; -4.918 ns ; WR ; uart_16750:inst|iMCR[0] ; CLK ; +; N/A ; None ; -4.921 ns ; WR ; uart_16750:inst|iSCR[0] ; CLK ; +; N/A ; None ; -4.953 ns ; WR ; uart_16750:inst|iFCR_TXFIFOReset ; CLK ; +; N/A ; None ; -4.954 ns ; CS ; uart_16750:inst|iFCR_FIFO64E ; CLK ; +; N/A ; None ; -4.956 ns ; WR ; uart_16750:inst|iFCR_RXFIFOReset ; CLK ; +; N/A ; None ; -5.034 ns ; CS ; uart_16750:inst|iMCR[4] ; CLK ; +; N/A ; None ; -5.034 ns ; CS ; uart_16750:inst|iMCR[5] ; CLK ; +; N/A ; None ; -5.034 ns ; CS ; uart_16750:inst|iMCR[0] ; CLK ; +; N/A ; None ; -5.037 ns ; CS ; uart_16750:inst|iSCR[0] ; CLK ; +; N/A ; None ; -5.053 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|usedw_is_2_dff ; CLK ; +; N/A ; None ; -5.055 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|usedw_is_0_dff ; CLK ; +; N/A ; None ; -5.056 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|usedw_is_1_dff ; CLK ; +; N/A ; None ; -5.063 ns ; CS ; uart_16750:inst|iDLM[5] ; CLK ; +; N/A ; None ; -5.063 ns ; CS ; uart_16750:inst|iDLM[6] ; CLK ; +; N/A ; None ; -5.063 ns ; CS ; uart_16750:inst|iDLM[4] ; CLK ; +; N/A ; None ; -5.063 ns ; CS ; uart_16750:inst|iDLM[7] ; CLK ; +; N/A ; None ; -5.064 ns ; CS ; uart_16750:inst|iIER[0] ; CLK ; +; N/A ; None ; -5.064 ns ; CS ; uart_16750:inst|iIER[1] ; CLK ; +; N/A ; None ; -5.064 ns ; CS ; uart_16750:inst|iIER[2] ; CLK ; +; N/A ; None ; -5.064 ns ; CS ; uart_16750:inst|iLSR_BI ; CLK ; +; N/A ; None ; -5.065 ns ; CS ; uart_16750:inst|iLSR_PE ; CLK ; +; N/A ; None ; -5.085 ns ; CS ; uart_16750:inst|iFCR_FIFOEnable ; CLK ; +; N/A ; None ; -5.085 ns ; CS ; uart_16750:inst|iFCR_RXTrigger[0] ; CLK ; +; N/A ; None ; -5.085 ns ; CS ; uart_16750:inst|iFCR_RXTrigger[1] ; CLK ; +; N/A ; None ; -5.090 ns ; CS ; uart_16750:inst|iIER[3] ; CLK ; +; N/A ; None ; -5.128 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[5] ; CLK ; +; N/A ; None ; -5.129 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[0] ; CLK ; +; N/A ; None ; -5.129 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[1] ; CLK ; +; N/A ; None ; -5.130 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[3] ; CLK ; +; N/A ; None ; -5.130 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[4] ; CLK ; +; N/A ; None ; -5.135 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|usedw_is_1_dff ; CLK ; +; N/A ; None ; -5.164 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|altsyncram_t681:FIFOram|ram_block1a0~porta_we_reg ; CLK ; +; N/A ; None ; -5.209 ns ; WR ; uart_16750:inst|iSCR[3] ; CLK ; +; N/A ; None ; -5.209 ns ; WR ; uart_16750:inst|iSCR[2] ; CLK ; +; N/A ; None ; -5.209 ns ; WR ; uart_16750:inst|iSCR[1] ; CLK ; +; N/A ; None ; -5.243 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg5 ; CLK ; +; N/A ; None ; -5.252 ns ; WR ; uart_16750:inst|iFCR_FIFO64E ; CLK ; +; N/A ; None ; -5.266 ns ; CS ; uart_16750:inst|iDLM[1] ; CLK ; +; N/A ; None ; -5.266 ns ; CS ; uart_16750:inst|iDLM[0] ; CLK ; +; N/A ; None ; -5.266 ns ; CS ; uart_16750:inst|iDLM[2] ; CLK ; +; N/A ; None ; -5.270 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg3 ; CLK ; +; N/A ; None ; -5.283 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg2 ; CLK ; +; N/A ; None ; -5.289 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[2] ; CLK ; +; N/A ; None ; -5.323 ns ; CS ; uart_16750:inst|iDLM[3] ; CLK ; +; N/A ; None ; -5.325 ns ; CS ; uart_16750:inst|iSCR[3] ; CLK ; +; N/A ; None ; -5.325 ns ; CS ; uart_16750:inst|iSCR[2] ; CLK ; +; N/A ; None ; -5.325 ns ; CS ; uart_16750:inst|iSCR[1] ; CLK ; +; N/A ; None ; -5.331 ns ; CS ; uart_16750:inst|iLCR[3] ; CLK ; +; N/A ; None ; -5.331 ns ; CS ; uart_16750:inst|iLCR[0] ; CLK ; +; N/A ; None ; -5.341 ns ; CS ; uart_16750:inst|iLCR[4] ; CLK ; +; N/A ; None ; -5.341 ns ; CS ; uart_16750:inst|iLCR[1] ; CLK ; +; N/A ; None ; -5.341 ns ; CS ; uart_16750:inst|iLCR[6] ; CLK ; +; N/A ; None ; -5.341 ns ; CS ; uart_16750:inst|iLCR[2] ; CLK ; +; N/A ; None ; -5.344 ns ; RD ; uart_16750:inst|iCharTimeout ; CLK ; +; N/A ; None ; -5.349 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_p57:usedw_counter|safe_q[0] ; CLK ; +; N/A ; None ; -5.350 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_p57:usedw_counter|safe_q[1] ; CLK ; +; N/A ; None ; -5.351 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|usedw_is_2_dff ; CLK ; +; N/A ; None ; -5.351 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_p57:usedw_counter|safe_q[3] ; CLK ; +; N/A ; None ; -5.351 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_p57:usedw_counter|safe_q[2] ; CLK ; +; N/A ; None ; -5.352 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_p57:usedw_counter|safe_q[4] ; CLK ; +; N/A ; None ; -5.353 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|usedw_is_0_dff ; CLK ; +; N/A ; None ; -5.354 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|usedw_is_1_dff ; CLK ; +; N/A ; None ; -5.361 ns ; WR ; uart_16750:inst|iDLM[5] ; CLK ; +; N/A ; None ; -5.361 ns ; WR ; uart_16750:inst|iDLM[6] ; CLK ; +; N/A ; None ; -5.361 ns ; WR ; uart_16750:inst|iDLM[4] ; CLK ; +; N/A ; None ; -5.361 ns ; WR ; uart_16750:inst|iDLM[7] ; CLK ; +; N/A ; None ; -5.362 ns ; WR ; uart_16750:inst|iIER[0] ; CLK ; +; N/A ; None ; -5.362 ns ; WR ; uart_16750:inst|iIER[1] ; CLK ; +; N/A ; None ; -5.362 ns ; WR ; uart_16750:inst|iIER[2] ; CLK ; +; N/A ; None ; -5.364 ns ; CS ; uart_16750:inst|iMSR_dCTS ; CLK ; +; N/A ; None ; -5.383 ns ; WR ; uart_16750:inst|iFCR_FIFOEnable ; CLK ; +; N/A ; None ; -5.383 ns ; WR ; uart_16750:inst|iFCR_RXTrigger[0] ; CLK ; +; N/A ; None ; -5.383 ns ; WR ; uart_16750:inst|iFCR_RXTrigger[1] ; CLK ; +; N/A ; None ; -5.384 ns ; CS ; uart_16750:inst|iTimeoutCount[5] ; CLK ; +; N/A ; None ; -5.384 ns ; CS ; uart_16750:inst|iTimeoutCount[4] ; CLK ; +; N/A ; None ; -5.384 ns ; CS ; uart_16750:inst|iTimeoutCount[3] ; CLK ; +; N/A ; None ; -5.384 ns ; CS ; uart_16750:inst|iTimeoutCount[2] ; CLK ; +; N/A ; None ; -5.384 ns ; CS ; uart_16750:inst|iTimeoutCount[1] ; CLK ; +; N/A ; None ; -5.384 ns ; CS ; uart_16750:inst|iTimeoutCount[0] ; CLK ; +; N/A ; None ; -5.388 ns ; WR ; uart_16750:inst|iIER[3] ; CLK ; +; N/A ; None ; -5.397 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[0] ; CLK ; +; N/A ; None ; -5.397 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[1] ; CLK ; +; N/A ; None ; -5.397 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[2] ; CLK ; +; N/A ; None ; -5.397 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[3] ; CLK ; +; N/A ; None ; -5.397 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_c5b:rd_ptr_msb|safe_q[4] ; CLK ; +; N/A ; None ; -5.422 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|empty_dff ; CLK ; +; N/A ; None ; -5.427 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|rd_ptr_lsb ; CLK ; +; N/A ; None ; -5.433 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_d5b:wr_ptr|safe_q[0] ; CLK ; +; N/A ; None ; -5.433 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_d5b:wr_ptr|safe_q[1] ; CLK ; +; N/A ; None ; -5.433 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_d5b:wr_ptr|safe_q[2] ; CLK ; +; N/A ; None ; -5.433 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_d5b:wr_ptr|safe_q[3] ; CLK ; +; N/A ; None ; -5.433 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_d5b:wr_ptr|safe_q[4] ; CLK ; +; N/A ; None ; -5.433 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_d5b:wr_ptr|safe_q[5] ; CLK ; +; N/A ; None ; -5.452 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|usedw_is_2_dff ; CLK ; +; N/A ; None ; -5.462 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|altsyncram_t681:FIFOram|ram_block1a0~porta_we_reg ; CLK ; +; N/A ; None ; -5.529 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_p57:usedw_counter|safe_q[4] ; CLK ; +; N/A ; None ; -5.529 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_p57:usedw_counter|safe_q[0] ; CLK ; +; N/A ; None ; -5.529 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_p57:usedw_counter|safe_q[1] ; CLK ; +; N/A ; None ; -5.529 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_p57:usedw_counter|safe_q[2] ; CLK ; +; N/A ; None ; -5.529 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_p57:usedw_counter|safe_q[5] ; CLK ; +; N/A ; None ; -5.529 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|cntr_p57:usedw_counter|safe_q[3] ; CLK ; +; N/A ; None ; -5.532 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg1 ; CLK ; +; N/A ; None ; -5.540 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg0 ; CLK ; +; N/A ; None ; -5.540 ns ; CS ; uart_16750:inst|iMSR_TERI ; CLK ; +; N/A ; None ; -5.542 ns ; CS ; uart_16750:inst|iMSR_dDCD ; CLK ; +; N/A ; None ; -5.564 ns ; WR ; uart_16750:inst|iDLM[1] ; CLK ; +; N/A ; None ; -5.564 ns ; WR ; uart_16750:inst|iDLM[0] ; CLK ; +; N/A ; None ; -5.564 ns ; WR ; uart_16750:inst|iDLM[2] ; CLK ; +; N/A ; None ; -5.581 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[5] ; CLK ; +; N/A ; None ; -5.582 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[0] ; CLK ; +; N/A ; None ; -5.582 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[1] ; CLK ; +; N/A ; None ; -5.583 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[3] ; CLK ; +; N/A ; None ; -5.583 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|low_addressa[4] ; CLK ; +; N/A ; None ; -5.588 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|usedw_is_1_dff ; CLK ; +; N/A ; None ; -5.591 ns ; CS ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|full_dff ; CLK ; +; N/A ; None ; -5.592 ns ; CS ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|full_dff ; CLK ; +; N/A ; None ; -5.621 ns ; WR ; uart_16750:inst|iDLM[3] ; CLK ; +; N/A ; None ; -5.629 ns ; WR ; uart_16750:inst|iLCR[3] ; CLK ; +; N/A ; None ; -5.629 ns ; WR ; uart_16750:inst|iLCR[0] ; CLK ; +; N/A ; None ; -5.639 ns ; WR ; uart_16750:inst|iLCR[4] ; CLK ; +; N/A ; None ; -5.639 ns ; WR ; uart_16750:inst|iLCR[1] ; CLK ; +; N/A ; None ; -5.639 ns ; WR ; uart_16750:inst|iLCR[6] ; CLK ; +; N/A ; None ; -5.639 ns ; WR ; uart_16750:inst|iLCR[2] ; CLK ; +; N/A ; None ; -5.647 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_p57:usedw_counter|safe_q[0] ; CLK ; +; N/A ; None ; -5.648 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_p57:usedw_counter|safe_q[1] ; CLK ; +; N/A ; None ; -5.649 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_p57:usedw_counter|safe_q[3] ; CLK ; +; N/A ; None ; -5.649 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_p57:usedw_counter|safe_q[2] ; CLK ; +; N/A ; None ; -5.650 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_p57:usedw_counter|safe_q[4] ; CLK ; +; N/A ; None ; -5.674 ns ; CS ; uart_16750:inst|iMSR_dDSR ; CLK ; +; N/A ; None ; -5.696 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg5 ; CLK ; +; N/A ; None ; -5.720 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|empty_dff ; CLK ; +; N/A ; None ; -5.723 ns ; RD ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg3 ; CLK ; +; N/A ; None ; -5.731 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_d5b:wr_ptr|safe_q[0] ; CLK ; +; N/A ; None ; -5.731 ns ; WR ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|cntr_d5b:wr_ptr|safe_q[1] ; CLK ; +; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ++-----------------------------------------+-----------------------------------------------------+-----------+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------+ + + ++--------------------------+ +; Timing Analyzer Messages ; ++--------------------------+ +Info: ******************************************************************* +Info: Running Quartus II Classic Timing Analyzer + Info: Version 8.0 Build 215 05/29/2008 SJ Full Version + Info: Processing started: Tue Feb 17 23:02:39 2009 +Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off UART16750 -c UART16750 --timing_analysis_only +Info: Slack time is 22.036 ns for clock "CLK" between source memory "uart_16750:inst|iTSR[3]" and destination register "uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4]" + Info: Fmax is 125.52 MHz (period= 7.967 ns) + Info: + Largest memory to register requirement is 29.788 ns + Info: + Setup relationship between source and destination is 30.003 ns + Info: + Latch edge is 30.003 ns + Info: Clock period of Destination clock "CLK" is 30.003 ns with offset of 0.000 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: - Launch edge is 0.000 ns + Info: Clock period of Source clock "CLK" is 30.003 ns with offset of 0.000 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: + Largest clock skew is -0.042 ns + Info: + Shortest clock path from clock "CLK" to destination register is 2.345 ns + Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H15; Fanout = 1; CLK Node = 'CLK' + Info: 2: + IC(0.119 ns) + CELL(0.000 ns) = 1.098 ns; Loc. = CLKCTRL_G6; Fanout = 357; COMB Node = 'CLK~clkctrl' + Info: 3: + IC(0.710 ns) + CELL(0.537 ns) = 2.345 ns; Loc. = LCFF_X18_Y4_N15; Fanout = 2; REG Node = 'uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4]' + Info: Total cell delay = 1.516 ns ( 64.65 % ) + Info: Total interconnect delay = 0.829 ns ( 35.35 % ) + Info: - Longest clock path from clock "CLK" to source memory is 2.387 ns + Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H15; Fanout = 1; CLK Node = 'CLK' + Info: 2: + IC(0.119 ns) + CELL(0.000 ns) = 1.098 ns; Loc. = CLKCTRL_G6; Fanout = 357; COMB Node = 'CLK~clkctrl' + Info: 3: + IC(0.653 ns) + CELL(0.636 ns) = 2.387 ns; Loc. = M4K_X23_Y5; Fanout = 2; MEM Node = 'uart_16750:inst|iTSR[3]' + Info: Total cell delay = 1.615 ns ( 67.66 % ) + Info: Total interconnect delay = 0.772 ns ( 32.34 % ) + Info: - Micro clock to output delay of source is 0.209 ns + Info: - Micro setup delay of destination is -0.036 ns + Info: - Longest memory to register delay is 7.752 ns + Info: 1: + IC(0.000 ns) + CELL(0.088 ns) = 0.088 ns; Loc. = M4K_X23_Y5; Fanout = 2; MEM Node = 'uart_16750:inst|iTSR[3]' + Info: 2: + IC(0.953 ns) + CELL(0.438 ns) = 1.479 ns; Loc. = LCCOMB_X21_Y4_N26; Fanout = 1; COMB Node = 'uart_16750:inst|uart_transmitter:UART_TX|Selector4~277' + Info: 3: + IC(0.249 ns) + CELL(0.416 ns) = 2.144 ns; Loc. = LCCOMB_X21_Y4_N14; Fanout = 1; COMB Node = 'uart_16750:inst|uart_transmitter:UART_TX|Selector4~278' + Info: 4: + IC(0.708 ns) + CELL(0.420 ns) = 3.272 ns; Loc. = LCCOMB_X21_Y4_N20; Fanout = 2; COMB Node = 'uart_16750:inst|uart_transmitter:UART_TX|Selector4~281' + Info: 5: + IC(0.977 ns) + CELL(0.438 ns) = 4.687 ns; Loc. = LCCOMB_X18_Y3_N6; Fanout = 1; COMB Node = 'uart_16750:inst|iSIN~127' + Info: 6: + IC(0.282 ns) + CELL(0.438 ns) = 5.407 ns; Loc. = LCCOMB_X18_Y3_N18; Fanout = 4; COMB Node = 'uart_16750:inst|iSIN~128' + Info: 7: + IC(0.727 ns) + CELL(0.275 ns) = 6.409 ns; Loc. = LCCOMB_X18_Y4_N2; Fanout = 2; COMB Node = 'uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|MV_PROC~0' + Info: 8: + IC(0.243 ns) + CELL(0.393 ns) = 7.045 ns; Loc. = LCCOMB_X18_Y4_N6; Fanout = 2; COMB Node = 'uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[0]~205' + Info: 9: + IC(0.000 ns) + CELL(0.071 ns) = 7.116 ns; Loc. = LCCOMB_X18_Y4_N8; Fanout = 2; COMB Node = 'uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[1]~207' + Info: 10: + IC(0.000 ns) + CELL(0.071 ns) = 7.187 ns; Loc. = LCCOMB_X18_Y4_N10; Fanout = 2; COMB Node = 'uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[2]~209' + Info: 11: + IC(0.000 ns) + CELL(0.071 ns) = 7.258 ns; Loc. = LCCOMB_X18_Y4_N12; Fanout = 1; COMB Node = 'uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[3]~211' + Info: 12: + IC(0.000 ns) + CELL(0.410 ns) = 7.668 ns; Loc. = LCCOMB_X18_Y4_N14; Fanout = 1; COMB Node = 'uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4]~212' + Info: 13: + IC(0.000 ns) + CELL(0.084 ns) = 7.752 ns; Loc. = LCFF_X18_Y4_N15; Fanout = 2; REG Node = 'uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4]' + Info: Total cell delay = 3.613 ns ( 46.61 % ) + Info: Total interconnect delay = 4.139 ns ( 53.39 % ) +Info: Minimum slack time is 391 ps for clock "CLK" between source register "uart_16750:inst|iLSR_FIFOERR" and destination register "uart_16750:inst|iLSR_FIFOERR" + Info: + Shortest register to register delay is 0.407 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X26_Y3_N1; Fanout = 2; REG Node = 'uart_16750:inst|iLSR_FIFOERR' + Info: 2: + IC(0.000 ns) + CELL(0.323 ns) = 0.323 ns; Loc. = LCCOMB_X26_Y3_N0; Fanout = 1; COMB Node = 'uart_16750:inst|iLSR_FIFOERR~77' + Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.407 ns; Loc. = LCFF_X26_Y3_N1; Fanout = 2; REG Node = 'uart_16750:inst|iLSR_FIFOERR' + Info: Total cell delay = 0.407 ns ( 100.00 % ) + Info: - Smallest register to register requirement is 0.016 ns + Info: + Hold relationship between source and destination is 0.000 ns + Info: + Latch edge is 0.000 ns + Info: Clock period of Destination clock "CLK" is 30.003 ns with offset of 0.000 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: Multicycle Hold factor for Destination register is 1 + Info: - Launch edge is 0.000 ns + Info: Clock period of Source clock "CLK" is 30.003 ns with offset of 0.000 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: Multicycle Hold factor for Source register is 1 + Info: + Smallest clock skew is 0.000 ns + Info: + Longest clock path from clock "CLK" to destination register is 2.360 ns + Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H15; Fanout = 1; CLK Node = 'CLK' + Info: 2: + IC(0.119 ns) + CELL(0.000 ns) = 1.098 ns; Loc. = CLKCTRL_G6; Fanout = 357; COMB Node = 'CLK~clkctrl' + Info: 3: + IC(0.725 ns) + CELL(0.537 ns) = 2.360 ns; Loc. = LCFF_X26_Y3_N1; Fanout = 2; REG Node = 'uart_16750:inst|iLSR_FIFOERR' + Info: Total cell delay = 1.516 ns ( 64.24 % ) + Info: Total interconnect delay = 0.844 ns ( 35.76 % ) + Info: - Shortest clock path from clock "CLK" to source register is 2.360 ns + Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H15; Fanout = 1; CLK Node = 'CLK' + Info: 2: + IC(0.119 ns) + CELL(0.000 ns) = 1.098 ns; Loc. = CLKCTRL_G6; Fanout = 357; COMB Node = 'CLK~clkctrl' + Info: 3: + IC(0.725 ns) + CELL(0.537 ns) = 2.360 ns; Loc. = LCFF_X26_Y3_N1; Fanout = 2; REG Node = 'uart_16750:inst|iLSR_FIFOERR' + Info: Total cell delay = 1.516 ns ( 64.24 % ) + Info: Total interconnect delay = 0.844 ns ( 35.76 % ) + Info: - Micro clock to output delay of source is 0.250 ns + Info: + Micro hold delay of destination is 0.266 ns +Info: Slack time is 2.58 ns for clock "CLK" between source pin "WR" and destination register "uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|empty_dff" + Info: + tsu requirement for source pin and destination register is 10.000 ns + Info: - tsu from clock to input pin is 7.420 ns + Info: + Longest pin to register delay is 9.802 ns + Info: 1: + IC(0.000 ns) + CELL(0.822 ns) = 0.822 ns; Loc. = PIN_E14; Fanout = 3; PIN Node = 'WR' + Info: 2: + IC(4.183 ns) + CELL(0.436 ns) = 5.441 ns; Loc. = LCCOMB_X25_Y5_N14; Fanout = 6; COMB Node = 'uart_16750:inst|iLCRWrite~27' + Info: 3: + IC(0.275 ns) + CELL(0.416 ns) = 6.132 ns; Loc. = LCCOMB_X25_Y5_N30; Fanout = 4; COMB Node = 'uart_16750:inst|iTHRWrite~26' + Info: 4: + IC(0.734 ns) + CELL(0.150 ns) = 7.016 ns; Loc. = LCCOMB_X25_Y5_N18; Fanout = 16; COMB Node = 'uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|valid_wreq~186' + Info: 5: + IC(0.959 ns) + CELL(0.275 ns) = 8.250 ns; Loc. = LCCOMB_X21_Y5_N0; Fanout = 1; COMB Node = 'uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|usedw_will_be_1~161' + Info: 6: + IC(0.256 ns) + CELL(0.416 ns) = 8.922 ns; Loc. = LCCOMB_X21_Y5_N10; Fanout = 2; COMB Node = 'uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|usedw_will_be_1~162' + Info: 7: + IC(0.646 ns) + CELL(0.150 ns) = 9.718 ns; Loc. = LCCOMB_X21_Y5_N4; Fanout = 1; COMB Node = 'uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|empty_dff~16' + Info: 8: + IC(0.000 ns) + CELL(0.084 ns) = 9.802 ns; Loc. = LCFF_X21_Y5_N5; Fanout = 17; REG Node = 'uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|empty_dff' + Info: Total cell delay = 2.749 ns ( 28.05 % ) + Info: Total interconnect delay = 7.053 ns ( 71.95 % ) + Info: + Micro setup delay of destination is -0.036 ns + Info: - Shortest clock path from clock "CLK" to destination register is 2.346 ns + Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H15; Fanout = 1; CLK Node = 'CLK' + Info: 2: + IC(0.119 ns) + CELL(0.000 ns) = 1.098 ns; Loc. = CLKCTRL_G6; Fanout = 357; COMB Node = 'CLK~clkctrl' + Info: 3: + IC(0.711 ns) + CELL(0.537 ns) = 2.346 ns; Loc. = LCFF_X21_Y5_N5; Fanout = 17; REG Node = 'uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|empty_dff' + Info: Total cell delay = 1.516 ns ( 64.62 % ) + Info: Total interconnect delay = 0.830 ns ( 35.38 % ) +Info: Slack time is 2.856 ns for clock "CLK" between source memory "uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg5" and destination pin "DOUT[3]" + Info: + tco requirement for source memory and destination pin is 15.000 ns + Info: - tco from clock to output pin is 12.144 ns + Info: + Longest clock path from clock "CLK" to source memory is 2.447 ns + Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H15; Fanout = 1; CLK Node = 'CLK' + Info: 2: + IC(0.119 ns) + CELL(0.000 ns) = 1.098 ns; Loc. = CLKCTRL_G6; Fanout = 357; COMB Node = 'CLK~clkctrl' + Info: 3: + IC(0.660 ns) + CELL(0.689 ns) = 2.447 ns; Loc. = M4K_X23_Y3; Fanout = 11; MEM Node = 'uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg5' + Info: Total cell delay = 1.668 ns ( 68.17 % ) + Info: Total interconnect delay = 0.779 ns ( 31.83 % ) + Info: + Micro clock to output delay of source is 0.209 ns + Info: + Longest memory to pin delay is 9.488 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X23_Y3; Fanout = 11; MEM Node = 'uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg5' + Info: 2: + IC(0.000 ns) + CELL(2.991 ns) = 2.991 ns; Loc. = M4K_X23_Y3; Fanout = 1; MEM Node = 'uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|q_b[3]' + Info: 3: + IC(0.421 ns) + CELL(0.150 ns) = 3.562 ns; Loc. = LCCOMB_X24_Y3_N2; Fanout = 1; COMB Node = 'uart_16750:inst|Mux4~35' + Info: 4: + IC(0.440 ns) + CELL(0.150 ns) = 4.152 ns; Loc. = LCCOMB_X25_Y3_N16; Fanout = 1; COMB Node = 'uart_16750:inst|Mux4~36' + Info: 5: + IC(0.252 ns) + CELL(0.275 ns) = 4.679 ns; Loc. = LCCOMB_X25_Y3_N28; Fanout = 1; COMB Node = 'uart_16750:inst|Mux4~37' + Info: 6: + IC(0.246 ns) + CELL(0.150 ns) = 5.075 ns; Loc. = LCCOMB_X25_Y3_N22; Fanout = 1; COMB Node = 'uart_16750:inst|Mux4~38' + Info: 7: + IC(1.345 ns) + CELL(3.068 ns) = 9.488 ns; Loc. = PIN_T11; Fanout = 0; PIN Node = 'DOUT[3]' + Info: Total cell delay = 6.784 ns ( 71.50 % ) + Info: Total interconnect delay = 2.704 ns ( 28.50 % ) +Info: Longest tpd from source pin "A[1]" to destination pin "DOUT[3]" is 14.563 ns + Info: 1: + IC(0.000 ns) + CELL(0.832 ns) = 0.832 ns; Loc. = PIN_F16; Fanout = 15; PIN Node = 'A[1]' + Info: 2: + IC(5.385 ns) + CELL(0.398 ns) = 6.615 ns; Loc. = LCCOMB_X24_Y5_N0; Fanout = 14; COMB Node = 'uart_16750:inst|Mux0~160' + Info: 3: + IC(1.607 ns) + CELL(0.415 ns) = 8.637 ns; Loc. = LCCOMB_X24_Y3_N2; Fanout = 1; COMB Node = 'uart_16750:inst|Mux4~35' + Info: 4: + IC(0.440 ns) + CELL(0.150 ns) = 9.227 ns; Loc. = LCCOMB_X25_Y3_N16; Fanout = 1; COMB Node = 'uart_16750:inst|Mux4~36' + Info: 5: + IC(0.252 ns) + CELL(0.275 ns) = 9.754 ns; Loc. = LCCOMB_X25_Y3_N28; Fanout = 1; COMB Node = 'uart_16750:inst|Mux4~37' + Info: 6: + IC(0.246 ns) + CELL(0.150 ns) = 10.150 ns; Loc. = LCCOMB_X25_Y3_N22; Fanout = 1; COMB Node = 'uart_16750:inst|Mux4~38' + Info: 7: + IC(1.345 ns) + CELL(3.068 ns) = 14.563 ns; Loc. = PIN_T11; Fanout = 0; PIN Node = 'DOUT[3]' + Info: Total cell delay = 5.288 ns ( 36.31 % ) + Info: Total interconnect delay = 9.275 ns ( 63.69 % ) +Info: th for register "uart_16750:inst|slib_edge_detect:UART_ED_WRITE|iDd" (data pin = "WR", clock pin = "CLK") is -2.602 ns + Info: + Longest clock path from clock "CLK" to destination register is 2.352 ns + Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H15; Fanout = 1; CLK Node = 'CLK' + Info: 2: + IC(0.119 ns) + CELL(0.000 ns) = 1.098 ns; Loc. = CLKCTRL_G6; Fanout = 357; COMB Node = 'CLK~clkctrl' + Info: 3: + IC(0.717 ns) + CELL(0.537 ns) = 2.352 ns; Loc. = LCFF_X25_Y5_N5; Fanout = 2; REG Node = 'uart_16750:inst|slib_edge_detect:UART_ED_WRITE|iDd' + Info: Total cell delay = 1.516 ns ( 64.46 % ) + Info: Total interconnect delay = 0.836 ns ( 35.54 % ) + Info: + Micro hold delay of destination is 0.266 ns + Info: - Shortest pin to register delay is 5.220 ns + Info: 1: + IC(0.000 ns) + CELL(0.822 ns) = 0.822 ns; Loc. = PIN_E14; Fanout = 3; PIN Node = 'WR' + Info: 2: + IC(4.164 ns) + CELL(0.150 ns) = 5.136 ns; Loc. = LCCOMB_X25_Y5_N4; Fanout = 1; COMB Node = 'uart_16750:inst|iCSWR' + Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 5.220 ns; Loc. = LCFF_X25_Y5_N5; Fanout = 2; REG Node = 'uart_16750:inst|slib_edge_detect:UART_ED_WRITE|iDd' + Info: Total cell delay = 1.056 ns ( 20.23 % ) + Info: Total interconnect delay = 4.164 ns ( 79.77 % ) +Info: All timing requirements were met for slow timing model timing analysis. See Report window for more details. +Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 127 megabytes + Info: Processing ended: Tue Feb 17 23:02:39 2009 + Info: Elapsed time: 00:00:00 + Info: Total CPU time (on all processors): 00:00:01 + +

trunk/syn/Altera/CycloneII/UART16750.tan.rpt Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/syn/Altera/CycloneII/UART16750.qsf =================================================================== --- trunk/syn/Altera/CycloneII/UART16750.qsf (nonexistent) +++ trunk/syn/Altera/CycloneII/UART16750.qsf (revision 16) @@ -0,0 +1,110 @@ +# Copyright (C) 1991-2008 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + + +# The default values for assignments are stored in the file +# UART16750_assignment_defaults.qdf +# If this file doesn't exist, and for assignments not listed, see file +# assignment_defaults.qdf + +# Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. + + +set_global_assignment -name FAMILY "Cyclone II" +set_global_assignment -name DEVICE EP2C5F256C6 +set_global_assignment -name TOP_LEVEL_ENTITY UART16750 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:40:30 JANUARY 16, 2009" +set_global_assignment -name LAST_QUARTUS_VERSION 8.0 +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 256 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE FASTEST +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_COLOR 14622752 -section_id Top +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" +set_global_assignment -name FMAX_REQUIREMENT "33.33 MHz" +set_global_assignment -name FMAX_REQUIREMENT "33.33 MHz" -section_id CLK +set_instance_assignment -name CLOCK_SETTINGS CLK -to CLK +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP" +set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED" +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_location_assignment PIN_G13 -to A[0] +set_location_assignment PIN_F15 -to A[2] +set_location_assignment PIN_F16 -to A[1] +set_location_assignment PIN_G12 -to CS +set_location_assignment PIN_M15 -to CTSN +set_location_assignment PIN_M16 -to DCDN +set_location_assignment PIN_E16 -to DDIS +set_location_assignment PIN_A14 -to DIN[7] +set_location_assignment PIN_A13 -to DIN[6] +set_location_assignment PIN_A12 -to DIN[5] +set_location_assignment PIN_A11 -to DIN[4] +set_location_assignment PIN_B14 -to DIN[3] +set_location_assignment PIN_B13 -to DIN[2] +set_location_assignment PIN_B12 -to DIN[1] +set_location_assignment PIN_B11 -to DIN[0] +set_location_assignment PIN_R11 -to DOUT[7] +set_location_assignment PIN_R12 -to DOUT[6] +set_location_assignment PIN_R13 -to DOUT[5] +set_location_assignment PIN_R14 -to DOUT[4] +set_location_assignment PIN_T11 -to DOUT[3] +set_location_assignment PIN_T12 -to DOUT[2] +set_location_assignment PIN_T13 -to DOUT[1] +set_location_assignment PIN_T14 -to DOUT[0] +set_location_assignment PIN_L14 -to DSRN +set_location_assignment PIN_L15 -to DTRN +set_location_assignment PIN_D16 -to INT +set_location_assignment PIN_N16 -to OUT1N +set_location_assignment PIN_N15 -to OUT2N +set_location_assignment PIN_D15 -to RD +set_location_assignment PIN_L16 -to RIN +set_location_assignment PIN_K15 -to RTSN +set_location_assignment PIN_G15 -to SIN +set_location_assignment PIN_K16 -to SOUT +set_location_assignment PIN_E14 -to WR +set_location_assignment PIN_H15 -to CLK +set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 3 +set_instance_assignment -name OUTPUT_PIN_LOAD 10 -to DDIS +set_instance_assignment -name OUTPUT_PIN_LOAD 10 -to DOUT +set_instance_assignment -name OUTPUT_PIN_LOAD 10 -to DTRN +set_instance_assignment -name OUTPUT_PIN_LOAD 10 -to INT +set_instance_assignment -name OUTPUT_PIN_LOAD 10 -to OUT1N +set_instance_assignment -name OUTPUT_PIN_LOAD 10 -to OUT2N +set_instance_assignment -name OUTPUT_PIN_LOAD 10 -to RTSN +set_instance_assignment -name OUTPUT_PIN_LOAD 10 -to SOUT +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE BALANCED +set_global_assignment -name TSU_REQUIREMENT "10 ns" +set_global_assignment -name TCO_REQUIREMENT "15 ns" +set_global_assignment -name USE_CONFIGURATION_DEVICE ON +set_global_assignment -name ENABLE_DA_RULE "C101, C102, C103, C104, C105, C106, R101, R102, R103, R104, R105, T101, T102, A101, A102, A103, A104, A105, A106, A107, A108, A109, A110, S101, S102, S103, S104, D101, D102, D103, H101, H102, M101, M102, M103, M104, M105" +set_global_assignment -name ENABLE_DRC_SETTINGS ON +set_location_assignment PIN_G16 -to RSTN +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/uart_transmitter.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/slib_clock_div.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/slib_counter.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/slib_edge_detect.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/slib_fifo_cyclone2.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/slib_input_filter.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/slib_input_sync.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/slib_mv_filter.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/uart_16750.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/uart_baudgen.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/uart_interrupt.vhd +set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/uart_receiver.vhd +set_global_assignment -name BDF_FILE UART16750.bdf \ No newline at end of file

trunk/syn/Altera/CycloneII/UART16750.qsf Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/syn/Altera/CycloneII/UART16750.fit.smsg =================================================================== --- trunk/syn/Altera/CycloneII/UART16750.fit.smsg (nonexistent) +++ trunk/syn/Altera/CycloneII/UART16750.fit.smsg (revision 16) @@ -0,0 +1,6 @@ +Extra Info: Performing register packing on registers with non-logic cell location assignments +Extra Info: Completed register packing on registers with non-logic cell location assignments +Extra Info: Started Fast Input/Output/OE register processing +Extra Info: Finished Fast Input/Output/OE register processing +Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density +Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks

trunk/syn/Altera/CycloneII/UART16750.fit.smsg Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/syn/Altera/CycloneII/UART16750.srf =================================================================== --- trunk/syn/Altera/CycloneII/UART16750.srf (nonexistent) +++ trunk/syn/Altera/CycloneII/UART16750.srf (revision 16) @@ -0,0 +1,11 @@ +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "iFCR uart_16750.vhd(226) " "Warning (10036): Verilog HDL or VHDL warning at uart_16750.vhd(226): object \"iFCR\" assigned a value but never read" { } { { "../../../rtl/vhdl/uart_16750.vhd" "" { Text "R:/uart16750/rtl/vhdl/uart_16750.vhd" 226 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 1 0 "" 0 0} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "iIER_ERBI uart_16750.vhd(234) " "Warning (10036): Verilog HDL or VHDL warning at uart_16750.vhd(234): object \"iIER_ERBI\" assigned a value but never read" { } { { "../../../rtl/vhdl/uart_16750.vhd" "" { Text "R:/uart16750/rtl/vhdl/uart_16750.vhd" 234 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 1 0 "" 0 0} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "iIER_ETBEI uart_16750.vhd(235) " "Warning (10036): Verilog HDL or VHDL warning at uart_16750.vhd(235): object \"iIER_ETBEI\" assigned a value but never read" { } { { "../../../rtl/vhdl/uart_16750.vhd" "" { Text "R:/uart16750/rtl/vhdl/uart_16750.vhd" 235 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 1 0 "" 0 0} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "iIER_ELSI uart_16750.vhd(236) " "Warning (10036): Verilog HDL or VHDL warning at uart_16750.vhd(236): object \"iIER_ELSI\" assigned a value but never read" { } { { "../../../rtl/vhdl/uart_16750.vhd" "" { Text "R:/uart16750/rtl/vhdl/uart_16750.vhd" 236 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 1 0 "" 0 0} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "iIER_EDSSI uart_16750.vhd(237) " "Warning (10036): Verilog HDL or VHDL warning at uart_16750.vhd(237): object \"iIER_EDSSI\" assigned a value but never read" { } { { "../../../rtl/vhdl/uart_16750.vhd" "" { Text "R:/uart16750/rtl/vhdl/uart_16750.vhd" 237 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 1 0 "" 0 0} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "iIIR_PI uart_16750.vhd(240) " "Warning (10036): Verilog HDL or VHDL warning at uart_16750.vhd(240): object \"iIIR_PI\" assigned a value but never read" { } { { "../../../rtl/vhdl/uart_16750.vhd" "" { Text "R:/uart16750/rtl/vhdl/uart_16750.vhd" 240 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 1 0 "" 0 0} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "iIIR_ID0 uart_16750.vhd(241) " "Warning (10036): Verilog HDL or VHDL warning at uart_16750.vhd(241): object \"iIIR_ID0\" assigned a value but never read" { } { { "../../../rtl/vhdl/uart_16750.vhd" "" { Text "R:/uart16750/rtl/vhdl/uart_16750.vhd" 241 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 1 0 "" 0 0} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "iIIR_ID1 uart_16750.vhd(242) " "Warning (10036): Verilog HDL or VHDL warning at uart_16750.vhd(242): object \"iIIR_ID1\" assigned a value but never read" { } { { "../../../rtl/vhdl/uart_16750.vhd" "" { Text "R:/uart16750/rtl/vhdl/uart_16750.vhd" 242 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 1 0 "" 0 0} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "iIIR_ID2 uart_16750.vhd(243) " "Warning (10036): Verilog HDL or VHDL warning at uart_16750.vhd(243): object \"iIIR_ID2\" assigned a value but never read" { } { { "../../../rtl/vhdl/uart_16750.vhd" "" { Text "R:/uart16750/rtl/vhdl/uart_16750.vhd" 243 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 1 0 "" 0 0} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "iIIR_FIFO64 uart_16750.vhd(244) " "Warning (10036): Verilog HDL or VHDL warning at uart_16750.vhd(244): object \"iIIR_FIFO64\" assigned a value but never read" { } { { "../../../rtl/vhdl/uart_16750.vhd" "" { Text "R:/uart16750/rtl/vhdl/uart_16750.vhd" 244 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 1 0 "" 0 0} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "iRInRE uart_16750.vhd(306) " "Warning (10036): Verilog HDL or VHDL warning at uart_16750.vhd(306): object \"iRInRE\" assigned a value but never read" { } { { "../../../rtl/vhdl/uart_16750.vhd" "" { Text "R:/uart16750/rtl/vhdl/uart_16750.vhd" 306 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 1 0 "" 0 0}

trunk/syn/Altera/CycloneII/UART16750.srf Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/syn/Altera/CycloneII/UART16750.bdf =================================================================== --- trunk/syn/Altera/CycloneII/UART16750.bdf (nonexistent) +++ trunk/syn/Altera/CycloneII/UART16750.bdf (revision 16) @@ -0,0 +1,991 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +//#pragma file_not_in_maxplusii_format +(header "graphic" (version "1.3")) +(pin + (input) + (rect 208 0 376 16) + (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) + (text "CLK" (rect 5 0 26 12)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 92 12)(pt 117 12)(line_width 1)) + (line (pt 92 4)(pt 117 4)(line_width 1)) + (line (pt 121 8)(pt 168 8)(line_width 1)) + (line (pt 92 12)(pt 92 4)(line_width 1)) + (line (pt 117 4)(pt 121 8)(line_width 1)) + (line (pt 117 12)(pt 121 8)(line_width 1)) + ) + (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 120 80 168 96)) +) +(pin + (input) + (rect 168 224 336 240) + (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) + (text "CS" (rect 5 0 20 12)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 92 12)(pt 117 12)(line_width 1)) + (line (pt 92 4)(pt 117 4)(line_width 1)) + (line (pt 121 8)(pt 168 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trunk/syn/Altera/CycloneII/UART16750.bdf Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property

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