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URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

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    from Rev 150 to Rev 151
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Rev 150 → Rev 151

/sdhc-sc-core/trunk/src/grpSd/unitSdCardModel/src/SdCardModel.sv
2,7 → 2,7
// file: SdCardModel.sv
// author: Rainer Kastl
//
// Models a SDCard for verification
// Models a SdCardModel for verification
//
 
`ifndef SDCARDMODEL
16,9 → 16,9
`include "SdBFM.sv";
`include "Logger.sv";
 
class SDCard;
class SdCardModel;
local SdBFM bfm;
local SDCardState state;
local SdCardModelState state;
local RCA_t rca;
local logic CCS;
local Mode_t mode;
301,7 → 301,7
endclass
 
class NoSDCard extends SDCard;
class NoSdCardModel extends SdCardModel;
 
function new(SdBFM bfm);
super.new(bfm);
/sdhc-sc-core/trunk/src/grpSd/unitSdCardModel/src/SdCardState.sv
2,7 → 2,7
// file: SdCardState.sv
// author: Rainer Kastl
//
// SDCardState class for use in the SdCardModel
// SdCardModelState class for use in the SdCardModel
//
 
`ifndef SDCARDSTATE
13,9 → 13,9
typedef enum {
idle = 0, ready = 1, ident = 2, stby = 3, trans = 4,
data = 5, rcv = 6, prg = 7, dis = 8
} SDCardStates;
} SdCardModelStates;
 
class SDCardState;
class SdCardModelState;
logic OutOfRange;
logic AddressError;
logic BlockLenError;
/sdhc-sc-core/trunk/src/grpSd/unitSdCardModel/src/SdCommand.sv
65,7 → 65,7
 
class SDCommandR1 extends DefaultSdResponse;
 
function new(int id, SDCardState state);
function new(int id, SdCardModelState state);
super.new(id, state.get());
endfunction
104,7 → 104,7
endclass
 
function SDCommandArg getArgFromRcaAndState(RCA_t rca, SDCardState state);
function SDCommandArg getArgFromRcaAndState(RCA_t rca, SdCardModelState state);
SDCommandArg arg;
arg[31:16] = rca;
arg[15] = state.ComCrcError;
122,7 → 122,7
 
class SDCommandR6 extends DefaultSdResponse;
 
function new(RCA_t rca, SDCardState state);
function new(RCA_t rca, SdCardModelState state);
super.new(cSdCmdSendRelAdr, getArgFromRcaAndState(rca, state));
endfunction
 
/sdhc-sc-core/trunk/src/grpSd/unitSdWbSlave/src/Wishbone-BFM.sv File deleted
/sdhc-sc-core/trunk/src/grpSd/unitSdWbSlave/src/WishboneBFM.sv
0,0 → 1,225
//
// file: Wishbone-BFM.sv
// author: Copyright 2010: Rainer Kastl
//
// Description: Bus functional model for wishbone registered feedback
// Wishbone spec Revision B.3
//
 
`ifndef WISHBONE
`define WISHBONE
 
`include "WishboneInterface.sv";
 
class WbBFM;
 
virtual WishboneInterface.Master Bus;
 
function new(virtual WishboneInterface.Master Bus);
this.Bus = Bus;
endfunction
 
task Idle();
 
@(posedge this.Bus.CLK_I)
this.Bus.cbMaster.CYC_O <= cNegated;
this.Bus.cbMaster.ADR_O <= '{default: cDontCare};
this.Bus.cbMaster.DAT_O <= '{default: cDontCare};
this.Bus.cbMaster.SEL_O <= '{default: cDontCare};
this.Bus.cbMaster.STB_O <= cNegated;
this.Bus.cbMaster.TGA_O <= '{default: cDontCare};
this.Bus.cbMaster.TGC_O <= '{default: cDontCare};
this.Bus.cbMaster.TGD_O <= cDontCare;
this.Bus.cbMaster.WE_O <= cDontCare;
this.Bus.cbMaster.LOCK_O <= cNegated;
this.Bus.cbMaster.CTI_O <= '{default: cDontCare};
$display("%t : Bus idle.", $time);
 
endtask;
 
function void checkResponse();
 
// Analyse slave response
if (this.Bus.cbMaster.ERR_I == cAsserted) begin
$display("%t : MasterWrite: ERR_I asserted; Slave encountered an error.", $time);
end
if (this.Bus.cbMaster.RTY_I == cAsserted) begin
$display("%t : MasterWrite: RTY_I asserted; Retry requested.", $time);
end
 
endfunction;
 
task Read(logic [`cWishboneWidth-1 : 0] Address,
ref logic [`cWishboneWidth-1 : 0] Data,
input logic [`cWishboneWidth-1 : 0] TGA = '{default: cDontCare},
input logic [`cWishboneWidth-1 : 0] BankSelect = '{default: 1});
 
@(posedge this.Bus.CLK_I);
this.Bus.cbMaster.ADR_O <= Address;
this.Bus.cbMaster.TGA_O <= TGA;
this.Bus.cbMaster.WE_O <= cNegated;
this.Bus.cbMaster.SEL_O <= BankSelect;
this.Bus.cbMaster.CYC_O <= cAsserted;
this.Bus.cbMaster.TGC_O <= cAsserted;
this.Bus.cbMaster.STB_O <= cAsserted;
this.Bus.cbMaster.CTI_O <= ClassicCycle;
 
//$display("%t : MasterRead: Waiting for slave resonse", $time);
// Wait until slave responds
wait ((this.Bus.cbMaster.ACK_I == cAsserted)
|| (this.Bus.cbMaster.ERR_I == cAsserted)
|| (this.Bus.cbMaster.RTY_I == cAsserted));
 
checkResponse();
 
Data = this.Bus.cbMaster.DAT_I; // latch it before the CLOCK???
//$display("%t : Reading %h", $time, Data);
 
this.Bus.cbMaster.STB_O <= cNegated;
this.Bus.cbMaster.CYC_O <= cNegated;
@(posedge this.Bus.CLK_I);
 
endtask;
 
task BlockRead(logic [`cWishboneWidth-1 : 0] Address,
ref logic [`cWishboneWidth-1 : 0] Data[],
input logic [`cWishboneWidth-1 : 0] TGA = '{default: cDontCare},
input logic [`cWishboneWidth-1 : 0] BankSelect = '{default: 1});
 
foreach(Data[i]) begin
this.Bus.cbMaster.WE_O <= cNegated;
this.Bus.cbMaster.CYC_O <= cAsserted;
this.Bus.cbMaster.TGC_O <= cAsserted;
this.Bus.cbMaster.STB_O <= cAsserted;
this.Bus.cbMaster.LOCK_O <= cAsserted;
this.Bus.cbMaster.ADR_O <= Address+i;
this.Bus.cbMaster.TGA_O <= TGA;
this.Bus.cbMaster.SEL_O <= BankSelect;
this.Bus.cbMaster.CTI_O <= ClassicCycle;
@(posedge this.Bus.CLK_I);
 
//$display("%t : MasterRead: Waiting for slave response.", $time);
// Wait until slave responds
wait ((this.Bus.cbMaster.ACK_I == cAsserted)
|| (this.Bus.cbMaster.ERR_I == cAsserted)
|| (this.Bus.cbMaster.RTY_I == cAsserted));
 
checkResponse();
Data[i] = this.Bus.cbMaster.DAT_I;
//$display("%t : Reading %h", $time, Data[i]);
end
 
this.Bus.cbMaster.STB_O <= cNegated;
this.Bus.cbMaster.CYC_O <= cNegated;
this.Bus.cbMaster.LOCK_O <= cNegated;
@(posedge this.Bus.CLK_I);
 
endtask;
 
task Write(logic [`cWishboneWidth-1 : 0] Address,
logic [`cWishboneWidth-1 : 0] Data,
logic [`cWishboneWidth-1 : 0] TGA = '{default: cDontCare},
logic [`cWishboneWidth-1 : 0] TGD = cDontCare,
logic [`cWishboneWidth-1 : 0] BankSelect = '{default: 1});
 
@(posedge this.Bus.CLK_I)
// CLOCK EDGE 0
this.Bus.cbMaster.ADR_O <= Address;
this.Bus.cbMaster.TGA_O <= TGA;
this.Bus.cbMaster.DAT_O <= Data;
this.Bus.cbMaster.TGD_O <= TGD;
this.Bus.cbMaster.WE_O <= cAsserted;
this.Bus.cbMaster.SEL_O <= BankSelect;
this.Bus.cbMaster.CYC_O <= cAsserted;
this.Bus.cbMaster.TGC_O <= cAsserted; // Assert all?
this.Bus.cbMaster.STB_O <= cAsserted;
this.Bus.cbMaster.CTI_O <= ClassicCycle;
//$display("%t : MasterWrite: Waiting for slave response.", $time);
// Wait until slave responds
 
wait ((this.Bus.cbMaster.ACK_I == cAsserted)
|| (this.Bus.cbMaster.ERR_I == cAsserted)
|| (this.Bus.cbMaster.RTY_I == cAsserted));
checkResponse();
this.Bus.cbMaster.STB_O <= cNegated;
this.Bus.cbMaster.CYC_O <= cNegated;
 
@(posedge this.Bus.CLK_I);
// CLOCK EDGE 1
//$display("%t : MasterWrite completed.", $time);
endtask;
 
task BlockWrite (logic [`cWishboneWidth-1 : 0] Address,
logic [`cWishboneWidth-1 : 0] Data [],
logic [`cWishboneWidth-1 : 0] TGA = '{default: cDontCare},
logic [`cWishboneWidth-1 : 0] TGD = cDontCare,
logic [`cWishboneWidth-1 : 0] BankSelect = '{default: 1}
);
 
foreach(Data[i]) begin
 
@(posedge this.Bus.CLK_I)
// CLOCK EDGE 0
this.Bus.cbMaster.ADR_O <= Address + i;
this.Bus.cbMaster.TGA_O <= TGA;
this.Bus.cbMaster.DAT_O <= Data[i];
this.Bus.cbMaster.TGD_O <= TGD;
this.Bus.cbMaster.WE_O <= cAsserted;
this.Bus.cbMaster.SEL_O <= BankSelect;
this.Bus.cbMaster.CYC_O <= cAsserted;
this.Bus.cbMaster.TGC_O <= cAsserted; // Assert all?
this.Bus.cbMaster.STB_O <= cAsserted;
this.Bus.cbMaster.LOCK_O <= cAsserted;
this.Bus.cbMaster.CTI_O <= ClassicCycle;
 
// Wait until slave responds
wait ((this.Bus.cbMaster.ACK_I == cAsserted)
|| (this.Bus.cbMaster.ERR_I == cAsserted)
|| (this.Bus.cbMaster.RTY_I == cAsserted));
checkResponse();
//$display("%t : MasterBlockWrite phase %d completed.", $time, i);
end
 
this.Bus.cbMaster.STB_O <= cNegated;
this.Bus.cbMaster.CYC_O <= cNegated;
this.Bus.cbMaster.LOCK_O <= cNegated;
@(posedge this.Bus.CLK_I);
// CLOCK EDGE 1
//$display("%t : MasterBlockWrite completed.", $time);
endtask;
 
task TestSingleOps (logic [`cWishboneWidth-1 : 0] Address,
logic [`cWishboneWidth-1 : 0] Data);
 
logic [`cWishboneWidth-1 : 0] rd;
 
this.Write(Address, Data);
this.Read(Address, rd);
 
$display("%t : %h (read) == %h (written)", $time, rd, Data);
assert (rd == Data);
endtask;
 
task TestBlockOps (logic [`cWishboneWidth-1 : 0] Address,
logic [`cWishboneWidth-1 : 0] Data []);
 
logic [`cWishboneWidth-1 : 0] blockData [];
 
blockData = new [Data.size()];
 
this.BlockWrite(Address, Data);
this.BlockRead(Address, blockData);
 
foreach(blockData[i]) begin
$display("%t : %h (read) == %h (written)", $time, blockData[i], Data[i]);
assert (Data[i] == blockData[i]);
end
 
blockData.delete();
 
endtask;
 
endclass
 
`endif
 
/sdhc-sc-core/trunk/src/grpSd/unitTbdSd/src/TbdSd.sv
14,7 → 14,7
initial begin
SdBusTransToken token;
SdBFM SdBfm = new(SdBus);
SDCard card = new(SdBfm);
SdCardModel card = new(SdBfm);
assert(card.randomize());
 
fork
/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/Files.tcl
30,7 → 30,7
set svunits {Sd SdCardModel
Sd SdVerificationTestbench}
 
set sysvlogparams [list +incdir+../../unitSdCardModel/src+../src+../../unitSdWbSlave/src+../../../grpVerification/unitLogger/src/]
set sysvlogparams [list +incdir+../../unitSdCardModel/src+../src+../../unitSdWbSlave/src+../../../grpVerification/unitLogger/src/+../../../grpSdVerification/unitSdCoreTransactionBFM/src+../../../grpSdVerification/unitSdCoreTransactionSeqGen/src+../../../grpSdVerification/unitSdCoreTransferFunction/src+../../../grpSdVerification/unitSdCoreChecker/src+../../../grpSdVerification/unitSdCoreTransaction/src]
 
#set tb
set top Testbed
/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/src/SdVerificationTestbench.sv
17,10 → 17,10
typedef logic [2:0] aCTI;
const aCTI ClassicCycle = "000";
 
 
`include "Harness.sv";
`include "SdCardModel.sv";
`include "SdCmdInterface.sv";
`include "Wishbone-BFM.sv";
`include "SdBusInterface.sv";
`include "WishboneInterface.sv";
 
`define cCmdCount 1000
 
28,9 → 28,7
 
program Test(ISdCard ICmd, WishboneInterface BusInterface);
initial begin
logic[31:0] rd;
Wishbone Bus = new(BusInterface.Master);
SDCard card = new(ICmd, $root.Testbed.CmdReceived, $root.Testbed.InitDone);
SdCardModel card = new(ICmd, $root.Testbed.CmdReceived, $root.Testbed.InitDone);
Logger log = new();
 
assert(card.randomize());
/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/src/Harness.sv
0,0 → 1,64
//
// file: harness.sv
// author: Rainer Kastl
//
// Verification harness for SD-Core
//
 
`ifndef HARNESS_SV
`define HARNESS_SV
 
`include "SdCardModel.sv";
`include "WishboneBFM.sv";
`include "SdBFM.sv";
`include "SdCoreTransactionBFM.sv";
`include "SdCoreTransactionSeqGen.sv";
`include "SdCoreTransferFunction.sv";
`include "SdCoreChecker.sv";
 
class harness;
 
SdCoreTransactionBFM TransBfm;
WbBFM WbBfm;
SdBFM SdBfm;
 
SdCoreTransactionSeqGen TransSeqGen;
 
SdCoreTransferFunction TransFunc;
 
SdCardModel Card;
 
SdCoreChecker Checker;
 
Logger Log;
 
extern function new(virtual ISdBus SdBus, virtual IWishboneBus WbBus);
 
endclass
 
function harness::new(virtual ISdBus SdBus, virtual IWishboneBus WbBus);
Log = new();
TransBfm = new();
WbBfm = new(WbBus);
SdBfm = new(SdBus);
 
TransFunc = new();
Checker = new();
 
Card.randomize();
TransSeqGen.randomize();
 
// connect Mailboxes
TransFunc.TransInMb = TransSeqGen.TransOutMb[0];
TransBfm.SdTransInMb = TransSeqGen.TransOutMb[1];
WbBfm.TransInMb = TransBfm.WbTransOutMb;
TransBfm.WbTransInMb = WbBfm.TransOutMb;
Checker.SdTransInMb = TransBfm.SdTransOutMb;
Checker.RamActionInMb = Card.RamActionOutMb;
Checker.ExpectedResultInMb = TransFunc.ExpectedResultOutMb;
endfunction
 
`endif
/sdhc-sc-core/trunk/src/grpSdVerification/unitSdCoreChecker/src/SdCoreChecker.sv
0,0 → 1,8
`ifndef SDCORECHECKER_SV
`define SDCORECHECKER_SV
 
class SdCoreChecker;
 
endclass
 
`endif
/sdhc-sc-core/trunk/src/grpSdVerification/unitSdCoreTransaction/src/SdCoreTransaction.sv
0,0 → 1,12
`ifndef SDCORETRANSACTION_SV
`define SDCORETRANSACTION_SV
 
class SdCoreTransaction;
endclass
 
class SdCoreTransactionSequence;
endclass
 
typedef mailbox #(SdCoreTransactionSequence) SdCoreTransSeqMb;
 
`endif
/sdhc-sc-core/trunk/src/grpSdVerification/unitSdCoreTransactionSeqGen/src/SdCoreTransactionSeqGen.sv
0,0 → 1,10
`ifndef SDCORETRANSACTIONSEQGEN_SV
`define SDCORETRANSACTIONSEQGEN_SV
 
`include "SdCoreTransaction.sv";
 
class SdCoreTransactionSeqGen;
SdCoreTransSeqMb TransOutMb[2];
endclass
 
`endif
/sdhc-sc-core/trunk/src/grpSdVerification/unitSdCoreTransactionBFM/src/SdCoreTransactionBFM.sv
0,0 → 1,8
`ifndef SDCORETRANSACTIONBFM_SV
`define SDCORETRANSACTIONBFM_SV
 
class SdCoreTransactionBFM;
 
endclass
 
`endif
/sdhc-sc-core/trunk/src/grpSdVerification/unitSdCoreTransferFunction/src/SdCoreTransferFunction.sv
0,0 → 1,11
`ifndef SDCORETRANSFERFUNCTION_SV
`define SDCORETRANSFERFUNCTION_SV
 
`include "SdCoreTransaction.sv";
 
class SdCoreTransferFunction;
SdCoreTransSeqMb TransInMb;
 
endclass
 
`endif

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