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URL https://opencores.org/ocsvn/or1k/or1k/trunk

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    from Rev 1502 to Rev 1503
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Rev 1502 → Rev 1503

/trunk/or1ksim/peripheral/16450.c
61,8 → 61,8
static void uart_clear_int(struct dev_16450 *uart, int intr);
void uart_tx_send(void *dat);
 
/* Number of clock cycles (one clock cycle is one call to the uart_clock())
before a single character is transmitted or received. */
/* Number of clock cycles (one clock cycle is when UART_CLOCK_DIVIDER simulator
* cycles have elapsed) before a single character is transmitted or received. */
static unsigned long char_clks(int dll, int dlh, int lcr)
{
unsigned int bauds_per_char = 2;
268,6 → 268,35
SCHED_ADD(uart_next_int, uart, 0);
}
 
/*----------------------------------------------------[ Loopback handling ]---*/
static void uart_loopback(struct dev_16450 *uart)
{
if(!(uart->regs.mcr & UART_MCR_LOOP))
return;
 
if((uart->regs.mcr & UART_MCR_AUX2) != ((uart->regs.msr & UART_MSR_DCD) >> 4))
uart->regs.msr |= UART_MSR_DDCD;
 
if((uart->regs.mcr & UART_MCR_AUX1) < ((uart->regs.msr & UART_MSR_RI) >> 4))
uart->regs.msr |= UART_MSR_TERI;
 
if((uart->regs.mcr & UART_MCR_RTS) != ((uart->regs.msr & UART_MSR_CTS) >> 3))
uart->regs.msr |= UART_MSR_DCTS;
 
if((uart->regs.mcr & UART_MCR_DTR) != ((uart->regs.msr & UART_MSR_DSR) >> 5))
uart->regs.msr |= UART_MSR_DDSR;
 
uart->regs.msr &= ~(UART_MSR_DCD | UART_MSR_RI | UART_MSR_DSR | UART_MSR_CTS);
uart->regs.msr |= ((uart->regs.mcr & UART_MCR_AUX2) << 4);
uart->regs.msr |= ((uart->regs.mcr & UART_MCR_AUX1) << 4);
uart->regs.msr |= ((uart->regs.mcr & UART_MCR_RTS) << 3);
uart->regs.msr |= ((uart->regs.mcr & UART_MCR_DTR) << 5);
 
if(uart->regs.msr & (UART_MSR_DCTS | UART_MSR_DDSR | UART_MSR_TERI |
UART_MSR_DDCD))
uart_int_msi(uart);
}
 
/*----------------------------------------------------[ Transmitter logic ]---*/
/* Sends the data in the shift register to the outside world */
static void send_char (struct dev_16450 *uart, int bits_send)
612,6 → 641,7
break;
case UART_MCR:
uart->regs.mcr = value & UART_VALID_MCR;
uart_loopback(uart);
break;
case UART_SCR:
uart->regs.scr = value;
704,6 → 734,7
value = uart->regs.msr & UART_VALID_MSR;
uart->regs.msr = 0;
uart_clear_int(uart, UART_IIR_MSI);
uart_loopback(uart);
break;
case UART_SCR:
value = uart->regs.scr;
815,48 → 846,6
uart_vapi_cmd(uart);
}
 
/* Simulation hook. Must be called every clock cycle to simulate all UART
devices. It does internal functional UART simulation. */
void uart_clock16 (void *dat)
{
struct dev_16450 *uart = dat;
 
/* Schedule for later */
SCHED_ADD (uart_clock16, dat, UART_CLOCK_DIVIDER);
 
TRACE("Running uart clock:\n");
/* If VAPI is not selected, UART communicates with two file streams;
if VAPI is selected, we use VAPI streams. */
/* if txfs is corrupted, skip this uart. */
if (!uart->vapi_id && !channel_ok(uart->channel)) return;
 
TRACE("\tChannel stream or VAPI checks out ok\n");
/***************** Loopback *****************/
if (uart->regs.mcr & UART_MCR_LOOP) {
TRACE("uart_clock: Loopback\n");
if ((uart->regs.mcr & UART_MCR_AUX2) !=
((uart->regs.msr & UART_MSR_DCD) >> 4))
uart->regs.msr |= UART_MSR_DDCD;
if ((uart->regs.mcr & UART_MCR_AUX1) <
((uart->regs.msr & UART_MSR_RI) >> 4))
uart->regs.msr |= UART_MSR_TERI;
if ((uart->regs.mcr & UART_MCR_RTS) !=
((uart->regs.msr & UART_MSR_CTS) >> 3))
uart->regs.msr |= UART_MSR_DCTS;
if ((uart->regs.mcr & UART_MCR_DTR) !=
((uart->regs.msr & UART_MSR_DSR) >> 5))
uart->regs.msr |= UART_MSR_DDSR;
uart->regs.msr &= ~(UART_MSR_DCD | UART_MSR_RI
| UART_MSR_DSR | UART_MSR_CTS);
uart->regs.msr |= ((uart->regs.mcr & UART_MCR_AUX2) << 4);
uart->regs.msr |= ((uart->regs.mcr & UART_MCR_AUX1) << 4);
uart->regs.msr |= ((uart->regs.mcr & UART_MCR_RTS) << 3);
uart->regs.msr |= ((uart->regs.mcr & UART_MCR_DTR) << 5);
}
}
 
/* Reset. It initializes all registers of all UART devices to zero values,
(re)opens all RX/TX file streams and places devices in memory address
space. */
922,7 → 911,6
uart->vapi_buf_tail_ptr = 0;
memset(uart->vapi_buf, 0, sizeof(uart->vapi_buf));
 
SCHED_ADD (uart_clock16, dat, UART_CLOCK_DIVIDER);
uart_sched_recv_check(uart);
}
 

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