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URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

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  • This comparison shows the changes necessary to convert path
    /
    from Rev 151 to Rev 152
    Reverse comparison

Rev 151 → Rev 152

/trunk/rtl/verilog/dbg_cpu.v
43,6 → 43,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.11 2004/04/07 19:28:55 igorm
// Zero is shifted out when CTRL_READ command is active.
//
// Revision 1.10 2004/04/01 10:22:45 igorm
// Signals for easier debugging removed.
//
253,11 → 256,11
end
else if (curr_cmd_rd_comm && crc_cnt_31) // Latching data (from internal regs)
begin
dr[`DBG_CPU_ACC_TYPE_LEN + `DBG_CPU_ADR_LEN + `DBG_CPU_LEN_LEN -1:0] <= #1 {acc_type, adr, len};
dr[`DBG_CPU_DR_LEN -1:0] <= #1 {acc_type, adr, len};
end
else if (curr_cmd_rd_ctrl && crc_cnt_31) // Latching data (from control regs)
begin
dr[`DBG_CPU_DR_LEN -1:`DBG_CPU_DR_LEN -`DBG_CPU_CTRL_LEN] <= #1 ctrl_reg;
dr[`DBG_CPU_DR_LEN -1:0] <= #1 {ctrl_reg, {`DBG_CPU_DR_LEN -`DBG_CPU_CTRL_LEN{1'b0}}};
end
else if (acc_type_read && curr_cmd_go && crc_cnt_31) // Latchind first data (from WB)
begin
886,14 → 889,10
begin
tdo_o = ~crc_match_reg;
end
else if (curr_cmd_rd_comm && crc_cnt_end && (!addr_len_cnt_end))
else if ((curr_cmd_rd_comm || curr_cmd_rd_ctrl) && crc_cnt_end && (!addr_len_cnt_end))
begin
tdo_o = dr[`DBG_CPU_ACC_TYPE_LEN + `DBG_CPU_ADR_LEN + `DBG_CPU_LEN_LEN -1];
end
else if (curr_cmd_rd_ctrl && crc_cnt_end && (!addr_len_cnt_end))
begin
tdo_o = 1'b0;
end
else if (status_cnt_en)
begin
tdo_o = status[3];

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