URL
https://opencores.org/ocsvn/neo430/neo430/trunk
Subversion Repositories neo430
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 154 to Rev 155
- ↔ Reverse comparison
Rev 154 → Rev 155
/neo430/trunk/rtl/top_templates/neo430_top_axi4lite.vhd
19,7 → 19,7
-- # You should have received a copy of the GNU Lesser General Public License along with this # |
-- # source; if not, download it from https://www.gnu.org/licenses/lgpl-3.0.en.html # |
-- # ********************************************************************************************* # |
-- # Stephan Nolting, Hannover, Germany 09.08.2018 # |
-- # Stephan Nolting, Hannover, Germany 23.08.2018 # |
-- ################################################################################################# |
|
library ieee; |
33,8 → 33,8
generic ( |
-- general configuration -- |
CLOCK_SPEED : natural := 100000000; -- main clock in Hz |
IMEM_SIZE : natural := 4*1024; -- internal IMEM size in bytes, max 48kB (default=4kB) |
DMEM_SIZE : natural := 2*1024; -- internal DMEM size in bytes, max 12kB (default=2kB) |
IMEM_SIZE : natural := 4*1024; -- internal IMEM size in bytes, max 32kB (default=4kB) |
DMEM_SIZE : natural := 2*1024; -- internal DMEM size in bytes, max 28kB (default=2kB) |
-- additional configuration -- |
USER_CODE : std_logic_vector(15 downto 0) := x"0000"; -- custom user code |
-- module configuration -- |
54,9 → 54,6
IMEM_AS_ROM : boolean := false -- implement IMEM as read-only memory? (default=false) |
); |
port ( |
-- global control -- |
clk_i : in std_logic; -- global clock, rising edge |
rst_i : in std_logic; -- global reset, async, low-active |
-- GPIO -- |
gpio_o : out std_logic_vector(15 downto 0); -- parallel output |
gpio_i : in std_logic_vector(15 downto 0); -- parallel input |
81,6 → 78,7
m_axi_awaddr : out std_logic_vector(31 downto 0); |
m_axi_awvalid : out std_logic; |
m_axi_awready : in std_logic; |
m_axi_awprot : out std_logic_vector(2 downto 0); |
-- Write Data Channel |
m_axi_wdata : out std_logic_vector(31 downto 0); |
m_axi_wstrb : out std_logic_vector(3 downto 0); |
90,6 → 88,7
m_axi_araddr : out std_logic_vector(31 downto 0); |
m_axi_arvalid : out std_logic; |
m_axi_arready : in std_logic; |
m_axi_arprot : out std_logic_vector(2 downto 0); |
-- Read Data Channel |
m_axi_rdata : in std_logic_vector(31 downto 0); |
m_axi_rresp : in std_logic_vector(1 downto 0); |
118,8 → 117,6
signal wb_core : wb_bus_t; |
|
-- other signals for conversion -- |
signal clk_i_int : std_ulogic; |
signal rst_i_int : std_ulogic; |
signal gpio_o_int : std_ulogic_vector(15 downto 0); |
signal gpio_i_int : std_ulogic_vector(15 downto 0); |
signal pwm_o_int : std_ulogic_vector(02 downto 0); |
134,12 → 131,12
constant usrcode_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(USER_CODE); |
|
-- AXI arbiter -- |
signal read_trans : std_ulogic; |
signal write_trans : std_ulogic; |
signal pending_rd : std_ulogic; -- pending read transfer |
signal pending_wr : std_ulogic; -- pending write transfer |
signal adr_valid : std_ulogic; |
signal axi_resp_ok : std_ulogic; |
signal read_trans : std_ulogic; |
signal write_trans : std_ulogic; |
signal pending_rd : std_ulogic; -- pending read transfer |
signal pending_wr : std_ulogic; -- pending write transfer |
signal adr_valid : std_ulogic; |
signal wresp_ok : std_logic; |
|
begin |
|
149,8 → 146,8
generic map ( |
-- general configuration -- |
CLOCK_SPEED => CLOCK_SPEED, -- main clock in Hz |
IMEM_SIZE => IMEM_SIZE, -- internal IMEM size in bytes, max 48kB (default=4kB) |
DMEM_SIZE => DMEM_SIZE, -- internal DMEM size in bytes, max 12kB (default=2kB) |
IMEM_SIZE => IMEM_SIZE, -- internal IMEM size in bytes, max 32kB (default=4kB) |
DMEM_SIZE => DMEM_SIZE, -- internal DMEM size in bytes, max 28kB (default=2kB) |
-- additional configuration -- |
USER_CODE => usrcode_c, -- custom user code |
-- module configuration -- |
202,8 → 199,6
|
-- Output Type Conversion --------------------------------------------------- |
-- ----------------------------------------------------------------------------- |
clk_i_int <= std_ulogic(clk_i); |
rst_i_int <= std_ulogic(rst_i); |
gpio_i_int <= std_ulogic_vector(gpio_i); |
uart_rxd_i_int <= std_ulogic(uart_rxd_i); |
spi_miso_i_int <= std_ulogic(spi_miso_i); |
230,11 → 225,12
begin |
if rising_edge(m_axi_aclk) then |
if (wb_core.cyc = '0') then |
pending_rd <= '0'; |
pending_wr <= '0'; |
adr_valid <= '0'; |
pending_rd <= '0'; |
pending_wr <= '0'; |
adr_valid <= '0'; |
m_axi_bready <= '0'; |
else |
-- address valid? |
-- read/write address valid -- |
if ((wb_core.cyc and wb_core.stb) = '1') then |
adr_valid <= '1'; |
elsif (m_axi_awready = '1') or (m_axi_arready = '1') then |
252,35 → 248,42
elsif (m_axi_wready = '1') then |
pending_wr <= '0'; |
end if; |
-- write response channel - |
if (write_trans = '1') then |
m_axi_bready <= '1'; |
elsif (m_axi_bvalid = '1') then |
m_axi_bready <= '0'; |
end if; |
end if; |
end if; |
end process axi_arbiter; |
|
-- Acknowledge Wishbone transfer -- |
wb_core.ack <= (pending_rd and std_ulogic(m_axi_rvalid)) or -- read transfer |
(pending_wr and std_ulogic(m_axi_wready)) or -- write transfer |
(axi_resp_ok and m_axi_bvalid); -- response channel |
wb_core.ack <= (pending_rd and std_ulogic(m_axi_rvalid)) or -- read transfer |
-- (pending_wr and std_ulogic(m_axi_wready)); -- write transfer |
(wresp_ok and m_axi_bvalid); -- acknowledged write transfer |
|
-- Read Address Channel -- |
m_axi_araddr <= std_logic_vector(wb_core.adr); |
m_axi_arvalid <= adr_valid; |
m_axi_arvalid <= std_logic(adr_valid) and std_logic(pending_rd); |
m_axi_arprot <= "000"; -- data access, secure, unprivileged |
|
-- Read Data Channel -- |
wb_core.di <= std_ulogic_vector(m_axi_rdata); |
m_axi_rready <= (not adr_valid) and pending_rd; |
m_axi_rready <= std_logic(pending_rd); |
|
-- Write Address Channel -- |
m_axi_awaddr <= std_logic_vector(wb_core.adr); |
m_axi_awvalid <= adr_valid; |
m_axi_awvalid <= std_logic(adr_valid) and std_logic(pending_wr); |
m_axi_awprot <= "000"; -- data access, secure, unprivileged |
|
-- Write Data Channel -- |
m_axi_wdata <= std_logic_vector(wb_core.do); |
m_axi_wstrb <= std_logic_vector(wb_core.sel); |
m_axi_wvalid <= (not adr_valid) and std_logic(pending_wr); |
m_axi_wvalid <= std_logic(pending_wr); |
|
-- Write Response Channel -- |
axi_resp_ok <= '1' when (m_axi_rresp = "00") else '0'; |
m_axi_bready <= wb_core.cyc; |
-- Write Data Response Channel -- |
wresp_ok <= '1' when (m_axi_bresp = "00") else '0'; |
|
|
end neo430_top_axi4lite_rtl; |