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URL https://opencores.org/ocsvn/395_vgs/395_vgs/trunk

Subversion Repositories 395_vgs

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  • This comparison shows the changes necessary to convert path 
    /
    from Rev 16 to Rev 17
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Rev 16 → Rev 17

/trunk/devkit/img2xes/make_images.cmd
1,2 → 1,2
perl img2xes.pl -x 320 -y 240 -d 3+2+3 -pi 8 -i neogeo.png -o neogeo.xes
perl img2xes.pl -x 320 -y 240 -d 3+2+3 -pi 8 -i vs.png -o vs.xes
perl img2xes.pl -x 320 -y 240 -d 3+2+3 -pi 8 -address 0x12600 -i vs.png -o vs.xes
/trunk/hdl/gpuchip.vhd
29,7 → 29,11
use WORK.xsasdram.all;
use WORK.sdram.all;
use WORK.vga_pckg.all;
<<<<<<< gpuchip.vhd
use WORK.gpu_core_pckg.all;
=======
use WORK.fillunit_pckg.all;
>>>>>>> 1.5
 
entity gpuChip is
64,6 → 68,12
pin_hsync_n : out std_logic;
pin_vsync_n : out std_logic;
 
-- SRAM Cache connections
pin_cData : inout std_logic_vector(15 downto 0); -- data bus to Cache
pin_cAddr : out std_logic_vector(14 downto 0); -- Cache address bus
pin_cwrite : out std_logic;
pin_cread : out std_logic;
 
-- SDRAM pin connections
pin_sclkfb : in std_logic; -- feedback SDRAM clock with PCB delays
pin_sclk : out std_logic; -- clock to SDRAM
277,31 → 287,53
blank => open
);
 
 
------------------------------------------------------------------------------------------------------------
-- instance of fill-unit
------------------------------------------------------------------------------------------------------------
u4: fillunit
generic map(
-- u4: fillunit
-- generic map(
-- FREQ => FREQ,
-- DATA_WIDTH => DATA_WIDTH,
-- HADDR_WIDTH => ADDR_WIDTH
-- )
-- port map(
-- clk => sdram_clk1x, -- master clock
-- reset => sysReset, -- reset for this entity
-- rd1 => rd1, -- initiate read operation
-- wr1 => wr1, -- initiate write operation
-- opBegun => opBegun1, --operation recieved
-- done1 => done1, -- read or write operation is done
-- hAddr1 => hAddr1, -- address to SDRAM
-- hDIn1 => hDIn1, -- data to dualport to SDRAM
-- hDOut1 => hDOut1 -- data from dualport to SDRAM
-- );
--
 
u5: gpu_core
generic map(
FREQ => FREQ,
DATA_WIDTH => DATA_WIDTH,
HADDR_WIDTH => ADDR_WIDTH
)
port map(
clk => sdram_clk1x, -- master clock
reset => sysReset, -- reset for this entity
rd1 => rd1, -- initiate read operation
wr1 => wr1, -- initiate write operation
opBegun => opBegun1, --operation recieved
done1 => done1, -- read or write operation is done
hAddr1 => hAddr1, -- address to SDRAM
hDIn1 => hDIn1, -- data to dualport to SDRAM
hDOut1 => hDOut1 -- data from dualport to SDRAM
);
port map (
clk =>sdram_clk1x,
rst =>sysReset,
rd1 =>rd1,
wr1 =>wr1,
opBegun =>opBegun1,
done1 =>done1,
rddone1 =>rddone1,
hAddr1 =>hAddr1,
hDIn1 =>hDIn1,
hDOut1 =>hDOut1,
CacheDIn =>pin_cData,
CacheAddr =>pin_cAddr,
cread =>pin_cread,
cwrite =>pin_cwrite
);
 
 
 
 
--------------------------------------------------------------------------------------------------------------
-- End of Submodules
--------------------------------------------------------------------------------------------------------------
311,7 → 343,7
rst_i <= sysReset;
pin_ce_n <= '1'; -- disable Flash RAM
rd0 <= ((not full) and drawframe); -- negate the full signal for use in controlling the SDRAM read operation
hDIn0 <= "0000000000000000000000"; -- don't need to write to port 0 (VGA Port)
hDIn0 <= "0000000000000000"; -- don't need to write to port 0 (VGA Port)
wr0 <= '0';
hAddr0 <= std_logic_vector(vga_address);
 
/trunk/hdl/gpuchip.ucf
13,11 → 13,44
NET "pin_ba<1>" LOC = "p137" ;
NET "pin_blue<0>" LOC = "p21" ;
NET "pin_blue<1>" LOC = "p22" ;
NET "pin_cAddr<0>" LOC = "p75" ;
NET "pin_cAddr<10>" LOC = "p38" ;
NET "pin_cAddr<11>" LOC = "p44" ;
NET "pin_cAddr<12>" LOC = "p46" ;
NET "pin_cAddr<13>" LOC = "p49" ;
NET "pin_cAddr<14>" LOC = "p57" ;
NET "pin_cAddr<1>" LOC = "p74" ;
NET "pin_cAddr<2>" LOC = "p30" ;
NET "pin_cAddr<3>" LOC = "p31" ;
NET "pin_cAddr<4>" LOC = "p78" ;
NET "pin_cAddr<5>" LOC = "p42" ;
NET "pin_cAddr<6>" LOC = "p40" ;
NET "pin_cAddr<7>" LOC = "p29" ;
NET "pin_cAddr<8>" LOC = "p28" ;
NET "pin_cAddr<9>" LOC = "p27" ;
NET "pin_cas_n" LOC = "p126" ;
NET "pin_cData<0>" LOC = "p80" ;
NET "pin_cData<10>" LOC = "p85" ;
NET "pin_cData<11>" LOC = "p86" ;
NET "pin_cData<12>" LOC = "p87" ;
NET "pin_cData<13>" LOC = "p94" ;
NET "pin_cData<14>" LOC = "p66" ;
NET "pin_cData<15>" LOC = "p64" ;
NET "pin_cData<1>" LOC = "p77" ;
NET "pin_cData<2>" LOC = "p83" ;
NET "pin_cData<3>" LOC = "p79" ;
NET "pin_cData<4>" LOC = "p76" ;
NET "pin_cData<5>" LOC = "p56" ;
NET "pin_cData<6>" LOC = "p54" ;
NET "pin_cData<7>" LOC = "p62" ;
NET "pin_cData<8>" LOC = "p67" ;
NET "pin_cData<9>" LOC = "p84" ;
NET "pin_ce_n" LOC = "p41" ;
NET "pin_cke" LOC = "p131" ;
NET "pin_clkin" LOC = "p88" ;
NET "pin_cread" LOC = "p39" ;
NET "pin_cs_n" LOC = "p132" ;
NET "pin_cwrite" LOC = "p59" ;
NET "pin_dqmh" LOC = "p124" ;
NET "pin_dqml" LOC = "p122" ;
NET "pin_green<0>" LOC = "p19" ;

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