URL
https://opencores.org/ocsvn/amber/amber/trunk
Subversion Repositories amber
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 16 to Rev 17
- ↔ Reverse comparison
Rev 16 → Rev 17
/amber/trunk/hw/tools/all.sh
49,7 → 49,7
mul mla \ |
swp \ |
\ |
irq firq swi undefined_ins addr_ex \ |
irq firq swi undefined_ins addr_ex irq_stm \ |
\ |
cache1 cache2 cache3 cache_swap \ |
cacheable_area cache_flush \ |
66,14 → 66,15
mlas_bug inflate_bug swp_lock_bug \ |
cache_swap_bug \ |
" |
LOF_FILE=$1 |
|
echo "----------------------------------" >> hw-tests.log |
date >> hw-tests.log |
echo "----------------------------------" >> ${LOF_FILE} |
date >> ${LOF_FILE} |
|
for i in $TEST_LIST; do |
echo "Run test $i" |
../tools/run.sh ${i} $1 $2 |
../tools/run.sh ${i} $2 $3 |
done |
|
echo "----------------------------------" >> hw-tests.log |
echo "----------------------------------" >> ${LOF_FILE} |
|
/amber/trunk/hw/tools/run.sh
45,6 → 45,7
#-------------------------------------------------------- |
AMBER_LOAD_MAIN_MEM=" " |
AMBER_TIMEOUT=0 |
AMBER_LOG_FILE="tests.log" |
SET_G=0 |
SET_M=0 |
SET_D=0 |
186,7 → 187,7
CORE=" " |
fi |
|
../tools/all.sh $TECH $CORE |
../tools/all.sh ${AMBER_LOG_FILE} ${TECH} ${CORE} |
exit |
fi |
|
232,7 → 233,6
popd > /dev/null |
BOOT_MEM_FILE="../tests/${AMBER_TEST_NAME}.mem" |
BOOT_MEM_PARAMS_FILE="../tests/${AMBER_TEST_NAME}_memparams.v" |
AMBER_LOG_FILE="hw-tests.log" |
# Get timeout |
AMBER_TIMEOUT=`../tools/get_timeout.sh ${AMBER_TEST_NAME}` |
echo "Timeout $AMBER_TIMEOUT" |
244,7 → 244,6
popd > /dev/null |
BOOT_MEM_FILE="../../sw/${AMBER_TEST_NAME}/${AMBER_TEST_NAME}.mem" |
BOOT_MEM_PARAMS_FILE="../../sw/${AMBER_TEST_NAME}/${AMBER_TEST_NAME}_memparams.v" |
AMBER_LOG_FILE="${AMBER_TEST_NAME}.log" |
|
elif [ $TEST_TYPE == 3 ] || [ $TEST_TYPE == 4 ]; then |
# sw test using boot loader |
268,7 → 267,6
BOOT_MEM_PARAMS_FILE="../../sw/boot-loader/boot-loader_memparams.v" |
MAIN_MEM_FILE="../../sw/${AMBER_TEST_NAME}/${AMBER_TEST_NAME}.mem" |
AMBER_LOAD_MAIN_MEM="+define+AMBER_LOAD_MAIN_MEM" |
AMBER_LOG_FILE="${AMBER_TEST_NAME}.log" |
|
else |
echo "Error unrecognized test type" |
311,9 → 309,9
|
# Set a timeout value for the test if it passed |
if [ $TEST_TYPE == 1 ]; then |
tail -1 < hw-tests.log | grep Passed > /dev/null |
tail -1 < ${AMBER_LOG_FILE} | grep Passed > /dev/null |
if [ $? == 0 ]; then |
TICKS=`tail -1 < hw-tests.log | awk '{print $3}'` |
TICKS=`tail -1 < ${AMBER_LOG_FILE} | awk '{print $3}'` |
TOTICKS=$(( $TICKS * 4 + 1000 )) |
../tools/set_timeout.sh ${AMBER_TEST_NAME} $TOTICKS |
fi |
/amber/trunk/hw/tests/timeouts.txt
29,6 → 29,7
swi 1620 |
undefined_ins 2748 |
addr_ex 1772 |
irq_stm 10220 |
cache1 16308 |
cache2 1460 |
cache3 106064 |
48,7 → 49,7
uart_reg 1824 |
uart_tx 136588 |
uart_rx 132384 |
uart_rxint 127264 |
uart_rxint 127204 |
bic_bug 1524 |
movs_bug 1592 |
flow_bug 1500 |
/amber/trunk/hw/tests/irq_stm.S
0,0 → 1,201
/***************************************************************** |
// // |
// Amber 2 Core Interrupt Test // |
// // |
// This file is part of the Amber project // |
// http://www.opencores.org/project,amber // |
// // |
// Description // |
// Tests executes a loop of stm instructions. During this, // |
// a whole bunch of IRQ interrupts are triggered using // |
// the random timer. The test checks that the stm is // |
// not executed twice in a row, once before the interrupt // |
// and again after the interrupt. // |
// // |
// Author(s): // |
// - Conor Santifort, csantifort.amber@gmail.com // |
// // |
////////////////////////////////////////////////////////////////// |
// // |
// Copyright (C) 2010 Authors and OPENCORES.ORG // |
// // |
// This source file may be used and distributed without // |
// restriction provided that this copyright statement is not // |
// removed from the file and that any derivative work contains // |
// the original copyright notice and the associated disclaimer. // |
// // |
// This source file is free software; you can redistribute it // |
// and/or modify it under the terms of the GNU Lesser General // |
// Public License as published by the Free Software Foundation; // |
// either version 2.1 of the License, or (at your option) any // |
// later version. // |
// // |
// This source is distributed in the hope that it will be // |
// useful, but WITHOUT ANY WARRANTY; without even the implied // |
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // |
// PURPOSE. See the GNU Lesser General Public License for more // |
// details. // |
// // |
// You should have received a copy of the GNU Lesser General // |
// Public License along with this source; if not, download it // |
// from http://www.opencores.org/lgpl.shtml // |
// // |
*****************************************************************/ |
|
#include "amber_registers.h" |
|
.section .text |
.globl main |
main: |
|
/* 0x00 Reset Interrupt vector address */ |
b start |
|
/* 0x04 Undefined Instruction Interrupt vector address */ |
b testfail |
|
/* 0x08 SWI Interrupt vector address */ |
b testfail |
|
/* 0x0c Prefetch abort Interrupt vector address */ |
b testfail |
|
/* 0x10 Data abort Interrupt vector address */ |
b testfail |
b testfail |
|
/* 0x18 IRQ vector address */ |
b service_irq |
|
/* 0x1c FIRQ vector address */ |
b testfail |
|
|
start: |
@ --------------------- |
@ Enable the cache |
@ --------------------- |
mvn r0, #0 |
mcr 15, 0, r0, cr3, cr0, 0 @ cacheable area |
mov r0, #1 |
mcr 15, 0, r0, cr2, cr0, 0 @ cache enable |
|
/* Set Supervisor Mode stack pointer */ |
ldr sp, AdrSVCStack |
|
/* Switch to IRQ Mode */ |
mov r0, #0x00000002 |
teqp pc, r0 |
/* Set IRQ Mode stack pointer */ |
ldr sp, AdrIRQStack |
|
/* Switch to User Mode */ |
/* and unset interrupt mask bits */ |
mov r0, #0x00000000 |
teqp pc, r0 |
|
/* Set User Mode stack pointer */ |
ldr sp, AdrUSRStack |
|
/* Configure IRQ Timer with a random time */ |
ldr r4, AdrRanNum |
ldr r5, [r4] |
and r5, r5, #0x1c |
add r5, r5, #5 |
ldr r6, AdrIRQTimer |
str r5, [r6] |
|
mov r2, #40 |
mov r3, #7 |
mov r7, #0x700 |
mov r13, r7 |
@ fill area with zeros |
mov r8, #0x200 |
|
1: str r8, [r7, -r8] |
subs r8, r8, #4 |
beq loop |
b 1b |
|
|
|
loop: |
|
mov r3, #5 |
ldmdb r7!, {r8-r11} |
orr r3, r3, r11, lsr #8 |
mov r11, r11, lsl #24 |
|
@ Follow the r7 address pointer and make |
@ sure it decrements correctly on each |
@ iteration of the loop |
sub r13, r13, #16 |
cmp r7, r13 |
movne r10, #100 |
bne testfail |
|
subs r2, r2, #1 |
beq testpass |
b loop |
|
@ just put these here in case |
@ the cpu incorrectly executes some instructions |
b testfail |
b testfail |
b testfail |
|
|
service_irq: |
@ Save lr to the stack |
stmfd sp!, {lr} |
|
@ Set the IRQ Timer to a random number |
ldr r5, [r4] |
and r5, r5, #0x7f |
|
@ Ensure that never set the IRQ timer to zero |
add r5, r5, #30 |
str r5, [r6] |
|
@ Restore lr from the stack |
ldmfd sp!, {lr} |
|
@ Jump straight back to normal execution |
subs pc, lr, #4 |
|
@ ------------------------------------------ |
@ ------------------------------------------ |
|
testfail: |
ldr r11, AdrTestStatus |
str r10, [r11] |
b testfail |
|
testpass: |
ldr r11, AdrTestStatus |
mov r10, #17 |
str r10, [r11] |
b testpass |
|
|
|
|
/* Write 17 to this address to generate a Test Passed message */ |
AdrTestStatus: .word ADR_AMBER_TEST_STATUS |
AdrRanNum: .word ADR_AMBER_TEST_RANDOM_NUM |
AdrIRQTimer: .word ADR_AMBER_TEST_IRQ_TIMER |
|
AdrText1: .word Text1 |
|
AdrSVCStack: .word 0x0800 |
AdrUSRStack: .word 0x1000 |
AdrIRQStack: .word 0x1800 |
|
|
.align 2 |
Text1: .ascii "Interrupt!\n\000" |
|
/* ========================================================================= */ |
/* ========================================================================= */ |
|
|
/amber/trunk/hw/vlog/system/system_config_defines.v
125,7 → 125,7
`define BOOT_MEM_PARAMS_FILE "not-defined" |
`endif |
`ifndef AMBER_LOG_FILE |
`define AMBER_LOG_FILE "test.log" |
`define AMBER_LOG_FILE "tests.log" |
`endif |
`ifndef AMBER_VCD_FILE |
`define AMBER_VCD_FILE "sim.vcd" |
/amber/trunk/hw/vlog/tb/dumpvcd.v
64,6 → 64,7
$dumpvars(1, `U_EXECUTE.o_exclusive); |
$dumpvars(1, `U_EXECUTE.o_write_data); |
$dumpvars(1, `U_EXECUTE.base_address); |
$dumpvars(1, `U_EXECUTE.pc); |
$dumpvars(1, `U_EXECUTE.u_register_bank.r0); |
$dumpvars(1, `U_EXECUTE.u_register_bank.r1); |
$dumpvars(1, `U_EXECUTE.u_register_bank.r2); |
79,6 → 80,7
$dumpvars(1, `U_EXECUTE.u_register_bank.r12); |
$dumpvars(1, `U_EXECUTE.u_register_bank.r13_out); |
$dumpvars(1, `U_EXECUTE.u_register_bank.r14_out); |
$dumpvars(1, `U_EXECUTE.u_register_bank.r14_irq); |
$dumpvars(1, `U_EXECUTE.u_register_bank.r15); |
|
|
85,7 → 87,6
$dumpvars(1, `U_FETCH); |
$dumpvars(1, `U_CACHE); |
$dumpvars(1, `U_DECODE); |
// $dumpvars(1, `U_COPRO15); |
$dumpvars(1, `U_WISHBONE); |
$dumpvars(1, `U_AMBER); |
|
102,13 → 103,13
if ( `U_DECOMPILE.clk_count == 10 ) |
begin |
$dumpon; |
$display("Dump on at %d ticks", `U_DECOMPILE.clk_count); |
$display("\nDump on at %d ticks", `U_DECOMPILE.clk_count); |
end |
|
if ( `U_DECOMPILE.clk_count == 20 ) |
begin |
$dumpoff; |
$display("Dump off at %d ticks", `U_DECOMPILE.clk_count); |
$display("\nDump off at %d ticks", `U_DECOMPILE.clk_count); |
end |
|
|
115,19 → 116,19
if ( `U_DECOMPILE.clk_count == ( `AMBER_DUMP_START + 0 ) ) |
begin |
$dumpon; |
$display("Dump on at %d ticks", `U_DECOMPILE.clk_count); |
$display("\nDump on at %d ticks", `U_DECOMPILE.clk_count); |
end |
|
if ( `U_DECOMPILE.clk_count == ( `AMBER_DUMP_START + `AMBER_DUMP_LENGTH ) ) |
begin |
$dumpoff; |
$display("Dump off at %d ticks", `U_DECOMPILE.clk_count); |
$display("\nDump off at %d ticks", `U_DECOMPILE.clk_count); |
end |
|
`ifdef AMBER_TERMINATE |
if ( `U_DECOMPILE.clk_count == ( `AMBER_DUMP_START + `AMBER_DUMP_LENGTH + 100) ) |
begin |
$display("Automatic test termination after dump has completed"); |
$display("\nAutomatic test termination after dump has completed"); |
`TB_ERROR_MESSAGE |
end |
`endif |
/amber/trunk/hw/vlog/amber25/a25_dcache.v
1,14 → 1,14
////////////////////////////////////////////////////////////////// |
// // |
// L1 Instruction Cache for Amber 25 Core // |
// L1 Data Cache for Amber 25 Core // |
// // |
// This file is part of the Amber project // |
// http://www.opencores.org/project,amber // |
// // |
// Description // |
// Synthesizable L1 Unified Data and Instruction Cache // |
// Cache is 4-way, 256 line and 16 bytes per line for // |
// a total of 16KB. The cache policy is write-through and // |
// Synthesizable L1 Data Cache // |
// Cache is 2, 3, 4 or 8 way, 256 line and 16 bytes per line. // |
// The cache policy is write-through and // |
// read allocate. For swap instructions (SWP and SWPB) the // |
// location is evicted from the cache and read from main // |
// memory. // |
/amber/trunk/hw/vlog/amber25/a25_icache.v
6,12 → 6,10
// http://www.opencores.org/project,amber // |
// // |
// Description // |
// Synthesizable L1 Unified Data and Instruction Cache // |
// Cache is 4-way, 256 line and 16 bytes per line for // |
// a total of 16KB. The cache policy is write-through and // |
// read allocate. For swap instructions (SWP and SWPB) the // |
// location is evicted from the cache and read from main // |
// memory. // |
// Synthesizable L1 Instruction Cache. // |
// Cache is 2,3,4 or 8 way, 256 line and 16 bytes per line. // |
// a total of 16KB. The cache is read only. Writes from // |
// the core to through the data cache. // |
// // |
// Author(s): // |
// - Conor Santifort, csantifort.amber@gmail.com // |
/amber/trunk/hw/vlog/amber25/a25_wishbone.v
7,11 → 7,11
// // |
// Description // |
// Turns memory access requests from the execute stage and // |
// cache into wishbone bus cycles. For 4-word read requests // |
// from the cache and swap accesses ( read followed by write // |
// to the same address) from the execute stage, // |
// a block transfer is done. All other requests result in // |
// single word transfers. // |
// instruction and data caches into wishbone bus cycles. // |
// For 4-word read requests from either cache and swap // |
// accesses ( read followed by write to the same address) // |
// from the execute stage, a block transfer is done. // |
// All other requests result in single word transfers. // |
// // |
// Write accesses can be done in a single clock cycle on // |
// the wishbone bus, is the destination allows it. The // |
/amber/trunk/hw/vlog/amber25/a25_decode.v
684,9 → 684,10
// interrupt is triggered if the execute condition is met in the execute stage |
assign interrupt = next_interrupt != 3'd0 && |
next_interrupt != 3'd7 && // SWI |
next_interrupt != 3'd6 ; // undefined interrupt |
next_interrupt != 3'd6 && // undefined interrupt |
!conflict ; // Wait for conflicts to resolve before |
// triggering int |
|
|
assign interrupt_mode = next_interrupt == 3'd2 ? FIRQ : |
next_interrupt == 3'd3 ? IRQ : |
next_interrupt == 3'd4 ? SVC : |
/amber/trunk/hw/vlog/amber25/a25_core.v
7,7 → 7,9
// // |
// Description // |
// Instantiates the core consisting of fetch, instruction // |
// decode, execute, and co-processor. // |
// decode, execute, memory access and write back. The // |
// Wishbone interface and Co-Processor modules are also // |
// instantiated here. // |
// // |
// Author(s): // |
// - Conor Santifort, csantifort.amber@gmail.com // |
73,7 → 75,6
wire [31:0] write_data; |
wire write_enable; |
wire [31:0] fetch_instruction; |
// wire priviledged; |
wire decode_exclusive; |
wire decode_iaccess; |
wire decode_daccess; |
118,7 → 119,6
wire [1:0] byte_enable_sel; |
wire [2:0] status_bits_sel; |
wire [2:0] reg_write_sel; |
// wire user_mode_regs_load; |
wire user_mode_regs_store_nxt; |
wire firq_not_user_mode; |
|
261,7 → 261,6
.o_byte_enable_sel ( byte_enable_sel ), |
.o_status_bits_sel ( status_bits_sel ), |
.o_reg_write_sel ( reg_write_sel ), |
// .o_user_mode_regs_load ( user_mode_regs_load ), |
.o_user_mode_regs_store_nxt ( user_mode_regs_store_nxt ), |
.o_firq_not_user_mode ( firq_not_user_mode ), |
.o_write_data_wen ( write_data_wen ), |
350,7 → 349,6
.i_byte_enable_sel ( byte_enable_sel ), |
.i_status_bits_sel ( status_bits_sel ), |
.i_reg_write_sel ( reg_write_sel ), |
// .i_user_mode_regs_load ( user_mode_regs_load ), |
.i_user_mode_regs_store_nxt ( user_mode_regs_store_nxt ), |
.i_firq_not_user_mode ( firq_not_user_mode ), |
.i_write_data_wen ( write_data_wen ), |
/amber/trunk/hw/vlog/amber25/a25_decompile.v
1,6 → 1,6
////////////////////////////////////////////////////////////////// |
// // |
// Decompiler for Amber 25 Core // |
// Decompiler for Amber 25 Core // |
// // |
// This file is part of the Amber project // |
// http://www.opencores.org/project,amber // |
/amber/trunk/hw/sim/wave.do
31,19 → 31,11
add wave -noupdate -group System -group {DDR3 Bus} -format Logic /tb/u_system/ddr3_reset_n |
add wave -noupdate -group System -group {DDR3 Bus} -format Logic /tb/u_system/ddr3_we_n |
add wave -noupdate -expand -group Amber -format Logic /tb/u_system/u_amber/fetch_stall |
add wave -noupdate -expand -group Amber -format Logic /tb/u_system/u_amber/mem_stall |
add wave -noupdate -expand -group Amber -group Fetch -format Literal /tb/u_system/u_amber/u_fetch/i_iaddress |
add wave -noupdate -expand -group Amber -group Fetch -format Logic /tb/u_system/u_amber/u_fetch/i_iaddress_valid |
add wave -noupdate -expand -group Amber -group Fetch -format Logic /tb/u_system/u_amber/u_fetch/o_fetch_stall |
add wave -noupdate -expand -group Amber -group Fetch -format Literal /tb/u_system/u_amber/u_fetch/o_fetch_instruction |
add wave -noupdate -expand -group Amber -group Fetch -format Logic /tb/u_system/u_amber/u_fetch/sel_cache |
add wave -noupdate -expand -group Amber -group Fetch -format Logic /tb/u_system/u_amber/u_fetch/wait_wb |
add wave -noupdate -expand -group Amber -group Fetch -group {Instruction Cache} -format Logic /tb/u_system/u_amber/u_fetch/u_cache/o_stall |
add wave -noupdate -expand -group Amber -group Fetch -group {Instruction Cache} -format Logic /tb/u_system/u_amber/u_fetch/u_cache/read_stall |
add wave -noupdate -expand -group Amber -group Fetch -group {Instruction Cache} -format Logic /tb/u_system/u_amber/u_fetch/u_cache/o_wb_req |
add wave -noupdate -expand -group Amber -group Fetch -group {Instruction Cache} -format Logic /tb/u_system/u_amber/u_fetch/u_cache/i_wb_ready |
add wave -noupdate -expand -group Amber -group Fetch -group {Instruction Cache} -format Literal /tb/u_system/u_amber/u_fetch/i_wb_read_data |
add wave -noupdate -expand -group Amber -group Fetch -group {Instruction Cache} -format Logic /tb/u_system/u_amber/u_fetch/u_cache/wb_hit |
add wave -noupdate -expand -group Amber -group Fetch -group {Instruction Cache} -format Literal -radix ascii /tb/u_system/u_amber/u_fetch/u_cache/xC_STATE |
add wave -noupdate -expand -group Amber -group Fetch -group {Instruction Cache} -format Literal /tb/u_system/u_amber/u_fetch/u_cache/miss_address |
add wave -noupdate -expand -group Amber -group Fetch -group {Instruction Cache} -format Logic /tb/u_system/u_amber/u_fetch/u_cache/read_miss |
56,48 → 48,25
add wave -noupdate -expand -group Amber -group Fetch -group {Instruction Cache} -format Literal /tb/u_system/u_amber/u_fetch/u_cache/tag_address |
add wave -noupdate -expand -group Amber -group Fetch -group {Instruction Cache} -format Logic /tb/u_system/u_amber/u_fetch/u_cache/tag_wenable |
add wave -noupdate -expand -group Amber -group Fetch -group {Instruction Cache} -format Literal /tb/u_system/u_amber/u_fetch/u_cache/data_wdata |
add wave -noupdate -expand -group Amber -group Decode -format Literal /tb/u_system/u_amber/u_fetch/i_iaddress_nxt |
add wave -noupdate -expand -group Amber -group Decode -format Literal -radix ascii /tb/u_system/u_amber/u_decode/xMODE |
add wave -noupdate -expand -group Amber -group Decode -format Literal -radix ascii /tb/u_system/u_amber/u_decode/xCONTROL_STATE |
add wave -noupdate -expand -group Amber -group Decode -format Literal /tb/u_system/u_amber/u_decode/mtrans_num_registers |
add wave -noupdate -expand -group Amber -group Decode -format Logic /tb/u_system/u_amber/u_decode/decode_iaccess_nxt |
add wave -noupdate -expand -group Amber -group Decode -format Literal /tb/u_system/u_amber/u_decode/iaddress_sel_nxt |
add wave -noupdate -expand -group Amber -group Decode -format Literal /tb/u_system/u_amber/u_decode/fetch_instruction_r |
add wave -noupdate -expand -group Amber -group Decode -format Logic /tb/u_system/u_amber/u_decode/pre_fetch_instruction_wen |
add wave -noupdate -expand -group Amber -group Decode -format Literal /tb/u_system/u_amber/u_decode/instruction |
add wave -noupdate -expand -group Amber -group Decode -format Logic /tb/u_system/u_amber/u_decode/instruction_valid |
add wave -noupdate -expand -group Amber -group Decode -format Logic /tb/u_system/u_amber/u_decode/instruction_execute |
add wave -noupdate -expand -group Amber -group Decode -format Logic /tb/u_system/u_amber/u_decode/saved_current_instruction_wen |
add wave -noupdate -expand -group Amber -group Decode -format Logic /tb/u_system/u_amber/u_decode/use_saved_current_instruction |
add wave -noupdate -expand -group Amber -group Decode -format Logic /tb/u_system/u_amber/u_decode/pc_wen_nxt |
add wave -noupdate -expand -group Amber -group Decode -format Logic /tb/u_system/u_amber/u_decode/write_pc |
add wave -noupdate -expand -group Amber -group Decode -format Literal -radix ascii /tb/u_system/u_amber/u_decode/xTYPE |
add wave -noupdate -expand -group Amber -group Decode -group Conflict -format Logic /tb/u_system/u_amber/u_decode/rd_conflict1 |
add wave -noupdate -expand -group Amber -group Decode -group Conflict -format Logic /tb/u_system/u_amber/u_decode/rd_conflict2 |
add wave -noupdate -expand -group Amber -group Decode -group Conflict -format Logic /tb/u_system/u_amber/u_decode/rm_conflict1 |
add wave -noupdate -expand -group Amber -group Decode -group Conflict -format Logic /tb/u_system/u_amber/u_decode/rm_conflict2 |
add wave -noupdate -expand -group Amber -group Decode -group Conflict -format Logic /tb/u_system/u_amber/u_decode/rn_conflict1 |
add wave -noupdate -expand -group Amber -group Decode -group Conflict -format Logic /tb/u_system/u_amber/u_decode/rn_conflict2 |
add wave -noupdate -expand -group Amber -group Decode -group Conflict -format Logic /tb/u_system/u_amber/u_decode/rs_conflict1 |
add wave -noupdate -expand -group Amber -group Decode -group Conflict -format Logic /tb/u_system/u_amber/u_decode/rs_conflict2 |
add wave -noupdate -expand -group Amber -group Decode -group Conflict -format Logic /tb/u_system/u_amber/u_decode/stm_conflict1a |
add wave -noupdate -expand -group Amber -group Decode -group Conflict -format Logic /tb/u_system/u_amber/u_decode/stm_conflict1b |
add wave -noupdate -expand -group Amber -group Decode -group Conflict -format Logic /tb/u_system/u_amber/u_decode/stm_conflict2a |
add wave -noupdate -expand -group Amber -group Decode -group Conflict -format Logic /tb/u_system/u_amber/u_decode/stm_conflict2b |
add wave -noupdate -expand -group Amber -group Decode -group Conflict -format Logic /tb/u_system/u_amber/u_decode/instruction_valid |
add wave -noupdate -expand -group Amber -group Decode -group Conflict -format Logic /tb/u_system/u_amber/u_decode/conflict1 |
add wave -noupdate -expand -group Amber -group Decode -group Conflict -format Logic /tb/u_system/u_amber/u_decode/conflict2 |
add wave -noupdate -expand -group Amber -group Decode -format Logic /tb/u_system/u_amber/u_decode/conflict |
add wave -noupdate -expand -group Amber -expand -group Decode -format Literal -radix ascii /tb/u_system/u_amber/u_decode/xMODE |
add wave -noupdate -expand -group Amber -expand -group Decode -format Literal -radix ascii /tb/u_system/u_amber/u_decode/xCONTROL_STATE |
add wave -noupdate -expand -group Amber -expand -group Decode -format Logic /tb/u_system/u_amber/u_decode/interrupt |
add wave -noupdate -expand -group Amber -expand -group Decode -format Literal /tb/u_system/u_amber/u_decode/mtrans_num_registers |
add wave -noupdate -expand -group Amber -expand -group Decode -format Logic /tb/u_system/u_amber/u_decode/pre_fetch_instruction_wen |
add wave -noupdate -expand -group Amber -expand -group Decode -format Literal /tb/u_system/u_amber/u_decode/instruction |
add wave -noupdate -expand -group Amber -expand -group Decode -format Logic /tb/u_system/u_amber/u_decode/instruction_valid |
add wave -noupdate -expand -group Amber -expand -group Decode -format Logic /tb/u_system/u_amber/u_decode/instruction_execute |
add wave -noupdate -expand -group Amber -expand -group Decode -format Logic /tb/u_system/u_amber/u_decode/saved_current_instruction_wen |
add wave -noupdate -expand -group Amber -expand -group Decode -format Logic /tb/u_system/u_amber/u_decode/use_saved_current_instruction |
add wave -noupdate -expand -group Amber -expand -group Decode -format Logic /tb/u_system/u_amber/u_decode/pc_wen_nxt |
add wave -noupdate -expand -group Amber -expand -group Decode -format Logic /tb/u_system/u_amber/u_decode/write_pc |
add wave -noupdate -expand -group Amber -expand -group Decode -expand -group Conflict -format Logic /tb/u_system/u_amber/u_decode/instruction_valid |
add wave -noupdate -expand -group Amber -group Execute -format Literal -radix ascii /tb/u_system/u_amber/u_decode/u_decompile/xINSTRUCTION_EXECUTE |
add wave -noupdate -expand -group Amber -group Execute -format Literal /tb/u_system/u_amber/u_execute/i_pc_sel |
add wave -noupdate -expand -group Amber -group Execute -expand -group Registers -format Literal /tb/u_system/u_amber/u_execute/u_register_bank/i_wb_read_data_rd |
add wave -noupdate -expand -group Amber -group Execute -expand -group Registers -format Logic /tb/u_system/u_amber/u_execute/u_register_bank/i_wb_read_data_valid |
add wave -noupdate -expand -group Amber -group Execute -expand -group Registers -format Literal /tb/u_system/u_amber/u_execute/u_register_bank/r0 |
add wave -noupdate -expand -group Amber -group Execute -expand -group Registers -format Literal /tb/u_system/u_amber/u_execute/u_register_bank/r1 |
add wave -noupdate -expand -group Amber -group Execute -expand -group Registers -format Literal /tb/u_system/u_amber/u_execute/u_register_bank/r2 |
add wave -noupdate -expand -group Amber -group Execute -expand -group Registers -format Literal /tb/u_system/u_amber/u_execute/u_register_bank/r3 |
add wave -noupdate -expand -group Amber -group Execute -expand -group Registers -format Logic {/tb/u_system/u_amber/u_execute/u_register_bank/read_data_wen[12]} |
add wave -noupdate -expand -group Amber -group Execute -expand -group Registers -format Logic {/tb/u_system/u_amber/u_execute/u_register_bank/reg_bank_wen_c[12]} |
add wave -noupdate -expand -group Amber -group Execute -expand -group Registers -format Literal /tb/u_system/u_amber/u_execute/u_register_bank/r12_out |
add wave -noupdate -expand -group Amber -group Execute -expand -group Registers -format Literal /tb/u_system/u_amber/u_execute/u_register_bank/r13_out |
add wave -noupdate -expand -group Amber -group Execute -expand -group Registers -format Literal /tb/u_system/u_amber/u_execute/u_register_bank/r14_out |
123,73 → 92,22
add wave -noupdate -expand -group Amber -group Execute -group internals -format Literal /tb/u_system/u_amber/u_execute/i_status_bits_sel |
add wave -noupdate -expand -group Amber -group Execute -group internals -format Literal /tb/u_system/u_amber/u_execute/i_condition |
add wave -noupdate -expand -group Amber -group Execute -group internals -format Logic /tb/u_system/u_amber/u_execute/execute |
add wave -noupdate -expand -group Amber -expand -group Memory -format Literal /tb/u_system/u_amber/u_mem/i_daddress |
add wave -noupdate -expand -group Amber -expand -group Memory -format Logic /tb/u_system/u_amber/u_mem/i_daddress_valid |
add wave -noupdate -expand -group Amber -expand -group Memory -format Logic /tb/u_system/u_amber/u_mem/i_write_enable |
add wave -noupdate -expand -group Amber -expand -group Memory -format Logic /tb/u_system/u_amber/u_mem/o_mem_stall |
add wave -noupdate -expand -group Amber -expand -group Memory -format Logic /tb/u_system/u_amber/u_mem/daddress_valid_p |
add wave -noupdate -expand -group Amber -expand -group Memory -format Logic /tb/u_system/u_amber/u_mem/o_mem_read_data_valid |
add wave -noupdate -expand -group Amber -expand -group Memory -format Logic /tb/u_system/u_amber/u_mem/uncached_wb_wait |
add wave -noupdate -expand -group Amber -expand -group Memory -group DCache -format Logic /tb/u_system/u_amber/u_mem/u_dcache/o_stall |
add wave -noupdate -expand -group Amber -expand -group Memory -group DCache -format Logic /tb/u_system/u_amber/u_mem/u_dcache/write_stall |
add wave -noupdate -expand -group Amber -expand -group Memory -group DCache -format Logic /tb/u_system/u_amber/u_mem/u_dcache/request_hold |
add wave -noupdate -expand -group Amber -expand -group Memory -group DCache -format Logic /tb/u_system/u_amber/u_mem/u_dcache/request_pulse |
add wave -noupdate -expand -group Amber -expand -group Memory -group DCache -format Logic /tb/u_system/u_amber/u_mem/u_dcache/request_r |
add wave -noupdate -expand -group Amber -expand -group Memory -group DCache -format Logic /tb/u_system/u_amber/u_mem/u_dcache/i_write_enable |
add wave -noupdate -expand -group Amber -expand -group Memory -group DCache -format Logic /tb/u_system/u_amber/u_mem/u_dcache/i_fetch_stall |
add wave -noupdate -expand -group Amber -expand -group Memory -group DCache -format Logic /tb/u_system/u_amber/u_mem/u_dcache/o_wb_req |
add wave -noupdate -expand -group Amber -expand -group Memory -group DCache -format Logic /tb/u_system/u_amber/u_mem/u_dcache/i_wb_ready |
add wave -noupdate -expand -group Amber -expand -group Memory -group DCache -format Logic /tb/u_system/u_amber/u_mem/u_dcache/wb_hit |
add wave -noupdate -expand -group Amber -expand -group Memory -group DCache -format Logic /tb/u_system/u_amber/u_mem/u_dcache/idle_hit |
add wave -noupdate -expand -group Amber -expand -group Memory -group DCache -format Logic /tb/u_system/u_amber/u_mem/u_dcache/read_stall |
add wave -noupdate -expand -group Amber -expand -group Memory -group DCache -format Literal -radix ascii /tb/u_system/u_amber/u_mem/u_dcache/xC_STATE |
add wave -noupdate -expand -group Amber -expand -group Memory -group DCache -format Logic /tb/u_system/u_amber/u_mem/u_dcache/consecutive_write |
add wave -noupdate -expand -group Amber -expand -group Memory -group DCache -format Literal /tb/u_system/u_amber/u_mem/u_dcache/miss_address |
add wave -noupdate -expand -group Amber -expand -group Memory -group DCache -format Logic /tb/u_system/u_amber/u_mem/u_dcache/read_miss |
add wave -noupdate -expand -group Amber -expand -group Memory -group DCache -format Logic /tb/u_system/u_amber/u_mem/u_dcache/write_hit |
add wave -noupdate -expand -group Amber -expand -group Memory -group DCache -format Logic /tb/u_system/u_amber/u_mem/u_dcache/write_miss |
add wave -noupdate -expand -group Amber -expand -group Memory -group DCache -format Logic /tb/u_system/u_amber/u_mem/u_dcache/consecutive_write |
add wave -noupdate -expand -group Amber -expand -group Memory -group DCache -format Literal -radix ascii /tb/u_system/u_amber/u_mem/u_dcache/xSOURCE_SEL |
add wave -noupdate -expand -group Amber -expand -group Wishbone -format Logic /tb/u_system/u_amber/u_wishbone/start_access |
add wave -noupdate -expand -group Amber -expand -group Wishbone -format Logic /tb/u_system/u_amber/u_wishbone/servicing_dcache_write_r |
add wave -noupdate -expand -group Amber -expand -group Wishbone -format Logic /tb/u_system/u_amber/u_wishbone/dcache_uncached_wreq_r |
add wave -noupdate -expand -group Amber -expand -group Wishbone -format Literal -radix ascii /tb/u_system/u_amber/u_wishbone/xWB_STATE |
add wave -noupdate -expand -group Amber -expand -group Wishbone -group ICache -format Logic /tb/u_system/u_amber/u_wishbone/i_icache_req |
add wave -noupdate -expand -group Amber -expand -group Wishbone -group ICache -format Logic /tb/u_system/u_amber/u_wishbone/i_icache_qword |
add wave -noupdate -expand -group Amber -expand -group Wishbone -group ICache -format Literal /tb/u_system/u_amber/u_wishbone/i_icache_address |
add wave -noupdate -expand -group Amber -expand -group Wishbone -group ICache -format Logic /tb/u_system/u_amber/u_fetch/i_iaddress_valid |
add wave -noupdate -expand -group Amber -expand -group Wishbone -group ICache -format Logic /tb/u_system/u_amber/u_wishbone/icache_read_req_c |
add wave -noupdate -expand -group Amber -expand -group Wishbone -group ICache -format Logic /tb/u_system/u_amber/u_wishbone/icache_read_req_r |
add wave -noupdate -expand -group Amber -expand -group Wishbone -group ICache -format Logic /tb/u_system/u_amber/u_wishbone/servicing_icache_r |
add wave -noupdate -expand -group Amber -expand -group Wishbone -group ICache -format Logic /tb/u_system/u_amber/u_wishbone/read_ack |
add wave -noupdate -expand -group Amber -expand -group Wishbone -group ICache -format Logic /tb/u_system/u_amber/u_wishbone/o_icache_ready |
add wave -noupdate -expand -group Amber -expand -group Wishbone -group ICache -format Literal /tb/u_system/u_amber/u_wishbone/o_icache_read_data |
add wave -noupdate -expand -group Amber -expand -group Wishbone -expand -group DCache -format Logic /tb/u_system/u_amber/u_wishbone/i_dcache_uncached_req |
add wave -noupdate -expand -group Amber -expand -group Wishbone -expand -group DCache -format Logic /tb/u_system/u_amber/u_wishbone/o_dcache_uncached_ready |
add wave -noupdate -expand -group Amber -expand -group Wishbone -expand -group DCache -format Logic /tb/u_system/u_amber/u_wishbone/i_dcache_cached_req |
add wave -noupdate -expand -group Amber -expand -group Wishbone -expand -group DCache -format Logic /tb/u_system/u_amber/u_wishbone/o_dcache_cached_ready |
add wave -noupdate -expand -group Amber -expand -group Wishbone -expand -group DCache -format Logic /tb/u_system/u_amber/u_wishbone/i_dcache_qword |
add wave -noupdate -expand -group Amber -expand -group Wishbone -expand -group DCache -format Logic /tb/u_system/u_amber/u_wishbone/i_dcache_write |
add wave -noupdate -expand -group Amber -expand -group Wishbone -expand -group DCache -format Literal /tb/u_system/u_amber/u_wishbone/i_dcache_address |
add wave -noupdate -expand -group Amber -expand -group Wishbone -expand -group DCache -format Literal /tb/u_system/u_amber/u_wishbone/o_dcache_read_data |
add wave -noupdate -expand -group Amber -expand -group Wishbone -expand -group {WB Bus} -format Logic /tb/u_system/u_amber/o_wb_cyc |
add wave -noupdate -expand -group Amber -expand -group Wishbone -expand -group {WB Bus} -format Literal /tb/u_system/u_amber/u_wishbone/o_wb_adr |
add wave -noupdate -expand -group Amber -expand -group Wishbone -expand -group {WB Bus} -format Logic /tb/u_system/u_amber/o_wb_stb |
add wave -noupdate -expand -group Amber -expand -group Wishbone -expand -group {WB Bus} -format Logic /tb/u_system/u_amber/i_wb_ack |
add wave -noupdate -expand -group Amber -expand -group Wishbone -expand -group {WB Bus} -format Literal /tb/u_system/u_amber/o_wb_dat |
add wave -noupdate -expand -group Amber -expand -group Wishbone -expand -group {WB Bus} -format Literal /tb/u_system/u_amber/o_wb_sel |
add wave -noupdate -expand -group Amber -expand -group Wishbone -expand -group {WB Bus} -format Logic /tb/u_system/u_amber/o_wb_we |
add wave -noupdate -expand -group Amber -expand -group Wishbone -expand -group {WB Bus} -format Literal /tb/u_system/u_amber/i_wb_dat |
add wave -noupdate -expand -group Amber -expand -group Wishbone -expand -group {WB Bus} -format Logic /tb/u_system/u_amber/i_wb_err |
add wave -noupdate -expand -group Amber -group Wishbone -expand -group {WB Bus} -format Logic /tb/u_system/u_amber/o_wb_cyc |
add wave -noupdate -expand -group Amber -group Wishbone -expand -group {WB Bus} -format Logic /tb/u_system/u_amber/o_wb_stb |
add wave -noupdate -expand -group Amber -group Wishbone -expand -group {WB Bus} -format Logic /tb/u_system/u_amber/i_wb_ack |
add wave -noupdate -expand -group Amber -group Wishbone -expand -group {WB Bus} -format Literal /tb/u_system/u_amber/o_wb_dat |
add wave -noupdate -expand -group Amber -group Wishbone -expand -group {WB Bus} -format Literal /tb/u_system/u_amber/o_wb_sel |
add wave -noupdate -expand -group Amber -group Wishbone -expand -group {WB Bus} -format Logic /tb/u_system/u_amber/o_wb_we |
add wave -noupdate -expand -group Amber -group Wishbone -expand -group {WB Bus} -format Literal /tb/u_system/u_amber/i_wb_dat |
add wave -noupdate -expand -group Amber -group Wishbone -expand -group {WB Bus} -format Logic /tb/u_system/u_amber/i_wb_err |
add wave -noupdate -expand -group Amber -group Co-Processor -format Literal /tb/u_system/u_amber/u_coprocessor/fault_address |
add wave -noupdate -expand -group Amber -group Co-Processor -format Literal /tb/u_system/u_amber/u_coprocessor/fault_status |
add wave -noupdate -format Logic /tb/u_system/u_amber/u_wishbone/dcache_cached_wreq_r |
add wave -noupdate -format Logic /tb/u_system/u_amber/u_wishbone/dcache_cached_wready |
add wave -noupdate -format Logic /tb/u_system/u_amber/u_wishbone/dcache_cached_rreq_in |
add wave -noupdate -format Logic /tb/u_system/u_amber/u_wishbone/dcache_cached_wreq_in |
add wave -noupdate -format Logic /tb/u_system/u_amber/u_wishbone/dcache_cached_wreq_c |
add wave -noupdate -format Literal /tb/u_system/u_amber/u_execute/pc |
add wave -noupdate -format Literal /tb/u_system/u_amber/u_execute/u_register_bank/r14_irq |
add wave -noupdate -format Literal /tb/u_system/u_amber/u_execute/i_pc_sel |
add wave -noupdate -format Logic /tb/u_system/u_amber/u_execute/pc_wen |
TreeUpdate [SetDefaultTree] |
WaveRestoreCursors {{Cursor 1} {10765720 ps} 0} {{Cursor 3} {10386717250 ps} 0} |
WaveRestoreCursors {{Cursor 1} {44481286 ps} 0} {{Cursor 3} {10386717250 ps} 0} |
configure wave -namecolwidth 279 |
configure wave -valuecolwidth 174 |
configure wave -justifyvalue left |
204,4 → 122,4
configure wave -timeline 0 |
configure wave -timelineunits ns |
update |
WaveRestoreZoom {10467540 ps} {11166660 ps} |
WaveRestoreZoom {57117684 ps} {57628017 ps} |
amber/trunk/hw/sim
Property changes :
Modified: svn:ignore
## -1,15 +1,17 ##
-work
+amber.dis
+getseg
+gtkwave.sav
+jumps
+*.log
+modelsim.ini
+prepre_processed.v
+p_temp*.txt
run
-amber.dis
-vsim.wlf
+sim.vcd
transcript
-*.log
veritak_command.txt
-p_temp*.txt
-jumps
+vsim.wlf
*.vtakdisk
*.vtakprj
-prepre_processed.v
*.vtakwave
-getseg
-modelsim.ini
+work