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Rev 16 → Rev 17

/trunk/bench/verilog/can_testbench.v
45,6 → 45,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.11 2003/01/14 12:19:29 mohor
// rx_fifo is now working.
//
// Revision 1.10 2003/01/10 17:51:28 mohor
// Temporary version (backup).
//
145,35 → 148,35
wait(start_tb);
 
// Set bus timing register 0
write_register(8'h6, {`CAN_TIMING0_SJW, `CAN_TIMING0_BRP});
write_register(8'd6, {`CAN_TIMING0_SJW, `CAN_TIMING0_BRP});
 
// Set bus timing register 1
write_register(8'h7, {`CAN_TIMING1_SAM, `CAN_TIMING1_TSEG2, `CAN_TIMING1_TSEG1});
write_register(8'd7, {`CAN_TIMING1_SAM, `CAN_TIMING1_TSEG2, `CAN_TIMING1_TSEG1});
 
 
 
// Set Clock Divider register
write_register(8'h31, {`CAN_CLOCK_DIVIDER_MODE, 7'h0}); // Setting the normal mode (not extended)
write_register(8'd31, {`CAN_CLOCK_DIVIDER_MODE, 7'h0}); // Setting the normal mode (not extended)
// Set Acceptance Code and Acceptance Mask registers (their address differs for basic and extended mode
if(`CAN_CLOCK_DIVIDER_MODE) // Extended mode
begin
// Set Acceptance Code and Acceptance Mask registers
write_register(8'h16, 8'ha6); // acceptance code 0
write_register(8'h17, 8'hb0); // acceptance code 1
write_register(8'h18, 8'h12); // acceptance code 2
write_register(8'h19, 8'h34); // acceptance code 3
write_register(8'h20, 8'h0); // acceptance mask 0
write_register(8'h21, 8'h0); // acceptance mask 1
write_register(8'h22, 8'h0); // acceptance mask 2
write_register(8'h23, 8'h0); // acceptance mask 3
write_register(8'd16, 8'ha6); // acceptance code 0
write_register(8'd17, 8'hb0); // acceptance code 1
write_register(8'd18, 8'h12); // acceptance code 2
write_register(8'd19, 8'h34); // acceptance code 3
write_register(8'd20, 8'h0); // acceptance mask 0
write_register(8'd21, 8'h0); // acceptance mask 1
write_register(8'd22, 8'h0); // acceptance mask 2
write_register(8'd23, 8'h0); // acceptance mask 3
end
else
begin
// Set Acceptance Code and Acceptance Mask registers
// write_register(8'h4, 8'ha6); // acceptance code
write_register(8'h4, 8'h08); // acceptance code
write_register(8'h5, 8'h00); // acceptance mask
// write_register(8'd4, 8'ha6); // acceptance code
write_register(8'd4, 8'h08); // acceptance code
write_register(8'd5, 8'h00); // acceptance mask
end
#10;
180,7 → 183,7
repeat (1000) @ (posedge clk);
// Switch-off reset mode
write_register(8'h0, {7'h0, ~(`CAN_MODE_RESET)});
write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)});
 
repeat (BRP) @ (posedge clk); // At least BRP clocks needed before bus goes to dominant level. Otherwise 1 quant difference is possible
// This difference is resynchronized later.
413,7 → 416,7
cs = 1;
rw = 1;
@ (posedge clk);
$display("(%0t) Reading register [0x%0x] = 0x%0x", $time, addr, data_out);
$display("(%0t) Reading register [%0d] = 0x%0x", $time, addr, data_out);
#1;
addr = 'hz;
cs = 0;
448,7 → 451,7
begin
if(`CAN_CLOCK_DIVIDER_MODE) // Extended mode
begin
for (i=8'h16; i<=8'h28; i=i+1)
for (i=8'd16; i<=8'd28; i=i+1)
read_register(i);
if (can_testbench.i_can_top.i_can_bsp.i_can_fifo.overrun_info[can_testbench.i_can_top.i_can_bsp.i_can_fifo.rd_info_pointer])
$display("\nWARNING: This packet was received with overrun.");
455,7 → 458,7
end
else
begin
for (i=8'h20; i<=8'h29; i=i+1)
for (i=8'd20; i<=8'd29; i=i+1)
read_register(i);
if (can_testbench.i_can_top.i_can_bsp.i_can_fifo.overrun_info[can_testbench.i_can_top.i_can_bsp.i_can_fifo.rd_info_pointer])
$display("\nWARNING: This packet was received with overrun.");
466,7 → 469,7
 
task release_rx_buffer;
begin
write_register(8'h1, 8'h4);
write_register(8'd1, 8'h4);
$display("(%0t) Rx buffer released.", $time);
repeat (2) @ (posedge clk); // Time to decrement all the counters
end
527,7 → 530,6
integer stuff_cnt;
reg [117:0] data;
reg previous_bit;
reg xxx;
reg stuff;
begin
 
564,9 → 566,6
 
for (cnt=0; cnt<=total_bits; cnt=cnt+1)
begin
xxx = data[pointer];
if (stuff_cnt == 5)
begin
stuff_cnt = 1;
/trunk/rtl/verilog/can_top.v
45,6 → 45,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7 2003/01/10 17:51:34 mohor
// Temporary version (backup).
//
// Revision 1.6 2003/01/09 21:54:45 mohor
// rx fifo added. Not 100 % verified, yet.
//
142,6 → 145,21
wire [7:0] acceptance_mask_3;
/* End: This section is for EXTENDED mode */
 
/* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */
wire [7:0] tx_data_0;
wire [7:0] tx_data_1;
wire [7:0] tx_data_2;
wire [7:0] tx_data_3;
wire [7:0] tx_data_4;
wire [7:0] tx_data_5;
wire [7:0] tx_data_6;
wire [7:0] tx_data_7;
wire [7:0] tx_data_8;
wire [7:0] tx_data_9;
wire [7:0] tx_data_10;
wire [7:0] tx_data_11;
wire [7:0] tx_data_12;
/* End: Tx data registers */
 
 
/* Connecting can_registers module */
200,14 → 218,30
/* Acceptance mask register */
.acceptance_mask_1(acceptance_mask_1),
.acceptance_mask_2(acceptance_mask_2),
.acceptance_mask_3(acceptance_mask_3)
.acceptance_mask_3(acceptance_mask_3),
/* End: This section is for EXTENDED mode */
 
/* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */
.tx_data_0(tx_data_0),
.tx_data_1(tx_data_1),
.tx_data_2(tx_data_2),
.tx_data_3(tx_data_3),
.tx_data_4(tx_data_4),
.tx_data_5(tx_data_5),
.tx_data_6(tx_data_6),
.tx_data_7(tx_data_7),
.tx_data_8(tx_data_8),
.tx_data_9(tx_data_9),
.tx_data_10(tx_data_10),
.tx_data_11(tx_data_11),
.tx_data_12(tx_data_12)
/* End: Tx data registers */
 
 
 
 
 
 
);
 
 
317,7 → 351,7
// Multiplexing data_out from registers and rx fifo
always @ (extended_mode or addr)
begin
if (extended_mode & ((addr >= 8'h16) && (addr <= 8'h28)) | (~extended_mode) & ((addr >= 8'h20) && (addr <= 8'h29)))
if (extended_mode & (~reset_mode) & ((addr >= 8'd16) && (addr <= 8'd28)) | (~extended_mode) & ((addr >= 8'd20) && (addr <= 8'd29)))
data_out_fifo_selected <= 1'b1;
else
data_out_fifo_selected <= 1'b0;
/trunk/rtl/verilog/can_fifo.v
45,6 → 45,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4 2003/01/14 12:19:35 mohor
// rx_fifo is now working.
//
// Revision 1.3 2003/01/09 21:54:45 mohor
// rx fifo added. Not 100 % verified, yet.
//
250,11 → 253,11
begin
if (extended_mode) // extended mode
begin
read_address <= rd_pointer + (addr - 8'h16);
read_address <= rd_pointer + (addr - 8'd16);
end
else // normal mode
begin
read_address <= rd_pointer + (addr - 8'h20);
read_address <= rd_pointer + (addr - 8'd20);
end
end
 
/trunk/rtl/verilog/can_registers.v
45,6 → 45,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7 2003/01/14 12:19:35 mohor
// rx_fifo is now working.
//
// Revision 1.6 2003/01/10 17:51:34 mohor
// Temporary version (backup).
//
128,9 → 131,24
/* Acceptance mask register */
acceptance_mask_1,
acceptance_mask_2,
acceptance_mask_3
acceptance_mask_3,
/* End: This section is for EXTENDED mode */
/* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */
tx_data_0,
tx_data_1,
tx_data_2,
tx_data_3,
tx_data_4,
tx_data_5,
tx_data_6,
tx_data_7,
tx_data_8,
tx_data_9,
tx_data_10,
tx_data_11,
tx_data_12
/* End: Tx data registers */
 
202,32 → 220,61
 
/* End: This section is for EXTENDED mode */
 
/* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */
output [7:0] tx_data_0;
output [7:0] tx_data_1;
output [7:0] tx_data_2;
output [7:0] tx_data_3;
output [7:0] tx_data_4;
output [7:0] tx_data_5;
output [7:0] tx_data_6;
output [7:0] tx_data_7;
output [7:0] tx_data_8;
output [7:0] tx_data_9;
output [7:0] tx_data_10;
output [7:0] tx_data_11;
output [7:0] tx_data_12;
/* End: Tx data registers */
 
 
 
 
wire we_mode = cs & (~rw) & (addr == 8'h0);
wire we_command = cs & (~rw) & (addr == 8'h1);
wire we_bus_timing_0 = cs & (~rw) & (addr == 8'h6) & reset_mode;
wire we_bus_timing_1 = cs & (~rw) & (addr == 8'h7) & reset_mode;
wire we_clock_divider_hi = cs & (~rw) & (addr == 8'h31) & reset_mode;
wire we_clock_divider_low = cs & (~rw) & (addr == 8'h31);
wire we_mode = cs & (~rw) & (addr == 8'd0);
wire we_command = cs & (~rw) & (addr == 8'd1);
wire we_bus_timing_0 = cs & (~rw) & (addr == 8'd6) & reset_mode;
wire we_bus_timing_1 = cs & (~rw) & (addr == 8'd7) & reset_mode;
wire we_clock_divider_low = cs & (~rw) & (addr == 8'd31);
wire we_clock_divider_hi = we_clock_divider_low & reset_mode;
 
wire read = cs & rw;
 
 
/* This section is for BASIC and EXTENDED mode */
wire we_acceptance_code_0 = cs & (~rw) & reset_mode & ((~extended_mode) & (addr == 8'h4) | extended_mode & (addr == 8'h16));
wire we_acceptance_mask_0 = cs & (~rw) & reset_mode & ((~extended_mode) & (addr == 8'h5) | extended_mode & (addr == 8'h20));
wire we_acceptance_code_0 = cs & (~rw) & reset_mode & ((~extended_mode) & (addr == 8'd4) | extended_mode & (addr == 8'd16));
wire we_acceptance_mask_0 = cs & (~rw) & reset_mode & ((~extended_mode) & (addr == 8'd5) | extended_mode & (addr == 8'd20));
wire we_tx_data_0 = cs & (~rw) & (~reset_mode) & ((~extended_mode) & (addr == 8'd10) | extended_mode & (addr == 8'd16));
wire we_tx_data_1 = cs & (~rw) & (~reset_mode) & ((~extended_mode) & (addr == 8'd11) | extended_mode & (addr == 8'd17));
wire we_tx_data_2 = cs & (~rw) & (~reset_mode) & ((~extended_mode) & (addr == 8'd12) | extended_mode & (addr == 8'd18));
wire we_tx_data_3 = cs & (~rw) & (~reset_mode) & ((~extended_mode) & (addr == 8'd13) | extended_mode & (addr == 8'd19));
wire we_tx_data_4 = cs & (~rw) & (~reset_mode) & ((~extended_mode) & (addr == 8'd14) | extended_mode & (addr == 8'd20));
wire we_tx_data_5 = cs & (~rw) & (~reset_mode) & ((~extended_mode) & (addr == 8'd15) | extended_mode & (addr == 8'd21));
wire we_tx_data_6 = cs & (~rw) & (~reset_mode) & ((~extended_mode) & (addr == 8'd16) | extended_mode & (addr == 8'd22));
wire we_tx_data_7 = cs & (~rw) & (~reset_mode) & ((~extended_mode) & (addr == 8'd17) | extended_mode & (addr == 8'd23));
wire we_tx_data_8 = cs & (~rw) & (~reset_mode) & ((~extended_mode) & (addr == 8'd18) | extended_mode & (addr == 8'd24));
wire we_tx_data_9 = cs & (~rw) & (~reset_mode) & ((~extended_mode) & (addr == 8'd19) | extended_mode & (addr == 8'd25));
wire we_tx_data_10 = cs & (~rw) & (~reset_mode) & ( extended_mode & (addr == 8'd26));
wire we_tx_data_11 = cs & (~rw) & (~reset_mode) & ( extended_mode & (addr == 8'd27));
wire we_tx_data_12 = cs & (~rw) & (~reset_mode) & ( extended_mode & (addr == 8'd28));
/* End: This section is for BASIC and EXTENDED mode */
 
 
/* This section is for EXTENDED mode */
wire we_acceptance_code_1 = cs & (~rw) & (addr == 8'h17) & reset_mode & extended_mode;
wire we_acceptance_code_2 = cs & (~rw) & (addr == 8'h18) & reset_mode & extended_mode;
wire we_acceptance_code_3 = cs & (~rw) & (addr == 8'h19) & reset_mode & extended_mode;
wire we_acceptance_mask_1 = cs & (~rw) & (addr == 8'h21) & reset_mode & extended_mode;
wire we_acceptance_mask_2 = cs & (~rw) & (addr == 8'h22) & reset_mode & extended_mode;
wire we_acceptance_mask_3 = cs & (~rw) & (addr == 8'h23) & reset_mode & extended_mode;
wire we_acceptance_code_1 = cs & (~rw) & (addr == 8'd17) & reset_mode & extended_mode;
wire we_acceptance_code_2 = cs & (~rw) & (addr == 8'd18) & reset_mode & extended_mode;
wire we_acceptance_code_3 = cs & (~rw) & (addr == 8'd19) & reset_mode & extended_mode;
wire we_acceptance_mask_1 = cs & (~rw) & (addr == 8'd21) & reset_mode & extended_mode;
wire we_acceptance_mask_2 = cs & (~rw) & (addr == 8'd22) & reset_mode & extended_mode;
wire we_acceptance_mask_3 = cs & (~rw) & (addr == 8'd23) & reset_mode & extended_mode;
/* End: This section is for EXTENDED mode */
 
 
349,12 → 396,143
.we(we_acceptance_mask_0),
.clk(clk)
);
/* End: Acceptance code register */
 
/* End: Acceptance mask register */
/* End: This section is for BASIC and EXTENDED mode */
 
 
/* Tx data 0 register. */
can_register #(8) TX_DATA_REG0
( .data_in(data_in),
.data_out(tx_data_0),
.we(we_tx_data_0),
.clk(clk)
);
/* End: Tx data 0 register. */
 
 
/* Tx data 1 register. */
can_register #(8) TX_DATA_REG1
( .data_in(data_in),
.data_out(tx_data_1),
.we(we_tx_data_1),
.clk(clk)
);
/* End: Tx data 1 register. */
 
 
/* Tx data 2 register. */
can_register #(8) TX_DATA_REG2
( .data_in(data_in),
.data_out(tx_data_2),
.we(we_tx_data_2),
.clk(clk)
);
/* End: Tx data 2 register. */
 
 
/* Tx data 3 register. */
can_register #(8) TX_DATA_REG3
( .data_in(data_in),
.data_out(tx_data_3),
.we(we_tx_data_3),
.clk(clk)
);
/* End: Tx data 3 register. */
 
 
/* Tx data 4 register. */
can_register #(8) TX_DATA_REG4
( .data_in(data_in),
.data_out(tx_data_4),
.we(we_tx_data_4),
.clk(clk)
);
/* End: Tx data 4 register. */
 
 
/* Tx data 5 register. */
can_register #(8) TX_DATA_REG5
( .data_in(data_in),
.data_out(tx_data_5),
.we(we_tx_data_5),
.clk(clk)
);
/* End: Tx data 5 register. */
 
 
/* Tx data 6 register. */
can_register #(8) TX_DATA_REG6
( .data_in(data_in),
.data_out(tx_data_6),
.we(we_tx_data_6),
.clk(clk)
);
/* End: Tx data 6 register. */
 
 
/* Tx data 7 register. */
can_register #(8) TX_DATA_REG7
( .data_in(data_in),
.data_out(tx_data_7),
.we(we_tx_data_7),
.clk(clk)
);
/* End: Tx data 7 register. */
 
 
/* Tx data 8 register. */
can_register #(8) TX_DATA_REG8
( .data_in(data_in),
.data_out(tx_data_8),
.we(we_tx_data_8),
.clk(clk)
);
/* End: Tx data 8 register. */
 
 
/* Tx data 9 register. */
can_register #(8) TX_DATA_REG9
( .data_in(data_in),
.data_out(tx_data_9),
.we(we_tx_data_9),
.clk(clk)
);
/* End: Tx data 9 register. */
 
 
/* Tx data 10 register. */
can_register #(8) TX_DATA_REG10
( .data_in(data_in),
.data_out(tx_data_10),
.we(we_tx_data_10),
.clk(clk)
);
/* End: Tx data 10 register. */
 
 
/* Tx data 11 register. */
can_register #(8) TX_DATA_REG11
( .data_in(data_in),
.data_out(tx_data_11),
.we(we_tx_data_11),
.clk(clk)
);
/* End: Tx data 11 register. */
 
 
/* Tx data 12 register. */
can_register #(8) TX_DATA_REG12
( .data_in(data_in),
.data_out(tx_data_12),
.we(we_tx_data_12),
.clk(clk)
);
/* End: Tx data 12 register. */
 
 
 
 
 
/* This section is for EXTENDED mode */
 
/* Acceptance code register 1 */
427,10 → 605,7
 
 
 
wire [7:0] fix_me = 8'h0; // This wire is used in many exuations that are not final, yet. Fix them !!!
 
 
 
// Reading data from registers
always @ ( addr or read or extended_mode or mode or bus_timing_0 or bus_timing_1 or clock_divider
)
440,20 → 615,25
if (extended_mode) // EXTENDED mode (Different register map depends on mode)
begin
case(addr)
8'h0 : data_out <= mode;
8'h1 : data_out <= 8'h0;
8'h6 : data_out <= bus_timing_0;
8'h7 : data_out <= bus_timing_1;
8'h16 : data_out <= reset_mode? acceptance_code_0 : fix_me; // + fix TX identifiers
8'h17 : data_out <= reset_mode? acceptance_code_1 : fix_me;
8'h18 : data_out <= reset_mode? acceptance_code_2 : fix_me;
8'h19 : data_out <= reset_mode? acceptance_code_3 : fix_me;
8'h20 : data_out <= reset_mode? acceptance_mask_0 : fix_me;
8'h21 : data_out <= reset_mode? acceptance_mask_1 : fix_me;
8'h22 : data_out <= reset_mode? acceptance_mask_2 : fix_me;
8'h23 : data_out <= reset_mode? acceptance_mask_3 : fix_me;
8'd0 : data_out <= mode;
8'd1 : data_out <= 8'h0;
8'd6 : data_out <= bus_timing_0;
8'd7 : data_out <= bus_timing_1;
8'd16 : data_out <= acceptance_code_0;
8'd17 : data_out <= acceptance_code_1;
8'd18 : data_out <= acceptance_code_2;
8'd19 : data_out <= acceptance_code_3;
8'd20 : data_out <= acceptance_mask_0;
8'd21 : data_out <= acceptance_mask_1;
8'd22 : data_out <= acceptance_mask_2;
8'd23 : data_out <= acceptance_mask_3;
8'd24 : data_out <= 8'h0;
8'd25 : data_out <= 8'h0;
8'd26 : data_out <= 8'h0;
8'd27 : data_out <= 8'h0;
8'd28 : data_out <= 8'h0;
8'h31 : data_out <= {clock_divider[7:5], 1'b0, clock_divider[3:0]};
8'd31 : data_out <= {clock_divider[7:5], 1'b0, clock_divider[3:0]};
default: data_out <= 8'h0;
endcase
461,15 → 641,24
else // BASIC mode
begin
case(addr)
8'h0 : data_out <= mode;
8'h1 : data_out <= 8'hff;
8'h4 : data_out <= reset_mode? acceptance_code_0 : 8'hff;
8'h5 : data_out <= reset_mode? acceptance_mask_0 : 8'hff;
8'h6 : data_out <= reset_mode? bus_timing_0 : 8'hff;
8'h7 : data_out <= reset_mode? bus_timing_1 : 8'hff;
8'd0 : data_out <= mode;
8'd1 : data_out <= 8'hff;
8'd4 : data_out <= reset_mode? acceptance_code_0 : 8'hff;
8'd5 : data_out <= reset_mode? acceptance_mask_0 : 8'hff;
8'd6 : data_out <= reset_mode? bus_timing_0 : 8'hff;
8'd7 : data_out <= reset_mode? bus_timing_1 : 8'hff;
8'd10 : data_out <= reset_mode? 8'hff : tx_data_0;
8'd11 : data_out <= reset_mode? 8'hff : tx_data_0;
8'd12 : data_out <= reset_mode? 8'hff : tx_data_0;
8'd13 : data_out <= reset_mode? 8'hff : tx_data_0;
8'd14 : data_out <= reset_mode? 8'hff : tx_data_0;
8'd15 : data_out <= reset_mode? 8'hff : tx_data_0;
8'd16 : data_out <= reset_mode? 8'hff : tx_data_0;
8'd17 : data_out <= reset_mode? 8'hff : tx_data_0;
8'd18 : data_out <= reset_mode? 8'hff : tx_data_0;
8'd19 : data_out <= reset_mode? 8'hff : tx_data_0;
8'd31 : data_out <= {clock_divider[7:5], 1'b0, clock_divider[3:0]};
8'h31 : data_out <= {clock_divider[7:5], 1'b0, clock_divider[3:0]};
default: data_out <= 8'h0;
endcase
end

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