URL
https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk
Subversion Repositories dbg_interface
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 16 to Rev 17
- ↔ Reverse comparison
Rev 16 → Rev 17
/trunk/bench/verilog/dbg_tb.v
45,6 → 45,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.8 2001/10/17 10:39:17 mohor |
// bs_chain_o added. |
// |
// Revision 1.7 2001/10/16 10:10:18 mohor |
// Signal names changed to lowercase. |
// |
79,7 → 82,7
// |
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`include "dbg_timescale.v" |
`include "timescale.v" |
`include "dbg_defines.v" |
`include "dbg_tb_defines.v" |
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/trunk/rtl/verilog/dbg_timescale.v
File deleted
/trunk/rtl/verilog/dbg_sync_clk1_clk2.v
41,12 → 41,15
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.1.1.1 2001/09/13 13:49:19 mohor |
// Initial official release. |
// |
// |
// |
// |
// |
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`include "dbg_timescale.v" |
`include "timescale.v" |
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// FF in clock domain 1 is being set by a signal from the clock domain 2 |
module dbg_sync_clk1_clk2 (clk1, clk2, reset1, reset2, set2, sync_out); |
/trunk/rtl/verilog/dbg_top.v
45,6 → 45,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.8 2001/10/17 10:39:03 mohor |
// bs_chain_o added. |
// |
// Revision 1.7 2001/10/16 10:09:56 mohor |
// Signal names changed to lowercase. |
// |
79,7 → 82,7
// |
// |
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`include "dbg_timescale.v" |
`include "timescale.v" |
`include "dbg_defines.v" |
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// Top module |
/trunk/rtl/verilog/dbg_crc8_d1.v
45,6 → 45,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2001/09/20 10:11:25 mohor |
// Working version. Few bugs fixed, comments added. |
// |
// Revision 1.1.1.1 2001/09/13 13:49:19 mohor |
// Initial official release. |
// |
80,7 → 83,7
// http://www.easics.com |
/////////////////////////////////////////////////////////////////////// |
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`include "dbg_timescale.v" |
`include "timescale.v" |
`include "dbg_defines.v" |
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/trunk/rtl/verilog/dbg_register.v
45,12 → 45,15
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.1.1.1 2001/09/13 13:49:19 mohor |
// Initial official release. |
// |
// |
// |
// |
// |
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`include "dbg_timescale.v" |
`include "timescale.v" |
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module dbg_register(DataIn, DataOut, Write, Clk, Reset, Default); |
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/trunk/rtl/verilog/dbg_registers.v
45,6 → 45,10
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2001/10/15 09:55:47 mohor |
// Wishbone interface added, few fixes for better performance, |
// hooks for boundary scan testing added. |
// |
// Revision 1.2 2001/09/18 14:13:47 mohor |
// Trace fixed. Some registers changed, trace simplified. |
// |
62,7 → 66,7
// |
// |
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`include "dbg_timescale.v" |
`include "timescale.v" |
`include "dbg_defines.v" |
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module dbg_registers(DataIn, DataOut, Address, RW, Access, Clk, Bp, Reset, |
/trunk/rtl/verilog/timescale.v
0,0 → 1,57
////////////////////////////////////////////////////////////////////// |
//// //// |
//// timescale.v //// |
//// //// |
//// //// |
//// This file is part of the SoC/OpenRISC Development Interface //// |
//// http://www.opencores.org/cores/DebugInterface/ //// |
//// //// |
//// //// |
//// Author(s): //// |
//// Igor Mohor //// |
//// igorm@opencores.org //// |
//// //// |
//// //// |
//// All additional information is avaliable in the README.txt //// |
//// file. //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000,2001 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.1.1.1 2001/09/13 13:49:19 mohor |
// Initial official release. |
// |
// |
// |
// |
// |
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`timescale 1ns / 1ns |
/trunk/rtl/verilog/dbg_trace.v
45,6 → 45,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.4 2001/09/20 10:11:25 mohor |
// Working version. Few bugs fixed, comments added. |
// |
// Revision 1.3 2001/09/19 11:55:13 mohor |
// Asynchronous set/reset not used in trace any more. |
// |
66,7 → 69,7
// |
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`include "dbg_timescale.v" |
`include "timescale.v" |
`include "dbg_defines.v" |
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// module Trace |
/trunk/sim/rtl_sim/run/do.do
3,7 → 3,7
vlog -reportprogress 30 -work work {C:/cvsroot/dbg_interface/rtl/verilog/dbg_register.v} |
vlog -reportprogress 30 -work work {C:/cvsroot/dbg_interface/rtl/verilog/dbg_registers.v} |
vlog -reportprogress 30 -work work {C:/cvsroot/dbg_interface/rtl/verilog/dbg_sync_clk1_clk2.v} |
vlog -reportprogress 30 -work work {C:/cvsroot/dbg_interface/rtl/verilog/dbg_timescale.v} |
vlog -reportprogress 30 -work work {C:/cvsroot/dbg_interface/rtl/verilog/timescale.v} |
vlog -reportprogress 30 -work work {C:/cvsroot/dbg_interface/rtl/verilog/dbg_top.v} |
vlog -reportprogress 30 -work work {C:/cvsroot/dbg_interface/rtl/verilog/dbg_trace.v} |
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