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URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

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Rev 16 → Rev 17

/neorv32/trunk/docs/NEORV32.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/neorv32/trunk/rtl/core/neorv32_cpu_bus.vhd
413,18 → 413,20
-- Physical Memory Protection (PMP) -------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- compute address masks --
pmp_masks: process(pmp_addr_i)
pmp_masks: process(clk_i)
begin
for r in 0 to PMP_NUM_REGIONS-1 loop -- iterate over all regions
pmp.addr_mask(r) <= (others => '0'); -- default
for i in PMP_GRANULARITY+1 to 33 loop
if (i = PMP_GRANULARITY+1) then
pmp.addr_mask(r)(i) <= '0';
else -- current bit = not AND(all previous bits)
pmp.addr_mask(r)(i) <= not (and_all_f(pmp_addr_i(r)(i-1 downto PMP_GRANULARITY)));
end if;
end loop; -- i
end loop; -- r
if rising_edge(clk_i) then -- address configuration (not the actual address check!) has a latency of +1 cycles
for r in 0 to PMP_NUM_REGIONS-1 loop -- iterate over all regions
pmp.addr_mask(r) <= (others => '0'); -- default
for i in PMP_GRANULARITY+1 to 33 loop
if (i = PMP_GRANULARITY+1) then
pmp.addr_mask(r)(i) <= '0';
else -- current bit = not AND(all previous bits)
pmp.addr_mask(r)(i) <= not (and_all_f(pmp_addr_i(r)(i-1 downto PMP_GRANULARITY)));
end if;
end loop; -- i
end loop; -- r
end if;
end process pmp_masks;
 
 
/neorv32/trunk/rtl/core/neorv32_package.vhd
41,7 → 41,7
-- Architecture Constants -----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
constant data_width_c : natural := 32; -- data width - FIXED!
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01030501"; -- no touchy!
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01030502"; -- no touchy!
constant pmp_max_r_c : natural := 8; -- max PMP regions
 
-- Helper Functions -----------------------------------------------------------------------
/neorv32/trunk/sw/example/cpu_test/main.c
169,8 → 169,21
}
#endif
 
// enable interrupt sources
install_err = neorv32_cpu_irq_enable(CPU_MIE_MSIE); // activate software interrupt
install_err += neorv32_cpu_irq_enable(CPU_MIE_MTIE); // activate timer interrupt
install_err += neorv32_cpu_irq_enable(CPU_MIE_MEIE); // activate external interrupt
install_err += neorv32_cpu_irq_enable(CPU_MIE_FIRQ0E);// activate fast interrupt channel 0
install_err += neorv32_cpu_irq_enable(CPU_MIE_FIRQ1E);// activate fast interrupt channel 1
install_err += neorv32_cpu_irq_enable(CPU_MIE_FIRQ2E);// activate fast interrupt channel 2
install_err += neorv32_cpu_irq_enable(CPU_MIE_FIRQ3E);// activate fast interrupt channel 3
 
if (install_err) {
neorv32_uart_printf("IRQ enable error (%i)!\n", install_err);
return 0;
}
 
 
// enable global interrupts
neorv32_cpu_eint();
 
300,13 → 313,11
 
// ----------------------------------------------------------
// Test fence instructions - make sure CPU does not crash here and throws no exception
// a more complex test is provided by the RISC-V compliance test
// ----------------------------------------------------------
exception_handler_answer = 0xFFFFFFFF;
neorv32_uart_printf("FENCE(.I): ");
neorv32_uart_printf("FENCE: ");
cnt_test++;
asm volatile ("fence");
asm volatile ("fence.i");
 
if (exception_handler_answer != 0xFFFFFFFF) {
test_fail();
317,6 → 328,30
 
 
// ----------------------------------------------------------
// Test fencei instructions - make sure CPU does not crash here and throws no exception
// a more complex test is provided by the RISC-V compliance test
// ----------------------------------------------------------
exception_handler_answer = 0xFFFFFFFF;
neorv32_uart_printf("FENCE.I: ");
asm volatile ("fence.i");
if (exception_handler_answer == TRAP_CODE_I_ILLEGAL) {
neorv32_uart_printf("skipped (not implemented)\n");
}
else {
cnt_test++;
exception_handler_answer = 0xFFFFFFFF;
asm volatile ("fence.i");
if (exception_handler_answer == 0xFFFFFFFF) {
test_ok();
}
else {
test_fail();
}
}
 
 
// ----------------------------------------------------------
// Illegal CSR access
// ----------------------------------------------------------
exception_handler_answer = 0xFFFFFFFF;
/neorv32/trunk/sw/lib/source/neorv32_rte.c
77,9 → 77,8
/**********************************************************************//**
* Install exception handler function to NEORV32 runtime environment.
*
* @note This function automatically activates the according CSR.mie bits when installing handlers for
* the MTIME (MTI), CLIC (MEI), machine software interrupt (MSI) or a fast IRQ. The global interrupt enable bit mstatus.mie has
* to be set by the user via neorv32_cpu_eint(void).
* @note Interrupt sources have to be explicitly enabled by the user via the CSR.mie bits via neorv32_cpu_irq_enable(uint8_t irq_sel)
* and the global interrupt enable bit mstatus.mie via neorv32_cpu_eint(void).
*
* @param[in] id Identifier (type) of the targeted exception. See #NEORV32_RTE_TRAP_enum.
* @param[in] handler The actual handler function for the specified exception (function MUST be of type "void function(void);").
94,15 → 93,6
(id == RTE_TRAP_MSI) || (id == RTE_TRAP_MTI) || (id == RTE_TRAP_MEI) ||
(id == RTE_TRAP_FIRQ_0) || (id == RTE_TRAP_FIRQ_1) || (id == RTE_TRAP_FIRQ_2) || (id == RTE_TRAP_FIRQ_3)) {
 
 
if (id == RTE_TRAP_MSI) { neorv32_cpu_irq_enable(CPU_MIE_MSIE); } // activate software interrupt
if (id == RTE_TRAP_MTI) { neorv32_cpu_irq_enable(CPU_MIE_MTIE); } // activate timer interrupt
if (id == RTE_TRAP_MEI) { neorv32_cpu_irq_enable(CPU_MIE_MEIE); } // activate external interrupt
if (id == RTE_TRAP_FIRQ_0) { neorv32_cpu_irq_enable(CPU_MIE_FIRQ0E); } // activate fast interrupt channel 0
if (id == RTE_TRAP_FIRQ_1) { neorv32_cpu_irq_enable(CPU_MIE_FIRQ1E); } // activate fast interrupt channel 1
if (id == RTE_TRAP_FIRQ_2) { neorv32_cpu_irq_enable(CPU_MIE_FIRQ2E); } // activate fast interrupt channel 2
if (id == RTE_TRAP_FIRQ_3) { neorv32_cpu_irq_enable(CPU_MIE_FIRQ3E); } // activate fast interrupt channel 3
 
__neorv32_rte_vector_lut[id] = (uint32_t)handler; // install handler
 
return 0;
115,9 → 105,8
* Uninstall exception handler function from NEORV32 runtime environment, which was
* previously installed via neorv32_rte_exception_install(uint8_t id, void (*handler)(void)).
*
* @note This function automatically clears the according CSR.mie bits when uninstalling handlers for
* the MTIME (MTI), CLIC (MEI), machine software interrupt (MSI) or fast IRQs. The global interrupt enable bit mstatus.mie has
* to be cleared by the user via neorv32_cpu_dint(void).
* @note Interrupt sources have to be explicitly disabled by the user via the CSR.mie bits via neorv32_cpu_irq_disable(uint8_t irq_sel)
* and/or the global interrupt enable bit mstatus.mie via neorv32_cpu_dint(void).
*
* @param[in] id Identifier (type) of the targeted exception. See #NEORV32_RTE_TRAP_enum.
* return 0 if success, 1 if error (invalid id or targeted exception not supported).
131,14 → 120,6
(id == RTE_TRAP_MSI) || (id == RTE_TRAP_MTI) || (id == RTE_TRAP_MEI) ||
(id == RTE_TRAP_FIRQ_0) || (id == RTE_TRAP_FIRQ_1) || (id == RTE_TRAP_FIRQ_2) || (id == RTE_TRAP_FIRQ_3)) {
 
if (id == RTE_TRAP_MSI) { neorv32_cpu_irq_disable(CPU_MIE_MSIE); } // deactivate software interrupt
if (id == RTE_TRAP_MTI) { neorv32_cpu_irq_disable(CPU_MIE_MTIE); } // deactivate timer interrupt
if (id == RTE_TRAP_MEI) { neorv32_cpu_irq_disable(CPU_MIE_MEIE); } // deactivate external interrupt
if (id == RTE_TRAP_FIRQ_0) { neorv32_cpu_irq_disable(CPU_MIE_FIRQ0E); } // deactivate fast interrupt channel 0
if (id == RTE_TRAP_FIRQ_1) { neorv32_cpu_irq_disable(CPU_MIE_FIRQ1E); } // deactivate fast interrupt channel 1
if (id == RTE_TRAP_FIRQ_2) { neorv32_cpu_irq_disable(CPU_MIE_FIRQ2E); } // deactivate fast interrupt channel 2
if (id == RTE_TRAP_FIRQ_3) { neorv32_cpu_irq_disable(CPU_MIE_FIRQ3E); } // deactivate fast interrupt channel 3
 
__neorv32_rte_vector_lut[id] = (uint32_t)(&__neorv32_rte_debug_exc_handler); // use dummy handler in case the exception is accidently triggered
 
return 0;
/neorv32/trunk/README.md
192,7 → 192,7
* Privilege levels: `M-mode` (Machine mode) + `U-mode` (User mode)
 
**Privileged architecture / FENCE.I** (`Zifencei` extension):
* System instructions: `FENCEI`
* System instructions: `FENCE.I`
 
**Physical memory protection** (`PMP`, requires `Zicsr` extension):
* Additional machine CSRs: `pmpcfgx` `pmpaddrx`

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