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Rev 16 → Rev 17

/trunk/vhdl/tb_id_stage_unit.vhd
36,10 → 36,12
rz : in REGISTER_T;
sr : in SR_REGISTER_T;
 
lock_register : in LOCK_REGISTER_T;
set_reg_lock : out std_logic;
lock_reg_addr : out REGISTER_ADDR_T;
 
lock_register : in LOCK_REGISTER_T;
set_reg_lock0 : out std_logic;
lock_reg_addr0 : out REGISTER_ADDR_T;
set_reg_lock1 : out std_logic;
lock_reg_addr1 : out REGISTER_ADDR_T;
stall_in : in std_logic;
stall_out : out std_logic;
clear_in : in std_logic
57,14 → 59,16
signal ry : REGISTER_T;
signal rz : REGISTER_T;
signal sr : SR_REGISTER_T;
signal lock_register : LOCK_REGISTER_T;
signal lock_register : LOCK_REGISTER_T := ( others => '0' );
--Outputs
signal id_ex_register : ID_EX_REGISTER_T;
signal rx_addr : std_logic_vector(REGISTER_ADDR_WIDTH - 1 downto 0);
signal ry_addr : std_logic_vector(REGISTER_ADDR_WIDTH - 1 downto 0);
signal rz_addr : std_logic_vector(REGISTER_ADDR_WIDTH - 1 downto 0);
signal set_reg_lock : std_logic;
signal lock_reg_addr : std_logic_vector(REGISTER_ADDR_WIDTH - 1 downto 0);
signal rx_addr : REGISTER_ADDR_T;
signal ry_addr : REGISTER_ADDR_T;
signal rz_addr : REGISTER_ADDR_T;
signal set_reg_lock0 : std_logic;
signal lock_reg_addr0 : REGISTER_ADDR_T;
signal set_reg_lock1 : std_logic;
signal lock_reg_addr1 : REGISTER_ADDR_T;
signal stall_out : std_logic;
 
constant TB_COND_TEST_VALUE : COND_T := COND_NONE;
93,8 → 97,10
rz => rz,
sr => sr,
lock_register => lock_register,
set_reg_lock => set_reg_lock,
lock_reg_addr => lock_reg_addr,
set_reg_lock0 => set_reg_lock0,
lock_reg_addr0 => lock_reg_addr0,
set_reg_lock1 => set_reg_lock1,
lock_reg_addr1 => lock_reg_addr1,
stall_in => stall_in,
stall_out => stall_out,
clear_in => clear_in
154,7 → 160,8
assert rx_addr = x"1";
assert id_ex_register.rX_addr = x"1";
assert id_ex_register.rX = TB_R1_TEST_VALUE;
 
assert ( lock_reg_addr0 = x"1" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"1" and set_reg_lock1 = '1' );
-- test case: OPCODE_LD_IMM_HB
if_id_register.ir <= "100"& "1" & x"1" & x"55";
wait for TB_CLOCK;
164,8 → 171,8
assert rx_addr = x"1";
assert id_ex_register.rX_addr = x"1";
assert id_ex_register.rX = TB_R1_TEST_VALUE;
assert ( lock_reg_addr0 = x"1" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"1" and set_reg_lock1 = '1' );
 
 
-- test case: OPCODE_LD_IMM_HB
if_id_register.ir <= "100"& "1" & x"1" & x"55";
wait for TB_CLOCK;
175,6 → 182,7
assert rx_addr = x"1";
assert id_ex_register.rX_addr = x"1";
assert id_ex_register.rX = TB_R1_TEST_VALUE;
assert ( lock_reg_addr0 = x"1" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"1" and set_reg_lock1 = '1' );
 
-- test case: OPCODE_LD_DISP
if_id_register.ir <= "101"& "000" & "11" & x"1" & x"2";
188,6 → 196,7
assert rx_addr = x"1";
assert ry_addr = x"2";
assert rz_addr = x"3";
assert ( lock_reg_addr0 = x"1" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"1" and set_reg_lock1 = '1' );
 
-- test case: OPCODE_LD_DISP_MS
if_id_register.ir <= "110" & "000" & "11" & x"1" & x"2";
201,6 → 210,7
assert rx_addr = x"1";
assert ry_addr = x"2";
assert rz_addr = x"3";
assert ( lock_reg_addr0 = x"1" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"1" and set_reg_lock1 = '1' );
 
-- test case: OPCODE_LD_REG
if_id_register.ir <= "00001" & "001" & x"2" & x"1";
212,7 → 222,120
assert id_ex_register.cond = COND_NOT_ZERO;
assert rx_addr = x"2";
assert ry_addr = x"1";
wait; -- will wait forever
assert ( lock_reg_addr0 = x"2" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"2" and set_reg_lock1 = '1' );
-- test case: OPCODE_LD_REG WITH STALL
lock_register(1) <= '1';
if_id_register.ir <= "00001" & "001" & x"2" & x"1";
wait for TB_CLOCK;
assert id_ex_register.opcode = OPCODE_LD_REG;
assert id_ex_register.rX_addr = x"2";
assert id_ex_register.rX = TB_R2_TEST_VALUE;
assert id_ex_register.rY = TB_R1_TEST_VALUE;
assert id_ex_register.cond = COND_NOT_ZERO;
assert rx_addr = x"2";
assert ry_addr = x"1";
assert stall_out = '1';
assert ( lock_reg_addr0 = x"2" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"2" and set_reg_lock1 = '1' );
lock_register(1) <= '0';
 
-- test case: OPCODE_ST_DISP
if_id_register.ir <= "111" & "100" & "11" & x"1" & x"2";
wait for TB_CLOCK;
assert id_ex_register.opcode = OPCODE_ST_DISP;
assert id_ex_register.rX_addr = x"1";
assert id_ex_register.rX = TB_R1_TEST_VALUE;
assert id_ex_register.rY = TB_R2_TEST_VALUE;
assert id_ex_register.rZ = TB_R3_TEST_VALUE;
assert id_ex_register.cond = COND_NEGATIVE;
assert rx_addr = x"1";
assert ry_addr = x"2";
assert rz_addr = x"3";
-- test case: OPCODE_ADD
if_id_register.ir <= "00010" & "000" & x"3" & x"2";
wait for TB_CLOCK;
assert id_ex_register.opcode = OPCODE_ADD;
assert id_ex_register.rX_addr = x"3";
assert id_ex_register.rX = TB_R3_TEST_VALUE;
assert id_ex_register.rY = TB_R2_TEST_VALUE;
assert id_ex_register.cond = COND_UNCONDITIONAL;
assert rx_addr = x"3";
assert ry_addr = x"2";
assert ( lock_reg_addr0 = x"3" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"3" and set_reg_lock1 = '1' );
-- test case: OPCODE_ADD_IMM
if_id_register.ir <= "00011" & "010" & x"2" & x"5";
wait for TB_CLOCK;
assert id_ex_register.opcode = OPCODE_ADD_IMM;
assert id_ex_register.rX_addr = x"2";
assert id_ex_register.rX = TB_R2_TEST_VALUE;
assert id_ex_register.immediate = x"0005";
assert id_ex_register.cond = COND_ZERO;
assert rx_addr = x"2";
assert ( lock_reg_addr0 = x"2" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"2" and set_reg_lock1 = '1' );
-- test case: OPCODE_SUB
if_id_register.ir <= "00100" & "011" & x"1" & x"2";
wait for TB_CLOCK;
assert id_ex_register.opcode = OPCODE_SUB;
assert id_ex_register.rX_addr = x"1";
assert id_ex_register.rX = TB_R1_TEST_VALUE;
assert id_ex_register.rY = TB_R2_TEST_VALUE;
assert id_ex_register.cond = COND_CARRY;
assert rx_addr = x"1";
assert ry_addr = x"2";
assert ( lock_reg_addr0 = x"1" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"1" and set_reg_lock1 = '1' );
-- test case: OPCODE_SUB_IMM
if_id_register.ir <= "00101" & "100" & x"1" & x"A";
wait for TB_CLOCK;
assert id_ex_register.opcode = OPCODE_SUB_IMM;
assert id_ex_register.rX_addr = x"1";
assert id_ex_register.rX = TB_R1_TEST_VALUE;
assert id_ex_register.immediate = x"000A";
assert id_ex_register.cond = COND_NEGATIVE;
assert rx_addr = x"1";
assert ( lock_reg_addr0 = x"1" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"1" and set_reg_lock1 = '1' );
-- test case: OPCODE_NEG
if_id_register.ir <= "00110" & "101" & x"2" & x"2";
wait for TB_CLOCK;
assert id_ex_register.opcode = OPCODE_NEG;
assert id_ex_register.rX_addr = x"2";
assert id_ex_register.rX = TB_R2_TEST_VALUE;
assert id_ex_register.rY = TB_R2_TEST_VALUE;
assert id_ex_register.cond = COND_OVERFLOW;
assert rx_addr = x"2";
assert ry_addr = x"2";
assert ( lock_reg_addr0 = x"2" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"2" and set_reg_lock1 = '1' );
-- test case: OPCODE_ARS
if_id_register.ir <= "00111" & "110" & x"3" & x"2";
wait for TB_CLOCK;
assert id_ex_register.opcode = OPCODE_ARS;
assert id_ex_register.rX_addr = x"3";
assert id_ex_register.rX = TB_R3_TEST_VALUE;
assert id_ex_register.rY = TB_R2_TEST_VALUE;
assert id_ex_register.cond = COND_ZERO_NEGATIVE;
assert rx_addr = x"3";
assert ry_addr = x"2";
assert ( lock_reg_addr0 = x"3" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"3" and set_reg_lock1 = '1' );
-- test case: OPCODE_ALS
if_id_register.ir <= "01000" & "000" & x"2" & x"1";
wait for TB_CLOCK;
assert id_ex_register.opcode = OPCODE_ALS;
assert id_ex_register.rX_addr = x"2";
assert id_ex_register.rX = TB_R2_TEST_VALUE;
assert id_ex_register.rY = TB_R1_TEST_VALUE;
assert id_ex_register.cond = COND_UNCONDITIONAL;
assert rx_addr = x"2";
assert ry_addr = x"1";
assert ( lock_reg_addr0 = x"2" and set_reg_lock0 = '1' ) or ( lock_reg_addr1 = x"2" and set_reg_lock1 = '1' );
wait;
end process;
 
end;

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