URL
https://opencores.org/ocsvn/storm_core/storm_core/trunk
Subversion Repositories storm_core
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- This comparison shows the changes necessary to convert path
/
- from Rev 16 to Rev 17
- ↔ Reverse comparison
Rev 16 → Rev 17
/storm_core/rtl/CACHE.vhd
82,7 → 82,7
architecture Behavioral of CACHE is |
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-- Are we simulating? -- |
constant IS_SIM : boolean := TRUE; |
constant IS_SIM : boolean := FALSE; |
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-- Cache Memory -- |
type cache_base_type is array(0 to (CACHE_PAGES*PAGE_SIZE)-1) of STD_LOGIC_VECTOR(07 downto 0); |
/storm_core/templates/MEMORY.vhd
38,7 → 38,7
architecture Behavioral of MEMORY is |
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--- Are we simulating? --- |
constant IS_SIM : boolean := TRUE; |
constant IS_SIM : boolean := FALSE; |
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--- Ack Buffer -- |
signal WB_ACK_O_INT : STD_LOGIC; |
130,13 → 130,13
-- Dummy memory for simulation ----------------------------------------------------------------------- |
-- -------------------------------------------------------------------------------------------------------- |
-- use this memory dummy for simulation output |
DEBUG_SIM_MEM: |
if (IS_SIM = TRUE) generate |
GEN_DEBUG_MEM: |
for i in 0 to MEM_SIZE - 1 generate |
SIM_MEM(i) <= MEM_FILE_HH(i) & MEM_FILE_HL(i) & MEM_FILE_LH(i) & MEM_FILE_LL(i); |
end generate; |
end generate; |
-- DEBUG_SIM_MEM: |
-- if (IS_SIM = TRUE) generate |
-- GEN_DEBUG_MEM: |
-- for i in 0 to MEM_SIZE - 1 generate |
-- SIM_MEM(i) <= MEM_FILE_HH(i) & MEM_FILE_HL(i) & MEM_FILE_LH(i) & MEM_FILE_LL(i); |
-- end generate; |
-- end generate; |
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end Behavioral; |