URL
https://opencores.org/ocsvn/uart_block/uart_block/trunk
Subversion Repositories uart_block
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 16 to Rev 17
- ↔ Reverse comparison
Rev 16 → Rev 17
/uart_block/trunk/hdl/iseProject/isim.log
17,4 → 17,3
In process testUart_wishbone_slave.vhd:stim_proc |
|
INFO: Simulator is stopped. |
# exit 0 |
/uart_block/trunk/hdl/iseProject/iseProject.gise
51,7 → 51,6
<file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/> |
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/> |
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/> |
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/> |
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="serial_receiver.cmd_log"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="serial_receiver.lso"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="serial_receiver.ngc"/> |
131,7 → 130,7
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1335878101" xil_pn:in_ck="-3791285954837163877" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1335878101"> |
<transform xil_pn:end_ts="1335878953" xil_pn:in_ck="-3791285954837163877" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1335878953"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="baud_generator.vhd"/> |
150,11 → 149,11
<outfile xil_pn:name="uart_control.vhd"/> |
<outfile xil_pn:name="uart_wishbone_slave.vhd"/> |
</transform> |
<transform xil_pn:end_ts="1335877111" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-5308805702929486166" xil_pn:start_ts="1335877111"> |
<transform xil_pn:end_ts="1335878937" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-5308805702929486166" xil_pn:start_ts="1335878937"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1335877111" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-1238851900205137108" xil_pn:start_ts="1335877111"> |
<transform xil_pn:end_ts="1335878937" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-1238851900205137108" xil_pn:start_ts="1335878937"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
162,7 → 161,7
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1335878101" xil_pn:in_ck="-3791285954837163877" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1335878101"> |
<transform xil_pn:end_ts="1335878953" xil_pn:in_ck="-3791285954837163877" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1335878953"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="baud_generator.vhd"/> |
181,23 → 180,19
<outfile xil_pn:name="uart_control.vhd"/> |
<outfile xil_pn:name="uart_wishbone_slave.vhd"/> |
</transform> |
<transform xil_pn:end_ts="1335878103" xil_pn:in_ck="-3791285954837163877" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="8691405173963172662" xil_pn:start_ts="1335878101"> |
<transform xil_pn:end_ts="1335878957" xil_pn:in_ck="-3791285954837163877" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="8691405173963172662" xil_pn:start_ts="1335878953"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="OutputChanged"/> |
<outfile xil_pn:name="fuse.log"/> |
<outfile xil_pn:name="isim"/> |
<outfile xil_pn:name="isim.log"/> |
<outfile xil_pn:name="testUart_wishbone_slave_beh.prj"/> |
<outfile xil_pn:name="testUart_wishbone_slave_isim_beh.exe"/> |
<outfile xil_pn:name="xilinxsim.ini"/> |
</transform> |
<transform xil_pn:end_ts="1335878103" xil_pn:in_ck="-5691276081812346650" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="7109246390254422178" xil_pn:start_ts="1335878103"> |
<transform xil_pn:end_ts="1335878957" xil_pn:in_ck="-5691276081812346650" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="7109246390254422178" xil_pn:start_ts="1335878957"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="isim.cmd"/> |
<outfile xil_pn:name="isim.log"/> |
<outfile xil_pn:name="testUart_wishbone_slave_isim_beh.wdb"/> |
</transform> |
<transform xil_pn:end_ts="1335863867" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1335863867"> |
/uart_block/trunk/hdl/iseProject/fuse.log
32,9 → 32,9
Compiling architecture behavioral of entity uart_wishbone_slave [uart_wishbone_slave_default] |
Compiling architecture behavior of entity testuart_wishbone_slave |
Time Resolution for simulation is 1ps. |
Waiting for 1 sub-compilation(s) to finish... |
Waiting for 5 sub-compilation(s) to finish... |
Compiled 21 VHDL Units |
Built simulation executable /home/laraujo/work/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.exe |
Fuse Memory Usage: 90276 KB |
Fuse Memory Usage: 90148 KB |
Fuse CPU Usage: 1280 ms |
GCC CPU Usage: 670 ms |
GCC CPU Usage: 4350 ms |
/uart_block/trunk/hdl/iseProject/testUart_wishbone_slave.vhd
114,6 → 114,32
STB_I <= '0'; |
ADR_I0 <= (others => 'U'); |
wait for CLK_I_period; |
|
-- Receive data... |
-- Receive 0x55 value (01010101) |
serial_in <= '0'; -- Start bit |
wait for 8.68 us; |
|
serial_in <= '1'; |
wait for 8.68 us; |
serial_in <= '0'; |
wait for 8.68 us; |
serial_in <= '1'; |
wait for 8.68 us; |
serial_in <= '0'; |
wait for 8.68 us; |
serial_in <= '1'; |
wait for 8.68 us; |
serial_in <= '0'; |
wait for 8.68 us; |
serial_in <= '1'; |
wait for 8.68 us; |
serial_in <= '0'; |
wait for 8.68 us; |
|
-- Stop bit here |
serial_in <= '1'; |
wait for CLK_I_period*20; |
|
-- Stop Simulation |
assert false report "NONE. End of simulation." severity failure; |