URL
https://opencores.org/ocsvn/versatile_fifo/versatile_fifo/trunk
Subversion Repositories versatile_fifo
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- This comparison shows the changes necessary to convert path
/
- from Rev 16 to Rev 17
- ↔ Reverse comparison
Rev 16 → Rev 17
/versatile_fifo/trunk/rtl/verilog/gray_counter.xls
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versatile_fifo/trunk/rtl/verilog/gray_counter.xls
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Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: versatile_fifo/trunk/rtl/verilog/vfifo.kpf
===================================================================
--- versatile_fifo/trunk/rtl/verilog/vfifo.kpf (nonexistent)
+++ versatile_fifo/trunk/rtl/verilog/vfifo.kpf (revision 17)
@@ -0,0 +1,7 @@
+
+
+
+
+ 1
+
+
Index: versatile_fifo/trunk/rtl/verilog/sd_counter.xls
===================================================================
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Index: versatile_fifo/trunk/rtl/verilog/sd_counter.xls
===================================================================
--- versatile_fifo/trunk/rtl/verilog/sd_counter.xls (nonexistent)
+++ versatile_fifo/trunk/rtl/verilog/sd_counter.xls (revision 17)
versatile_fifo/trunk/rtl/verilog/sd_counter.xls
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_sc_sw.v
===================================================================
--- versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_sc_sw.v (revision 16)
+++ versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_sc_sw.v (revision 17)
@@ -7,8 +7,8 @@
adr_b,
clk
);
- parameter DATA_WIDTH = 8;
- parameter ADDR_WIDTH = 9;
+ parameter DATA_WIDTH = `DATA_WIDTH;
+ parameter ADDR_WIDTH = `ADDR_WIDTH;
input [(DATA_WIDTH-1):0] d_a;
input [(ADDR_WIDTH-1):0] adr_a;
input [(ADDR_WIDTH-1):0] adr_b;
@@ -16,7 +16,7 @@
output [(DATA_WIDTH-1):0] q_b;
input clk;
reg [(ADDR_WIDTH-1):0] adr_b_reg;
- reg [DATA_WIDTH-1:0] ram [2**ADDR_WIDTH-1:0] ;
+ reg [DATA_WIDTH-1:0] ram [(1< versatile_fifo_dual_port_ram_sc_sw.v
- vppp +define+TYPE+"sc_dw" +define+DW --simple versatile_fifo_dual_port_ram.v > versatile_fifo_dual_port_ram_sc_dw.v
- vppp +define+TYPE+"dc_sw" +define+DC --simple versatile_fifo_dual_port_ram.v > versatile_fifo_dual_port_ram_dc_sw.v
- vppp +define+TYPE+"dc_dw" +define+DC +define+DW --simple versatile_fifo_dual_port_ram.v > versatile_fifo_dual_port_ram_dc_dw.v
+ vppreproc +define+TYPE+"sc_sw" --simple versatile_fifo_dual_port_ram.v > versatile_fifo_dual_port_ram_sc_sw.v
+ vppreproc +define+TYPE+"sc_dw" +define+DW --simple versatile_fifo_dual_port_ram.v > versatile_fifo_dual_port_ram_sc_dw.v
+ vppreproc +define+TYPE+"dc_sw" +define+DC --simple versatile_fifo_dual_port_ram.v > versatile_fifo_dual_port_ram_dc_sw.v
+ vppreproc +define+TYPE+"dc_dw" +define+DC +define+DW --simple versatile_fifo_dual_port_ram.v > versatile_fifo_dual_port_ram_dc_dw.v
svn_export_versatile_counter:
- svn export http://opencores.org/ocsvn/versatile_counter/versatile_counter/trunk/rtl/verilog/copyright.v
- svn export http://opencores.org/ocsvn/versatile_counter/versatile_counter/trunk/rtl/verilog/lfsr_polynom.v
- svn export http://opencores.org/ocsvn/versatile_counter/versatile_counter/trunk/rtl/verilog/versatile_counter.v
+ svn export http://opencores.org/ocsvn/versatile_counter/versatile_counter/trunk/rtl/verilog/CSV.class.php
+ svn export http://opencores.org/ocsvn/versatile_counter/versatile_counter/trunk/rtl/verilog/versatile_counter_generator.php
export: svn_export_versatile_counter
gray_counter:
- cp gray_counter_defines.v versatile_counter_defines.v
- vpp versatile_counter.v > tmp1.v
- vppp --simple tmp1.v | cat copyright.v - > gray_counter.v
+ excel2csv gray_counter.xls -S ,
+ ./versatile_counter_generator.php gray_counter.csv > gray_counter.v
sd:
- cp sd_counter_defines.v versatile_counter_defines.v
- vpp versatile_counter.v > tmp1.v
- vppp --simple tmp1.v | cat copyright.v - > sd_counter.v
+ excel2csv sd_counter.xls -S ,
+ ./versatile_counter_generator.php sd_counter.csv > sd_counter.v
+
+all: dual_port_ram export gray_counter gray_counter sd
/versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_dc_dw.v
11,8 → 11,8
we_b, |
clk_b |
); |
parameter DATA_WIDTH = 8; |
parameter ADDR_WIDTH = 9; |
parameter DATA_WIDTH = `DATA_WIDTH; |
parameter ADDR_WIDTH = `ADDR_WIDTH; |
input [(DATA_WIDTH-1):0] d_a; |
input [(ADDR_WIDTH-1):0] adr_a; |
input [(ADDR_WIDTH-1):0] adr_b; |
23,7 → 23,7
input we_b; |
input clk_a, clk_b; |
reg [(DATA_WIDTH-1):0] q_b; |
reg [DATA_WIDTH-1:0] ram [2**ADDR_WIDTH-1:0] ; |
reg [DATA_WIDTH-1:0] ram [(1<<ADDR_WIDTH)-1:0] ; |
always @ (posedge clk_a) |
begin |
q_a <= ram[adr_a]; |
/versatile_fifo/trunk/doc/src/versatile_fifo.odt
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svn:mime-type = application/octet-stream
/versatile_fifo/trunk/doc/versatile_fifo.pdf
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream