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URL https://opencores.org/ocsvn/vg_z80_sbc/vg_z80_sbc/trunk

Subversion Repositories vg_z80_sbc

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  • This comparison shows the changes necessary to convert path
    /
    from Rev 16 to Rev 17
    Reverse comparison

Rev 16 → Rev 17

/trunk/rtl/wb_sram.v
1,7 → 1,7
//////////////////////////////////////////////////////////////////////
//// ////
//// $Id: wb_sram.v,v 1.2 2008-12-08 02:09:19 hharte Exp $ ////
//// wb_mmu.v - SRAM with Wishbone Slave interface. ////
//// $Id: wb_sram.v,v 1.3 2008-12-08 06:55:36 hharte Exp $ ////
//// wb_sram.v - SRAM with Wishbone Slave interface. ////
//// ////
//// This file is part of the Vector Graphic Z80 SBC Project ////
//// http://www.opencores.org/projects/vg_z80_sbc/ ////
35,7 → 35,7
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
module wb_sram
module wb_sram
#(
parameter mem_file_name = "none",
parameter adr_width = 14,
/trunk/rtl/wb_vhdfd.v
1,6 → 1,6
//////////////////////////////////////////////////////////////////////
//// ////
//// $Id: wb_vhdfd.v,v 1.2 2008-12-08 02:34:19 hharte Exp $ ////
//// $Id: wb_vhdfd.v,v 1.3 2008-12-08 06:55:36 hharte Exp $ ////
//// wb_vhdfd.v - Vector Graphic HD/FD Disk Controller with ////
//// Wishbone Slave interface. ////
//// ////
57,16 → 57,16
flash_adr_o,flash_dat_o, flash_dat_i, flash_oe, flash_ce, flash_we
);
 
input clk_i;
input nrst_i;
input [2:0] wbs_adr_i;
output reg [8:0] wbs_dat_o;
input clk_i;
input nrst_i;
input [2:0] wbs_adr_i;
output reg [8:0] wbs_dat_o;
input [8:0] wbs_dat_i;
input [3:0] wbs_sel_i;
input [3:0] wbs_sel_i;
input wbs_we_i;
input wbs_stb_i;
input wbs_cyc_i;
output reg wbs_ack_o;
input wbs_stb_i;
input wbs_cyc_i;
output reg wbs_ack_o;
 
// FLASH Interface
output [23:0] flash_adr_o;

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