OpenCores

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trunk/doc/dma_doc.pdf Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/doc/STATUS.txt =================================================================== --- trunk/doc/STATUS.txt (revision 16) +++ trunk/doc/STATUS.txt (nonexistent) @@ -1,60 +0,0 @@ -This file describes the current status of the checked in HDL code. -Please submit all bugs/comments/suggestions regarding the DMA core -to: cores@opencores.org - -Need Help ---------- -I'm looking for help in verifying the core. If you think you can help, -please send an email to the list or to me directly. -Even though I have written a test bench and a few test, I would prefer -if someone else could verify the core as well. - - -STATUS -====== - -Latest Release (10/19/2001) ---------------------------- -- Made the core parameterizable - no more editing of the - wb_defines.v file, just pass the configuration to the core - when instantiating it ! - -Third Release (7/27/2001) --------------------------- -- Added dma_rest_i. It allows to restart the current transfer at - the beginning. Beginning is defined as the original values that - where either written to the channel registers, or where fetched - from the last external descriptor fetch. -- Made some minor changes: - - Parametarized HW handshake signals (ack, req, nd, rest) -- There still might be many bugs ! Only little testing has been done ! -- Please do not modify the sources (yet !) ! I'm still working on the core. -- Things that are not implemented yet, or are known not to work yet: - - The DMA currently ignores the RTY_I (retry) input. - - -Second Release (5/6/2001) -------------------------- -- Made many, many changes, almost rewrote the entire thing ! - The main changes are: - - - Added Support of up to 31 channels - - Added support for 2,4 and 8 priority levels - - Now can have up to 31 channels - - Added many configuration items - - Changed reset to async - -- There still might be many bugs ! Only little testing has been done ! -- Please do not modify the sources (yet !) ! I'm still working on the core. -- Things that are not implemented yet, or are known not to work yet: - - The DMA currently ignores the RTY_I (retry) input. - - -Initial Release (19/3/2001) ---------------------------- -- This is the very first release of the core -- There might be still many bugs ! Only little testing has been done ! -- Please do not modify the sources (yet !) ! I'm still working on the core. -- Things that are not implemented yet, or are known not to work yet: - - The DMA currently ignores the RTY_I (retry) input. - Index: trunk/sim/rtl_sim/bin/Makefile =================================================================== --- trunk/sim/rtl_sim/bin/Makefile (revision 16) +++ trunk/sim/rtl_sim/bin/Makefile (nonexistent) @@ -1,93 +0,0 @@ - -all: sim -SHELL = /bin/sh -MS=-s - -########################################################################## -# -# DUT Sources -# -########################################################################## -DUT_SRC_DIR=../../../rtl/verilog -_TARGETS_= $(DUT_SRC_DIR)/wb_dma_ch_pri_enc.v \ - $(DUT_SRC_DIR)/wb_dma_ch_arb.v \ - $(DUT_SRC_DIR)/wb_dma_pri_enc_sub.v \ - $(DUT_SRC_DIR)/wb_dma_ch_sel.v \ - $(DUT_SRC_DIR)/wb_dma_top.v \ - $(DUT_SRC_DIR)/wb_dma_ch_rf.v \ - $(DUT_SRC_DIR)/wb_dma_rf.v \ - $(DUT_SRC_DIR)/wb_dma_wb_if.v \ - $(DUT_SRC_DIR)/wb_dma_wb_mast.v \ - $(DUT_SRC_DIR)/wb_dma_wb_slv.v \ - $(DUT_SRC_DIR)/wb_dma_de.v \ - $(DUT_SRC_DIR)/wb_dma_inc30r.v - -########################################################################## -# -# Test Bench Sources -# -########################################################################## -_TOP_=test -TB_SRC_DIR=../../../bench/verilog -_TB_= $(TB_SRC_DIR)/test_bench_top.v \ - $(TB_SRC_DIR)/wb_slv_model.v \ - $(TB_SRC_DIR)/wb_mast_model.v - -########################################################################## -# -# Misc Variables -# -########################################################################## - -#INCDIR="-INCDIR ./$(DUT_SRC_DIR)/ -INCDIR ./$(TB_SRC_DIR)/" -#LOGF=-LOGFILE .nclog -#NCCOMMON=-CDSLIB ncwork/cds.lib -HDLVAR ncwork/hdl.var -NOCOPYRIGHT - -INCDIR=+incdir+./$(DUT_SRC_DIR)/ +incdir+./$(TB_SRC_DIR)/ -LOGF=-l .nclog - -UMC_LIB=/tools/dc_libraries/virtual_silicon/umc_lib.v -GATE_NETLIST = ../../../syn/out/wb_dma_top_ps.v - -########################################################################## -# -# Make Targets -# -########################################################################## - -ss: - signalscan -do waves/waves.do -waves waves/waves.trn & - -simxl: - verilog +incdir+$(DUT_SRC_DIR) +incdir+$(TB_SRC_DIR) \ - $(_TARGETS_) $(_TB_) - -simw: - @$(MAKE) -s sim ACCESS="+access+r " WAVES="+define+WAVES" - -sim: - ncverilog -q +define+RUDIS_TB $(_TARGETS_) $(_TB_) \ - $(INCDIR) $(WAVES) $(ACCESS) $(LOGF) +ncstatus \ - +ncuid+`hostname` - -gatew: - @$(MAKE) -s gate ACCESS="+access+r" WAVES="+define+WAVES" - -gate: - ncverilog -q +define+RUDIS_TB $(_TB_) $(UMC_LIB) \ - $(GATE_NETLIST) $(INCDIR) $(WAVES) $(ACCESS) \ - $(LOGF) +ncstatus +ncuid+`hostname` - -hal: - @echo "" - @echo "----- Running HAL ... ----------" - @hal -NOP -NOS -nocheck STYVAL:USEPRT:NOBLKN:DLNBLK \ - +incdir+$(DUT_SRC_DIR) $(_TARGETS_) - @echo "----- DONE ... ----------" - -clean: - rm -rf ./waves/*.dsn ./waves/*.trn \ - ncwork/inc* ncwork/.inc* ncverilog.key \ - ./verilog.* .nclog hal.log INCA_libs - -##########################################################################

trunk/sim/rtl_sim/bin/Makefile Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/syn/bin/comp.dc =================================================================== --- trunk/syn/bin/comp.dc (revision 16) +++ trunk/syn/bin/comp.dc (nonexistent) @@ -1,121 +0,0 @@ -################################################################################# -# -# Actual Synthesis Script -# -# This script does the actual synthesis -# -# Author: Rudolf Usselmann -# rudi@asics.ws -# -# Revision: -# 3/7/01 RU Initial Sript -# -# -################################################################################# - -# ============================================== -# Setup Design Parameters -source ../bin/design_spec.dc - -# ============================================== -# Setup Libraries -source ../bin/lib_spec.dc - -# ============================================== -# Setup IO Files - -append log_file ../log/$active_design "_cmp.log" -append pre_comp_db_file ../out/$design_name "_pre.db" -append post_comp_db_file ../out/$design_name ".db" -append post_syn_verilog_file ../out/$design_name "_ps.v" - -set junk_file /dev/null -sh rm -f $log_file - -# ============================================== -# Setup Misc Variables - -set hdlin_enable_vpp true ;# Important - this enables 'ifdefs - -# ============================================== -# Read Design - -echo "+++++++++ Reading Design ..." >> $log_file -read_file $pre_comp_db_file >> $log_file - -# ============================================== -# Operating conditions - -echo "+++++++++ Setting up Operation Conditions ..." >> $log_file -current_design $design_name -set_operating_conditions WORST >> $log_file - -# Turn off automatic wire load selection, as this -# always (WHY ???) defaults to "zero_load" -#set auto_wire_load_selection false - -#set_wire_load_mode enclosed >> $log_file -#set_wire_load_mode top >> $log_file -#set_wire_load_model -name suggested_40K >> $log_file - -# ============================================== -# Setup Clocks and Resets - -echo "+++++++++ Setting up Clocks ..." >> $log_file - -set_drive 0 [find port {clk_i}] - -# !!! WISHBONE Clock !!! -set clock_period 5 -create_clock -period $clock_period clk_i -set_clock_skew -uncertainty 0.2 clk_i -set_clock_transition 0.2 clk_i -set_dont_touch_network clk_i - -# !!! Reset !!! -set_drive 0 [find port {rst*}] -set_dont_touch_network [find port {rst*}] - -# ============================================== -# Setup IOs - -echo "+++++++++ Setting up IOs ..." >> $log_file - -# Need to spell out external IOs - -set_driving_cell -cell NAND2D2 -pin Z [all_inputs] >> $junk_file -set_load 0.2 [all_outputs] - -set_input_delay 2.0 -clock clk_i [all_inputs] -set_output_delay 2.0 -clock clk_i [all_outputs] - -# ============================================== -# Setup Area Constrains -set_max_area 0.0 -set compile_sequential_area_recovery true - -# ============================================== -# Force Ultra -set_ultra_optimization -f - -# ============================================== -# Compile Design - -echo "+++++++++ Starting Compile ..." >> $log_file -compile -map_effort low -area_effort low >> $log_file -#compile -map_effort high -area_effort high -boundary_optimization -auto_ungroup >> $log_file - -# ============================================== -# Write Out the optimized design - -echo "+++++++++ Saving Optimized Design ..." >> $log_file -write_file -hierarchy -format verilog -output $post_syn_verilog_file -write_file -hierarchy -format db -output $post_comp_db_file - -# ============================================== -# Create Some Basic Reports - -echo "+++++++++ Reporting Final Results ..." >> $log_file -report_timing -nworst 10 >> $log_file -report_area >> $log_file - Index: trunk/syn/bin/lib_spec.dc =================================================================== --- trunk/syn/bin/lib_spec.dc (revision 16) +++ trunk/syn/bin/lib_spec.dc (nonexistent) @@ -1,36 +0,0 @@ -################################################################################# -# -# Library Specification -# -# Author: Rudolf Usselmann -# rudi@asics.ws -# -# Revision: -# 3/7/01 RU Initial Sript -# -# -################################################################################# - -# ============================================== -# Setup Libraries - -set search_path [list $search_path . \ - /tools/dc_libraries/virtual_silicon/UMCL18U250D2_2.2/design_compiler/ \ - $hdl_src_dir] - -set snps [getenv "SYNOPSYS"] - -set synthetic_library "" -append synthetic_library $snps "/libraries/syn/dw01.sldb " -append synthetic_library $snps "/libraries/syn/dw02.sldb " -append synthetic_library $snps "/libraries/syn/dw03.sldb " -append synthetic_library $snps "/libraries/syn/dw04.sldb " -append synthetic_library $snps "/libraries/syn/dw05.sldb " -append synthetic_library $snps "/libraries/syn/dw06.sldb " -append synthetic_library $snps "/libraries/syn/dw07.sldb " - -set target_library { umcl18u250t2_wc.db } -set link_library "" -append link_library $target_library " " $synthetic_library -set symbol_library { umcl18u250t2.sdb } - Index: trunk/syn/bin/design_spec.dc =================================================================== --- trunk/syn/bin/design_spec.dc (revision 16) +++ trunk/syn/bin/design_spec.dc (nonexistent) @@ -1,26 +0,0 @@ -################################################################################# -# -# Design Specification -# -# Author: Rudolf Usselmann -# rudi@asics.ws -# -# Revision: -# 3/7/01 RU Initial Sript -# -# -################################################################################# - -# ============================================== -# Setup Design Parameters - -set design_files {wb_dma_inc30r wb_dma_ch_arb wb_dma_pri_enc_sub wb_dma_ch_pri_enc wb_dma_ch_sel wb_dma_ch_rf wb_dma_rf wb_dma_wb_mast wb_dma_wb_slv wb_dma_wb_if wb_dma_de wb_dma_top } - -set design_name wb_dma_top -set active_design wb_dma_top - -# Next Statement defines all clocks and resets in the design -set special_net {rst clk} - -set hdl_src_dir ../../rtl/verilog/ - Index: trunk/syn/bin/read.dc =================================================================== --- trunk/syn/bin/read.dc (revision 16) +++ trunk/syn/bin/read.dc (nonexistent) @@ -1,65 +0,0 @@ -################################################################################# -# -# Pre Synthesis Script -# -# This script only reads in the design and saves it in a DB file -# -# Author: Rudolf Usselmann -# rudi@asics.ws -# -# Revision: -# 3/7/01 RU Initial Sript -# -# -################################################################################# - -# ============================================== -# Setup Design Parameters -source ../bin/design_spec.dc - -# ============================================== -# Setup Libraries -source ../bin/lib_spec.dc - -# ============================================== -# Setup IO Files - -append log_file ../log/$active_design "_pre.log" -append pre_comp_db_file ../out/$design_name "_pre.db" -sh rm -f $log_file - -# ============================================== -# Setup Misc Variables - -set hdlin_enable_vpp true ;# Important - this enables 'ifdefs - -# ============================================== -# Read Design - -echo "+++++++++ Analyzing all design files ..." >> $log_file - -foreach module $design_files { - echo "+++++++++ Reading: $module" >> $log_file - echo +++++++++ Reading: $module - set module_file_name "" - append module_file_name $module ".v" - analyze -f verilog $module_file_name >> $log_file - elaborate $module >> $log_file - } - -current_design $active_design - -echo "+++++++++ Linking Design ..." >> $log_file -link >> $log_file - -echo "+++++++++ Uniquifying Design ..." >> $log_file -uniquify >> $log_file - -echo "+++++++++ Checking Design ..." >> $log_file -check_design >> $log_file - -# ============================================== -# Save Design -echo "+++++++++ Saving Design ..." >> $log_file -write_file -hierarchy -format db -output $pre_comp_db_file - Index: trunk/bench/verilog/wb_mast_model.v =================================================================== --- trunk/bench/verilog/wb_mast_model.v (revision 16) +++ trunk/bench/verilog/wb_mast_model.v (nonexistent) @@ -1,687 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// WISHBONE Master Model //// -//// //// -//// //// -//// Author: Rudolf Usselmann //// -//// rudi@asics.ws //// -//// //// -//// //// -//// Downloaded from: http://www.opencores.org/cores/wb_dma/ //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000-2002 Rudolf Usselmann //// -//// www.asics.ws //// -//// rudi@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: wb_mast_model.v,v 1.3 2002-02-01 01:55:44 rudi Exp $ -// -// $Date: 2002-02-01 01:55:44 $ -// $Revision: 1.3 $ -// $Author: rudi $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: not supported by cvs2svn $ -// Revision 1.2 2001/09/07 15:34:36 rudi -// -// Changed reset to active high. -// -// Revision 1.1 2001/07/29 08:57:02 rudi -// -// -// 1) Changed Directory Structure -// 2) Added restart signal (REST) -// -// Revision 1.1.1.1 2001/03/19 13:11:34 rudi -// Initial Release -// -// -// - -`include "wb_model_defines.v" - -module wb_mast(clk, rst, adr, din, dout, cyc, stb, sel, we, ack, err, rty); - -input clk, rst; -output [31:0] adr; -input [31:0] din; -output [31:0] dout; -output cyc, stb; -output [3:0] sel; -output we; -input ack, err, rty; - -//////////////////////////////////////////////////////////////////// -// -// Local Wires -// - -parameter mem_size = 4096; - -reg [31:0] adr; -reg [31:0] dout; -reg cyc, stb; -reg [3:0] sel; -reg we; - -reg [31:0] rd_mem[mem_size:0]; -reg [31:0] wr_mem[mem_size:0]; -integer rd_cnt; -integer wr_cnt; - -//////////////////////////////////////////////////////////////////// -// -// Memory Logic -// - -initial - begin - //adr = 32'hxxxx_xxxx; - //adr = 0; - adr = 32'hffff_ffff; - dout = 32'hxxxx_xxxx; - cyc = 0; - stb = 0; - sel = 4'hx; - we = 1'hx; - rd_cnt = 0; - wr_cnt = 0; - #1; - $display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n"); - end - - - -task mem_fill; - -integer n; -begin -rd_cnt = 0; -wr_cnt = 0; -for(n=0;n5000) - begin - $display("\n\n*************************************\n"); - $display("ERROR: Watch Dog Counter Expired\n"); - $display("*************************************\n\n\n"); - $finish; - end - -always #5 clk = ~clk; - -///////////////////////////////////////////////////////////////////// -// -// WISHBONE DMA IP Core -// - - -// Module Prototype - -wb_dma_top - #( 4'hb, // register file address - 2'd1, // Number of priorities (4) - `CH_COUNT, // Number of channels - 4'hf, - 4'hf, - 4'hf, - 4'hf, - 4'hf, - 4'hf, - 4'hf, - 4'hf - ) - u0( - .clk_i( clk ), - .rst_i( rst ), - .wb0s_data_i( wb0s_data_i ), - .wb0s_data_o( wb0s_data_o ), - .wb0_addr_i( wb0_addr_i ), - .wb0_sel_i( wb0_sel_i ), - .wb0_we_i( wb0_we_i ), - .wb0_cyc_i( wb0_cyc_i ), - .wb0_stb_i( wb0_stb_i ), - .wb0_ack_o( wb0_ack_o ), - .wb0_err_o( wb0_err_o ), - .wb0_rty_o( wb0_rty_o ), - .wb0m_data_i( wb0m_data_i ), - .wb0m_data_o( wb0m_data_o ), - .wb0_addr_o( wb0_addr_o ), - .wb0_sel_o( wb0_sel_o ), - .wb0_we_o( wb0_we_o ), - .wb0_cyc_o( wb0_cyc_o ), - .wb0_stb_o( wb0_stb_o ), - .wb0_ack_i( wb0_ack_i ), - .wb0_err_i( wb0_err_i ), - .wb0_rty_i( wb0_rty_i ), - .wb1s_data_i( wb1s_data_i ), - .wb1s_data_o( wb1s_data_o ), - .wb1_addr_i( wb1_addr_i ), - .wb1_sel_i( wb1_sel_i ), - .wb1_we_i( wb1_we_i ), - .wb1_cyc_i( wb1_cyc_i ), - .wb1_stb_i( wb1_stb_i ), - .wb1_ack_o( wb1_ack_o ), - .wb1_err_o( wb1_err_o ), - .wb1_rty_o( wb1_rty_o ), - .wb1m_data_i( wb1m_data_i ), - .wb1m_data_o( wb1m_data_o ), - .wb1_addr_o( wb1_addr_o ), - .wb1_sel_o( wb1_sel_o ), - .wb1_we_o( wb1_we_o ), - .wb1_cyc_o( wb1_cyc_o ), - .wb1_stb_o( wb1_stb_o ), - .wb1_ack_i( wb1_ack_i ), - .wb1_err_i( wb1_err_i ), - .wb1_rty_i( wb1_rty_i ), - .dma_req_i( req_i ), - .dma_ack_o( ack_o ), - .dma_nd_i( nd_i ), - .dma_rest_i( rest_i ), - .inta_o( inta_o ), - .intb_o( intb_o ) - ); - -wb_slv #(14) s0( - .clk( clk ), - .rst( ~rst ), - .adr( wb0_addr_o ), - .din( wb0s_data_o ), - .dout( wb0s_data_i ), - .cyc( wb0_cyc_o ), - .stb( wb0_stb_o ), - .sel( wb0_sel_o ), - .we( wb0_we_o ), - .ack( wb0_ack_i ), - .err( wb0_err_i ), - .rty( wb0_rty_i ) - ); - -wb_slv #(14) s1( - .clk( clk ), - .rst( ~rst ), - .adr( wb1_addr_o ), - .din( wb1s_data_o ), - .dout( wb1s_data_i ), - .cyc( wb1_cyc_o ), - .stb( wb1_stb_o ), - .sel( wb1_sel_o ), - .we( wb1_we_o ), - .ack( wb1_ack_i ), - .err( wb1_err_i ), - .rty( wb1_rty_i ) - ); - -wb_mast m0( - .clk( clk ), - .rst( ~rst ), - .adr( wb0_addr_i ), - .din( wb0m_data_o ), - .dout( wb0m_data_i ), - .cyc( wb0_cyc_i ), - .stb( wb0_stb_i ), - .sel( wb0_sel_i ), - .we( wb0_we_i ), - .ack( wb0_ack_o ), - .err( wb0_err_o ), - .rty( wb0_rty_o ) - ); - -wb_mast m1( - .clk( clk ), - .rst( ~rst ), - .adr( wb1_addr_i ), - .din( wb1m_data_o ), - .dout( wb1m_data_i ), - .cyc( wb1_cyc_i ), - .stb( wb1_stb_i ), - .sel( wb1_sel_i ), - .we( wb1_we_i ), - .ack( wb1_ack_o ), - .err( wb1_err_o ), - .rty( wb1_rty_o ) - ); - -`include "tests.v" - -endmodule - Index: trunk/bench/verilog/tests.v =================================================================== --- trunk/bench/verilog/tests.v (revision 16) +++ trunk/bench/verilog/tests.v (nonexistent) @@ -1,2502 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// DMA Test Cases //// -//// //// -//// //// -//// Author: Rudolf Usselmann //// -//// rudi@asics.ws //// -//// //// -//// //// -//// Downloaded from: http://www.opencores.org/cores/wb_dma/ //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000 Rudolf Usselmann //// -//// rudi@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: tests.v,v 1.3 2001-09-07 15:34:36 rudi Exp $ -// -// $Date: 2001-09-07 15:34:36 $ -// $Revision: 1.3 $ -// $Author: rudi $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: not supported by cvs2svn $ -// Revision 1.2 2001/08/15 05:40:29 rudi -// -// - Changed IO names to be more clear. -// - Uniquifyed define names to be core specific. -// - Added Section 3.10, describing DMA restart. -// -// Revision 1.1 2001/07/29 08:57:02 rudi -// -// -// 1) Changed Directory Structure -// 2) Added restart signal (REST) -// -// Revision 1.1.1.1 2001/03/19 13:12:39 rudi -// Initial Release -// -// -// - -task sw_ext_desc1; -input quick; - -integer quick, tot_sz_max, chunk_sz_max, del_max; - -reg [7:0] mode; -reg [15:0] tot_sz; -reg [15:0] chunk_sz; -integer ii, n,del; -reg [31:0] int_src, d0, d1; - -begin -$display("\n\n"); -$display("*****************************************************"); -$display("*** SW DMA No Buffer Ext. Descr LL ... ***"); -$display("*****************************************************\n"); - -rst = 1; -repeat(10) @(posedge clk); -rst = 0; -repeat(10) @(posedge clk); - -if(quick) - begin - tot_sz_max = 32; - del_max = 2; - chunk_sz_max = 4; - end -else - begin - tot_sz_max = 128; - del_max = 6; - chunk_sz_max = 8; - end - - -mode = 1; -tot_sz = 64; -chunk_sz=3; -del = 0; - -for(del=0;del8) tot_sz = tot_sz + 2; -if(tot_sz>16) tot_sz = tot_sz + 2; -if(tot_sz>32) tot_sz = tot_sz + 12; - - -for(chunk_sz=0;chunk_sz0, "); - 1: $write("Mode: 0->1, "); - 2: $write("Mode: 1->0, "); - 3: $write("Mode: 1->1, "); - endcase - $display("Total Size: %0d, Chunk Size: %0d, Slave Delay: %0d", - tot_sz, chunk_sz, del); - - ack_cnt_clr = 1; - @(posedge clk); - ack_cnt_clr = 0; - - s0.delay = del; - s1.delay = del; - - s0.fill_mem(1); - s1.fill_mem(1); - - s0.mem[0] = (32'h000c_0000 | (mode[1:0]<<16)) + tot_sz; - s0.mem[1] = 32'h0000_0100; - s0.mem[2] = 32'h0000_0400; - s0.mem[3] = 32'h0000_0010; - - s0.mem[4] = (32'h001c_0000 | (mode[1:0]<<16)) + tot_sz; - s0.mem[5] = 32'h0000_0100 + (tot_sz * 4); - s0.mem[6] = 32'h0000_0400 + (tot_sz * 4); - s0.mem[7] = 32'h0000_0000; - - - s0.mem[8] = (32'h000c_0000 | (mode[1:0]<<16)) + tot_sz; - s0.mem[9] = 32'h0000_0800; - s0.mem[10] = 32'h0000_0c00; - s0.mem[11] = 32'h0000_0030; - - s0.mem[12] = (32'h001c_0000 | (mode[1:0]<<16)) + tot_sz; - s0.mem[13] = 32'h0000_0800 + (tot_sz * 4); - s0.mem[14] = 32'h0000_0c00 + (tot_sz * 4); - s0.mem[15] = 32'h0000_0000; - - - m0.wb_wr1(`REG_BASE + `INT_MASKA,4'hf,32'hffff_ffff); - - m0.wb_wr1(`REG_BASE + `PTR0, 4'hf, 32'h0000_0020); - m0.wb_wr1(`REG_BASE + `CH0_TXSZ,4'hf, {chunk_sz, 12'h0}); - m0.wb_wr1(`REG_BASE + `CH0_ADR0,4'hf,32'h0000_0080); - m0.wb_wr1(`REG_BASE + `CH0_ADR1,4'hf,32'h0000_4000); - - m0.wb_wr1(`REG_BASE + `CH0_CSR,4'hf, - {15'h0002, 3'b000, 1'b0, 6'h1, 4'b0011, 2'b00, 1'b1}); - - - m0.wb_wr1(`REG_BASE + `PTR1, 4'hf, 32'h0000_0000); - m0.wb_wr1(`REG_BASE + `CH1_TXSZ,4'hf, {chunk_sz, 12'h0}); - m0.wb_wr1(`REG_BASE + `CH1_ADR0,4'hf,32'h0000_0080); - m0.wb_wr1(`REG_BASE + `CH1_ADR1,4'hf,32'h0000_4000); - - m0.wb_wr1(`REG_BASE + `CH1_CSR,4'hf, - {15'h0002, 3'b000, 1'b0, 6'h1, 4'b0011, 2'b00, 1'b1}); - - -for(ii=0;ii<2;ii=ii+1) -begin - repeat(5) @(posedge clk); - while(!inta_o) @(posedge clk); - - m0.wb_rd1(`REG_BASE + `INT_SRCA, 4'hf, int_src); - - if(int_src[0]) - begin - for(n=0;n>2) + n ]; - else d0=s0.mem[(s0.mem[9]>>2) + n ]; - if(mode[0]) d1=s1.mem[(s0.mem[10]>>2) + n ]; - else d1=s0.mem[(s0.mem[10]>>2) + n ]; - - if( d1 !== d0 ) - begin - $display("ERROR: CH0: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)", - n, d0, d1, $time); - error_cnt = error_cnt + 1; - end - end - m0.wb_rd1(`REG_BASE + `CH0_CSR, 4'hf, d1); - d0 = {24'h0064_089, 1'b1, mode[1:0], 1'b0}; - if( d1 !== d0 ) - begin - $display("ERROR: CH0_CSR Mismatch: Expected: %x, Got: %x (%0t)", - d0, d1, $time); - error_cnt = error_cnt + 1; - end - end - - - if(int_src[1]) - begin - for(n=0;n>2) + n ]; - else d0=s0.mem[(s0.mem[1]>>2) + n ]; - if(mode[0]) d1=s1.mem[(s0.mem[2]>>2) + n ]; - else d1=s0.mem[(s0.mem[2]>>2) + n ]; - - if( d1 !== d0 ) - begin - $display("ERROR: CH1: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)", - n, d0, d1, $time); - error_cnt = error_cnt + 1; - end - end - m0.wb_rd1(`REG_BASE + `CH1_CSR, 4'hf, d1); - d0 = {24'h0064_089, 1'b1, mode[1:0], 1'b0}; - if( d1 !== d0 ) - begin - $display("ERROR: CH1_CSR Mismatch: Expected: %x, Got: %x (%0t)", - d0, d1, $time); - error_cnt = error_cnt + 1; - end - end - -end - - if(ack_cnt != ((tot_sz*4)+(4*2))*2 ) - begin - $display("ERROR: ACK count Mismatch: Expected: %0d, Got: %0d (%0t)", - ((tot_sz*4)+(4*2)), ack_cnt, $time); - error_cnt = error_cnt + 1; - end - - repeat(5) @(posedge clk); - -end -end - -show_errors; -$display("*****************************************************"); -$display("*** Test DONE ... ***"); -$display("*****************************************************\n\n"); -end - - -endtask - - - -task arb_test1; - -reg [7:0] mode; -reg [15:0] tot_sz; -reg [15:0] chunk_sz0; -reg [15:0] chunk_sz1; -reg [15:0] chunk_sz2; -reg [15:0] chunk_sz3; -integer a,n,ptr; -reg [31:0] d0,d1; -reg [7:0] pri, order, finish; - -begin -$display("\n\n"); -$display("*****************************************************"); -$display("*** SW DMA No Buffer 4 ch pri ... ***"); -$display("*****************************************************\n"); - -mode = 0; -tot_sz = 32; -chunk_sz0=4; -chunk_sz1=4; -chunk_sz2=4; -chunk_sz3=4; -a=0; - -m0.wb_wr1(`REG_BASE + `CH0_CSR,4'hf, 32'h0); -m0.wb_wr1(`REG_BASE + `CH1_CSR,4'hf, 32'h0); -m0.wb_wr1(`REG_BASE + `CH2_CSR,4'hf, 32'h0); -m0.wb_wr1(`REG_BASE + `CH3_CSR,4'hf, 32'h0); - -m0.wb_rd1(`REG_BASE + `INT_SRCA, 4'hf, d0); - -for(mode=0;mode<4;mode=mode+1) -for(a=0;a<17;a=a+1) -begin - - chunk_sz0=4; - chunk_sz1=4; - chunk_sz2=4; - chunk_sz3=4; - - s0.delay = 0; - s1.delay = 0; - - case(a) // ch3 ch2 ch1 ch0 - 0: - begin - pri = 8'b10_10_10_10; // All equal 0,1,2,3 - order = {2'd0, 2'd1, 2'd2, 2'd3}; - end - - // One channel with High Priority - // The other depend oon the ARB state - 1: - begin - pri = 8'b00_00_00_10; // 3,1,0,2 - order = {2'b0, 2'd3, 2'd1, 2'd2}; - end - 2: - begin - pri = 8'b00_00_10_00; // 2,3,0,1 - order = {2'd1, 2'd0, 2'd2, 2'd3}; - end - 3: - begin - pri = 8'b00_10_00_00; // 1,0,2,3 - order = {2'd2, 2'd0, 2'd1, 2'd3}; - end - 4: - begin - pri = 8'b10_00_00_00; // 0,3,1,2 - order = {2'd3, 2'd0, 2'd1, 2'd2}; - end - - // Specific order for all Channels - 5: - begin - pri = 8'b10_00_01_11; // 3,0,2,1 - order = {2'd0, 2'd3, 2'd1, 2'd2}; - end - - 6: - begin - pri = 8'b00_10_11_01; // 2,1,3,0 - order = {2'd1, 2'd2, 2'd0, 2'd3}; - end - - 7: - begin - pri = 8'b00_11_01_10; // 1,3,2,0 - order = {2'd2, 2'd0, 2'd1, 2'd3}; - end - - 8: - begin - pri = 8'b00_01_10_11; // 3,2,1,0 - order = {2'd0, 2'd1, 2'd2, 2'd3}; - end - - // One channel with High Priority - // The other depend oon the ARB state - // Chunk Size varies - // First channel small chunkc size - 9: - begin - pri = 8'b00_00_00_10; // 3,1,0,2 - order = {2'd0, 2'd1, 2'd2, 2'd3}; - chunk_sz3=1; - end - 10: - begin - pri = 8'b00_00_10_00; // 2,0,1,3 - order = {2'd1, 2'd0, 2'd3, 2'd2}; - chunk_sz2=1; - end - 11: - begin - pri = 8'b00_10_00_00; // 1,0,2,3 - order = {2'd2, 2'd0, 2'd3, 2'd1}; - chunk_sz1=1; - end - 12: - begin - pri = 8'b10_00_00_00; // 0,2,3,1 - order = {2'd3, 2'd1, 2'd2, 2'd0}; - chunk_sz0=1; - end - - // First channel large chunkc size - 13: - begin - pri = 8'b00_00_00_10; // 3,0,2,1 - order = {2'd0, 2'd3, 2'd1, 2'd2}; - chunk_sz3=8; - end - 14: - begin - pri = 8'b00_00_10_00; // 2,0,3,1 - order = {2'd1, 2'd2, 2'd0, 2'd3}; - chunk_sz2=8; - end - 15: - begin - pri = 8'b00_10_00_00; // 1,0,3,2 - order = {2'd2, 2'd1, 2'd0, 2'd3}; - chunk_sz1=8; - end - 16: - begin - pri = 8'b10_00_00_00; // 0,2,3,1 - order = {2'd3, 2'd0, 2'd1, 2'd2}; - chunk_sz0=8; - end - - endcase - -case(mode) - 0: $write("Mode: 0->0, "); - 1: $write("Mode: 0->1, "); - 2: $write("Mode: 1->0, "); - 3: $write("Mode: 1->1, "); -endcase -$display("a: %0d", a); - - ack_cnt_clr = 1; - @(posedge clk); - ack_cnt_clr = 0; - - s0.fill_mem(1); - s1.fill_mem(1); - - m0.wb_wr1(`REG_BASE + `CH0_CSR,4'hf, - {17'h00000, pri[1:0], 6'h0, 4'b0011, mode[1:0], 1'b0}); - - m0.wb_wr1(`REG_BASE + `CH1_CSR,4'hf, - {17'h00000, pri[3:2], 6'h0, 4'b0011, mode[1:0], 1'b0}); - - m0.wb_wr1(`REG_BASE + `CH2_CSR,4'hf, - {17'h00000, pri[5:4], 6'h0, 4'b0011, mode[1:0], 1'b0}); - - m0.wb_wr1(`REG_BASE + `CH3_CSR,4'hf, - {17'h00000, pri[7:6], 6'h0, 4'b0011, mode[1:0], 1'b0}); - - m0.wb_wr1(`REG_BASE + `INT_MASKA,4'hf,32'hffff_ffff); - - m0.wb_wr1(`REG_BASE + `CH0_TXSZ,4'hf, {chunk_sz0, tot_sz}); - m0.wb_wr1(`REG_BASE + `CH0_ADR0,4'hf,32'h0000_0000); - m0.wb_wr1(`REG_BASE + `CH0_ADR1,4'hf,32'h0000_4000); - - m0.wb_wr1(`REG_BASE + `CH1_TXSZ,4'hf, {chunk_sz1, tot_sz}); - m0.wb_wr1(`REG_BASE + `CH1_ADR0,4'hf,32'h0000_0080); - m0.wb_wr1(`REG_BASE + `CH1_ADR1,4'hf,32'h0000_4080); - - m0.wb_wr1(`REG_BASE + `CH2_TXSZ,4'hf, {chunk_sz2, tot_sz}); - m0.wb_wr1(`REG_BASE + `CH2_ADR0,4'hf,32'h0000_0100); - m0.wb_wr1(`REG_BASE + `CH2_ADR1,4'hf,32'h0000_4100); - - m0.wb_wr1(`REG_BASE + `CH3_TXSZ,4'hf, {chunk_sz3, tot_sz}); - m0.wb_wr1(`REG_BASE + `CH3_ADR0,4'hf,32'h0000_0180); - m0.wb_wr1(`REG_BASE + `CH3_ADR1,4'hf,32'h0000_4180); - - - m0.wb_wr1(`REG_BASE + `CH0_CSR,4'hf, - {12'h000, 3'b010, 1'b0, 1'b0, pri[1:0], 6'h0, 4'b0011, mode[1:0], 1'b1}); - - //{15'h0002, 3'b000, 1'b0, 6'h1, 4'b0011, 2'b00, 1'b1}); - - m0.wb_wr1(`REG_BASE + `CH1_CSR,4'hf, - {12'h000, 3'b010, 1'b0, 1'b0, pri[3:2], 6'h0, 4'b0011, mode[1:0], 1'b1}); - - m0.wb_wr1(`REG_BASE + `CH2_CSR,4'hf, - {12'h000, 3'b010, 1'b0, 1'b0, pri[5:4], 6'h0, 4'b0011, mode[1:0], 1'b1}); - - - - m0.wb_wr1(`REG_BASE + `CH3_CSR,4'hf, - {12'h0000, 3'b010, 1'b0, 1'b0, pri[7:6], 6'h0, 4'b0011, mode[1:0], 1'b1}); - - repeat(1) @(posedge clk); - - // Wait for interrupt, Check completion order - - ptr=0; - finish = 8'hxx; - - while(ptr!=4) - begin - while(!inta_o) @(posedge clk); - m0.wb_rd1(`REG_BASE + `INT_SRCA, 4'hf, d0); - - if(d0[0]) d0[1:0] = 0; - else - if(d0[1]) d0[1:0] = 1; - else - if(d0[2]) d0[1:0] = 2; - else - if(d0[3]) d0[1:0] = 3; - - case(ptr) - 0: finish[7:6] = d0[1:0]; - 1: finish[5:4] = d0[1:0]; - 2: finish[3:2] = d0[1:0]; - 3: finish[1:0] = d0[1:0]; - endcase - - case(d0[1:0]) - 0: m0.wb_rd1(`REG_BASE + `CH0_CSR, 4'hf, d0); - 1: m0.wb_rd1(`REG_BASE + `CH1_CSR, 4'hf, d0); - 2: m0.wb_rd1(`REG_BASE + `CH2_CSR, 4'hf, d0); - 3: m0.wb_rd1(`REG_BASE + `CH3_CSR, 4'hf, d0); - endcase - - ptr=ptr+1; - repeat(4) @(posedge clk); - end - - - if(finish !== order) - begin - $display("ERROR: Completion Order[%0d] Mismatch: Expected: %b, Got: %b (%0t)", - a, order, finish, $time); - error_cnt = error_cnt + 1; - end - - - for(n=0;n0, chunk_size: %0d", chunk_sz); - 1: $display("Mode: 0->1, chunk_size: %0d", chunk_sz); - 2: $display("Mode: 1->0, chunk_size: %0d", chunk_sz); - 3: $display("Mode: 1->1, chunk_size: %0d", chunk_sz); -endcase - -for(rep=0;rep<4;rep=rep+1) - begin - ack_cnt_clr = 1; - @(posedge clk); - ack_cnt_clr = 0; - - if(del==4) del = 10; - - s0.delay = del; - s1.delay = del; - - if(chunk_sz==0) k = 1; - else - begin - k = tot_sz/chunk_sz; - if((k*chunk_sz) != tot_sz) k = k + 1; - end - - s0.fill_mem(1); - s1.fill_mem(1); - - fork - begin - - for(m=0;m < k;m=m+1) - begin - repeat(del) @(posedge clk); - #1; - req_i[0] = 1; - while(!ack_o[0]) @(posedge clk); - #1; - req_i[0] = 0; - end - - end - - begin - repeat(1) @(posedge clk); - while(!u0.dma_done_all) @(posedge clk); - -/* - repeat(5) @(posedge clk); - while(!inta_o) @(posedge clk); - - m0.wb_rd1(`REG_BASE + `INT_SRCA, 4'hf, d1); - d0 = 32'h0000_0002; - if( d1 !== d0 ) - begin - $display("ERROR: INT_SRC Mismatch: Expected: %x, Got: %x (%0t)", - d0, d1, $time); - error_cnt = error_cnt + 1; - end - - m0.wb_rd1(`REG_BASE + `CH0_CSR, 4'hf, d1); - d0 = {24'h0000_081, 1'b1, mode[1:0], 1'b0}; - if( d1 !== d0 ) - begin - $display("ERROR: CH0_CSR Mismatch: Expected: %x, Got: %x (%0t)", - d0, d1, $time); - error_cnt = error_cnt + 1; - end -*/ - - - for(n=0;n4) tot_sz = tot_sz + 4; -if(tot_sz>16) tot_sz = tot_sz + 12; -if(tot_sz>64) tot_sz = tot_sz + 48; - -for(del=0;del0, chunk_size: %0d", chunk_sz); - 1: $display("Mode: 0->1, chunk_size: %0d", chunk_sz); - 2: $display("Mode: 1->0, chunk_size: %0d", chunk_sz); - 3: $display("Mode: 1->1, chunk_size: %0d", chunk_sz); - endcase - - ack_cnt_clr = 1; - @(posedge clk); - ack_cnt_clr = 0; - - if(chunk_sz==0) k = 1; - else - begin - k = tot_sz/chunk_sz; - if((k*chunk_sz) != tot_sz) k = k + 1; - end - - k = k * 2; - - fork - begin - repeat(5) @(posedge clk); - for(m0=0;m0 < k;m0=m0+1) - begin - repeat(del) @(posedge clk); - #1; - req_i[0] = 1; - while(!ack_o[0]) @(posedge clk); - #1; - req_i[0] = 0; - end - end - - begin - repeat(5) @(posedge clk); - for(m1=0;m1 < k;m1=m1+1) - begin - repeat(del) @(posedge clk); - #1; - req_i[1] = 1; - while(!ack_o[1]) @(posedge clk); - #1; - req_i[1] = 0; - end - end - - begin - repeat(5) @(posedge clk); - for(m2=0;m2 < k;m2=m2+1) - begin - repeat(del) @(posedge clk); - #1; - req_i[2] = 1; - while(!ack_o[2]) @(posedge clk); - #1; - req_i[2] = 0; - end - end - - begin - repeat(5) @(posedge clk); - for(m3=0;m3 < k;m3=m3+1) - begin - repeat(del) @(posedge clk); - #1; - req_i[3] = 1; - while(!ack_o[3]) @(posedge clk); - #1; - req_i[3] = 0; - end - end - - for(i=0;i<4;i=i) - begin - repeat(5) @(posedge clk); - while(!inta_o) @(posedge clk); - m0.wb_rd1(`REG_BASE + `INT_SRCA, 4'hf, int_src); - - if(int_src[0]) - begin - m0.wb_rd1(`REG_BASE + `CH0_CSR, 4'hf, d0); - i=i+1; - for(n=0;n>2) + n ]; - else d0=s0.mem[(s0.mem[1]>>2) + n ]; - if(mode[0]) d1=s1.mem[(s0.mem[2]>>2) + n ]; - else d1=s0.mem[(s0.mem[2]>>2) + n ]; - - if( d1 !== d0 ) - begin - $display("ERROR: CH0: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)", - n, d0, d1, $time); - error_cnt = error_cnt + 1; - end - end - end - - if(int_src[1]) - begin - m0.wb_rd1(`REG_BASE + `CH1_CSR, 4'hf, d0); - i=i+1; - for(n=0;n>2) + n ]; - else d0=s0.mem[(s0.mem[9]>>2) + n ]; - if(mode[0]) d1=s1.mem[(s0.mem[10]>>2) + n ]; - else d1=s0.mem[(s0.mem[10]>>2) + n ]; - - if( d1 !== d0 ) - begin - $display("ERROR: CH1: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)", - n, d0, d1, $time); - error_cnt = error_cnt + 1; - end - end - end - - if(int_src[2]) - begin - m0.wb_rd1(`REG_BASE + `CH2_CSR, 4'hf, d0); - i=i+1; - for(n=0;n>2) + n ]; - else d0=s0.mem[(s0.mem[17]>>2) + n ]; - if(mode[0]) d1=s1.mem[(s0.mem[18]>>2) + n ]; - else d1=s0.mem[(s0.mem[18]>>2) + n ]; - - if( d1 !== d0 ) - begin - $display("ERROR: CH2: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)", - n, d0, d1, $time); - error_cnt = error_cnt + 1; - end - end - end - - if(int_src[3]) - begin - m0.wb_rd1(`REG_BASE + `CH3_CSR, 4'hf, d0); - i=i+1; - for(n=0;n>2) + n ]; - else d0=s0.mem[(s0.mem[25]>>2) + n ]; - if(mode[0]) d1=s1.mem[(s0.mem[26]>>2) + n ]; - else d1=s0.mem[(s0.mem[26]>>2) + n ]; - - if( d1 !== d0 ) - begin - $display("ERROR: CH3: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)", - n, d0, d1, $time); - error_cnt = error_cnt + 1; - end - end - end - - end - - join - - - if(ack_cnt != ((tot_sz*2*4*2)+(4*4*2)) ) - begin - $display("ERROR: ACK count Mismatch: Expected: %0d, Got: %0d (%0t)", - ((tot_sz*2*4*2)+(4*4*2)), ack_cnt, $time); - error_cnt = error_cnt + 1; - end - - repeat(5) @(posedge clk); - -end -end - - s0.delay = 0; - s1.delay = 0; - -show_errors; -$display("*****************************************************"); -$display("*** Test DONE ... ***"); -$display("*****************************************************\n\n"); -end - -endtask - - - - - - -task hw_dma3; -input quick; - -integer quick, tot_sz_max, chunk_sz_max, del_max; - -reg [7:0] mode; -reg [15:0] chunk_sz, tot_sz; -integer odd, i, iz, n,m0, m1, m2, m3, k, k1, rep,del; -reg [31:0] int_src, d0,d1; - -begin -$display("\n\n"); -$display("*****************************************************"); -$display("*** HW DMA Ext Descr. 4 Channels ND Test ... ***"); -$display("*****************************************************\n"); - -case(quick) - default: - begin - del_max = 6; - chunk_sz_max = 8; - end - 1: - begin - del_max = 4; - chunk_sz_max = 4; - end - 2: - begin - del_max = 3; - chunk_sz_max = 4; - end -endcase - -mode = 0; -tot_sz = 64; -chunk_sz=4; -del = 0; - -m0.wb_wr1(`REG_BASE + `CH0_CSR,4'hf, 32'h0); -m0.wb_wr1(`REG_BASE + `CH1_CSR,4'hf, 32'h0); -m0.wb_wr1(`REG_BASE + `CH2_CSR,4'hf, 32'h0); -m0.wb_wr1(`REG_BASE + `CH3_CSR,4'hf, 32'h0); - -m0.wb_rd1(`REG_BASE + `INT_SRCA, 4'hf, int_src); - - -for(del=0;del0, chunk_size: %0d", chunk_sz); - 1: $display("Mode: 0->1, chunk_size: %0d", chunk_sz); - 2: $display("Mode: 1->0, chunk_size: %0d", chunk_sz); - 3: $display("Mode: 1->1, chunk_size: %0d", chunk_sz); - endcase - - ack_cnt_clr = 1; - @(posedge clk); - ack_cnt_clr = 0; - - if(chunk_sz==0) k = 1; - else - begin - k = tot_sz/chunk_sz; - if((k*chunk_sz) != tot_sz) k = k + 1; - if((k*chunk_sz) != tot_sz) odd = 1; - else odd = 0; - end - - if(chunk_sz==0) k1 = 4; - else - begin - k1 = tot_sz/chunk_sz; - if((k1*chunk_sz) != tot_sz) k1 = k1 + 1; - k1 = k1 * 4; - end - - k1 = k * 4; - iz = k; - - fork - begin - repeat(5) @(posedge clk); - for(m0=0;m0 < k1+1;m0=m0+1) - begin - repeat(del) @(posedge clk); - #1; - - if(m0==iz) nd_i[0] = 1; - else - if(m0==(iz*2)) nd_i[0] = 1; - else - if(m0==(iz*3)) nd_i[0] = 1; - else - if(m0==(iz*4)) nd_i[0] = 1; - else req_i[0] = 1; - - if(nd_i[0]==1) - begin - @(posedge clk); - #1; - nd_i[0] = 0; - repeat(1) @(posedge clk); - #1; - req_i[0] = 1; - end - - while(!ack_o[0] & (m0 < k1)) @(posedge clk); - #1; - req_i[0] = 0; - nd_i[0] = 0; - end - end - - begin - repeat(5) @(posedge clk); - for(m1=0;m1 < k1;m1=m1+1) - begin - repeat(del) @(posedge clk); - #1; - if(m1==k-1) nd_i[1] = 1; - if(m1==(k*2)-1) nd_i[1] = 1; - if(m1==(k*3)-1) nd_i[1] = 1; - if(m1==(k*4)-1) nd_i[1] = 1; - req_i[1] = 1; - while(!ack_o[1]) @(posedge clk); - #1; - req_i[1] = 0; - nd_i[1] = 0; - end - end - - begin - repeat(5) @(posedge clk); - for(m2=0;m2 < k1+1;m2=m2+1) - begin - repeat(del) @(posedge clk); - #1; - - if(m2==k) nd_i[2] = 1; - else - if(m2==(k*2)) nd_i[2] = 1; - else - if(m2==(k*3)) nd_i[2] = 1; - else - if(m2==(k*4)) nd_i[2] = 1; - else req_i[2] = 1; - - if(nd_i[2]==1) - begin - @(posedge clk); - #1; - nd_i[2] = 0; - repeat(1) @(posedge clk); - #1; - req_i[2] = 1; - end - - while(!ack_o[2] & (m2 < k1)) @(posedge clk); - #1; - req_i[2] = 0; - nd_i[2] = 0; - end - end - - - begin - repeat(5) @(posedge clk); - for(m3=0;m3 < k1;m3=m3+1) - begin - repeat(del) @(posedge clk); - #1; - if(m3==k-1) nd_i[3] = 1; - if(m3==(k*2)-1) nd_i[3] = 1; - if(m3==(k*3)-1) nd_i[3] = 1; - if(m3==(k*4)-1) nd_i[3] = 1; - req_i[3] = 1; - while(!ack_o[3]) @(posedge clk); - #1; - req_i[3] = 0; - nd_i[3] = 0; - end - end - - - for(i=0;i<4;i=i) - begin - repeat(5) @(posedge clk); - while(!inta_o) @(posedge clk); - m0.wb_rd1(`REG_BASE + `INT_SRCA, 4'hf, int_src); - - if(int_src[0]) - begin - i=i+1; - for(n=0;n>2) + n ]; - else d0=s0.mem[(s0.mem[1]>>2) + n ]; - if(mode[0]) d1=s1.mem[(s0.mem[2]>>2) + n ]; - else d1=s0.mem[(s0.mem[2]>>2) + n ]; - - if( d1 !== d0 ) - begin - $display("ERROR: CH0: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)", - n, d0, d1, $time); - error_cnt = error_cnt + 1; - end - end - repeat(1) @(posedge clk); - d1 = {28'h0064_09b, 1'b1, mode[1:0], 1'b0}; - m0.wb_rd1(`REG_BASE + `CH0_CSR, 4'hf, d0); - repeat(1) @(posedge clk); - if( d1 !== d0 ) - begin - $display("ERROR: CH0: CSR Mismatch: Expected: %x, Got: %x (%0t)", - d1, d0, $time); - error_cnt = error_cnt + 1; - end - end - - if(int_src[1]) - begin - i=i+1; - for(n=0;n>2) + n ]; - else d0=s0.mem[(s0.mem[17]>>2) + n ]; - if(mode[0]) d1=s1.mem[(s0.mem[18]>>2) + n ]; - else d1=s0.mem[(s0.mem[18]>>2) + n ]; - - if( d1 !== d0 ) - begin - $display("ERROR: CH1: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)", - n, d0, d1, $time); - error_cnt = error_cnt + 1; - end - end - repeat(1) @(posedge clk); - d1 = {28'h0064_09b, 1'b1, mode[1:0], 1'b0}; - m0.wb_rd1(`REG_BASE + `CH1_CSR, 4'hf, d0); - repeat(1) @(posedge clk); - if( d1 !== d0 ) - begin - $display("ERROR: CH1: CSR Mismatch: Expected: %x, Got: %x (%0t)", - d1, d0, $time); - error_cnt = error_cnt + 1; - end - repeat(1) @(posedge clk); - case(chunk_sz) - default: d1 = 32'h0000_00c0; - 3: d1 = 32'h0000_00be; - 5: d1 = 32'h0000_00bf; - 6: d1 = 32'h0000_00be; - 7: d1 = 32'h0000_00ba; - endcase - d0 = s0.mem[16]; - repeat(1) @(posedge clk); - if( d1 !== d0 ) - begin - $display("ERROR: CH1: DESC_CSR Mismatch: Expected: %x, Got: %x (%0t)", - d1, d0, $time); - error_cnt = error_cnt + 1; - end - end - - if(int_src[2]) - begin - i=i+1; - for(n=0;n>2) + n ]; - else d0=s0.mem[(s0.mem[33]>>2) + n ]; - if(mode[0]) d1=s1.mem[(s0.mem[34]>>2) + n ]; - else d1=s0.mem[(s0.mem[34]>>2) + n ]; - - if( d1 !== d0 ) - begin - $display("ERROR: CH2: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)", - n, d0, d1, $time); - error_cnt = error_cnt + 1; - end - end - repeat(1) @(posedge clk); - d1 = {28'h0064_09b, 1'b1, mode[1:0], 1'b0}; - m0.wb_rd1(`REG_BASE + `CH2_CSR, 4'hf, d0); - repeat(1) @(posedge clk); - if( d1 !== d0 ) - begin - $display("ERROR: CH2: CSR Mismatch: Expected: %x, Got: %x (%0t)", - d1, d0, $time); - error_cnt = error_cnt + 1; - end - end - - if(int_src[3]) - begin - i=i+1; - for(n=0;n>2) + n ]; - else d0=s0.mem[(s0.mem[49]>>2) + n ]; - if(mode[0]) d1=s1.mem[(s0.mem[50]>>2) + n ]; - else d1=s0.mem[(s0.mem[50]>>2) + n ]; - - if( d1 !== d0 ) - begin - $display("ERROR: CH3: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)", - n, d0, d1, $time); - error_cnt = error_cnt + 1; - end - end - repeat(1) @(posedge clk); - d1 = {28'h0064_09b, 1'b1, mode[1:0], 1'b0}; - m0.wb_rd1(`REG_BASE + `CH3_CSR, 4'hf, d0); - repeat(1) @(posedge clk); - if( d1 !== d0 ) - begin - $display("ERROR: CH3: CSR Mismatch: Expected: %x, Got: %x (%0t)", - d1, d0, $time); - error_cnt = error_cnt + 1; - end - repeat(1) @(posedge clk); - case(chunk_sz) - default: d1 = 32'h0000_00c0; - 3: d1 = 32'h0000_00be; - 5: d1 = 32'h0000_00bf; - 6: d1 = 32'h0000_00be; - 7: d1 = 32'h0000_00ba; - endcase - d0 = s0.mem[48]; - repeat(1) @(posedge clk); - if( d1 !== d0 ) - begin - $display("ERROR: CH3: DESC_CSR Mismatch: Expected: %x, Got: %x (%0t)", - d1, d0, $time); - error_cnt = error_cnt + 1; - end - - end - - end - join - - // CH0: 528 Acks - // CH1: 532 Acks - // CH2: 528 Acks - // CH3: 532 Acks - - case(chunk_sz) - default: k = 2120; - 3: k = 2184; - 5: k = 2152; - 6: k = 2184; - 7: k = 2312; - endcase - - if(ack_cnt != k ) - begin - $display("ERROR: ACK count Mismatch: Expected: %0d, Got: %0d (%0t)", - k, ack_cnt, $time); - error_cnt = error_cnt + 1; - end - - repeat(5) @(posedge clk); - -end - -s0.delay = 0; -s1.delay = 0; - -show_errors; -$display("*****************************************************"); -$display("*** Test DONE ... ***"); -$display("*****************************************************\n\n"); -end - -endtask - - - - - -task sw_dma1; -input quick; - -integer quick, tot_sz_max, chunk_sz_max; -reg [7:0] mode; -reg [15:0] chunk_sz, tot_sz; -integer n; -reg [31:0] d0,d1; - -begin -$display("\n\n"); -$display("*****************************************************"); -$display("*** SW DMA No Buffer (tx & chunk size test) ... ***"); -$display("*****************************************************\n"); - -case(quick) - default: - begin - tot_sz_max = 1024; - chunk_sz_max = 256; - end - 1: - begin - tot_sz_max = 128; - chunk_sz_max = 64; - end - 2: - begin - tot_sz_max = 32; - chunk_sz_max = 4; - end -endcase - -mode = 1; -tot_sz = 2048; -tot_sz = 16; -chunk_sz=4; - -for(mode=0;mode<4;mode=mode+1) -for(tot_sz=1;tot_sz64) tot_sz=tot_sz+4; -if(tot_sz>128) tot_sz=tot_sz+12; -case(mode) - 0: $display("Mode: 0->0, tot_size: %0d", tot_sz); - 1: $display("Mode: 0->1, tot_size: %0d", tot_sz); - 2: $display("Mode: 1->0, tot_size: %0d", tot_sz); - 3: $display("Mode: 1->1, tot_size: %0d", tot_sz); -endcase - -for(chunk_sz=0;chunk_sz128) tot_sz=tot_sz+4; - -$write("Slv 0 delay: %0d, Slv 1 Delay: %0d - ",del0, del1); -case(mode) - 0: $display("Mode: 0->0, tot_size: %0d", tot_sz); - 1: $display("Mode: 0->1, tot_size: %0d", tot_sz); - 2: $display("Mode: 1->0, tot_size: %0d", tot_sz); - 3: $display("Mode: 1->1, tot_size: %0d", tot_sz); -endcase - -for(chunk_sz=0;chunk_sz 4)) chunk_sz = chunk_sz + 1; - - s0.delay = del0; - s1.delay = del1; - - ack_cnt_clr = 1; - @(posedge clk); - ack_cnt_clr = 0; - - s0.fill_mem(1); - s1.fill_mem(1); - m0.wb_wr1(`REG_BASE + `INT_MASKB,4'hf,32'hffff_ffff); - m0.wb_wr1(`REG_BASE + `CH0_TXSZ,4'hf, {chunk_sz, tot_sz}); - m0.wb_wr1(`REG_BASE + `CH0_ADR0,4'hf,32'h0000_0000); - m0.wb_wr1(`REG_BASE + `CH0_ADR1,4'hf,32'h0000_4000); - m0.wb_wr1(`REG_BASE + `CH0_CSR,4'hf, - {12'h0000, 3'b010, 1'b0, 11'h000, 2'b11, mode[1:0], 1'b1}); - - repeat(5) @(posedge clk); - while(!intb_o) @(posedge clk); - - m0.wb_rd1(`REG_BASE + `INT_SRCB, 4'hf, d1); - d0 = 32'h0000_0001; - if( d1 !== d0 ) - begin - $display("ERROR: INT_SRC Mismatch: Expected: %x, Got: %x (%0t)", - d0, d1, $time); - error_cnt = error_cnt + 1; - end - - m0.wb_rd1(`REG_BASE + `CH0_CSR, 4'hf, d1); - d0 = {24'h0064_081, 1'b1, mode[1:0], 1'b0}; - if( d1 !== d0 ) - begin - $display("ERROR: CH0_CSR Mismatch: Expected: %x, Got: %x (%0t)", - d0, d1, $time); - error_cnt = error_cnt + 1; - end - - for(n=0;n0 Read Test .... ***"); -$display("*****************************************************\n"); - -s0.fill_mem(1); -s1.fill_mem(1); -d=0; -n=16; - -for(d=0;d<16;d=d+1) - begin - $display("INFO: PT10 RD4, delay %0d",d); - for(n=0;n<512;n=n+4) - begin - m0.wb_rd4(n<<2,4'hf,d,d0,d1,d2,d3); - - if( (s1.mem[n+0] !== d0) | (s1.mem[n+1] !== d1) | - (s1.mem[n+2] !== d2) | (s1.mem[n+3] !== d3) ) - begin - $display("ERROR: Memory Read Data (%0d) Mismatch: (%0t)",n,$time); - $display("D0: Expected: %x, Got %x", s1.mem[n+0], d0); - $display("D1: Expected: %x, Got %x", s1.mem[n+1], d1); - $display("D2: Expected: %x, Got %x", s1.mem[n+2], d2); - $display("D3: Expected: %x, Got %x", s1.mem[n+3], d3); - error_cnt = error_cnt + 1; - end - end - end - - -$display("\nINFO: PT10 RD1"); - for(n=0;n<512;n=n+1) - begin - m0.wb_rd1(n<<2,4'hf,d0); - - if( s1.mem[n] !== d0 ) - begin - $display("ERROR: Memory Read Data (%0d) Mismatch: (%0t)",n,$time); - $display("D0: Expected: %x, Got %x", s1.mem[n], d0); - error_cnt = error_cnt + 1; - end - end - - -show_errors; -$display("*****************************************************"); -$display("*** Test DONE ... ***"); -$display("*****************************************************\n"); -end -endtask - - -task pt01_rd; - -// Misc Variables -reg [31:0] d0,d1,d2,d3; -integer d,n; - -begin -$display("\n"); -$display("*****************************************************"); -$display("*** Running Path Through 0->1 Read Test .... ***"); -$display("*****************************************************\n"); - -s0.fill_mem(1); -s1.fill_mem(1); - -d=1; -n=0; -for(d=0;d<16;d=d+1) - begin - $display("INFO: PT01 RD4, delay %0d",d); - for(n=0;n<512;n=n+4) - begin - m1.wb_rd4(n<<2,4'hf,d,d0,d1,d2,d3); - @(posedge clk); - - if( (s0.mem[n+0] !== d0) | (s0.mem[n+1] !== d1) | - (s0.mem[n+2] !== d2) | (s0.mem[n+3] !== d3) ) - begin - $display("ERROR: Memory Read Data (%0d) Mismatch: (%0t)",n,$time); - $display("D0: Expected: %x, Got %x", s0.mem[n+0], d0); - $display("D1: Expected: %x, Got %x", s0.mem[n+1], d1); - $display("D2: Expected: %x, Got %x", s0.mem[n+2], d2); - $display("D3: Expected: %x, Got %x", s0.mem[n+3], d3); - error_cnt = error_cnt + 1; - end - end - end - -$display("\nINFO: PT01 RD1"); - for(n=0;n<512;n=n+1) - begin - m1.wb_rd1(n<<2,4'hf,d0); - - if( s0.mem[n+0] !== d0 ) - begin - $display("ERROR: Memory Read Data (%0d) Mismatch: (%0t)",n,$time); - $display("D0: Expected: %x, Got %x", s0.mem[n+0], d0); - error_cnt = error_cnt + 1; - end - end - -show_errors; -$display("*****************************************************"); -$display("*** Test DONE ... ***"); -$display("*****************************************************\n"); -end -endtask - - - - -task pt10_wr; - -// Misc Variables -reg [31:0] d0,d1,d2,d3; -integer d,n; - -begin - -$display("\n"); -$display("*****************************************************"); -$display("*** Running Path Through 1->0 Write Test .... ***"); -$display("*****************************************************\n"); - - -s0.fill_mem(1); -s1.fill_mem(1); -d=1; -n=0; -for(d=0;d<16;d=d+1) - begin - $display("INFO: PT10 WR4, delay %0d",d); - for(n=0;n<512;n=n+4) - begin - - d0 = $random; - d1 = $random; - d2 = $random; - d3 = $random; - m0.wb_wr4(n<<2,4'hf,d,d0,d1,d2,d3); - @(posedge clk); - - if( (s1.mem[n+0] !== d0) | (s1.mem[n+1] !== d1) | - (s1.mem[n+2] !== d2) | (s1.mem[n+3] !== d3) ) - begin - $display("ERROR: Memory Write Data (%0d) Mismatch: (%0t)",n,$time); - $display("D0: Expected: %x, Got %x", s1.mem[n+0], d0); - $display("D1: Expected: %x, Got %x", s1.mem[n+1], d1); - $display("D2: Expected: %x, Got %x", s1.mem[n+2], d2); - $display("D3: Expected: %x, Got %x", s1.mem[n+3], d3); - error_cnt = error_cnt + 1; - end - end - end - -$display("\nINFO: PT10 WR1"); - for(n=0;n<512;n=n+1) - begin - d0 = $random; - m0.wb_wr1(n<<2,4'hf,d0); - @(posedge clk); - - if( s1.mem[n+0] !== d0 ) - begin - $display("ERROR: Memory Write Data (%0d) Mismatch: (%0t)",n,$time); - $display("D0: Expected: %x, Got %x", s1.mem[n+0], d0); - error_cnt = error_cnt + 1; - end - end - -show_errors; -$display("*****************************************************"); -$display("*** Test DONE ... ***"); -$display("*****************************************************\n"); -end -endtask - - - -task pt01_wr; - -// Misc Variables -reg [31:0] d0,d1,d2,d3; -integer d,n; - -begin - -$display("\n"); -$display("*****************************************************"); -$display("*** Running Path Through 0->1 Write Test .... ***"); -$display("*****************************************************\n"); - - -s0.fill_mem(1); -s1.fill_mem(1); - -d=1; -n=0; -for(d=0;d<16;d=d+1) - begin - $display("INFO: PT01 WR4, delay %0d",d); - for(n=0;n<512;n=n+4) - begin - - d0 = $random; - d1 = $random; - d2 = $random; - d3 = $random; - m1.wb_wr4(n<<2,4'hf,d,d0,d1,d2,d3); - @(posedge clk); - - if( (s0.mem[n+0] !== d0) | (s0.mem[n+1] !== d1) | - (s0.mem[n+2] !== d2) | (s0.mem[n+3] !== d3) ) - begin - $display("ERROR: Memory Write Data (%0d) Mismatch: (%0t)",n,$time); - $display("D0: Expected: %x, Got %x", s0.mem[n+0], d0); - $display("D1: Expected: %x, Got %x", s0.mem[n+1], d1); - $display("D2: Expected: %x, Got %x", s0.mem[n+2], d2); - $display("D3: Expected: %x, Got %x", s0.mem[n+3], d3); - error_cnt = error_cnt + 1; - end - end - end - - $display("\nINFO: PT01 WR1"); - for(n=0;n<512;n=n+1) - begin - d0 = $random; - m1.wb_wr1(n<<2,4'hf,d0); - @(posedge clk); - - if( s0.mem[n+0] !== d0 ) - begin - $display("ERROR: Memory Write Data (%0d) Mismatch: (%0t)",n,$time); - $display("D0: Expected: %x, Got %x", s0.mem[n+0], d0); - error_cnt = error_cnt + 1; - end - end - -show_errors; -$display("*****************************************************"); -$display("*** Test DONE ... ***"); -$display("*****************************************************\n"); -end -endtask - - - - - - - -task show_errors; - -begin - -$display("\n"); -$display(" +--------------------+"); -$display(" | Total ERRORS: %0d |", error_cnt); -$display(" +--------------------+"); - -end -endtask - - - -task hw_dma4; -input quick; - -integer quick, tot_sz_max, chunk_sz_max, del_max; - -reg [7:0] mode; -reg [15:0] chunk_sz, tot_sz; -integer i, n,m0, m1, m2, m3, k,rep,del; -reg [31:0] int_src, d0,d1; -reg do_rest; -integer rest_del; -integer rest_del_t; - -begin -$display("\n\n"); -$display("*****************************************************"); -$display("*** HW DMA No Buffer Ext Descr. REST Test ... ***"); -$display("*****************************************************\n"); - -case(quick) - default: - begin - del_max = 6; - tot_sz_max = 200; - chunk_sz_max = 8; - end - 1: - begin - del_max = 4; - tot_sz_max = 128; - chunk_sz_max = 4; - end - 2: - begin - del_max = 3; - tot_sz_max = 32; - chunk_sz_max = 4; - end -endcase - -mode = 1; -tot_sz = 32; -chunk_sz=7; -del = 0; -do_rest = 1; -rest_del = 7; - - m0.wb_wr1(`REG_BASE + `CH0_CSR,4'hf, 32'h0); - m0.wb_wr1(`REG_BASE + `CH1_CSR,4'hf, 32'h0); - m0.wb_wr1(`REG_BASE + `CH2_CSR,4'hf, 32'h0); - m0.wb_wr1(`REG_BASE + `CH3_CSR,4'hf, 32'h0); - - m0.wb_rd1(`REG_BASE + `INT_SRCA, 4'hf, int_src); - -for(tot_sz=1;tot_sz4) tot_sz = tot_sz + 4; -if(tot_sz>16) tot_sz = tot_sz + 12; -if(tot_sz>64) tot_sz = tot_sz + 48; - -for(del=0;del= k) rest_del_t = k - 1; - else rest_del_t = rest_del; - - k = k * 2; - - - $write("Total Size: %0d, Delay: %0d REST_del: %0d ",tot_sz, del, rest_del_t); - case(mode) - 0: $display("Mode: 0->0, chunk_size: %0d", chunk_sz); - 1: $display("Mode: 0->1, chunk_size: %0d", chunk_sz); - 2: $display("Mode: 1->0, chunk_size: %0d", chunk_sz); - 3: $display("Mode: 1->1, chunk_size: %0d", chunk_sz); - endcase - - - -//$display("k=%0d",k); - - fork - begin // Hardware Handshake Channel 0 - repeat(5) @(posedge clk); - for(m0=0;m0 < k;m0=m0+1) - begin - repeat(del) @(posedge clk); - #1; - req_i[0] = 1; - while(!ack_o[0]) @(posedge clk); - #1; - req_i[0] = 0; - end - end - - begin // Hardware Handshake Channel 1 - repeat(5) @(posedge clk); - for(m1=0;m1 < (k + rest_del_t + 1);m1=m1+1) - begin - repeat(del) @(posedge clk); - #1; - req_i[1] = 1; - while(!ack_o[1]) @(posedge clk); - #1; - req_i[1] = 0; -//$display("m1=%0d",m1); - if( (do_rest==1) & (m1==rest_del_t) ) - //if( do_rest==1 ) - begin -//$display("Asserting Restart ..."); - @(posedge clk); - #1; - rest_i[1] = 1; - @(posedge clk); - #1; - rest_i[1] = 0; - do_rest = 0; - @(posedge clk); - @(posedge clk); - end - - end - end - - begin // Hardware Handshake Channel 2 - repeat(5) @(posedge clk); - for(m2=0;m2 < k;m2=m2+1) - begin - repeat(del) @(posedge clk); - #1; - req_i[2] = 1; - while(!ack_o[2]) @(posedge clk); - #1; - req_i[2] = 0; - end - end - - begin // Hardware Handshake Channel 3 - repeat(5) @(posedge clk); - for(m3=0;m3 < k;m3=m3+1) - begin - repeat(del) @(posedge clk); - #1; - req_i[3] = 1; - while(!ack_o[3]) @(posedge clk); - #1; - req_i[3] = 0; - end - end - - for(i=0;i<4;i=i) - begin - repeat(5) @(posedge clk); - while(!inta_o) @(posedge clk); - m0.wb_rd1(`REG_BASE + `INT_SRCA, 4'hf, int_src); - - if(int_src[0]) - begin - m0.wb_rd1(`REG_BASE + `CH0_CSR, 4'hf, d0); - i=i+1; - for(n=0;n>2) + n ]; - else d0=s0.mem[(s0.mem[1]>>2) + n ]; - if(mode[0]) d1=s1.mem[(s0.mem[2]>>2) + n ]; - else d1=s0.mem[(s0.mem[2]>>2) + n ]; - - if( d1 !== d0 ) - begin - $display("ERROR: CH0: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)", - n, d0, d1, $time); - error_cnt = error_cnt + 1; - end - end - end - - if(int_src[1]) - begin - m0.wb_rd1(`REG_BASE + `CH1_CSR, 4'hf, d0); - i=i+1; - for(n=0;n>2) + n ]; - else d0=s0.mem[(s0.mem[9]>>2) + n ]; - if(mode[0]) d1=s1.mem[(s0.mem[10]>>2) + n ]; - else d1=s0.mem[(s0.mem[10]>>2) + n ]; - - if( d1 !== d0 ) - begin - $display("ERROR: CH1: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)", - n, d0, d1, $time); - error_cnt = error_cnt + 1; - end - end - end - - if(int_src[2]) - begin - m0.wb_rd1(`REG_BASE + `CH2_CSR, 4'hf, d0); - i=i+1; - for(n=0;n>2) + n ]; - else d0=s0.mem[(s0.mem[17]>>2) + n ]; - if(mode[0]) d1=s1.mem[(s0.mem[18]>>2) + n ]; - else d1=s0.mem[(s0.mem[18]>>2) + n ]; - - if( d1 !== d0 ) - begin - $display("ERROR: CH2: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)", - n, d0, d1, $time); - error_cnt = error_cnt + 1; - end - end - end - - if(int_src[3]) - begin - m0.wb_rd1(`REG_BASE + `CH3_CSR, 4'hf, d0); - i=i+1; - for(n=0;n>2) + n ]; - else d0=s0.mem[(s0.mem[25]>>2) + n ]; - if(mode[0]) d1=s1.mem[(s0.mem[26]>>2) + n ]; - else d1=s0.mem[(s0.mem[26]>>2) + n ]; - - if( d1 !== d0 ) - begin - $display("ERROR: CH3: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)", - n, d0, d1, $time); - error_cnt = error_cnt + 1; - end - end - end - - end - - join - - -/* - if(ack_cnt != ((tot_sz*2*4*2)+(4*4*2)) ) - begin - $display("ERROR: ACK count Mismatch: Expected: %0d, Got: %0d (%0t)", - ((tot_sz*2*4*2)+(4*4*2)), ack_cnt, $time); - error_cnt = error_cnt + 1; - end -*/ - - repeat(5) @(posedge clk); - -end -end - - s0.delay = 0; - s1.delay = 0; - -show_errors; -$display("*****************************************************"); -$display("*** Test DONE ... ***"); -$display("*****************************************************\n\n"); -end - -endtask - - - - Index: trunk/bench/verilog/wb_model_defines.v =================================================================== --- trunk/bench/verilog/wb_model_defines.v (revision 16) +++ trunk/bench/verilog/wb_model_defines.v (nonexistent) @@ -1,63 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// WISHBONE Model Definitions //// -//// //// -//// //// -//// Author: Rudolf Usselmann //// -//// rudi@asics.ws //// -//// //// -//// //// -//// Downloaded from: http://www.opencores.org/cores/wb_dma/ //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000-2002 Rudolf Usselmann //// -//// www.asics.ws //// -//// rudi@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: wb_model_defines.v,v 1.2 2002-02-01 01:55:44 rudi Exp $ -// -// $Date: 2002-02-01 01:55:44 $ -// $Revision: 1.2 $ -// $Author: rudi $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: not supported by cvs2svn $ -// Revision 1.1 2001/07/29 08:57:02 rudi -// -// -// 1) Changed Directory Structure -// 2) Added restart signal (REST) -// -// Revision 1.1.1.1 2001/03/19 13:12:48 rudi -// Initial Release -// -// -// - -`timescale 1ns / 10ps Index: trunk/rtl/verilog/wb_dma_wb_if.v =================================================================== --- trunk/rtl/verilog/wb_dma_wb_if.v (revision 16) +++ trunk/rtl/verilog/wb_dma_wb_if.v (nonexistent) @@ -1,219 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// WISHBONE DMA WISHBONE Interface //// -//// //// -//// //// -//// Author: Rudolf Usselmann //// -//// rudi@asics.ws //// -//// //// -//// //// -//// Downloaded from: http://www.opencores.org/cores/wb_dma/ //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000-2002 Rudolf Usselmann //// -//// www.asics.ws //// -//// rudi@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: wb_dma_wb_if.v,v 1.3 2002-02-01 01:54:45 rudi Exp $ -// -// $Date: 2002-02-01 01:54:45 $ -// $Revision: 1.3 $ -// $Author: rudi $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: not supported by cvs2svn $ -// Revision 1.2 2001/10/19 04:35:04 rudi -// -// - Made the core parameterized -// -// Revision 1.1 2001/07/29 08:57:02 rudi -// -// -// 1) Changed Directory Structure -// 2) Added restart signal (REST) -// -// Revision 1.2 2001/06/05 10:22:37 rudi -// -// -// - Added Support of up to 31 channels -// - Added support for 2,4 and 8 priority levels -// - Now can have up to 31 channels -// - Added many configuration items -// - Changed reset to async -// -// Revision 1.1.1.1 2001/03/19 13:10:54 rudi -// Initial Release -// -// -// - -`include "wb_dma_defines.v" - -module wb_dma_wb_if(clk, rst, - - // Wishbone - wbs_data_i, wbs_data_o, wb_addr_i, wb_sel_i, wb_we_i, wb_cyc_i, - wb_stb_i, wb_ack_o, wb_err_o, wb_rty_o, - wbm_data_i, wbm_data_o, wb_addr_o, wb_sel_o, wb_we_o, wb_cyc_o, - wb_stb_o, wb_ack_i, wb_err_i, wb_rty_i, - - // Master - mast_go, mast_we, mast_adr, mast_din, mast_dout, mast_err, - mast_drdy, mast_wait, pt_sel_i, mast_pt_in, mast_pt_out, - - // Slave - slv_adr, slv_din, slv_dout, slv_re, slv_we, - pt_sel_o, slv_pt_out, slv_pt_in - - ); - -parameter rf_addr = 0; - -input clk, rst; - -// -------------------------------------- -// WISHBONE INTERFACE - -// Slave Interface -input [31:0] wbs_data_i; -output [31:0] wbs_data_o; -input [31:0] wb_addr_i; -input [3:0] wb_sel_i; -input wb_we_i; -input wb_cyc_i; -input wb_stb_i; -output wb_ack_o; -output wb_err_o; -output wb_rty_o; - -// Master Interface -input [31:0] wbm_data_i; -output [31:0] wbm_data_o; -output [31:0] wb_addr_o; -output [3:0] wb_sel_o; -output wb_we_o; -output wb_cyc_o; -output wb_stb_o; -input wb_ack_i; -input wb_err_i; -input wb_rty_i; - -// -------------------------------------- -// MASTER INTERFACE -input mast_go; // Perform a Master Cycle (as long as this - // line is asserted) -input mast_we; // Read/Write -input [31:0] mast_adr; // Address for the transfer -input [31:0] mast_din; // Internal Input Data -output [31:0] mast_dout; // Internal Output Data -output mast_err; // Indicates an error has occurred - -output mast_drdy; // Indicated that either data is available - // during a read, or that the master can accept - // the next data during a write -input mast_wait; // Tells the master to insert wait cycles - // because data can not be accepted/provided - -// Pass Through Interface -input pt_sel_i; // Pass Through Mode Selected -input [70:0] mast_pt_in; // Grouped WISHBONE inputs -output [34:0] mast_pt_out; // Grouped WISHBONE outputs - -// -------------------------------------- -// Slave INTERFACE - -// This is the register File Interface -output [31:0] slv_adr; // Slave Address -input [31:0] slv_din; // Slave Input Data -output [31:0] slv_dout; // Slave Output Data -output slv_re; // Slave Read Enable -output slv_we; // Slave Write Enable - -// Pass through Interface -output pt_sel_o; // Pass Through Mode Active -output [70:0] slv_pt_out; // Grouped WISHBONE out signals -input [34:0] slv_pt_in; // Grouped WISHBONE in signals - -//////////////////////////////////////////////////////////////////// -// -// Modules -// - -wb_dma_wb_mast u0( - .clk( clk ), - .rst( rst ), - .wb_data_i( wbs_data_i ), - .wb_data_o( wbs_data_o ), - .wb_addr_o( wb_addr_o ), - .wb_sel_o( wb_sel_o ), - .wb_we_o( wb_we_o ), - .wb_cyc_o( wb_cyc_o ), - .wb_stb_o( wb_stb_o ), - .wb_ack_i( wb_ack_i ), - .wb_err_i( wb_err_i ), - .wb_rty_i( wb_rty_i ), - .mast_go( mast_go ), - .mast_we( mast_we ), - .mast_adr( mast_adr ), - .mast_din( mast_din ), - .mast_dout( mast_dout ), - .mast_err( mast_err ), - .mast_drdy( mast_drdy ), - .mast_wait( mast_wait ), - .pt_sel( pt_sel_i ), - .mast_pt_in( mast_pt_in ), - .mast_pt_out( mast_pt_out ) - ); - - -wb_dma_wb_slv #(rf_addr) u1( - .clk( clk ), - .rst( rst ), - .wb_data_i( wbm_data_i ), - .wb_data_o( wbm_data_o ), - .wb_addr_i( wb_addr_i ), - .wb_sel_i( wb_sel_i ), - .wb_we_i( wb_we_i ), - .wb_cyc_i( wb_cyc_i ), - .wb_stb_i( wb_stb_i ), - .wb_ack_o( wb_ack_o ), - .wb_err_o( wb_err_o ), - .wb_rty_o( wb_rty_o ), - .slv_adr( slv_adr ), - .slv_din( slv_din ), - .slv_dout( slv_dout ), - .slv_re( slv_re ), - .slv_we( slv_we ), - .pt_sel( pt_sel_o ), - .slv_pt_out( slv_pt_out ), - .slv_pt_in( slv_pt_in ) - ); - - -endmodule Index: trunk/rtl/verilog/wb_dma_rf.v =================================================================== --- trunk/rtl/verilog/wb_dma_rf.v (revision 16) +++ trunk/rtl/verilog/wb_dma_rf.v (nonexistent) @@ -1,1856 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// WISHBONE DMA Register File //// -//// //// -//// //// -//// Author: Rudolf Usselmann //// -//// rudi@asics.ws //// -//// //// -//// //// -//// Downloaded from: http://www.opencores.org/cores/wb_dma/ //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000-2002 Rudolf Usselmann //// -//// www.asics.ws //// -//// rudi@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: wb_dma_rf.v,v 1.4 2002-02-01 01:54:45 rudi Exp $ -// -// $Date: 2002-02-01 01:54:45 $ -// $Revision: 1.4 $ -// $Author: rudi $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: not supported by cvs2svn $ -// Revision 1.3 2001/10/19 04:35:04 rudi -// -// - Made the core parameterized -// -// Revision 1.2 2001/08/15 05:40:30 rudi -// -// - Changed IO names to be more clear. -// - Uniquifyed define names to be core specific. -// - Added Section 3.10, describing DMA restart. -// -// Revision 1.1 2001/07/29 08:57:02 rudi -// -// -// 1) Changed Directory Structure -// 2) Added restart signal (REST) -// -// Revision 1.4 2001/06/14 08:50:46 rudi -// -// Changed name of channel register file module. -// -// Revision 1.3 2001/06/13 02:26:48 rudi -// -// -// Small changes after running lint. -// -// Revision 1.2 2001/06/05 10:22:37 rudi -// -// -// - Added Support of up to 31 channels -// - Added support for 2,4 and 8 priority levels -// - Now can have up to 31 channels -// - Added many configuration items -// - Changed reset to async -// -// Revision 1.1.1.1 2001/03/19 13:10:11 rudi -// Initial Release -// -// -// - -`include "wb_dma_defines.v" - -module wb_dma_rf(clk, rst, - - // WISHBONE Access - wb_rf_adr, wb_rf_din, wb_rf_dout, wb_rf_re, wb_rf_we, - - // WISHBONE Interrupt outputs - inta_o, intb_o, - - // DMA Registers Outputs - pointer0, pointer0_s, ch0_csr, ch0_txsz, ch0_adr0, ch0_adr1, ch0_am0, ch0_am1, - pointer1, pointer1_s, ch1_csr, ch1_txsz, ch1_adr0, ch1_adr1, ch1_am0, ch1_am1, - pointer2, pointer2_s, ch2_csr, ch2_txsz, ch2_adr0, ch2_adr1, ch2_am0, ch2_am1, - pointer3, pointer3_s, ch3_csr, ch3_txsz, ch3_adr0, ch3_adr1, ch3_am0, ch3_am1, - pointer4, pointer4_s, ch4_csr, ch4_txsz, ch4_adr0, ch4_adr1, ch4_am0, ch4_am1, - pointer5, pointer5_s, ch5_csr, ch5_txsz, ch5_adr0, ch5_adr1, ch5_am0, ch5_am1, - pointer6, pointer6_s, ch6_csr, ch6_txsz, ch6_adr0, ch6_adr1, ch6_am0, ch6_am1, - pointer7, pointer7_s, ch7_csr, ch7_txsz, ch7_adr0, ch7_adr1, ch7_am0, ch7_am1, - pointer8, pointer8_s, ch8_csr, ch8_txsz, ch8_adr0, ch8_adr1, ch8_am0, ch8_am1, - pointer9, pointer9_s, ch9_csr, ch9_txsz, ch9_adr0, ch9_adr1, ch9_am0, ch9_am1, - pointer10, pointer10_s, ch10_csr, ch10_txsz, ch10_adr0, ch10_adr1, ch10_am0, ch10_am1, - pointer11, pointer11_s, ch11_csr, ch11_txsz, ch11_adr0, ch11_adr1, ch11_am0, ch11_am1, - pointer12, pointer12_s, ch12_csr, ch12_txsz, ch12_adr0, ch12_adr1, ch12_am0, ch12_am1, - pointer13, pointer13_s, ch13_csr, ch13_txsz, ch13_adr0, ch13_adr1, ch13_am0, ch13_am1, - pointer14, pointer14_s, ch14_csr, ch14_txsz, ch14_adr0, ch14_adr1, ch14_am0, ch14_am1, - pointer15, pointer15_s, ch15_csr, ch15_txsz, ch15_adr0, ch15_adr1, ch15_am0, ch15_am1, - pointer16, pointer16_s, ch16_csr, ch16_txsz, ch16_adr0, ch16_adr1, ch16_am0, ch16_am1, - pointer17, pointer17_s, ch17_csr, ch17_txsz, ch17_adr0, ch17_adr1, ch17_am0, ch17_am1, - pointer18, pointer18_s, ch18_csr, ch18_txsz, ch18_adr0, ch18_adr1, ch18_am0, ch18_am1, - pointer19, pointer19_s, ch19_csr, ch19_txsz, ch19_adr0, ch19_adr1, ch19_am0, ch19_am1, - pointer20, pointer20_s, ch20_csr, ch20_txsz, ch20_adr0, ch20_adr1, ch20_am0, ch20_am1, - pointer21, pointer21_s, ch21_csr, ch21_txsz, ch21_adr0, ch21_adr1, ch21_am0, ch21_am1, - pointer22, pointer22_s, ch22_csr, ch22_txsz, ch22_adr0, ch22_adr1, ch22_am0, ch22_am1, - pointer23, pointer23_s, ch23_csr, ch23_txsz, ch23_adr0, ch23_adr1, ch23_am0, ch23_am1, - pointer24, pointer24_s, ch24_csr, ch24_txsz, ch24_adr0, ch24_adr1, ch24_am0, ch24_am1, - pointer25, pointer25_s, ch25_csr, ch25_txsz, ch25_adr0, ch25_adr1, ch25_am0, ch25_am1, - pointer26, pointer26_s, ch26_csr, ch26_txsz, ch26_adr0, ch26_adr1, ch26_am0, ch26_am1, - pointer27, pointer27_s, ch27_csr, ch27_txsz, ch27_adr0, ch27_adr1, ch27_am0, ch27_am1, - pointer28, pointer28_s, ch28_csr, ch28_txsz, ch28_adr0, ch28_adr1, ch28_am0, ch28_am1, - pointer29, pointer29_s, ch29_csr, ch29_txsz, ch29_adr0, ch29_adr1, ch29_am0, ch29_am1, - pointer30, pointer30_s, ch30_csr, ch30_txsz, ch30_adr0, ch30_adr1, ch30_am0, ch30_am1, - - // DMA Registers Write Back Channel Select - ch_sel, ndnr, - - // DMA Engine Status - pause_req, paused, dma_abort, dma_busy, dma_err, dma_done, dma_done_all, - - // DMA Engine Reg File Update ctrl signals - de_csr, de_txsz, de_adr0, de_adr1, - de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we, de_fetch_descr, dma_rest, - ptr_set - ); - -//////////////////////////////////////////////////////////////////// -// -// Module Parameters -// - -// chXX_conf = { CBUF, ED, ARS, EN } -parameter [3:0] ch0_conf = 4'h1; -parameter [3:0] ch1_conf = 4'h0; -parameter [3:0] ch2_conf = 4'h0; -parameter [3:0] ch3_conf = 4'h0; -parameter [3:0] ch4_conf = 4'h0; -parameter [3:0] ch5_conf = 4'h0; -parameter [3:0] ch6_conf = 4'h0; -parameter [3:0] ch7_conf = 4'h0; -parameter [3:0] ch8_conf = 4'h0; -parameter [3:0] ch9_conf = 4'h0; -parameter [3:0] ch10_conf = 4'h0; -parameter [3:0] ch11_conf = 4'h0; -parameter [3:0] ch12_conf = 4'h0; -parameter [3:0] ch13_conf = 4'h0; -parameter [3:0] ch14_conf = 4'h0; -parameter [3:0] ch15_conf = 4'h0; -parameter [3:0] ch16_conf = 4'h0; -parameter [3:0] ch17_conf = 4'h0; -parameter [3:0] ch18_conf = 4'h0; -parameter [3:0] ch19_conf = 4'h0; -parameter [3:0] ch20_conf = 4'h0; -parameter [3:0] ch21_conf = 4'h0; -parameter [3:0] ch22_conf = 4'h0; -parameter [3:0] ch23_conf = 4'h0; -parameter [3:0] ch24_conf = 4'h0; -parameter [3:0] ch25_conf = 4'h0; -parameter [3:0] ch26_conf = 4'h0; -parameter [3:0] ch27_conf = 4'h0; -parameter [3:0] ch28_conf = 4'h0; -parameter [3:0] ch29_conf = 4'h0; -parameter [3:0] ch30_conf = 4'h0; - -//////////////////////////////////////////////////////////////////// -// -// Module IOs -// - -input clk, rst; - -// WISHBONE Access -input [7:0] wb_rf_adr; -input [31:0] wb_rf_din; -output [31:0] wb_rf_dout; -input wb_rf_re; -input wb_rf_we; - -// WISHBONE Interrupt outputs -output inta_o, intb_o; - -// Channel Registers Inputs -output [31:0] pointer0, pointer0_s, ch0_csr, ch0_txsz, ch0_adr0, ch0_adr1, ch0_am0, ch0_am1; -output [31:0] pointer1, pointer1_s, ch1_csr, ch1_txsz, ch1_adr0, ch1_adr1, ch1_am0, ch1_am1; -output [31:0] pointer2, pointer2_s, ch2_csr, ch2_txsz, ch2_adr0, ch2_adr1, ch2_am0, ch2_am1; -output [31:0] pointer3, pointer3_s, ch3_csr, ch3_txsz, ch3_adr0, ch3_adr1, ch3_am0, ch3_am1; -output [31:0] pointer4, pointer4_s, ch4_csr, ch4_txsz, ch4_adr0, ch4_adr1, ch4_am0, ch4_am1; -output [31:0] pointer5, pointer5_s, ch5_csr, ch5_txsz, ch5_adr0, ch5_adr1, ch5_am0, ch5_am1; -output [31:0] pointer6, pointer6_s, ch6_csr, ch6_txsz, ch6_adr0, ch6_adr1, ch6_am0, ch6_am1; -output [31:0] pointer7, pointer7_s, ch7_csr, ch7_txsz, ch7_adr0, ch7_adr1, ch7_am0, ch7_am1; -output [31:0] pointer8, pointer8_s, ch8_csr, ch8_txsz, ch8_adr0, ch8_adr1, ch8_am0, ch8_am1; -output [31:0] pointer9, pointer9_s, ch9_csr, ch9_txsz, ch9_adr0, ch9_adr1, ch9_am0, ch9_am1; -output [31:0] pointer10, pointer10_s, ch10_csr, ch10_txsz, ch10_adr0, ch10_adr1, ch10_am0, ch10_am1; -output [31:0] pointer11, pointer11_s, ch11_csr, ch11_txsz, ch11_adr0, ch11_adr1, ch11_am0, ch11_am1; -output [31:0] pointer12, pointer12_s, ch12_csr, ch12_txsz, ch12_adr0, ch12_adr1, ch12_am0, ch12_am1; -output [31:0] pointer13, pointer13_s, ch13_csr, ch13_txsz, ch13_adr0, ch13_adr1, ch13_am0, ch13_am1; -output [31:0] pointer14, pointer14_s, ch14_csr, ch14_txsz, ch14_adr0, ch14_adr1, ch14_am0, ch14_am1; -output [31:0] pointer15, pointer15_s, ch15_csr, ch15_txsz, ch15_adr0, ch15_adr1, ch15_am0, ch15_am1; -output [31:0] pointer16, pointer16_s, ch16_csr, ch16_txsz, ch16_adr0, ch16_adr1, ch16_am0, ch16_am1; -output [31:0] pointer17, pointer17_s, ch17_csr, ch17_txsz, ch17_adr0, ch17_adr1, ch17_am0, ch17_am1; -output [31:0] pointer18, pointer18_s, ch18_csr, ch18_txsz, ch18_adr0, ch18_adr1, ch18_am0, ch18_am1; -output [31:0] pointer19, pointer19_s, ch19_csr, ch19_txsz, ch19_adr0, ch19_adr1, ch19_am0, ch19_am1; -output [31:0] pointer20, pointer20_s, ch20_csr, ch20_txsz, ch20_adr0, ch20_adr1, ch20_am0, ch20_am1; -output [31:0] pointer21, pointer21_s, ch21_csr, ch21_txsz, ch21_adr0, ch21_adr1, ch21_am0, ch21_am1; -output [31:0] pointer22, pointer22_s, ch22_csr, ch22_txsz, ch22_adr0, ch22_adr1, ch22_am0, ch22_am1; -output [31:0] pointer23, pointer23_s, ch23_csr, ch23_txsz, ch23_adr0, ch23_adr1, ch23_am0, ch23_am1; -output [31:0] pointer24, pointer24_s, ch24_csr, ch24_txsz, ch24_adr0, ch24_adr1, ch24_am0, ch24_am1; -output [31:0] pointer25, pointer25_s, ch25_csr, ch25_txsz, ch25_adr0, ch25_adr1, ch25_am0, ch25_am1; -output [31:0] pointer26, pointer26_s, ch26_csr, ch26_txsz, ch26_adr0, ch26_adr1, ch26_am0, ch26_am1; -output [31:0] pointer27, pointer27_s, ch27_csr, ch27_txsz, ch27_adr0, ch27_adr1, ch27_am0, ch27_am1; -output [31:0] pointer28, pointer28_s, ch28_csr, ch28_txsz, ch28_adr0, ch28_adr1, ch28_am0, ch28_am1; -output [31:0] pointer29, pointer29_s, ch29_csr, ch29_txsz, ch29_adr0, ch29_adr1, ch29_am0, ch29_am1; -output [31:0] pointer30, pointer30_s, ch30_csr, ch30_txsz, ch30_adr0, ch30_adr1, ch30_am0, ch30_am1; - -input [4:0] ch_sel; // Write Back Channel Select -input [30:0] ndnr; // Next Descriptor No Request - -// DMA Engine Abort -output dma_abort; - -// DMA Engine Status -output pause_req; -input paused; -input dma_busy, dma_err, dma_done, dma_done_all; - -// DMA Engine Reg File Update ctrl signals -input [31:0] de_csr; -input [11:0] de_txsz; -input [31:0] de_adr0; -input [31:0] de_adr1; -input de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we, ptr_set; -input de_fetch_descr; -input [30:0] dma_rest; - -//////////////////////////////////////////////////////////////////// -// -// Local Wires and Registers -// - -reg [31:0] wb_rf_dout; -reg inta_o, intb_o; -reg [30:0] int_maska_r, int_maskb_r; -wire [31:0] int_maska, int_maskb; -wire [31:0] int_srca, int_srcb; -wire int_maska_we, int_maskb_we; -wire [30:0] ch_int; -wire csr_we; -wire [31:0] csr; -reg [7:0] csr_r; - -wire [30:0] ch_stop; -wire [30:0] ch_dis; - -wire [31:0] ch0_csr, ch0_txsz, ch0_adr0, ch0_adr1, ch0_am0, ch0_am1; -wire [31:0] ch1_csr, ch1_txsz, ch1_adr0, ch1_adr1, ch1_am0, ch1_am1; -wire [31:0] ch2_csr, ch2_txsz, ch2_adr0, ch2_adr1, ch2_am0, ch2_am1; -wire [31:0] ch3_csr, ch3_txsz, ch3_adr0, ch3_adr1, ch3_am0, ch3_am1; -wire [31:0] ch4_csr, ch4_txsz, ch4_adr0, ch4_adr1, ch4_am0, ch4_am1; -wire [31:0] ch5_csr, ch5_txsz, ch5_adr0, ch5_adr1, ch5_am0, ch5_am1; -wire [31:0] ch6_csr, ch6_txsz, ch6_adr0, ch6_adr1, ch6_am0, ch6_am1; -wire [31:0] ch7_csr, ch7_txsz, ch7_adr0, ch7_adr1, ch7_am0, ch7_am1; -wire [31:0] ch8_csr, ch8_txsz, ch8_adr0, ch8_adr1, ch8_am0, ch8_am1; -wire [31:0] ch9_csr, ch9_txsz, ch9_adr0, ch9_adr1, ch9_am0, ch9_am1; -wire [31:0] ch10_csr, ch10_txsz, ch10_adr0, ch10_adr1, ch10_am0, ch10_am1; -wire [31:0] ch11_csr, ch11_txsz, ch11_adr0, ch11_adr1, ch11_am0, ch11_am1; -wire [31:0] ch12_csr, ch12_txsz, ch12_adr0, ch12_adr1, ch12_am0, ch12_am1; -wire [31:0] ch13_csr, ch13_txsz, ch13_adr0, ch13_adr1, ch13_am0, ch13_am1; -wire [31:0] ch14_csr, ch14_txsz, ch14_adr0, ch14_adr1, ch14_am0, ch14_am1; -wire [31:0] ch15_csr, ch15_txsz, ch15_adr0, ch15_adr1, ch15_am0, ch15_am1; -wire [31:0] ch16_csr, ch16_txsz, ch16_adr0, ch16_adr1, ch16_am0, ch16_am1; -wire [31:0] ch17_csr, ch17_txsz, ch17_adr0, ch17_adr1, ch17_am0, ch17_am1; -wire [31:0] ch18_csr, ch18_txsz, ch18_adr0, ch18_adr1, ch18_am0, ch18_am1; -wire [31:0] ch19_csr, ch19_txsz, ch19_adr0, ch19_adr1, ch19_am0, ch19_am1; -wire [31:0] ch20_csr, ch20_txsz, ch20_adr0, ch20_adr1, ch20_am0, ch20_am1; -wire [31:0] ch21_csr, ch21_txsz, ch21_adr0, ch21_adr1, ch21_am0, ch21_am1; -wire [31:0] ch22_csr, ch22_txsz, ch22_adr0, ch22_adr1, ch22_am0, ch22_am1; -wire [31:0] ch23_csr, ch23_txsz, ch23_adr0, ch23_adr1, ch23_am0, ch23_am1; -wire [31:0] ch24_csr, ch24_txsz, ch24_adr0, ch24_adr1, ch24_am0, ch24_am1; -wire [31:0] ch25_csr, ch25_txsz, ch25_adr0, ch25_adr1, ch25_am0, ch25_am1; -wire [31:0] ch26_csr, ch26_txsz, ch26_adr0, ch26_adr1, ch26_am0, ch26_am1; -wire [31:0] ch27_csr, ch27_txsz, ch27_adr0, ch27_adr1, ch27_am0, ch27_am1; -wire [31:0] ch28_csr, ch28_txsz, ch28_adr0, ch28_adr1, ch28_am0, ch28_am1; -wire [31:0] ch29_csr, ch29_txsz, ch29_adr0, ch29_adr1, ch29_am0, ch29_am1; -wire [31:0] ch30_csr, ch30_txsz, ch30_adr0, ch30_adr1, ch30_am0, ch30_am1; - -wire [31:0] sw_pointer0, sw_pointer1, sw_pointer2, sw_pointer3; -wire [31:0] sw_pointer4, sw_pointer5, sw_pointer6, sw_pointer7; -wire [31:0] sw_pointer8, sw_pointer9, sw_pointer10, sw_pointer11; -wire [31:0] sw_pointer12, sw_pointer13, sw_pointer14, sw_pointer15; -wire [31:0] sw_pointer16, sw_pointer17, sw_pointer18, sw_pointer19; -wire [31:0] sw_pointer20, sw_pointer21, sw_pointer22, sw_pointer23; -wire [31:0] sw_pointer24, sw_pointer25, sw_pointer26, sw_pointer27; -wire [31:0] sw_pointer28, sw_pointer29, sw_pointer30; - -//////////////////////////////////////////////////////////////////// -// -// Aliases -// - -assign int_maska = {1'h0, int_maska_r}; -assign int_maskb = {1'h0, int_maskb_r}; -assign csr = {31'h0, paused}; - -//////////////////////////////////////////////////////////////////// -// -// Misc Logic -// - -assign dma_abort = |ch_stop; -assign pause_req = csr_r[0]; - -//////////////////////////////////////////////////////////////////// -// -// WISHBONE Register Read Logic -// - -always @(posedge clk) - case(wb_rf_adr) // synopsys parallel_case full_case - 8'h0: wb_rf_dout <= #1 csr; - 8'h1: wb_rf_dout <= #1 int_maska; - 8'h2: wb_rf_dout <= #1 int_maskb; - 8'h3: wb_rf_dout <= #1 int_srca; - 8'h4: wb_rf_dout <= #1 int_srcb; - - 8'h8: wb_rf_dout <= #1 ch0_csr; - 8'h9: wb_rf_dout <= #1 ch0_txsz; - 8'ha: wb_rf_dout <= #1 ch0_adr0; - 8'hb: wb_rf_dout <= #1 ch0_am0; - 8'hc: wb_rf_dout <= #1 ch0_adr1; - 8'hd: wb_rf_dout <= #1 ch0_am1; - 8'he: wb_rf_dout <= #1 pointer0; - 8'hf: wb_rf_dout <= #1 sw_pointer0; - - 8'h10: wb_rf_dout <= #1 ch1_conf[0] ? ch1_csr : 32'h0; - 8'h11: wb_rf_dout <= #1 ch1_conf[0] ? ch1_txsz : 32'h0; - 8'h12: wb_rf_dout <= #1 ch1_conf[0] ? ch1_adr0 : 32'h0; - 8'h13: wb_rf_dout <= #1 ch1_conf[0] ? ch1_am0 : 32'h0; - 8'h14: wb_rf_dout <= #1 ch1_conf[0] ? ch1_adr1 : 32'h0; - 8'h15: wb_rf_dout <= #1 ch1_conf[0] ? ch1_am1 : 32'h0; - 8'h16: wb_rf_dout <= #1 ch1_conf[0] ? pointer1 : 32'h0; - 8'h17: wb_rf_dout <= #1 ch1_conf[0] ? sw_pointer1 : 32'h0; - - 8'h18: wb_rf_dout <= #1 ch2_conf[0] ? ch2_csr : 32'h0; - 8'h19: wb_rf_dout <= #1 ch2_conf[0] ? ch2_txsz : 32'h0; - 8'h1a: wb_rf_dout <= #1 ch2_conf[0] ? ch2_adr0 : 32'h0; - 8'h1b: wb_rf_dout <= #1 ch2_conf[0] ? ch2_am0 : 32'h0; - 8'h1c: wb_rf_dout <= #1 ch2_conf[0] ? ch2_adr1 : 32'h0; - 8'h1d: wb_rf_dout <= #1 ch2_conf[0] ? ch2_am1 : 32'h0; - 8'h1e: wb_rf_dout <= #1 ch2_conf[0] ? pointer2 : 32'h0; - 8'h1f: wb_rf_dout <= #1 ch2_conf[0] ? sw_pointer2 : 32'h0; - - 8'h20: wb_rf_dout <= #1 ch3_conf[0] ? ch3_csr : 32'h0; - 8'h21: wb_rf_dout <= #1 ch3_conf[0] ? ch3_txsz : 32'h0; - 8'h22: wb_rf_dout <= #1 ch3_conf[0] ? ch3_adr0 : 32'h0; - 8'h23: wb_rf_dout <= #1 ch3_conf[0] ? ch3_am0 : 32'h0; - 8'h24: wb_rf_dout <= #1 ch3_conf[0] ? ch3_adr1 : 32'h0; - 8'h25: wb_rf_dout <= #1 ch3_conf[0] ? ch3_am1 : 32'h0; - 8'h26: wb_rf_dout <= #1 ch3_conf[0] ? pointer3 : 32'h0; - 8'h27: wb_rf_dout <= #1 ch3_conf[0] ? sw_pointer3 : 32'h0; - - 8'h28: wb_rf_dout <= #1 ch4_conf[0] ? ch4_csr : 32'h0; - 8'h29: wb_rf_dout <= #1 ch4_conf[0] ? ch4_txsz : 32'h0; - 8'h2a: wb_rf_dout <= #1 ch4_conf[0] ? ch4_adr0 : 32'h0; - 8'h2b: wb_rf_dout <= #1 ch4_conf[0] ? ch4_am0 : 32'h0; - 8'h2c: wb_rf_dout <= #1 ch4_conf[0] ? ch4_adr1 : 32'h0; - 8'h2d: wb_rf_dout <= #1 ch4_conf[0] ? ch4_am1 : 32'h0; - 8'h2e: wb_rf_dout <= #1 ch4_conf[0] ? pointer4 : 32'h0; - 8'h2f: wb_rf_dout <= #1 ch4_conf[0] ? sw_pointer4 : 32'h0; - - 8'h30: wb_rf_dout <= #1 ch5_conf[0] ? ch5_csr : 32'h0; - 8'h31: wb_rf_dout <= #1 ch5_conf[0] ? ch5_txsz : 32'h0; - 8'h32: wb_rf_dout <= #1 ch5_conf[0] ? ch5_adr0 : 32'h0; - 8'h33: wb_rf_dout <= #1 ch5_conf[0] ? ch5_am0 : 32'h0; - 8'h34: wb_rf_dout <= #1 ch5_conf[0] ? ch5_adr1 : 32'h0; - 8'h35: wb_rf_dout <= #1 ch5_conf[0] ? ch5_am1 : 32'h0; - 8'h36: wb_rf_dout <= #1 ch5_conf[0] ? pointer5 : 32'h0; - 8'h37: wb_rf_dout <= #1 ch5_conf[0] ? sw_pointer5 : 32'h0; - - 8'h38: wb_rf_dout <= #1 ch6_conf[0] ? ch6_csr : 32'h0; - 8'h39: wb_rf_dout <= #1 ch6_conf[0] ? ch6_txsz : 32'h0; - 8'h3a: wb_rf_dout <= #1 ch6_conf[0] ? ch6_adr0 : 32'h0; - 8'h3b: wb_rf_dout <= #1 ch6_conf[0] ? ch6_am0 : 32'h0; - 8'h3c: wb_rf_dout <= #1 ch6_conf[0] ? ch6_adr1 : 32'h0; - 8'h3d: wb_rf_dout <= #1 ch6_conf[0] ? ch6_am1 : 32'h0; - 8'h3e: wb_rf_dout <= #1 ch6_conf[0] ? pointer6 : 32'h0; - 8'h3f: wb_rf_dout <= #1 ch6_conf[0] ? sw_pointer6 : 32'h0; - - 8'h40: wb_rf_dout <= #1 ch7_conf[0] ? ch7_csr : 32'h0; - 8'h41: wb_rf_dout <= #1 ch7_conf[0] ? ch7_txsz : 32'h0; - 8'h42: wb_rf_dout <= #1 ch7_conf[0] ? ch7_adr0 : 32'h0; - 8'h43: wb_rf_dout <= #1 ch7_conf[0] ? ch7_am0 : 32'h0; - 8'h44: wb_rf_dout <= #1 ch7_conf[0] ? ch7_adr1 : 32'h0; - 8'h45: wb_rf_dout <= #1 ch7_conf[0] ? ch7_am1 : 32'h0; - 8'h46: wb_rf_dout <= #1 ch7_conf[0] ? pointer7 : 32'h0; - 8'h47: wb_rf_dout <= #1 ch7_conf[0] ? sw_pointer7 : 32'h0; - - 8'h48: wb_rf_dout <= #1 ch8_conf[0] ? ch8_csr : 32'h0; - 8'h49: wb_rf_dout <= #1 ch8_conf[0] ? ch8_txsz : 32'h0; - 8'h4a: wb_rf_dout <= #1 ch8_conf[0] ? ch8_adr0 : 32'h0; - 8'h4b: wb_rf_dout <= #1 ch8_conf[0] ? ch8_am0 : 32'h0; - 8'h4c: wb_rf_dout <= #1 ch8_conf[0] ? ch8_adr1 : 32'h0; - 8'h4d: wb_rf_dout <= #1 ch8_conf[0] ? ch8_am1 : 32'h0; - 8'h4e: wb_rf_dout <= #1 ch8_conf[0] ? pointer8 : 32'h0; - 8'h4f: wb_rf_dout <= #1 ch8_conf[0] ? sw_pointer8 : 32'h0; - - 8'h50: wb_rf_dout <= #1 ch9_conf[0] ? ch9_csr : 32'h0; - 8'h51: wb_rf_dout <= #1 ch9_conf[0] ? ch9_txsz : 32'h0; - 8'h52: wb_rf_dout <= #1 ch9_conf[0] ? ch9_adr0 : 32'h0; - 8'h53: wb_rf_dout <= #1 ch9_conf[0] ? ch9_am0 : 32'h0; - 8'h54: wb_rf_dout <= #1 ch9_conf[0] ? ch9_adr1 : 32'h0; - 8'h55: wb_rf_dout <= #1 ch9_conf[0] ? ch9_am1 : 32'h0; - 8'h56: wb_rf_dout <= #1 ch9_conf[0] ? pointer9 : 32'h0; - 8'h57: wb_rf_dout <= #1 ch9_conf[0] ? sw_pointer9 : 32'h0; - - 8'h58: wb_rf_dout <= #1 ch10_conf[0] ? ch10_csr : 32'h0; - 8'h59: wb_rf_dout <= #1 ch10_conf[0] ? ch10_txsz : 32'h0; - 8'h5a: wb_rf_dout <= #1 ch10_conf[0] ? ch10_adr0 : 32'h0; - 8'h5b: wb_rf_dout <= #1 ch10_conf[0] ? ch10_am0 : 32'h0; - 8'h5c: wb_rf_dout <= #1 ch10_conf[0] ? ch10_adr1 : 32'h0; - 8'h5d: wb_rf_dout <= #1 ch10_conf[0] ? ch10_am1 : 32'h0; - 8'h5e: wb_rf_dout <= #1 ch10_conf[0] ? pointer10 : 32'h0; - 8'h5f: wb_rf_dout <= #1 ch10_conf[0] ? sw_pointer10 : 32'h0; - - 8'h60: wb_rf_dout <= #1 ch11_conf[0] ? ch11_csr : 32'h0; - 8'h61: wb_rf_dout <= #1 ch11_conf[0] ? ch11_txsz : 32'h0; - 8'h62: wb_rf_dout <= #1 ch11_conf[0] ? ch11_adr0 : 32'h0; - 8'h63: wb_rf_dout <= #1 ch11_conf[0] ? ch11_am0 : 32'h0; - 8'h64: wb_rf_dout <= #1 ch11_conf[0] ? ch11_adr1 : 32'h0; - 8'h65: wb_rf_dout <= #1 ch11_conf[0] ? ch11_am1 : 32'h0; - 8'h66: wb_rf_dout <= #1 ch11_conf[0] ? pointer11 : 32'h0; - 8'h67: wb_rf_dout <= #1 ch11_conf[0] ? sw_pointer11 : 32'h0; - - 8'h68: wb_rf_dout <= #1 ch12_conf[0] ? ch12_csr : 32'h0; - 8'h69: wb_rf_dout <= #1 ch12_conf[0] ? ch12_txsz : 32'h0; - 8'h6a: wb_rf_dout <= #1 ch12_conf[0] ? ch12_adr0 : 32'h0; - 8'h6b: wb_rf_dout <= #1 ch12_conf[0] ? ch12_am0 : 32'h0; - 8'h6c: wb_rf_dout <= #1 ch12_conf[0] ? ch12_adr1 : 32'h0; - 8'h6d: wb_rf_dout <= #1 ch12_conf[0] ? ch12_am1 : 32'h0; - 8'h6e: wb_rf_dout <= #1 ch12_conf[0] ? pointer12 : 32'h0; - 8'h6f: wb_rf_dout <= #1 ch12_conf[0] ? sw_pointer12 : 32'h0; - - 8'h70: wb_rf_dout <= #1 ch13_conf[0] ? ch13_csr : 32'h0; - 8'h71: wb_rf_dout <= #1 ch13_conf[0] ? ch13_txsz : 32'h0; - 8'h72: wb_rf_dout <= #1 ch13_conf[0] ? ch13_adr0 : 32'h0; - 8'h73: wb_rf_dout <= #1 ch13_conf[0] ? ch13_am0 : 32'h0; - 8'h74: wb_rf_dout <= #1 ch13_conf[0] ? ch13_adr1 : 32'h0; - 8'h75: wb_rf_dout <= #1 ch13_conf[0] ? ch13_am1 : 32'h0; - 8'h76: wb_rf_dout <= #1 ch13_conf[0] ? pointer13 : 32'h0; - 8'h77: wb_rf_dout <= #1 ch13_conf[0] ? sw_pointer13 : 32'h0; - - 8'h78: wb_rf_dout <= #1 ch14_conf[0] ? ch14_csr : 32'h0; - 8'h79: wb_rf_dout <= #1 ch14_conf[0] ? ch14_txsz : 32'h0; - 8'h7a: wb_rf_dout <= #1 ch14_conf[0] ? ch14_adr0 : 32'h0; - 8'h7b: wb_rf_dout <= #1 ch14_conf[0] ? ch14_am0 : 32'h0; - 8'h7c: wb_rf_dout <= #1 ch14_conf[0] ? ch14_adr1 : 32'h0; - 8'h7d: wb_rf_dout <= #1 ch14_conf[0] ? ch14_am1 : 32'h0; - 8'h7e: wb_rf_dout <= #1 ch14_conf[0] ? pointer14 : 32'h0; - 8'h7f: wb_rf_dout <= #1 ch14_conf[0] ? sw_pointer14 : 32'h0; - - 8'h80: wb_rf_dout <= #1 ch15_conf[0] ? ch15_csr : 32'h0; - 8'h81: wb_rf_dout <= #1 ch15_conf[0] ? ch15_txsz : 32'h0; - 8'h82: wb_rf_dout <= #1 ch15_conf[0] ? ch15_adr0 : 32'h0; - 8'h83: wb_rf_dout <= #1 ch15_conf[0] ? ch15_am0 : 32'h0; - 8'h84: wb_rf_dout <= #1 ch15_conf[0] ? ch15_adr1 : 32'h0; - 8'h85: wb_rf_dout <= #1 ch15_conf[0] ? ch15_am1 : 32'h0; - 8'h86: wb_rf_dout <= #1 ch15_conf[0] ? pointer15 : 32'h0; - 8'h87: wb_rf_dout <= #1 ch15_conf[0] ? sw_pointer15 : 32'h0; - - 8'h88: wb_rf_dout <= #1 ch16_conf[0] ? ch16_csr : 32'h0; - 8'h89: wb_rf_dout <= #1 ch16_conf[0] ? ch16_txsz : 32'h0; - 8'h8a: wb_rf_dout <= #1 ch16_conf[0] ? ch16_adr0 : 32'h0; - 8'h8b: wb_rf_dout <= #1 ch16_conf[0] ? ch16_am0 : 32'h0; - 8'h8c: wb_rf_dout <= #1 ch16_conf[0] ? ch16_adr1 : 32'h0; - 8'h8d: wb_rf_dout <= #1 ch16_conf[0] ? ch16_am1 : 32'h0; - 8'h8e: wb_rf_dout <= #1 ch16_conf[0] ? pointer16 : 32'h0; - 8'h8f: wb_rf_dout <= #1 ch16_conf[0] ? sw_pointer16 : 32'h0; - - 8'h90: wb_rf_dout <= #1 ch17_conf[0] ? ch17_csr : 32'h0; - 8'h91: wb_rf_dout <= #1 ch17_conf[0] ? ch17_txsz : 32'h0; - 8'h92: wb_rf_dout <= #1 ch17_conf[0] ? ch17_adr0 : 32'h0; - 8'h93: wb_rf_dout <= #1 ch17_conf[0] ? ch17_am0 : 32'h0; - 8'h94: wb_rf_dout <= #1 ch17_conf[0] ? ch17_adr1 : 32'h0; - 8'h95: wb_rf_dout <= #1 ch17_conf[0] ? ch17_am1 : 32'h0; - 8'h96: wb_rf_dout <= #1 ch17_conf[0] ? pointer17 : 32'h0; - 8'h97: wb_rf_dout <= #1 ch17_conf[0] ? sw_pointer17 : 32'h0; - - 8'h98: wb_rf_dout <= #1 ch18_conf[0] ? ch18_csr : 32'h0; - 8'h99: wb_rf_dout <= #1 ch18_conf[0] ? ch18_txsz : 32'h0; - 8'h9a: wb_rf_dout <= #1 ch18_conf[0] ? ch18_adr0 : 32'h0; - 8'h9b: wb_rf_dout <= #1 ch18_conf[0] ? ch18_am0 : 32'h0; - 8'h9c: wb_rf_dout <= #1 ch18_conf[0] ? ch18_adr1 : 32'h0; - 8'h9d: wb_rf_dout <= #1 ch18_conf[0] ? ch18_am1 : 32'h0; - 8'h9e: wb_rf_dout <= #1 ch18_conf[0] ? pointer18 : 32'h0; - 8'h9f: wb_rf_dout <= #1 ch18_conf[0] ? sw_pointer18 : 32'h0; - - 8'ha0: wb_rf_dout <= #1 ch19_conf[0] ? ch19_csr : 32'h0; - 8'ha1: wb_rf_dout <= #1 ch19_conf[0] ? ch19_txsz : 32'h0; - 8'ha2: wb_rf_dout <= #1 ch19_conf[0] ? ch19_adr0 : 32'h0; - 8'ha3: wb_rf_dout <= #1 ch19_conf[0] ? ch19_am0 : 32'h0; - 8'ha4: wb_rf_dout <= #1 ch19_conf[0] ? ch19_adr1 : 32'h0; - 8'ha5: wb_rf_dout <= #1 ch19_conf[0] ? ch19_am1 : 32'h0; - 8'ha6: wb_rf_dout <= #1 ch19_conf[0] ? pointer19 : 32'h0; - 8'ha7: wb_rf_dout <= #1 ch19_conf[0] ? sw_pointer19 : 32'h0; - - 8'ha8: wb_rf_dout <= #1 ch20_conf[0] ? ch20_csr : 32'h0; - 8'ha9: wb_rf_dout <= #1 ch20_conf[0] ? ch20_txsz : 32'h0; - 8'haa: wb_rf_dout <= #1 ch20_conf[0] ? ch20_adr0 : 32'h0; - 8'hab: wb_rf_dout <= #1 ch20_conf[0] ? ch20_am0 : 32'h0; - 8'hac: wb_rf_dout <= #1 ch20_conf[0] ? ch20_adr1 : 32'h0; - 8'had: wb_rf_dout <= #1 ch20_conf[0] ? ch20_am1 : 32'h0; - 8'hae: wb_rf_dout <= #1 ch20_conf[0] ? pointer20 : 32'h0; - 8'haf: wb_rf_dout <= #1 ch20_conf[0] ? sw_pointer20 : 32'h0; - - 8'hb0: wb_rf_dout <= #1 ch21_conf[0] ? ch21_csr : 32'h0; - 8'hb1: wb_rf_dout <= #1 ch21_conf[0] ? ch21_txsz : 32'h0; - 8'hb2: wb_rf_dout <= #1 ch21_conf[0] ? ch21_adr0 : 32'h0; - 8'hb3: wb_rf_dout <= #1 ch21_conf[0] ? ch21_am0 : 32'h0; - 8'hb4: wb_rf_dout <= #1 ch21_conf[0] ? ch21_adr1 : 32'h0; - 8'hb5: wb_rf_dout <= #1 ch21_conf[0] ? ch21_am1 : 32'h0; - 8'hb6: wb_rf_dout <= #1 ch21_conf[0] ? pointer21 : 32'h0; - 8'hb7: wb_rf_dout <= #1 ch21_conf[0] ? sw_pointer21 : 32'h0; - - 8'hb8: wb_rf_dout <= #1 ch22_conf[0] ? ch22_csr : 32'h0; - 8'hb9: wb_rf_dout <= #1 ch22_conf[0] ? ch22_txsz : 32'h0; - 8'hba: wb_rf_dout <= #1 ch22_conf[0] ? ch22_adr0 : 32'h0; - 8'hbb: wb_rf_dout <= #1 ch22_conf[0] ? ch22_am0 : 32'h0; - 8'hbc: wb_rf_dout <= #1 ch22_conf[0] ? ch22_adr1 : 32'h0; - 8'hbd: wb_rf_dout <= #1 ch22_conf[0] ? ch22_am1 : 32'h0; - 8'hbe: wb_rf_dout <= #1 ch22_conf[0] ? pointer22 : 32'h0; - 8'hbf: wb_rf_dout <= #1 ch22_conf[0] ? sw_pointer22 : 32'h0; - - 8'hc0: wb_rf_dout <= #1 ch23_conf[0] ? ch23_csr : 32'h0; - 8'hc1: wb_rf_dout <= #1 ch23_conf[0] ? ch23_txsz : 32'h0; - 8'hc2: wb_rf_dout <= #1 ch23_conf[0] ? ch23_adr0 : 32'h0; - 8'hc3: wb_rf_dout <= #1 ch23_conf[0] ? ch23_am0 : 32'h0; - 8'hc4: wb_rf_dout <= #1 ch23_conf[0] ? ch23_adr1 : 32'h0; - 8'hc5: wb_rf_dout <= #1 ch23_conf[0] ? ch23_am1 : 32'h0; - 8'hc6: wb_rf_dout <= #1 ch23_conf[0] ? pointer23 : 32'h0; - 8'hc7: wb_rf_dout <= #1 ch23_conf[0] ? sw_pointer23 : 32'h0; - - 8'hc8: wb_rf_dout <= #1 ch24_conf[0] ? ch24_csr : 32'h0; - 8'hc9: wb_rf_dout <= #1 ch24_conf[0] ? ch24_txsz : 32'h0; - 8'hca: wb_rf_dout <= #1 ch24_conf[0] ? ch24_adr0 : 32'h0; - 8'hcb: wb_rf_dout <= #1 ch24_conf[0] ? ch24_am0 : 32'h0; - 8'hcc: wb_rf_dout <= #1 ch24_conf[0] ? ch24_adr1 : 32'h0; - 8'hcd: wb_rf_dout <= #1 ch24_conf[0] ? ch24_am1 : 32'h0; - 8'hce: wb_rf_dout <= #1 ch24_conf[0] ? pointer24 : 32'h0; - 8'hcf: wb_rf_dout <= #1 ch24_conf[0] ? sw_pointer24 : 32'h0; - - 8'hd0: wb_rf_dout <= #1 ch25_conf[0] ? ch25_csr : 32'h0; - 8'hd1: wb_rf_dout <= #1 ch25_conf[0] ? ch25_txsz : 32'h0; - 8'hd2: wb_rf_dout <= #1 ch25_conf[0] ? ch25_adr0 : 32'h0; - 8'hd3: wb_rf_dout <= #1 ch25_conf[0] ? ch25_am0 : 32'h0; - 8'hd4: wb_rf_dout <= #1 ch25_conf[0] ? ch25_adr1 : 32'h0; - 8'hd5: wb_rf_dout <= #1 ch25_conf[0] ? ch25_am1 : 32'h0; - 8'hd6: wb_rf_dout <= #1 ch25_conf[0] ? pointer25 : 32'h0; - 8'hd7: wb_rf_dout <= #1 ch25_conf[0] ? sw_pointer25 : 32'h0; - - 8'hd8: wb_rf_dout <= #1 ch26_conf[0] ? ch26_csr : 32'h0; - 8'hd9: wb_rf_dout <= #1 ch26_conf[0] ? ch26_txsz : 32'h0; - 8'hda: wb_rf_dout <= #1 ch26_conf[0] ? ch26_adr0 : 32'h0; - 8'hdb: wb_rf_dout <= #1 ch26_conf[0] ? ch26_am0 : 32'h0; - 8'hdc: wb_rf_dout <= #1 ch26_conf[0] ? ch26_adr1 : 32'h0; - 8'hdd: wb_rf_dout <= #1 ch26_conf[0] ? ch26_am1 : 32'h0; - 8'hde: wb_rf_dout <= #1 ch26_conf[0] ? pointer26 : 32'h0; - 8'hdf: wb_rf_dout <= #1 ch26_conf[0] ? sw_pointer26 : 32'h0; - - 8'he0: wb_rf_dout <= #1 ch27_conf[0] ? ch27_csr : 32'h0; - 8'he1: wb_rf_dout <= #1 ch27_conf[0] ? ch27_txsz : 32'h0; - 8'he2: wb_rf_dout <= #1 ch27_conf[0] ? ch27_adr0 : 32'h0; - 8'he3: wb_rf_dout <= #1 ch27_conf[0] ? ch27_am0 : 32'h0; - 8'he4: wb_rf_dout <= #1 ch27_conf[0] ? ch27_adr1 : 32'h0; - 8'he5: wb_rf_dout <= #1 ch27_conf[0] ? ch27_am1 : 32'h0; - 8'he6: wb_rf_dout <= #1 ch27_conf[0] ? pointer27 : 32'h0; - 8'he7: wb_rf_dout <= #1 ch27_conf[0] ? sw_pointer27 : 32'h0; - - 8'he8: wb_rf_dout <= #1 ch28_conf[0] ? ch28_csr : 32'h0; - 8'he9: wb_rf_dout <= #1 ch28_conf[0] ? ch28_txsz : 32'h0; - 8'hea: wb_rf_dout <= #1 ch28_conf[0] ? ch28_adr0 : 32'h0; - 8'heb: wb_rf_dout <= #1 ch28_conf[0] ? ch28_am0 : 32'h0; - 8'hec: wb_rf_dout <= #1 ch28_conf[0] ? ch28_adr1 : 32'h0; - 8'hed: wb_rf_dout <= #1 ch28_conf[0] ? ch28_am1 : 32'h0; - 8'hee: wb_rf_dout <= #1 ch28_conf[0] ? pointer28 : 32'h0; - 8'hef: wb_rf_dout <= #1 ch28_conf[0] ? sw_pointer28 : 32'h0; - - 8'hf0: wb_rf_dout <= #1 ch29_conf[0] ? ch29_csr : 32'h0; - 8'hf1: wb_rf_dout <= #1 ch29_conf[0] ? ch29_txsz : 32'h0; - 8'hf2: wb_rf_dout <= #1 ch29_conf[0] ? ch29_adr0 : 32'h0; - 8'hf3: wb_rf_dout <= #1 ch29_conf[0] ? ch29_am0 : 32'h0; - 8'hf4: wb_rf_dout <= #1 ch29_conf[0] ? ch29_adr1 : 32'h0; - 8'hf5: wb_rf_dout <= #1 ch29_conf[0] ? ch29_am1 : 32'h0; - 8'hf6: wb_rf_dout <= #1 ch29_conf[0] ? pointer29 : 32'h0; - 8'hf7: wb_rf_dout <= #1 ch29_conf[0] ? sw_pointer29 : 32'h0; - - 8'hf8: wb_rf_dout <= #1 ch30_conf[0] ? ch30_csr : 32'h0; - 8'hf9: wb_rf_dout <= #1 ch30_conf[0] ? ch30_txsz : 32'h0; - 8'hfa: wb_rf_dout <= #1 ch30_conf[0] ? ch30_adr0 : 32'h0; - 8'hfb: wb_rf_dout <= #1 ch30_conf[0] ? ch30_am0 : 32'h0; - 8'hfc: wb_rf_dout <= #1 ch30_conf[0] ? ch30_adr1 : 32'h0; - 8'hfd: wb_rf_dout <= #1 ch30_conf[0] ? ch30_am1 : 32'h0; - 8'hfe: wb_rf_dout <= #1 ch30_conf[0] ? pointer30 : 32'h0; - 8'hff: wb_rf_dout <= #1 ch30_conf[0] ? sw_pointer30 : 32'h0; - - endcase - - -//////////////////////////////////////////////////////////////////// -// -// WISHBONE Register Write Logic -// And DMA Engine register Update Logic -// - -// Global Registers -assign csr_we = wb_rf_we & (wb_rf_adr == 8'h0); -assign int_maska_we = wb_rf_we & (wb_rf_adr == 8'h1); -assign int_maskb_we = wb_rf_we & (wb_rf_adr == 8'h2); - -// --------------------------------------------------- - -always @(posedge clk or negedge rst) - if(!rst) csr_r <= #1 8'h0; - else - if(csr_we) csr_r <= #1 wb_rf_din[7:0]; - -// --------------------------------------------------- -// INT_MASK -always @(posedge clk or negedge rst) - if(!rst) int_maska_r <= #1 31'h0; - else - if(int_maska_we) int_maska_r <= #1 wb_rf_din[30:0]; - -always @(posedge clk or negedge rst) - if(!rst) int_maskb_r <= #1 31'h0; - else - if(int_maskb_we) int_maskb_r <= #1 wb_rf_din[30:0]; - -//////////////////////////////////////////////////////////////////// -// -// Interrupts -// - -assign int_srca = {1'b0, (int_maska_r & ch_int) }; -assign int_srcb = {1'b0, (int_maskb_r & ch_int) }; - -// Interrupt Outputs -always @(posedge clk) - inta_o <= #1 |int_srca; - -always @(posedge clk) - intb_o <= #1 |int_srcb; - -//////////////////////////////////////////////////////////////////// -// -// Channel Register File -// - -// chXX_conf = { CBUF, ED, ARS, EN } - -wb_dma_ch_rf #(0, ch0_conf[0], ch0_conf[1], ch0_conf[2], ch0_conf[3]) u0( - .clk( clk ), - .rst( rst ), - .pointer( pointer0 ), - .pointer_s( pointer0_s ), - .ch_csr( ch0_csr ), - .ch_txsz( ch0_txsz ), - .ch_adr0( ch0_adr0 ), - .ch_adr1( ch0_adr1 ), - .ch_am0( ch0_am0 ), - .ch_am1( ch0_am1 ), - .sw_pointer( sw_pointer0 ), - .ch_stop( ch_stop[0] ), - .ch_dis( ch_dis[0] ), - .int( ch_int[0] ), - .wb_rf_din( wb_rf_din ), - .wb_rf_adr( wb_rf_adr ), - .wb_rf_we( wb_rf_we ), - .wb_rf_re( wb_rf_re ), - .ch_sel( ch_sel ), - .ndnr( ndnr[0] ), - .dma_busy( dma_busy ), - .dma_err( dma_err ), - .dma_done( dma_done ), - .dma_done_all( dma_done_all ), - .de_csr( de_csr ), - .de_txsz( de_txsz ), - .de_adr0( de_adr0 ), - .de_adr1( de_adr1 ), - .de_csr_we( de_csr_we ), - .de_txsz_we( de_txsz_we ), - .de_adr0_we( de_adr0_we ), - .de_adr1_we( de_adr1_we ), - .de_fetch_descr(de_fetch_descr ), - .dma_rest( dma_rest[0] ), - .ptr_set( ptr_set ) - ); - -wb_dma_ch_rf #(1, ch1_conf[0], ch1_conf[1], ch1_conf[2], ch1_conf[3]) u1( - .clk( clk ), - .rst( rst ), - .pointer( pointer1 ), - .pointer_s( pointer1_s ), - .ch_csr( ch1_csr ), - .ch_txsz( ch1_txsz ), - .ch_adr0( ch1_adr0 ), - .ch_adr1( ch1_adr1 ), - .ch_am0( ch1_am0 ), - .ch_am1( ch1_am1 ), - .sw_pointer( sw_pointer1 ), - .ch_stop( ch_stop[1] ), - .ch_dis( ch_dis[1] ), - .int( ch_int[1] ), - .wb_rf_din( wb_rf_din ), - .wb_rf_adr( wb_rf_adr ), - .wb_rf_we( wb_rf_we ), - .wb_rf_re( wb_rf_re ), - .ch_sel( ch_sel ), - .ndnr( ndnr[1] ), - .dma_busy( dma_busy ), - .dma_err( dma_err ), - .dma_done( dma_done ), - .dma_done_all( dma_done_all ), - .de_csr( de_csr ), - .de_txsz( de_txsz ), - .de_adr0( de_adr0 ), - .de_adr1( de_adr1 ), - .de_csr_we( de_csr_we ), - .de_txsz_we( de_txsz_we ), - .de_adr0_we( de_adr0_we ), - .de_adr1_we( de_adr1_we ), - .de_fetch_descr(de_fetch_descr ), - .dma_rest( dma_rest[1] ), - .ptr_set( ptr_set ) - ); - -wb_dma_ch_rf #(2, ch2_conf[0], ch2_conf[1], ch2_conf[2], ch2_conf[3]) u2( - .clk( clk ), - .rst( rst ), - .pointer( pointer2 ), - .pointer_s( pointer2_s ), - .ch_csr( ch2_csr ), - .ch_txsz( ch2_txsz ), - .ch_adr0( ch2_adr0 ), - .ch_adr1( ch2_adr1 ), - .ch_am0( ch2_am0 ), - .ch_am1( ch2_am1 ), - .sw_pointer( sw_pointer2 ), - .ch_stop( ch_stop[2] ), - .ch_dis( ch_dis[2] ), - .int( ch_int[2] ), - .wb_rf_din( wb_rf_din ), - .wb_rf_adr( wb_rf_adr ), - .wb_rf_we( wb_rf_we ), - .wb_rf_re( wb_rf_re ), - .ch_sel( ch_sel ), - .ndnr( ndnr[2] ), - .dma_busy( dma_busy ), - .dma_err( dma_err ), - .dma_done( dma_done ), - .dma_done_all( dma_done_all ), - .de_csr( de_csr ), - .de_txsz( de_txsz ), - .de_adr0( de_adr0 ), - .de_adr1( de_adr1 ), - .de_csr_we( de_csr_we ), - .de_txsz_we( de_txsz_we ), - .de_adr0_we( de_adr0_we ), - .de_adr1_we( de_adr1_we ), - .de_fetch_descr(de_fetch_descr ), - .dma_rest( dma_rest[2] ), - .ptr_set( ptr_set ) - ); - -wb_dma_ch_rf #(3, ch3_conf[0], ch3_conf[1], ch3_conf[2], ch3_conf[3]) u3( - .clk( clk ), - .rst( rst ), - .pointer( pointer3 ), - .pointer_s( pointer3_s ), - .ch_csr( ch3_csr ), - .ch_txsz( ch3_txsz ), - .ch_adr0( ch3_adr0 ), - .ch_adr1( ch3_adr1 ), - .ch_am0( ch3_am0 ), - .ch_am1( ch3_am1 ), - .sw_pointer( sw_pointer3 ), - .ch_stop( ch_stop[3] ), - .ch_dis( ch_dis[3] ), - .int( ch_int[3] ), - .wb_rf_din( wb_rf_din ), - .wb_rf_adr( wb_rf_adr ), - .wb_rf_we( wb_rf_we ), - .wb_rf_re( wb_rf_re ), - .ch_sel( ch_sel ), - .ndnr( ndnr[3] ), - .dma_busy( dma_busy ), - .dma_err( dma_err ), - .dma_done( dma_done ), - .dma_done_all( dma_done_all ), - .de_csr( de_csr ), - .de_txsz( de_txsz ), - .de_adr0( de_adr0 ), - .de_adr1( de_adr1 ), - .de_csr_we( de_csr_we ), - .de_txsz_we( de_txsz_we ), - .de_adr0_we( de_adr0_we ), - .de_adr1_we( de_adr1_we ), - .de_fetch_descr(de_fetch_descr ), - .dma_rest( dma_rest[3] ), - .ptr_set( ptr_set ) - ); - -wb_dma_ch_rf #(4, ch4_conf[0], ch4_conf[1], ch4_conf[2], ch4_conf[3]) u4( - .clk( clk ), - .rst( rst ), - .pointer( pointer4 ), - .pointer_s( pointer4_s ), - .ch_csr( ch4_csr ), - .ch_txsz( ch4_txsz ), - .ch_adr0( ch4_adr0 ), - .ch_adr1( ch4_adr1 ), - .ch_am0( ch4_am0 ), - .ch_am1( ch4_am1 ), - .sw_pointer( sw_pointer4 ), - .ch_stop( ch_stop[4] ), - .ch_dis( ch_dis[4] ), - .int( ch_int[4] ), - .wb_rf_din( wb_rf_din ), - .wb_rf_adr( wb_rf_adr ), - .wb_rf_we( wb_rf_we ), - .wb_rf_re( wb_rf_re ), - .ch_sel( ch_sel ), - .ndnr( ndnr[4] ), - .dma_busy( dma_busy ), - .dma_err( dma_err ), - .dma_done( dma_done ), - .dma_done_all( dma_done_all ), - .de_csr( de_csr ), - .de_txsz( de_txsz ), - .de_adr0( de_adr0 ), - .de_adr1( de_adr1 ), - .de_csr_we( de_csr_we ), - .de_txsz_we( de_txsz_we ), - .de_adr0_we( de_adr0_we ), - .de_adr1_we( de_adr1_we ), - .de_fetch_descr(de_fetch_descr ), - .dma_rest( dma_rest[4] ), - .ptr_set( ptr_set ) - ); - -wb_dma_ch_rf #(5, ch5_conf[0], ch5_conf[1], ch5_conf[2], ch5_conf[3]) u5( - .clk( clk ), - .rst( rst ), - .pointer( pointer5 ), - .pointer_s( pointer5_s ), - .ch_csr( ch5_csr ), - .ch_txsz( ch5_txsz ), - .ch_adr0( ch5_adr0 ), - .ch_adr1( ch5_adr1 ), - .ch_am0( ch5_am0 ), - .ch_am1( ch5_am1 ), - .sw_pointer( sw_pointer5 ), - .ch_stop( ch_stop[5] ), - .ch_dis( ch_dis[5] ), - .int( ch_int[5] ), - .wb_rf_din( wb_rf_din ), - .wb_rf_adr( wb_rf_adr ), - .wb_rf_we( wb_rf_we ), - .wb_rf_re( wb_rf_re ), - .ch_sel( ch_sel ), - .ndnr( ndnr[5] ), - .dma_busy( dma_busy ), - .dma_err( dma_err ), - .dma_done( dma_done ), - .dma_done_all( dma_done_all ), - .de_csr( de_csr ), - .de_txsz( de_txsz ), - .de_adr0( de_adr0 ), - .de_adr1( de_adr1 ), - .de_csr_we( de_csr_we ), - .de_txsz_we( de_txsz_we ), - .de_adr0_we( de_adr0_we ), - .de_adr1_we( de_adr1_we ), - .de_fetch_descr(de_fetch_descr ), - .dma_rest( dma_rest[5] ), - .ptr_set( ptr_set ) - ); - -wb_dma_ch_rf #(6, ch6_conf[0], ch6_conf[1], ch6_conf[2], ch6_conf[3]) u6( - .clk( clk ), - .rst( rst ), - .pointer( pointer6 ), - .pointer_s( pointer6_s ), - .ch_csr( ch6_csr ), - .ch_txsz( ch6_txsz ), - .ch_adr0( ch6_adr0 ), - .ch_adr1( ch6_adr1 ), - .ch_am0( ch6_am0 ), - .ch_am1( ch6_am1 ), - .sw_pointer( sw_pointer6 ), - .ch_stop( ch_stop[6] ), - .ch_dis( ch_dis[6] ), - .int( ch_int[6] ), - .wb_rf_din( wb_rf_din ), - .wb_rf_adr( wb_rf_adr ), - .wb_rf_we( wb_rf_we ), - .wb_rf_re( wb_rf_re ), - .ch_sel( ch_sel ), - .ndnr( ndnr[6] ), - .dma_busy( dma_busy ), - .dma_err( dma_err ), - .dma_done( dma_done ), - .dma_done_all( dma_done_all ), - .de_csr( de_csr ), - .de_txsz( de_txsz ), - .de_adr0( de_adr0 ), - .de_adr1( de_adr1 ), - .de_csr_we( de_csr_we ), - .de_txsz_we( de_txsz_we ), - .de_adr0_we( de_adr0_we ), - .de_adr1_we( de_adr1_we ), - .de_fetch_descr(de_fetch_descr ), - .dma_rest( dma_rest[6] ), - .ptr_set( ptr_set ) - ); - -wb_dma_ch_rf #(7, ch7_conf[0], ch7_conf[1], ch7_conf[2], ch7_conf[3]) u7( - .clk( clk ), - .rst( rst ), - .pointer( pointer7 ), - .pointer_s( pointer7_s ), - .ch_csr( ch7_csr ), - .ch_txsz( ch7_txsz ), - .ch_adr0( ch7_adr0 ), - .ch_adr1( ch7_adr1 ), - .ch_am0( ch7_am0 ), - .ch_am1( ch7_am1 ), - .sw_pointer( sw_pointer7 ), - .ch_stop( ch_stop[7] ), - .ch_dis( ch_dis[7] ), - .int( ch_int[7] ), - .wb_rf_din( wb_rf_din ), - .wb_rf_adr( wb_rf_adr ), - .wb_rf_we( wb_rf_we ), - .wb_rf_re( wb_rf_re ), - .ch_sel( ch_sel ), - .ndnr( ndnr[7] ), - .dma_busy( dma_busy ), - .dma_err( dma_err ), - .dma_done( dma_done ), - .dma_done_all( dma_done_all ), - .de_csr( de_csr ), - .de_txsz( de_txsz ), - .de_adr0( de_adr0 ), - .de_adr1( de_adr1 ), - .de_csr_we( de_csr_we ), - .de_txsz_we( de_txsz_we ), - .de_adr0_we( de_adr0_we ), - .de_adr1_we( de_adr1_we ), - .de_fetch_descr(de_fetch_descr ), - .dma_rest( dma_rest[7] ), - .ptr_set( ptr_set ) - ); - -wb_dma_ch_rf #(8, ch8_conf[0], ch8_conf[1], ch8_conf[2], ch8_conf[3]) u8( - .clk( clk ), - .rst( rst ), - .pointer( pointer8 ), - .pointer_s( pointer8_s ), - .ch_csr( ch8_csr ), - .ch_txsz( ch8_txsz ), - .ch_adr0( ch8_adr0 ), - .ch_adr1( ch8_adr1 ), - .ch_am0( ch8_am0 ), - .ch_am1( ch8_am1 ), - .sw_pointer( sw_pointer8 ), - .ch_stop( ch_stop[8] ), - .ch_dis( ch_dis[8] ), - .int( ch_int[8] ), - .wb_rf_din( wb_rf_din ), - .wb_rf_adr( wb_rf_adr ), - .wb_rf_we( wb_rf_we ), - .wb_rf_re( wb_rf_re ), - .ch_sel( ch_sel ), - .ndnr( ndnr[8] ), - .dma_busy( dma_busy ), - .dma_err( dma_err ), - .dma_done( dma_done ), - .dma_done_all( dma_done_all ), - .de_csr( de_csr ), - .de_txsz( de_txsz ), - .de_adr0( de_adr0 ), - .de_adr1( de_adr1 ), - .de_csr_we( de_csr_we ), - .de_txsz_we( de_txsz_we ), - .de_adr0_we( de_adr0_we ), - .de_adr1_we( de_adr1_we ), - .de_fetch_descr(de_fetch_descr ), - .dma_rest( dma_rest[8] ), - .ptr_set( ptr_set ) - ); - -wb_dma_ch_rf #(9, ch9_conf[0], ch9_conf[1], ch9_conf[2], ch9_conf[3]) u9( - .clk( clk ), - .rst( rst ), - .pointer( pointer9 ), - .pointer_s( pointer9_s ), - .ch_csr( ch9_csr ), - .ch_txsz( ch9_txsz ), - .ch_adr0( ch9_adr0 ), - .ch_adr1( ch9_adr1 ), - .ch_am0( ch9_am0 ), - .ch_am1( ch9_am1 ), - .sw_pointer( sw_pointer9 ), - .ch_stop( ch_stop[9] ), - .ch_dis( ch_dis[9] ), - .int( ch_int[9] ), - .wb_rf_din( wb_rf_din ), - .wb_rf_adr( wb_rf_adr ), - .wb_rf_we( wb_rf_we ), - .wb_rf_re( wb_rf_re ), - .ch_sel( ch_sel ), - .ndnr( ndnr[9] ), - .dma_busy( dma_busy ), - .dma_err( dma_err ), - .dma_done( dma_done ), - .dma_done_all( dma_done_all ), - .de_csr( de_csr ), - .de_txsz( de_txsz ), - .de_adr0( de_adr0 ), - .de_adr1( de_adr1 ), - .de_csr_we( de_csr_we ), - .de_txsz_we( de_txsz_we ), - .de_adr0_we( de_adr0_we ), - .de_adr1_we( de_adr1_we ), - .de_fetch_descr(de_fetch_descr ), - .dma_rest( dma_rest[9] ), - .ptr_set( ptr_set ) - ); - -wb_dma_ch_rf #(10, ch10_conf[0], ch10_conf[1], ch10_conf[2], ch10_conf[3]) u10( - .clk( clk ), - .rst( rst ), - .pointer( pointer10 ), - .pointer_s( pointer10_s ), - .ch_csr( ch10_csr ), - .ch_txsz( ch10_txsz ), - .ch_adr0( ch10_adr0 ), - .ch_adr1( ch10_adr1 ), - .ch_am0( ch10_am0 ), - .ch_am1( ch10_am1 ), - .sw_pointer( sw_pointer10 ), - .ch_stop( ch_stop[10] ), - .ch_dis( ch_dis[10] ), - .int( ch_int[10] ), - .wb_rf_din( wb_rf_din ), - .wb_rf_adr( wb_rf_adr ), - .wb_rf_we( wb_rf_we ), - .wb_rf_re( wb_rf_re ), - .ch_sel( ch_sel ), - .ndnr( ndnr[10] ), - .dma_busy( dma_busy ), - .dma_err( dma_err ), - .dma_done( dma_done ), - .dma_done_all( dma_done_all ), - .de_csr( de_csr ), - .de_txsz( de_txsz ), - .de_adr0( de_adr0 ), - .de_adr1( de_adr1 ), - .de_csr_we( de_csr_we ), - .de_txsz_we( de_txsz_we ), - .de_adr0_we( de_adr0_we ), - .de_adr1_we( de_adr1_we ), - .de_fetch_descr(de_fetch_descr ), - .dma_rest( dma_rest[10] ), - .ptr_set( ptr_set ) - ); - -wb_dma_ch_rf #(11, ch11_conf[0], ch11_conf[1], ch11_conf[2], ch11_conf[3]) u11( - .clk( clk ), - .rst( rst ), - .pointer( pointer11 ), - .pointer_s( pointer11_s ), - .ch_csr( ch11_csr ), - .ch_txsz( ch11_txsz ), - .ch_adr0( ch11_adr0 ), - .ch_adr1( ch11_adr1 ), - .ch_am0( ch11_am0 ), - .ch_am1( ch11_am1 ), - .sw_pointer( sw_pointer11 ), - .ch_stop( ch_stop[11] ), - .ch_dis( ch_dis[11] ), - .int( ch_int[11] ), - .wb_rf_din( wb_rf_din ), - .wb_rf_adr( wb_rf_adr ), - .wb_rf_we( wb_rf_we ), - .wb_rf_re( wb_rf_re ), - .ch_sel( ch_sel ), - .ndnr( ndnr[11] ), - .dma_busy( dma_busy ), - .dma_err( dma_err ), - .dma_done( dma_done ), - .dma_done_all( dma_done_all ), - .de_csr( de_csr ), - .de_txsz( de_txsz ), - .de_adr0( de_adr0 ), - .de_adr1( de_adr1 ), - .de_csr_we( de_csr_we ), - .de_txsz_we( de_txsz_we ), - .de_adr0_we( de_adr0_we ), - .de_adr1_we( de_adr1_we ), - .de_fetch_descr(de_fetch_descr ), - .dma_rest( dma_rest[11] ), - .ptr_set( ptr_set ) - ); - -wb_dma_ch_rf #(12, ch12_conf[0], ch12_conf[1], ch12_conf[2], ch12_conf[3]) u12( - .clk( clk ), - .rst( rst ), - .pointer( pointer12 ), - .pointer_s( pointer12_s ), - .ch_csr( ch12_csr ), - .ch_txsz( ch12_txsz ), - .ch_adr0( ch12_adr0 ), - .ch_adr1( ch12_adr1 ), - .ch_am0( ch12_am0 ), - .ch_am1( ch12_am1 ), - .sw_pointer( sw_pointer12 ), - .ch_stop( ch_stop[12] ), - .ch_dis( ch_dis[12] ), - .int( ch_int[12] ), - .wb_rf_din( wb_rf_din ), - .wb_rf_adr( wb_rf_adr ), - .wb_rf_we( wb_rf_we ), - .wb_rf_re( wb_rf_re ), - .ch_sel( ch_sel ), - .ndnr( ndnr[12] ), - .dma_busy( dma_busy ), - .dma_err( dma_err ), - .dma_done( dma_done ), - .dma_done_all( dma_done_all ), - .de_csr( de_csr ), - .de_txsz( de_txsz ), - .de_adr0( de_adr0 ), - .de_adr1( de_adr1 ), - .de_csr_we( de_csr_we ), - .de_txsz_we( de_txsz_we ), - .de_adr0_we( de_adr0_we ), - .de_adr1_we( de_adr1_we ), - .de_fetch_descr(de_fetch_descr ), - .dma_rest( dma_rest[12] ), - .ptr_set( ptr_set ) - ); - -wb_dma_ch_rf #(13, ch13_conf[0], ch13_conf[1], ch13_conf[2], ch13_conf[3]) u13( - .clk( clk ), - .rst( rst ), - .pointer( pointer13 ), - .pointer_s( pointer13_s ), - .ch_csr( ch13_csr ), - .ch_txsz( ch13_txsz ), - .ch_adr0( ch13_adr0 ), - .ch_adr1( ch13_adr1 ), - .ch_am0( ch13_am0 ), - .ch_am1( ch13_am1 ), - .sw_pointer( sw_pointer13 ), - .ch_stop( ch_stop[13] ), - .ch_dis( ch_dis[13] ), - .int( ch_int[13] ), - .wb_rf_din( wb_rf_din ), - .wb_rf_adr( wb_rf_adr ), - .wb_rf_we( wb_rf_we ), - .wb_rf_re( wb_rf_re ), - .ch_sel( ch_sel ), - .ndnr( ndnr[13] ), - .dma_busy( dma_busy ), - .dma_err( dma_err ), - .dma_done( dma_done ), - .dma_done_all( dma_done_all ), - .de_csr( de_csr ), - .de_txsz( de_txsz ), - .de_adr0( de_adr0 ), - .de_adr1( de_adr1 ), - .de_csr_we( de_csr_we ), - .de_txsz_we( de_txsz_we ), - .de_adr0_we( de_adr0_we ), - .de_adr1_we( de_adr1_we ), - .de_fetch_descr(de_fetch_descr ), - .dma_rest( dma_rest[13] ), - .ptr_set( ptr_set ) - ); - -wb_dma_ch_rf #(14, ch14_conf[0], ch14_conf[1], ch14_conf[2], ch14_conf[3]) u14( - .clk( clk ), - .rst( rst ), - .pointer( pointer14 ), - .pointer_s( pointer14_s ), - .ch_csr( ch14_csr ), - .ch_txsz( ch14_txsz ), - .ch_adr0( ch14_adr0 ), - .ch_adr1( ch14_adr1 ), - .ch_am0( ch14_am0 ), - .ch_am1( ch14_am1 ), - .sw_pointer( sw_pointer14 ), - .ch_stop( ch_stop[14] ), - .ch_dis( ch_dis[14] ), - .int( ch_int[14] ), - .wb_rf_din( wb_rf_din ), - .wb_rf_adr( wb_rf_adr ), - .wb_rf_we( wb_rf_we ), - .wb_rf_re( wb_rf_re ), - .ch_sel( ch_sel ), - .ndnr( ndnr[14] ), - .dma_busy( dma_busy ), - .dma_err( dma_err ), - .dma_done( dma_done ), - .dma_done_all( dma_done_all ), - .de_csr( de_csr ), - .de_txsz( de_txsz ), - .de_adr0( de_adr0 ), - .de_adr1( de_adr1 ), - .de_csr_we( de_csr_we ), - .de_txsz_we( de_txsz_we ), - .de_adr0_we( de_adr0_we ), - .de_adr1_we( de_adr1_we ), - .de_fetch_descr(de_fetch_descr ), - .dma_rest( dma_rest[14] ), - .ptr_set( ptr_set ) - ); - -wb_dma_ch_rf #(15, ch15_conf[0], ch15_conf[1], ch15_conf[2], ch15_conf[3]) u15( - .clk( clk ), - .rst( rst ), - .pointer( pointer15 ), - .pointer_s( pointer15_s ), - .ch_csr( ch15_csr ), - .ch_txsz( ch15_txsz ), - .ch_adr0( ch15_adr0 ), - .ch_adr1( ch15_adr1 ), - .ch_am0( ch15_am0 ), - .ch_am1( ch15_am1 ), - .sw_pointer( sw_pointer15 ), - .ch_stop( ch_stop[15] ), - .ch_dis( ch_dis[15] ), - .int( ch_int[15] ), - .wb_rf_din( wb_rf_din ), - .wb_rf_adr( wb_rf_adr ), - .wb_rf_we( wb_rf_we ), - .wb_rf_re( wb_rf_re ), - .ch_sel( ch_sel ), - .ndnr( ndnr[15] ), - .dma_busy( dma_busy ), - .dma_err( dma_err ), - .dma_done( dma_done ), - .dma_done_all( dma_done_all ), - .de_csr( de_csr ), - .de_txsz( de_txsz ), - .de_adr0( de_adr0 ), - .de_adr1( de_adr1 ), - .de_csr_we( de_csr_we ), - .de_txsz_we( de_txsz_we ), - .de_adr0_we( de_adr0_we ), - .de_adr1_we( de_adr1_we ), - .de_fetch_descr(de_fetch_descr ), - .dma_rest( dma_rest[15] ), - .ptr_set( ptr_set ) - ); - -wb_dma_ch_rf #(16, ch16_conf[0], ch16_conf[1], ch16_conf[2], ch16_conf[3]) u16( - .clk( clk ), - .rst( rst ), - .pointer( pointer16 ), - .pointer_s( pointer16_s ), - .ch_csr( ch16_csr ), - .ch_txsz( ch16_txsz ), - .ch_adr0( ch16_adr0 ), - .ch_adr1( ch16_adr1 ), - .ch_am0( ch16_am0 ), - .ch_am1( ch16_am1 ), - .sw_pointer( sw_pointer16 ), - .ch_stop( ch_stop[16] ), - .ch_dis( ch_dis[16] ), - .int( ch_int[16] ), - .wb_rf_din( wb_rf_din ), - .wb_rf_adr( wb_rf_adr ), - .wb_rf_we( wb_rf_we ), - .wb_rf_re( wb_rf_re ), - .ch_sel( ch_sel ), - .ndnr( ndnr[16] ), - .dma_busy( dma_busy ), - .dma_err( dma_err ), - .dma_done( dma_done ), - .dma_done_all( dma_done_all ), - .de_csr( de_csr ), - .de_txsz( de_txsz ), - .de_adr0( de_adr0 ), - .de_adr1( de_adr1 ), - .de_csr_we( de_csr_we ), - .de_txsz_we( de_txsz_we ), - .de_adr0_we( de_adr0_we ), - .de_adr1_we( de_adr1_we ), - .de_fetch_descr(de_fetch_descr ), - .dma_rest( dma_rest[16] ), - .ptr_set( ptr_set ) - ); - -wb_dma_ch_rf #(17, ch17_conf[0], ch17_conf[1], ch17_conf[2], ch17_conf[3]) u17( - .clk( clk ), - .rst( rst ), - .pointer( pointer17 ), - .pointer_s( pointer17_s ), - .ch_csr( ch17_csr ), - .ch_txsz( ch17_txsz ), - .ch_adr0( ch17_adr0 ), - .ch_adr1( ch17_adr1 ), - .ch_am0( ch17_am0 ), - .ch_am1( ch17_am1 ), - .sw_pointer( sw_pointer17 ), - .ch_stop( ch_stop[17] ), - .ch_dis( ch_dis[17] ), - .int( ch_int[17] ), - .wb_rf_din( wb_rf_din ), - .wb_rf_adr( wb_rf_adr ), - .wb_rf_we( wb_rf_we ), - .wb_rf_re( wb_rf_re ), - .ch_sel( ch_sel ), - .ndnr( ndnr[17] ), - .dma_busy( dma_busy ), - .dma_err( dma_err ), - .dma_done( dma_done ), - .dma_done_all( dma_done_all ), - .de_csr( de_csr ), - .de_txsz( de_txsz ), - .de_adr0( de_adr0 ), - .de_adr1( de_adr1 ), - .de_csr_we( de_csr_we ), - .de_txsz_we( de_txsz_we ), - .de_adr0_we( de_adr0_we ), - .de_adr1_we( de_adr1_we ), - .de_fetch_descr(de_fetch_descr ), - .dma_rest( dma_rest[17] ), - .ptr_set( ptr_set ) - ); - -wb_dma_ch_rf #(18, ch18_conf[0], ch18_conf[1], ch18_conf[2], ch18_conf[3]) u18( - .clk( clk ), - .rst( rst ), - .pointer( pointer18 ), - .pointer_s( pointer18_s ), - .ch_csr( ch18_csr ), - .ch_txsz( ch18_txsz ), - .ch_adr0( ch18_adr0 ), - .ch_adr1( ch18_adr1 ), - .ch_am0( ch18_am0 ), - .ch_am1( ch18_am1 ), - .sw_pointer( sw_pointer18 ), - .ch_stop( ch_stop[18] ), - .ch_dis( ch_dis[18] ), - .int( ch_int[18] ), - .wb_rf_din( wb_rf_din ), - .wb_rf_adr( wb_rf_adr ), - .wb_rf_we( wb_rf_we ), - .wb_rf_re( wb_rf_re ), - .ch_sel( ch_sel ), - .ndnr( ndnr[18] ), - .dma_busy( dma_busy ), - .dma_err( dma_err ), - .dma_done( dma_done ), - .dma_done_all( dma_done_all ), - .de_csr( de_csr ), - .de_txsz( de_txsz ), - .de_adr0( de_adr0 ), - .de_adr1( de_adr1 ), - .de_csr_we( de_csr_we ), - .de_txsz_we( de_txsz_we ), - .de_adr0_we( de_adr0_we ), - .de_adr1_we( de_adr1_we ), - .de_fetch_descr(de_fetch_descr ), - .dma_rest( dma_rest[18] ), - .ptr_set( ptr_set ) - ); - -wb_dma_ch_rf #(19, ch19_conf[0], ch19_conf[1], ch19_conf[2], ch19_conf[3]) u19( - .clk( clk ), - .rst( rst ), - .pointer( pointer19 ), - .pointer_s( pointer19_s ), - .ch_csr( ch19_csr ), - .ch_txsz( ch19_txsz ), - .ch_adr0( ch19_adr0 ), - .ch_adr1( ch19_adr1 ), - .ch_am0( ch19_am0 ), - .ch_am1( ch19_am1 ), - .sw_pointer( sw_pointer19 ), - .ch_stop( ch_stop[19] ), - .ch_dis( ch_dis[19] ), - .int( ch_int[19] ), - .wb_rf_din( wb_rf_din ), - .wb_rf_adr( wb_rf_adr ), - .wb_rf_we( wb_rf_we ), - .wb_rf_re( wb_rf_re ), - .ch_sel( ch_sel ), - .ndnr( ndnr[19] ), - .dma_busy( dma_busy ), - .dma_err( dma_err ), - .dma_done( dma_done ), - .dma_done_all( dma_done_all ), - .de_csr( de_csr ), - .de_txsz( de_txsz ), - .de_adr0( de_adr0 ), - .de_adr1( de_adr1 ), - .de_csr_we( de_csr_we ), - .de_txsz_we( de_txsz_we ), - .de_adr0_we( de_adr0_we ), - .de_adr1_we( de_adr1_we ), - .de_fetch_descr(de_fetch_descr ), - .dma_rest( dma_rest[19] ), - .ptr_set( ptr_set ) - ); - -wb_dma_ch_rf #(20, ch20_conf[0], ch20_conf[1], ch20_conf[2], ch20_conf[3]) u20( - .clk( clk ), - .rst( rst ), - .pointer( pointer20 ), - .pointer_s( pointer20_s ), - .ch_csr( ch20_csr ), - .ch_txsz( ch20_txsz ), - .ch_adr0( ch20_adr0 ), - .ch_adr1( ch20_adr1 ), - .ch_am0( ch20_am0 ), - .ch_am1( ch20_am1 ), - .sw_pointer( sw_pointer20 ), - .ch_stop( ch_stop[20] ), - .ch_dis( ch_dis[20] ), - .int( ch_int[20] ), - .wb_rf_din( wb_rf_din ), - .wb_rf_adr( wb_rf_adr ), - .wb_rf_we( wb_rf_we ), - .wb_rf_re( wb_rf_re ), - .ch_sel( ch_sel ), - .ndnr( ndnr[20] ), - .dma_busy( dma_busy ), - .dma_err( dma_err ), - .dma_done( dma_done ), - .dma_done_all( dma_done_all ), - .de_csr( de_csr ), - .de_txsz( de_txsz ), - .de_adr0( de_adr0 ), - .de_adr1( de_adr1 ), - .de_csr_we( de_csr_we ), - .de_txsz_we( de_txsz_we ), - .de_adr0_we( de_adr0_we ), - .de_adr1_we( de_adr1_we ), - .de_fetch_descr(de_fetch_descr ), - .dma_rest( dma_rest[20] ), - .ptr_set( ptr_set ) - ); - -wb_dma_ch_rf #(21, ch21_conf[0], ch21_conf[1], ch21_conf[2], ch21_conf[3]) u21( - .clk( clk ), - .rst( rst ), - .pointer( pointer21 ), - .pointer_s( pointer21_s ), - .ch_csr( ch21_csr ), - .ch_txsz( ch21_txsz ), - .ch_adr0( ch21_adr0 ), - .ch_adr1( ch21_adr1 ), - .ch_am0( ch21_am0 ), - .ch_am1( ch21_am1 ), - .sw_pointer( sw_pointer21 ), - .ch_stop( ch_stop[21] ), - .ch_dis( ch_dis[21] ), - .int( ch_int[21] ), - .wb_rf_din( wb_rf_din ), - .wb_rf_adr( wb_rf_adr ), - .wb_rf_we( wb_rf_we ), - .wb_rf_re( wb_rf_re ), - .ch_sel( ch_sel ), - .ndnr( ndnr[21] ), - .dma_busy( dma_busy ), - .dma_err( dma_err ), - .dma_done( dma_done ), - .dma_done_all( dma_done_all ), - .de_csr( de_csr ), - .de_txsz( de_txsz ), - .de_adr0( de_adr0 ), - .de_adr1( de_adr1 ), - .de_csr_we( de_csr_we ), - .de_txsz_we( de_txsz_we ), - .de_adr0_we( de_adr0_we ), - .de_adr1_we( de_adr1_we ), - .de_fetch_descr(de_fetch_descr ), - .dma_rest( dma_rest[21] ), - .ptr_set( ptr_set ) - ); - -wb_dma_ch_rf #(22, ch22_conf[0], ch22_conf[1], ch22_conf[2], ch22_conf[3]) u22( - .clk( clk ), - .rst( rst ), - .pointer( pointer22 ), - .pointer_s( pointer22_s ), - .ch_csr( ch22_csr ), - .ch_txsz( ch22_txsz ), - .ch_adr0( ch22_adr0 ), - .ch_adr1( ch22_adr1 ), - .ch_am0( ch22_am0 ), - .ch_am1( ch22_am1 ), - .sw_pointer( sw_pointer22 ), - .ch_stop( ch_stop[22] ), - .ch_dis( ch_dis[22] ), - .int( ch_int[22] ), - .wb_rf_din( wb_rf_din ), - .wb_rf_adr( wb_rf_adr ), - .wb_rf_we( wb_rf_we ), - .wb_rf_re( wb_rf_re ), - .ch_sel( ch_sel ), - .ndnr( ndnr[22] ), - .dma_busy( dma_busy ), - .dma_err( dma_err ), - .dma_done( dma_done ), - .dma_done_all( dma_done_all ), - .de_csr( de_csr ), - .de_txsz( de_txsz ), - .de_adr0( de_adr0 ), - .de_adr1( de_adr1 ), - .de_csr_we( de_csr_we ), - .de_txsz_we( de_txsz_we ), - .de_adr0_we( de_adr0_we ), - .de_adr1_we( de_adr1_we ), - .de_fetch_descr(de_fetch_descr ), - .dma_rest( dma_rest[22] ), - .ptr_set( ptr_set ) - ); - -wb_dma_ch_rf #(23, ch23_conf[0], ch23_conf[1], ch23_conf[2], ch23_conf[3]) u23( - .clk( clk ), - .rst( rst ), - .pointer( pointer23 ), - .pointer_s( pointer23_s ), - .ch_csr( ch23_csr ), - .ch_txsz( ch23_txsz ), - .ch_adr0( ch23_adr0 ), - .ch_adr1( ch23_adr1 ), - .ch_am0( ch23_am0 ), - .ch_am1( ch23_am1 ), - .sw_pointer( sw_pointer23 ), - .ch_stop( ch_stop[23] ), - .ch_dis( ch_dis[23] ), - .int( ch_int[23] ), - .wb_rf_din( wb_rf_din ), - .wb_rf_adr( wb_rf_adr ), - .wb_rf_we( wb_rf_we ), - .wb_rf_re( wb_rf_re ), - .ch_sel( ch_sel ), - .ndnr( ndnr[23] ), - .dma_busy( dma_busy ), - .dma_err( dma_err ), - .dma_done( dma_done ), - .dma_done_all( dma_done_all ), - .de_csr( de_csr ), - .de_txsz( de_txsz ), - .de_adr0( de_adr0 ), - .de_adr1( de_adr1 ), - .de_csr_we( de_csr_we ), - .de_txsz_we( de_txsz_we ), - .de_adr0_we( de_adr0_we ), - .de_adr1_we( de_adr1_we ), - .de_fetch_descr(de_fetch_descr ), - .dma_rest( dma_rest[23] ), - .ptr_set( ptr_set ) - ); - -wb_dma_ch_rf #(24, ch24_conf[0], ch24_conf[1], ch24_conf[2], ch24_conf[3]) u24( - .clk( clk ), - .rst( rst ), - .pointer( pointer24 ), - .pointer_s( pointer24_s ), - .ch_csr( ch24_csr ), - .ch_txsz( ch24_txsz ), - .ch_adr0( ch24_adr0 ), - .ch_adr1( ch24_adr1 ), - .ch_am0( ch24_am0 ), - .ch_am1( ch24_am1 ), - .sw_pointer( sw_pointer24 ), - .ch_stop( ch_stop[24] ), - .ch_dis( ch_dis[24] ), - .int( ch_int[24] ), - .wb_rf_din( wb_rf_din ), - .wb_rf_adr( wb_rf_adr ), - .wb_rf_we( wb_rf_we ), - .wb_rf_re( wb_rf_re ), - .ch_sel( ch_sel ), - .ndnr( ndnr[24] ), - .dma_busy( dma_busy ), - .dma_err( dma_err ), - .dma_done( dma_done ), - .dma_done_all( dma_done_all ), - .de_csr( de_csr ), - .de_txsz( de_txsz ), - .de_adr0( de_adr0 ), - .de_adr1( de_adr1 ), - .de_csr_we( de_csr_we ), - .de_txsz_we( de_txsz_we ), - .de_adr0_we( de_adr0_we ), - .de_adr1_we( de_adr1_we ), - .de_fetch_descr(de_fetch_descr ), - .dma_rest( dma_rest[24] ), - .ptr_set( ptr_set ) - ); - -wb_dma_ch_rf #(25, ch25_conf[0], ch25_conf[1], ch25_conf[2], ch25_conf[3]) u25( - .clk( clk ), - .rst( rst ), - .pointer( pointer25 ), - .pointer_s( pointer25_s ), - .ch_csr( ch25_csr ), - .ch_txsz( ch25_txsz ), - .ch_adr0( ch25_adr0 ), - .ch_adr1( ch25_adr1 ), - .ch_am0( ch25_am0 ), - .ch_am1( ch25_am1 ), - .sw_pointer( sw_pointer25 ), - .ch_stop( ch_stop[25] ), - .ch_dis( ch_dis[25] ), - .int( ch_int[25] ), - .wb_rf_din( wb_rf_din ), - .wb_rf_adr( wb_rf_adr ), - .wb_rf_we( wb_rf_we ), - .wb_rf_re( wb_rf_re ), - .ch_sel( ch_sel ), - .ndnr( ndnr[25] ), - .dma_busy( dma_busy ), - .dma_err( dma_err ), - .dma_done( dma_done ), - .dma_done_all( dma_done_all ), - .de_csr( de_csr ), - .de_txsz( de_txsz ), - .de_adr0( de_adr0 ), - .de_adr1( de_adr1 ), - .de_csr_we( de_csr_we ), - .de_txsz_we( de_txsz_we ), - .de_adr0_we( de_adr0_we ), - .de_adr1_we( de_adr1_we ), - .de_fetch_descr(de_fetch_descr ), - .dma_rest( dma_rest[25] ), - .ptr_set( ptr_set ) - ); - -wb_dma_ch_rf #(26, ch26_conf[0], ch26_conf[1], ch26_conf[2], ch26_conf[3]) u26( - .clk( clk ), - .rst( rst ), - .pointer( pointer26 ), - .pointer_s( pointer26_s ), - .ch_csr( ch26_csr ), - .ch_txsz( ch26_txsz ), - .ch_adr0( ch26_adr0 ), - .ch_adr1( ch26_adr1 ), - .ch_am0( ch26_am0 ), - .ch_am1( ch26_am1 ), - .sw_pointer( sw_pointer26 ), - .ch_stop( ch_stop[26] ), - .ch_dis( ch_dis[26] ), - .int( ch_int[26] ), - .wb_rf_din( wb_rf_din ), - .wb_rf_adr( wb_rf_adr ), - .wb_rf_we( wb_rf_we ), - .wb_rf_re( wb_rf_re ), - .ch_sel( ch_sel ), - .ndnr( ndnr[26] ), - .dma_busy( dma_busy ), - .dma_err( dma_err ), - .dma_done( dma_done ), - .dma_done_all( dma_done_all ), - .de_csr( de_csr ), - .de_txsz( de_txsz ), - .de_adr0( de_adr0 ), - .de_adr1( de_adr1 ), - .de_csr_we( de_csr_we ), - .de_txsz_we( de_txsz_we ), - .de_adr0_we( de_adr0_we ), - .de_adr1_we( de_adr1_we ), - .de_fetch_descr(de_fetch_descr ), - .dma_rest( dma_rest[26] ), - .ptr_set( ptr_set ) - ); - -wb_dma_ch_rf #(27, ch27_conf[0], ch27_conf[1], ch27_conf[2], ch27_conf[3]) u27( - .clk( clk ), - .rst( rst ), - .pointer( pointer27 ), - .pointer_s( pointer27_s ), - .ch_csr( ch27_csr ), - .ch_txsz( ch27_txsz ), - .ch_adr0( ch27_adr0 ), - .ch_adr1( ch27_adr1 ), - .ch_am0( ch27_am0 ), - .ch_am1( ch27_am1 ), - .sw_pointer( sw_pointer27 ), - .ch_stop( ch_stop[27] ), - .ch_dis( ch_dis[27] ), - .int( ch_int[27] ), - .wb_rf_din( wb_rf_din ), - .wb_rf_adr( wb_rf_adr ), - .wb_rf_we( wb_rf_we ), - .wb_rf_re( wb_rf_re ), - .ch_sel( ch_sel ), - .ndnr( ndnr[27] ), - .dma_busy( dma_busy ), - .dma_err( dma_err ), - .dma_done( dma_done ), - .dma_done_all( dma_done_all ), - .de_csr( de_csr ), - .de_txsz( de_txsz ), - .de_adr0( de_adr0 ), - .de_adr1( de_adr1 ), - .de_csr_we( de_csr_we ), - .de_txsz_we( de_txsz_we ), - .de_adr0_we( de_adr0_we ), - .de_adr1_we( de_adr1_we ), - .de_fetch_descr(de_fetch_descr ), - .dma_rest( dma_rest[27] ), - .ptr_set( ptr_set ) - ); - -wb_dma_ch_rf #(28, ch28_conf[0], ch28_conf[1], ch28_conf[2], ch28_conf[3]) u28( - .clk( clk ), - .rst( rst ), - .pointer( pointer28 ), - .pointer_s( pointer28_s ), - .ch_csr( ch28_csr ), - .ch_txsz( ch28_txsz ), - .ch_adr0( ch28_adr0 ), - .ch_adr1( ch28_adr1 ), - .ch_am0( ch28_am0 ), - .ch_am1( ch28_am1 ), - .sw_pointer( sw_pointer28 ), - .ch_stop( ch_stop[28] ), - .ch_dis( ch_dis[28] ), - .int( ch_int[28] ), - .wb_rf_din( wb_rf_din ), - .wb_rf_adr( wb_rf_adr ), - .wb_rf_we( wb_rf_we ), - .wb_rf_re( wb_rf_re ), - .ch_sel( ch_sel ), - .ndnr( ndnr[28] ), - .dma_busy( dma_busy ), - .dma_err( dma_err ), - .dma_done( dma_done ), - .dma_done_all( dma_done_all ), - .de_csr( de_csr ), - .de_txsz( de_txsz ), - .de_adr0( de_adr0 ), - .de_adr1( de_adr1 ), - .de_csr_we( de_csr_we ), - .de_txsz_we( de_txsz_we ), - .de_adr0_we( de_adr0_we ), - .de_adr1_we( de_adr1_we ), - .de_fetch_descr(de_fetch_descr ), - .dma_rest( dma_rest[28] ), - .ptr_set( ptr_set ) - ); - -wb_dma_ch_rf #(29, ch29_conf[0], ch29_conf[1], ch29_conf[2], ch29_conf[3]) u29( - .clk( clk ), - .rst( rst ), - .pointer( pointer29 ), - .pointer_s( pointer29_s ), - .ch_csr( ch29_csr ), - .ch_txsz( ch29_txsz ), - .ch_adr0( ch29_adr0 ), - .ch_adr1( ch29_adr1 ), - .ch_am0( ch29_am0 ), - .ch_am1( ch29_am1 ), - .sw_pointer( sw_pointer29 ), - .ch_stop( ch_stop[29] ), - .ch_dis( ch_dis[29] ), - .int( ch_int[29] ), - .wb_rf_din( wb_rf_din ), - .wb_rf_adr( wb_rf_adr ), - .wb_rf_we( wb_rf_we ), - .wb_rf_re( wb_rf_re ), - .ch_sel( ch_sel ), - .ndnr( ndnr[29] ), - .dma_busy( dma_busy ), - .dma_err( dma_err ), - .dma_done( dma_done ), - .dma_done_all( dma_done_all ), - .de_csr( de_csr ), - .de_txsz( de_txsz ), - .de_adr0( de_adr0 ), - .de_adr1( de_adr1 ), - .de_csr_we( de_csr_we ), - .de_txsz_we( de_txsz_we ), - .de_adr0_we( de_adr0_we ), - .de_adr1_we( de_adr1_we ), - .de_fetch_descr(de_fetch_descr ), - .dma_rest( dma_rest[29] ), - .ptr_set( ptr_set ) - ); - -wb_dma_ch_rf #(30, ch30_conf[0], ch30_conf[1], ch30_conf[2], ch30_conf[3]) u30( - .clk( clk ), - .rst( rst ), - .pointer( pointer30 ), - .pointer_s( pointer30_s ), - .ch_csr( ch30_csr ), - .ch_txsz( ch30_txsz ), - .ch_adr0( ch30_adr0 ), - .ch_adr1( ch30_adr1 ), - .ch_am0( ch30_am0 ), - .ch_am1( ch30_am1 ), - .sw_pointer( sw_pointer30 ), - .ch_stop( ch_stop[30] ), - .ch_dis( ch_dis[30] ), - .int( ch_int[30] ), - .wb_rf_din( wb_rf_din ), - .wb_rf_adr( wb_rf_adr ), - .wb_rf_we( wb_rf_we ), - .wb_rf_re( wb_rf_re ), - .ch_sel( ch_sel ), - .ndnr( ndnr[30] ), - .dma_busy( dma_busy ), - .dma_err( dma_err ), - .dma_done( dma_done ), - .dma_done_all( dma_done_all ), - .de_csr( de_csr ), - .de_txsz( de_txsz ), - .de_adr0( de_adr0 ), - .de_adr1( de_adr1 ), - .de_csr_we( de_csr_we ), - .de_txsz_we( de_txsz_we ), - .de_adr0_we( de_adr0_we ), - .de_adr1_we( de_adr1_we ), - .de_fetch_descr(de_fetch_descr ), - .dma_rest( dma_rest[30] ), - .ptr_set( ptr_set ) - ); - -endmodule Index: trunk/rtl/verilog/wb_dma_de.v =================================================================== --- trunk/rtl/verilog/wb_dma_de.v (revision 16) +++ trunk/rtl/verilog/wb_dma_de.v (nonexistent) @@ -1,628 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// WISHBONE DMA DMA Engine Core //// -//// //// -//// //// -//// Author: Rudolf Usselmann //// -//// rudi@asics.ws //// -//// //// -//// //// -//// Downloaded from: http://www.opencores.org/cores/wb_dma/ //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000-2002 Rudolf Usselmann //// -//// www.asics.ws //// -//// rudi@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: wb_dma_de.v,v 1.3 2002-02-01 01:54:45 rudi Exp $ -// -// $Date: 2002-02-01 01:54:45 $ -// $Revision: 1.3 $ -// $Author: rudi $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: not supported by cvs2svn $ -// Revision 1.2 2001/08/15 05:40:30 rudi -// -// - Changed IO names to be more clear. -// - Uniquifyed define names to be core specific. -// - Added Section 3.10, describing DMA restart. -// -// Revision 1.1 2001/07/29 08:57:02 rudi -// -// -// 1) Changed Directory Structure -// 2) Added restart signal (REST) -// -// Revision 1.3 2001/06/13 02:26:48 rudi -// -// -// Small changes after running lint. -// -// Revision 1.2 2001/06/05 10:22:36 rudi -// -// -// - Added Support of up to 31 channels -// - Added support for 2,4 and 8 priority levels -// - Now can have up to 31 channels -// - Added many configuration items -// - Changed reset to async -// -// Revision 1.1.1.1 2001/03/19 13:10:44 rudi -// Initial Release -// -// -// - -`include "wb_dma_defines.v" - -module wb_dma_de(clk, rst, - - // WISHBONE MASTER INTERFACE 0 - mast0_go, mast0_we, mast0_adr, mast0_din, - mast0_dout, mast0_err, mast0_drdy, mast0_wait, - - // WISHBONE MASTER INTERFACE 1 - mast1_go, mast1_we, mast1_adr, mast1_din, - mast1_dout, mast1_err, mast1_drdy, mast1_wait, - - // DMA Engine Init & Setup - de_start, nd, csr, pointer, pointer_s, txsz, - adr0, adr1, am0, am1, - - // DMA Engine Register File Update Outputs - de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we, ptr_set, - de_csr, de_txsz, de_adr0, de_adr1, de_fetch_descr, - - // DMA Engine Control Outputs - next_ch, de_ack, - - // DMA Engine Status - pause_req, paused, - dma_abort, dma_busy, dma_err, dma_done, dma_done_all - ); - -input clk, rst; - -// -------------------------------------- -// WISHBONE MASTER INTERFACE 0 - -output mast0_go; // Perform a Master Cycle -output mast0_we; // Read/Write -output [31:0] mast0_adr; // Address for the transfer -input [31:0] mast0_din; // Internal Input Data -output [31:0] mast0_dout; // Internal Output Data -input mast0_err; // Indicates an error has occurred -input mast0_drdy; // Indicated that either data is available - // during a read, or that the master can accept - // the next data during a write -output mast0_wait; // Tells the master to insert wait cycles - // because data can not be accepted/provided - -// -------------------------------------- -// WISHBONE MASTER INTERFACE 1 - -output mast1_go; // Perform a Master Cycle -output mast1_we; // Read/Write -output [31:0] mast1_adr; // Address for the transfer -input [31:0] mast1_din; // Internal Input Data -output [31:0] mast1_dout; // Internal Output Data -input mast1_err; // Indicates an error has occurred -input mast1_drdy; // Indicated that either data is available - // during a read, or that the master can accept - // the next data during a write -output mast1_wait; // Tells the master to insert wait cycles - // because data can not be accepted/provided - -// -------------------------------------- -// DMA Engine Signals - -// DMA Engine Init & Setup -input de_start; // Start DMA Engine Indicator -input nd; // Next Descriptor Indicator -input [31:0] csr; // Selected Channel CSR -input [31:0] pointer; // Linked List Descriptor pointer -input [31:0] pointer_s; // Previous Pointer -input [31:0] txsz; // Selected Channel Transfer Size -input [31:0] adr0, adr1; // Selected Channel Addresses -input [31:0] am0, am1; // Selected Channel Address Masks - -// DMA Engine Register File Update Outputs -output de_csr_we; // Write enable for csr register -output de_txsz_we; // Write enable for txsz register -output de_adr0_we; // Write enable for adr0 register -output de_adr1_we; // Write enable for adr1 register -output ptr_set; // Set Pointer as Valid -output [31:0] de_csr; // Write Data for CSR when loading External Desc. -output [11:0] de_txsz; // Write back data for txsz register -output [31:0] de_adr0; // Write back data for adr0 register -output [31:0] de_adr1; // Write back data for adr1 register -output de_fetch_descr; // Indicates that we are fetching a descriptor - -// DMA Engine Control Outputs -output next_ch; // Indicates the DMA Engine is done -output de_ack; - -// DMA Abort from RF (software forced abort) -input dma_abort; - -// DMA Engine Status -input pause_req; -output paused; -output dma_busy, dma_err, dma_done, dma_done_all; - -//////////////////////////////////////////////////////////////////// -// -// Local Wires -// - -parameter [10:0] // synopsys enum state - IDLE = 11'b000_0000_0001, - READ = 11'b000_0000_0010, - WRITE = 11'b000_0000_0100, - UPDATE = 11'b000_0000_1000, - LD_DESC1 = 11'b000_0001_0000, - LD_DESC2 = 11'b000_0010_0000, - LD_DESC3 = 11'b000_0100_0000, - LD_DESC4 = 11'b000_1000_0000, - LD_DESC5 = 11'b001_0000_0000, - WB = 11'b010_0000_0000, - PAUSE = 11'b100_0000_0000; - -reg [10:0] /* synopsys enum state */ state, next_state; -// synopsys state_vector state - -reg [31:0] mast0_adr, mast1_adr; - -reg [29:0] adr0_cnt, adr1_cnt; -wire [29:0] adr0_cnt_next, adr1_cnt_next; -wire [29:0] adr0_cnt_next1, adr1_cnt_next1; -reg adr0_inc, adr1_inc; - -reg [8:0] chunk_cnt; -reg chunk_dec; - -reg [11:0] tsz_cnt; -reg tsz_dec; - -reg de_txsz_we; -reg de_csr_we; -reg de_adr0_we; -reg de_adr1_we; -reg ld_desc_sel; - -wire chunk_cnt_is_0_d; -reg chunk_cnt_is_0_r; -wire tsz_cnt_is_0_d; -reg tsz_cnt_is_0_r; - -reg read, write; -reg read_r, write_r; -wire rd_ack, wr_ack; -reg rd_ack_r; - -reg chunk_0; -wire done; -reg dma_done_d; -reg dma_done_r; -reg dma_abort_r; -reg next_ch; -wire read_hold, write_hold; -reg write_hold_r; - -reg [1:0] ptr_adr_low; -reg m0_go; -reg m0_we; -reg ptr_set; - -// Aliases -wire a0_inc_en = csr[4]; // Source Address (Adr 0) increment enable -wire a1_inc_en = csr[3]; // Dest. Address (Adr 1) increment enable -wire ptr_valid = pointer[0]; -wire use_ed = csr[`WDMA_USE_ED]; - -reg mast0_drdy_r; -reg paused; - -reg de_fetch_descr; // Indicates that we are fetching a descriptor -//////////////////////////////////////////////////////////////////// -// -// Misc Logic -// - -always @(posedge clk) - dma_done_r <= #1 dma_done; - -// Address Counter 0 (Source Address) -always @(posedge clk) - if(de_start | ptr_set) adr0_cnt <= #1 adr0[31:2]; - else - if(adr0_inc & a0_inc_en) adr0_cnt <= #1 adr0_cnt_next; - -// 30 Bit Incrementor (registered) -wb_dma_inc30r u0( .clk( clk ), - .in( adr0_cnt ), - .out( adr0_cnt_next1 ) ); - -assign adr0_cnt_next[1:0] = adr0_cnt_next1[1:0]; -assign adr0_cnt_next[2] = am0[4] ? adr0_cnt_next1[2] : adr0_cnt[2]; -assign adr0_cnt_next[3] = am0[5] ? adr0_cnt_next1[3] : adr0_cnt[3]; -assign adr0_cnt_next[4] = am0[6] ? adr0_cnt_next1[4] : adr0_cnt[4]; -assign adr0_cnt_next[5] = am0[7] ? adr0_cnt_next1[5] : adr0_cnt[5]; -assign adr0_cnt_next[6] = am0[8] ? adr0_cnt_next1[6] : adr0_cnt[6]; -assign adr0_cnt_next[7] = am0[9] ? adr0_cnt_next1[7] : adr0_cnt[7]; -assign adr0_cnt_next[8] = am0[10] ? adr0_cnt_next1[8] : adr0_cnt[8]; -assign adr0_cnt_next[9] = am0[11] ? adr0_cnt_next1[9] : adr0_cnt[9]; -assign adr0_cnt_next[10] = am0[12] ? adr0_cnt_next1[10] : adr0_cnt[10]; -assign adr0_cnt_next[11] = am0[13] ? adr0_cnt_next1[11] : adr0_cnt[11]; -assign adr0_cnt_next[12] = am0[14] ? adr0_cnt_next1[12] : adr0_cnt[12]; -assign adr0_cnt_next[13] = am0[15] ? adr0_cnt_next1[13] : adr0_cnt[13]; -assign adr0_cnt_next[14] = am0[16] ? adr0_cnt_next1[14] : adr0_cnt[14]; -assign adr0_cnt_next[15] = am0[17] ? adr0_cnt_next1[15] : adr0_cnt[15]; -assign adr0_cnt_next[16] = am0[18] ? adr0_cnt_next1[16] : adr0_cnt[16]; -assign adr0_cnt_next[17] = am0[19] ? adr0_cnt_next1[17] : adr0_cnt[17]; -assign adr0_cnt_next[18] = am0[20] ? adr0_cnt_next1[18] : adr0_cnt[18]; -assign adr0_cnt_next[19] = am0[21] ? adr0_cnt_next1[19] : adr0_cnt[19]; -assign adr0_cnt_next[20] = am0[22] ? adr0_cnt_next1[20] : adr0_cnt[20]; -assign adr0_cnt_next[21] = am0[23] ? adr0_cnt_next1[21] : adr0_cnt[21]; -assign adr0_cnt_next[22] = am0[24] ? adr0_cnt_next1[22] : adr0_cnt[22]; -assign adr0_cnt_next[23] = am0[25] ? adr0_cnt_next1[23] : adr0_cnt[23]; -assign adr0_cnt_next[24] = am0[26] ? adr0_cnt_next1[24] : adr0_cnt[24]; -assign adr0_cnt_next[25] = am0[27] ? adr0_cnt_next1[25] : adr0_cnt[25]; -assign adr0_cnt_next[26] = am0[28] ? adr0_cnt_next1[26] : adr0_cnt[26]; -assign adr0_cnt_next[27] = am0[29] ? adr0_cnt_next1[27] : adr0_cnt[27]; -assign adr0_cnt_next[28] = am0[30] ? adr0_cnt_next1[28] : adr0_cnt[28]; -assign adr0_cnt_next[29] = am0[31] ? adr0_cnt_next1[29] : adr0_cnt[29]; - - -// Address Counter 1 (Destination Address) -always @(posedge clk) - if(de_start | ptr_set) adr1_cnt <= #1 adr1[31:2]; - else - if(adr1_inc & a1_inc_en) adr1_cnt <= #1 adr1_cnt_next; - -// 30 Bit Incrementor (registered) -wb_dma_inc30r u1( .clk( clk ), - .in( adr1_cnt ), - .out( adr1_cnt_next1 ) ); - -assign adr1_cnt_next[1:0] = adr1_cnt_next1[1:0]; -assign adr1_cnt_next[2] = am1[4] ? adr1_cnt_next1[2] : adr1_cnt[2]; -assign adr1_cnt_next[3] = am1[5] ? adr1_cnt_next1[3] : adr1_cnt[3]; -assign adr1_cnt_next[4] = am1[6] ? adr1_cnt_next1[4] : adr1_cnt[4]; -assign adr1_cnt_next[5] = am1[7] ? adr1_cnt_next1[5] : adr1_cnt[5]; -assign adr1_cnt_next[6] = am1[8] ? adr1_cnt_next1[6] : adr1_cnt[6]; -assign adr1_cnt_next[7] = am1[9] ? adr1_cnt_next1[7] : adr1_cnt[7]; -assign adr1_cnt_next[8] = am1[10] ? adr1_cnt_next1[8] : adr1_cnt[8]; -assign adr1_cnt_next[9] = am1[11] ? adr1_cnt_next1[9] : adr1_cnt[9]; -assign adr1_cnt_next[10] = am1[12] ? adr1_cnt_next1[10] : adr1_cnt[10]; -assign adr1_cnt_next[11] = am1[13] ? adr1_cnt_next1[11] : adr1_cnt[11]; -assign adr1_cnt_next[12] = am1[14] ? adr1_cnt_next1[12] : adr1_cnt[12]; -assign adr1_cnt_next[13] = am1[15] ? adr1_cnt_next1[13] : adr1_cnt[13]; -assign adr1_cnt_next[14] = am1[16] ? adr1_cnt_next1[14] : adr1_cnt[14]; -assign adr1_cnt_next[15] = am1[17] ? adr1_cnt_next1[15] : adr1_cnt[15]; -assign adr1_cnt_next[16] = am1[18] ? adr1_cnt_next1[16] : adr1_cnt[16]; -assign adr1_cnt_next[17] = am1[19] ? adr1_cnt_next1[17] : adr1_cnt[17]; -assign adr1_cnt_next[18] = am1[20] ? adr1_cnt_next1[18] : adr1_cnt[18]; -assign adr1_cnt_next[19] = am1[21] ? adr1_cnt_next1[19] : adr1_cnt[19]; -assign adr1_cnt_next[20] = am1[22] ? adr1_cnt_next1[20] : adr1_cnt[20]; -assign adr1_cnt_next[21] = am1[23] ? adr1_cnt_next1[21] : adr1_cnt[21]; -assign adr1_cnt_next[22] = am1[24] ? adr1_cnt_next1[22] : adr1_cnt[22]; -assign adr1_cnt_next[23] = am1[25] ? adr1_cnt_next1[23] : adr1_cnt[23]; -assign adr1_cnt_next[24] = am1[26] ? adr1_cnt_next1[24] : adr1_cnt[24]; -assign adr1_cnt_next[25] = am1[27] ? adr1_cnt_next1[25] : adr1_cnt[25]; -assign adr1_cnt_next[26] = am1[28] ? adr1_cnt_next1[26] : adr1_cnt[26]; -assign adr1_cnt_next[27] = am1[29] ? adr1_cnt_next1[27] : adr1_cnt[27]; -assign adr1_cnt_next[28] = am1[30] ? adr1_cnt_next1[28] : adr1_cnt[28]; -assign adr1_cnt_next[29] = am1[31] ? adr1_cnt_next1[29] : adr1_cnt[29]; - -// Chunk Counter -always @(posedge clk) - if(de_start) chunk_cnt <= #1 txsz[24:16]; - else - if(chunk_dec & !chunk_cnt_is_0_r) chunk_cnt <= #1 chunk_cnt - 9'h1; - -assign chunk_cnt_is_0_d = (chunk_cnt == 9'h0); - -always @(posedge clk) - chunk_cnt_is_0_r <= #1 chunk_cnt_is_0_d; - -// Total Size Counter -always @(posedge clk) - if(de_start | ptr_set) tsz_cnt <= #1 txsz[11:0]; - else - if(tsz_dec & !tsz_cnt_is_0_r) tsz_cnt <= #1 tsz_cnt - 12'h1; - -assign tsz_cnt_is_0_d = (tsz_cnt == 12'h0) & !txsz[15]; - -always @(posedge clk) - tsz_cnt_is_0_r <= #1 tsz_cnt_is_0_d; - -// Counter Control Logic -always @(posedge clk) - chunk_dec <= #1 read & !read_r; - -always @(posedge clk) - tsz_dec <= #1 read & !read_r; - -//always @(posedge clk) -always @(rd_ack or read_r) - adr0_inc = rd_ack & read_r; - -//always @(posedge clk) -always @(wr_ack or write_r) - adr1_inc = wr_ack & write_r; - -// Done logic -always @(posedge clk) - chunk_0 <= #1 (txsz[24:16] == 9'h0); - -assign done = chunk_0 ? tsz_cnt_is_0_d : (tsz_cnt_is_0_d | chunk_cnt_is_0_d); -assign dma_done = dma_done_d & done; -assign dma_done_all = dma_done_d & (tsz_cnt_is_0_r | (nd & chunk_cnt_is_0_d)); - -always @(posedge clk) - next_ch <= #1 dma_done; - -// Register Update Outputs -assign de_txsz = ld_desc_sel ? mast0_din[11:0] : tsz_cnt; -assign de_adr0 = ld_desc_sel ? mast0_din : {adr0_cnt, 2'b00}; -assign de_adr1 = ld_desc_sel ? mast0_din : {adr1_cnt, 2'b00}; -assign de_csr = mast0_din; - -// Abort logic -always @(posedge clk) - dma_abort_r <= #1 dma_abort | mast0_err | mast1_err; - -assign dma_err = dma_abort_r; - -assign dma_busy = (state != IDLE); - -//////////////////////////////////////////////////////////////////// -// -// WISHBONE Interface Logic -// - -always @(posedge clk) - read_r <= #1 read; - -always @(posedge clk) - write_r <= #1 write; - -always @(posedge clk) - rd_ack_r <= #1 read_r; - -// Data Path -assign mast0_dout = m0_we ? {20'h0, tsz_cnt} : csr[2] ? mast1_din : mast0_din; -assign mast1_dout = csr[2] ? mast1_din : mast0_din; - -// Address Path -always @(posedge clk) - mast0_adr <= #1 m0_go ? - (m0_we ? pointer_s : {pointer[31:4], ptr_adr_low, 2'b00}) : - read ? {adr0_cnt, 2'b00} : {adr1_cnt, 2'b00}; - -always @(posedge clk) - mast1_adr <= #1 read ? {adr0_cnt, 2'b00} : {adr1_cnt, 2'b00}; - -// CTRL -assign write_hold = (read | write) & write_hold_r; - -always @(posedge clk) - write_hold_r <= #1 read | write; - -assign read_hold = done ? read : (read | write); - -assign mast0_go = (!csr[2] & read_hold) | (!csr[1] & write_hold) | m0_go; -assign mast1_go = ( csr[2] & read_hold) | ( csr[1] & write_hold); - -assign mast0_we = m0_go ? m0_we : (!csr[1] & write); -assign mast1_we = csr[1] & write; - -assign rd_ack = (csr[2] ? mast1_drdy : mast0_drdy); -assign wr_ack = (csr[1] ? mast1_drdy : mast0_drdy); - -assign mast0_wait = !((!csr[2] & read) | (!csr[1] & write)) & !m0_go; -assign mast1_wait = !(( csr[2] & read) | ( csr[1] & write)); - -always @(posedge clk) - mast0_drdy_r <= #1 mast0_drdy; - -assign de_ack = dma_done; - -//////////////////////////////////////////////////////////////////// -// -// State Machine -// - -always @(posedge clk or negedge rst) - if(!rst) state <= #1 IDLE; - else state <= #1 next_state; - -always @(state or pause_req or dma_abort_r or de_start or rd_ack or wr_ack or - done or ptr_valid or use_ed or mast0_drdy or mast0_drdy_r or csr or nd) - begin - next_state = state; // Default keep state - read = 1'b0; - write = 1'b0; - dma_done_d = 1'b0; - de_csr_we = 1'b0; - de_txsz_we = 1'b0; - de_adr0_we = 1'b0; - de_adr1_we = 1'b0; - de_fetch_descr = 1'b0; - - m0_go = 1'b0; - m0_we = 1'b0; - ptr_adr_low = 2'h0; - ptr_set = 1'b0; - ld_desc_sel = 1'b0; - paused = 1'b0; - - case(state) // synopsys parallel_case full_case - - IDLE: - begin - if(pause_req) next_state = PAUSE; - else - if(de_start & !csr[`WDMA_ERR]) - begin - if(use_ed & !ptr_valid) next_state = LD_DESC1; - else next_state = READ; - end - end - - PAUSE: - begin - paused = 1'b1; - if(!pause_req) next_state = IDLE; - end - - READ: // Read From Source - begin - if(dma_abort_r) next_state = UPDATE; - else - if(!rd_ack) read = 1'b1; - else - begin - write = 1'b1; - next_state = WRITE; - end - end - - WRITE: // Write To Destination - begin - if(dma_abort_r) next_state = UPDATE; - else - if(!wr_ack) write = 1'b1; - else - begin - if(done) next_state = UPDATE; - else - begin - read = 1'b1; - next_state = READ; - end - end - end - - UPDATE: // Update Registers - begin - dma_done_d = 1'b1; - de_txsz_we = 1'b1; - de_adr0_we = 1'b1; - de_adr1_we = 1'b1; - if(use_ed & csr[`WDMA_WRB] & nd) - begin - m0_we = 1'b1; - m0_go = 1'b1; - next_state = WB; - end - else next_state = IDLE; - end - - WB: - begin - m0_we = 1'b1; - if(mast0_drdy) - begin - next_state = IDLE; - end - else m0_go = 1'b1; - end - - LD_DESC1: // Load Descriptor from memory to registers - begin - ptr_adr_low = 2'h0; - ld_desc_sel = 1'b1; - m0_go = 1'b1; - de_csr_we = 1'b1; - de_txsz_we = 1'b1; - de_fetch_descr = 1'b1; - if(mast0_drdy) - begin - ptr_adr_low = 2'h1; - next_state = LD_DESC2; - end - end - - LD_DESC2: - begin - de_fetch_descr = 1'b1; - if(mast0_drdy_r) de_csr_we = 1'b1; - if(mast0_drdy_r) de_txsz_we = 1'b1; - ptr_adr_low = 2'h1; - ld_desc_sel = 1'b1; - m0_go = 1'b1; - if(mast0_drdy) - begin - ptr_adr_low = 2'h2; - next_state = LD_DESC3; - end - end - - LD_DESC3: - begin - de_fetch_descr = 1'b1; - if(mast0_drdy_r) de_adr0_we = 1'b1; - ptr_adr_low = 2'h2; - ld_desc_sel = 1'b1; - m0_go = 1'b1; - if(mast0_drdy) - begin - ptr_adr_low = 2'h3; - next_state = LD_DESC4; - end - end - - LD_DESC4: - begin - de_fetch_descr = 1'b1; - if(mast0_drdy_r) de_adr1_we = 1'b1; - ptr_adr_low = 2'h3; - ld_desc_sel = 1'b1; - if(mast0_drdy) - begin - next_state = LD_DESC5; - end - else m0_go = 1'b1; - end - - LD_DESC5: - begin - de_fetch_descr = 1'b1; - ptr_set = 1'b1; - next_state = READ; - end - - endcase - - end - -endmodule Index: trunk/rtl/verilog/wb_dma_pri_enc_sub.v =================================================================== --- trunk/rtl/verilog/wb_dma_pri_enc_sub.v (revision 16) +++ trunk/rtl/verilog/wb_dma_pri_enc_sub.v (nonexistent) @@ -1,142 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// WISHBONE DMA Priority Encoder Sub-Module //// -//// //// -//// //// -//// Author: Rudolf Usselmann //// -//// rudi@asics.ws //// -//// //// -//// //// -//// Downloaded from: http://www.opencores.org/cores/wb_dma/ //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000-2002 Rudolf Usselmann //// -//// www.asics.ws //// -//// rudi@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: wb_dma_pri_enc_sub.v,v 1.4 2002-02-01 01:54:45 rudi Exp $ -// -// $Date: 2002-02-01 01:54:45 $ -// $Revision: 1.4 $ -// $Author: rudi $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: not supported by cvs2svn $ -// Revision 1.3 2001/10/19 04:35:04 rudi -// -// - Made the core parameterized -// -// Revision 1.2 2001/08/15 05:40:30 rudi -// -// - Changed IO names to be more clear. -// - Uniquifyed define names to be core specific. -// - Added Section 3.10, describing DMA restart. -// -// Revision 1.1 2001/08/07 08:00:43 rudi -// -// -// Split up priority encoder modules to separate files -// -// -// -// -// -// - -`include "wb_dma_defines.v" - -// Priority Encoder -// -// Determines the channel with the highest priority, also takes -// the valid bit in consideration - -module wb_dma_pri_enc_sub(valid, pri_in, pri_out); - -parameter [3:0] ch_conf = 4'b0000; -parameter [1:0] pri_sel = 2'd0; - -input valid; -input [2:0] pri_in; -output [7:0] pri_out; - -wire [7:0] pri_out; -reg [7:0] pri_out_d; -reg [7:0] pri_out_d0; -reg [7:0] pri_out_d1; -reg [7:0] pri_out_d2; - -assign pri_out = ch_conf[0] ? pri_out_d : 8'h0; - -// Select Configured Priority -always @(pri_sel or pri_out_d0 or pri_out_d1 or pri_out_d2) - case(pri_sel) // synopsys parallel_case full_case - 2'd0: pri_out_d = pri_out_d0; - 2'd1: pri_out_d = pri_out_d1; - 2'd2: pri_out_d = pri_out_d2; - endcase - -// 8 Priority Levels -always @(valid or pri_in) - if(!valid) pri_out_d2 = 8'b0000_0001; - else - if(pri_in==3'h0) pri_out_d2 = 8'b0000_0001; - else - if(pri_in==3'h1) pri_out_d2 = 8'b0000_0010; - else - if(pri_in==3'h2) pri_out_d2 = 8'b0000_0100; - else - if(pri_in==3'h3) pri_out_d2 = 8'b0000_1000; - else - if(pri_in==3'h4) pri_out_d2 = 8'b0001_0000; - else - if(pri_in==3'h5) pri_out_d2 = 8'b0010_0000; - else - if(pri_in==3'h6) pri_out_d2 = 8'b0100_0000; - else pri_out_d2 = 8'b1000_0000; - -// 4 Priority Levels -always @(valid or pri_in) - if(!valid) pri_out_d1 = 8'b0000_0001; - else - if(pri_in==3'h0) pri_out_d1 = 8'b0000_0001; - else - if(pri_in==3'h1) pri_out_d1 = 8'b0000_0010; - else - if(pri_in==3'h2) pri_out_d1 = 8'b0000_0100; - else pri_out_d1 = 8'b0000_1000; - -// 2 Priority Levels -always @(valid or pri_in) - if(!valid) pri_out_d0 = 8'b0000_0001; - else - if(pri_in==3'h0) pri_out_d0 = 8'b0000_0001; - else pri_out_d0 = 8'b0000_0010; - -endmodule - Index: trunk/rtl/verilog/wb_dma_ch_pri_enc.v =================================================================== --- trunk/rtl/verilog/wb_dma_ch_pri_enc.v (revision 16) +++ trunk/rtl/verilog/wb_dma_ch_pri_enc.v (nonexistent) @@ -1,380 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// WISHBONE DMA Priority Encoder //// -//// //// -//// //// -//// Author: Rudolf Usselmann //// -//// rudi@asics.ws //// -//// //// -//// //// -//// Downloaded from: http://www.opencores.org/cores/wb_dma/ //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000-2002 Rudolf Usselmann //// -//// www.asics.ws //// -//// rudi@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: wb_dma_ch_pri_enc.v,v 1.5 2002-02-01 01:54:44 rudi Exp $ -// -// $Date: 2002-02-01 01:54:44 $ -// $Revision: 1.5 $ -// $Author: rudi $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: not supported by cvs2svn $ -// Revision 1.4 2001/10/19 04:35:04 rudi -// -// - Made the core parameterized -// -// Revision 1.3 2001/08/15 05:40:30 rudi -// -// - Changed IO names to be more clear. -// - Uniquifyed define names to be core specific. -// - Added Section 3.10, describing DMA restart. -// -// Revision 1.2 2001/08/07 08:00:43 rudi -// -// -// Split up priority encoder modules to separate files -// -// Revision 1.1 2001/07/29 08:57:02 rudi -// -// -// 1) Changed Directory Structure -// 2) Added restart signal (REST) -// -// Revision 1.2 2001/06/05 10:22:36 rudi -// -// -// - Added Support of up to 31 channels -// - Added support for 2,4 and 8 priority levels -// - Now can have up to 31 channels -// - Added many configuration items -// - Changed reset to async -// -// Revision 1.1.1.1 2001/03/19 13:10:50 rudi -// Initial Release -// -// -// - -`include "wb_dma_defines.v" - -// Priority Encoder -// -// Determines the channel with the highest priority, also takes -// the valid bit in consideration - -module wb_dma_ch_pri_enc(clk, valid, - pri0, pri1, pri2, pri3, - pri4, pri5, pri6, pri7, - pri8, pri9, pri10, pri11, - pri12, pri13, pri14, pri15, - pri16, pri17, pri18, pri19, - pri20, pri21, pri22, pri23, - pri24, pri25, pri26, pri27, - pri28, pri29, pri30, - pri_out); - -//////////////////////////////////////////////////////////////////// -// -// Module Parameters -// - -// chXX_conf = { CBUF, ED, ARS, EN } -parameter [1:0] pri_sel = 2'd0; -parameter [3:0] ch0_conf = 4'h1; -parameter [3:0] ch1_conf = 4'h0; -parameter [3:0] ch2_conf = 4'h0; -parameter [3:0] ch3_conf = 4'h0; -parameter [3:0] ch4_conf = 4'h0; -parameter [3:0] ch5_conf = 4'h0; -parameter [3:0] ch6_conf = 4'h0; -parameter [3:0] ch7_conf = 4'h0; -parameter [3:0] ch8_conf = 4'h0; -parameter [3:0] ch9_conf = 4'h0; -parameter [3:0] ch10_conf = 4'h0; -parameter [3:0] ch11_conf = 4'h0; -parameter [3:0] ch12_conf = 4'h0; -parameter [3:0] ch13_conf = 4'h0; -parameter [3:0] ch14_conf = 4'h0; -parameter [3:0] ch15_conf = 4'h0; -parameter [3:0] ch16_conf = 4'h0; -parameter [3:0] ch17_conf = 4'h0; -parameter [3:0] ch18_conf = 4'h0; -parameter [3:0] ch19_conf = 4'h0; -parameter [3:0] ch20_conf = 4'h0; -parameter [3:0] ch21_conf = 4'h0; -parameter [3:0] ch22_conf = 4'h0; -parameter [3:0] ch23_conf = 4'h0; -parameter [3:0] ch24_conf = 4'h0; -parameter [3:0] ch25_conf = 4'h0; -parameter [3:0] ch26_conf = 4'h0; -parameter [3:0] ch27_conf = 4'h0; -parameter [3:0] ch28_conf = 4'h0; -parameter [3:0] ch29_conf = 4'h0; -parameter [3:0] ch30_conf = 4'h0; - -//////////////////////////////////////////////////////////////////// -// -// Module IOs -// - -input clk; -input [30:0] valid; // Channel Valid bits -input [2:0] pri0, pri1, pri2, pri3; // Channel Priorities -input [2:0] pri4, pri5, pri6, pri7; -input [2:0] pri8, pri9, pri10, pri11; -input [2:0] pri12, pri13, pri14, pri15; -input [2:0] pri16, pri17, pri18, pri19; -input [2:0] pri20, pri21, pri22, pri23; -input [2:0] pri24, pri25, pri26, pri27; -input [2:0] pri28, pri29, pri30; -output [2:0] pri_out; // Highest unserviced priority - -wire [7:0] pri0_out, pri1_out, pri2_out, pri3_out; -wire [7:0] pri4_out, pri5_out, pri6_out, pri7_out; -wire [7:0] pri8_out, pri9_out, pri10_out, pri11_out; -wire [7:0] pri12_out, pri13_out, pri14_out, pri15_out; -wire [7:0] pri16_out, pri17_out, pri18_out, pri19_out; -wire [7:0] pri20_out, pri21_out, pri22_out, pri23_out; -wire [7:0] pri24_out, pri25_out, pri26_out, pri27_out; -wire [7:0] pri28_out, pri29_out, pri30_out; - -wire [7:0] pri_out_tmp; -reg [2:0] pri_out; -reg [2:0] pri_out2; -reg [2:0] pri_out1; -reg [2:0] pri_out0; - -wb_dma_pri_enc_sub #(ch1_conf,pri_sel) u0( // Use channel config 1 for channel 0 encoder - .valid( valid[0] ), - .pri_in( pri0 ), - .pri_out( pri0_out ) - ); -wb_dma_pri_enc_sub #(ch1_conf,pri_sel) u1( - .valid( valid[1] ), - .pri_in( pri1 ), - .pri_out( pri1_out ) - ); -wb_dma_pri_enc_sub #(ch2_conf,pri_sel) u2( - .valid( valid[2] ), - .pri_in( pri2 ), - .pri_out( pri2_out ) - ); -wb_dma_pri_enc_sub #(ch3_conf,pri_sel) u3( - .valid( valid[3] ), - .pri_in( pri3 ), - .pri_out( pri3_out ) - ); -wb_dma_pri_enc_sub #(ch4_conf,pri_sel) u4( - .valid( valid[4] ), - .pri_in( pri4 ), - .pri_out( pri4_out ) - ); -wb_dma_pri_enc_sub #(ch5_conf,pri_sel) u5( - .valid( valid[5] ), - .pri_in( pri5 ), - .pri_out( pri5_out ) - ); -wb_dma_pri_enc_sub #(ch6_conf,pri_sel) u6( - .valid( valid[6] ), - .pri_in( pri6 ), - .pri_out( pri6_out ) - ); -wb_dma_pri_enc_sub #(ch7_conf,pri_sel) u7( - .valid( valid[7] ), - .pri_in( pri7 ), - .pri_out( pri7_out ) - ); -wb_dma_pri_enc_sub #(ch8_conf,pri_sel) u8( - .valid( valid[8] ), - .pri_in( pri8 ), - .pri_out( pri8_out ) - ); -wb_dma_pri_enc_sub #(ch9_conf,pri_sel) u9( - .valid( valid[9] ), - .pri_in( pri9 ), - .pri_out( pri9_out ) - ); -wb_dma_pri_enc_sub #(ch10_conf,pri_sel) u10( - .valid( valid[10] ), - .pri_in( pri10 ), - .pri_out( pri10_out ) - ); -wb_dma_pri_enc_sub #(ch11_conf,pri_sel) u11( - .valid( valid[11] ), - .pri_in( pri11 ), - .pri_out( pri11_out ) - ); -wb_dma_pri_enc_sub #(ch12_conf,pri_sel) u12( - .valid( valid[12] ), - .pri_in( pri12 ), - .pri_out( pri12_out ) - ); -wb_dma_pri_enc_sub #(ch13_conf,pri_sel) u13( - .valid( valid[13] ), - .pri_in( pri13 ), - .pri_out( pri13_out ) - ); -wb_dma_pri_enc_sub #(ch14_conf,pri_sel) u14( - .valid( valid[14] ), - .pri_in( pri14 ), - .pri_out( pri14_out ) - ); -wb_dma_pri_enc_sub #(ch15_conf,pri_sel) u15( - .valid( valid[15] ), - .pri_in( pri15 ), - .pri_out( pri15_out ) - ); -wb_dma_pri_enc_sub #(ch16_conf,pri_sel) u16( - .valid( valid[16] ), - .pri_in( pri16 ), - .pri_out( pri16_out ) - ); -wb_dma_pri_enc_sub #(ch17_conf,pri_sel) u17( - .valid( valid[17] ), - .pri_in( pri17 ), - .pri_out( pri17_out ) - ); -wb_dma_pri_enc_sub #(ch18_conf,pri_sel) u18( - .valid( valid[18] ), - .pri_in( pri18 ), - .pri_out( pri18_out ) - ); -wb_dma_pri_enc_sub #(ch19_conf,pri_sel) u19( - .valid( valid[19] ), - .pri_in( pri19 ), - .pri_out( pri19_out ) - ); -wb_dma_pri_enc_sub #(ch20_conf,pri_sel) u20( - .valid( valid[20] ), - .pri_in( pri20 ), - .pri_out( pri20_out ) - ); -wb_dma_pri_enc_sub #(ch21_conf,pri_sel) u21( - .valid( valid[21] ), - .pri_in( pri21 ), - .pri_out( pri21_out ) - ); -wb_dma_pri_enc_sub #(ch22_conf,pri_sel) u22( - .valid( valid[22] ), - .pri_in( pri22 ), - .pri_out( pri22_out ) - ); -wb_dma_pri_enc_sub #(ch23_conf,pri_sel) u23( - .valid( valid[23] ), - .pri_in( pri23 ), - .pri_out( pri23_out ) - ); -wb_dma_pri_enc_sub #(ch24_conf,pri_sel) u24( - .valid( valid[24] ), - .pri_in( pri24 ), - .pri_out( pri24_out ) - ); -wb_dma_pri_enc_sub #(ch25_conf,pri_sel) u25( - .valid( valid[25] ), - .pri_in( pri25 ), - .pri_out( pri25_out ) - ); -wb_dma_pri_enc_sub #(ch26_conf,pri_sel) u26( - .valid( valid[26] ), - .pri_in( pri26 ), - .pri_out( pri26_out ) - ); -wb_dma_pri_enc_sub #(ch27_conf,pri_sel) u27( - .valid( valid[27] ), - .pri_in( pri27 ), - .pri_out( pri27_out ) - ); -wb_dma_pri_enc_sub #(ch28_conf,pri_sel) u28( - .valid( valid[28] ), - .pri_in( pri28 ), - .pri_out( pri28_out ) - ); -wb_dma_pri_enc_sub #(ch29_conf,pri_sel) u29( - .valid( valid[29] ), - .pri_in( pri29 ), - .pri_out( pri29_out ) - ); -wb_dma_pri_enc_sub #(ch30_conf,pri_sel) u30( - .valid( valid[30] ), - .pri_in( pri30 ), - .pri_out( pri30_out ) - ); - -assign pri_out_tmp = pri0_out | pri1_out | pri2_out | pri3_out | - pri4_out | pri5_out | pri6_out | pri7_out | - pri8_out | pri9_out | pri10_out | pri11_out | - pri12_out | pri13_out | pri14_out | pri15_out | - pri16_out | pri17_out | pri18_out | pri19_out | - pri20_out | pri21_out | pri22_out | pri23_out | - pri24_out | pri25_out | pri26_out | pri27_out | - pri28_out | pri29_out | pri30_out; - -// 8 Priority Levels -always @(posedge clk) - if(pri_out_tmp[7]) pri_out2 <= #1 3'h7; - else - if(pri_out_tmp[6]) pri_out2 <= #1 3'h6; - else - if(pri_out_tmp[5]) pri_out2 <= #1 3'h5; - else - if(pri_out_tmp[4]) pri_out2 <= #1 3'h4; - else - if(pri_out_tmp[3]) pri_out2 <= #1 3'h3; - else - if(pri_out_tmp[2]) pri_out2 <= #1 3'h2; - else - if(pri_out_tmp[1]) pri_out2 <= #1 3'h1; - else pri_out2 <= #1 3'h0; - -// 4 Priority Levels -always @(posedge clk) - if(pri_out_tmp[3]) pri_out1 <= #1 3'h3; - else - if(pri_out_tmp[2]) pri_out1 <= #1 3'h2; - else - if(pri_out_tmp[1]) pri_out1 <= #1 3'h1; - else pri_out1 <= #1 3'h0; - -// 2 Priority Levels -always @(posedge clk) - if(pri_out_tmp[1]) pri_out0 <= #1 3'h1; - else pri_out0 <= #1 3'h0; - -// Select configured priority -always @(pri_sel or pri_out0 or pri_out1 or pri_out2) - case(pri_sel) // synopsys parallel_case full_case - 2'd0: pri_out = pri_out0; - 2'd1: pri_out = pri_out1; - 2'd2: pri_out = pri_out2; - endcase - -endmodule Index: trunk/rtl/verilog/wb_dma_wb_mast.v =================================================================== --- trunk/rtl/verilog/wb_dma_wb_mast.v (revision 16) +++ trunk/rtl/verilog/wb_dma_wb_mast.v (nonexistent) @@ -1,166 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// WISHBONE DMA WISHBONE Master Interface //// -//// //// -//// //// -//// Author: Rudolf Usselmann //// -//// rudi@asics.ws //// -//// //// -//// //// -//// Downloaded from: http://www.opencores.org/cores/wb_dma/ //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000-2002 Rudolf Usselmann //// -//// www.asics.ws //// -//// rudi@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: wb_dma_wb_mast.v,v 1.2 2002-02-01 01:54:45 rudi Exp $ -// -// $Date: 2002-02-01 01:54:45 $ -// $Revision: 1.2 $ -// $Author: rudi $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: not supported by cvs2svn $ -// Revision 1.1 2001/07/29 08:57:02 rudi -// -// -// 1) Changed Directory Structure -// 2) Added restart signal (REST) -// -// Revision 1.2 2001/06/05 10:22:37 rudi -// -// -// - Added Support of up to 31 channels -// - Added support for 2,4 and 8 priority levels -// - Now can have up to 31 channels -// - Added many configuration items -// - Changed reset to async -// -// Revision 1.1.1.1 2001/03/19 13:11:05 rudi -// Initial Release -// -// -// - -`include "wb_dma_defines.v" - -module wb_dma_wb_mast(clk, rst, - - wb_data_i, wb_data_o, wb_addr_o, wb_sel_o, wb_we_o, wb_cyc_o, - wb_stb_o, wb_ack_i, wb_err_i, wb_rty_i, - - mast_go, mast_we, mast_adr, mast_din, mast_dout, mast_err, - mast_drdy, mast_wait, - - pt_sel, mast_pt_in, mast_pt_out - ); - -input clk, rst; - -// -------------------------------------- -// WISHBONE INTERFACE - -input [31:0] wb_data_i; -output [31:0] wb_data_o; -output [31:0] wb_addr_o; -output [3:0] wb_sel_o; -output wb_we_o; -output wb_cyc_o; -output wb_stb_o; -input wb_ack_i; -input wb_err_i; -input wb_rty_i; - -// -------------------------------------- -// INTERNAL DMA INTERFACE -input mast_go; // Perform a Master Cycle (as long as this - // line is asserted) -input mast_we; // Read/Write -input [31:0] mast_adr; // Address for the transfer -input [31:0] mast_din; // Internal Input Data -output [31:0] mast_dout; // Internal Output Data -output mast_err; // Indicates an error has occurred - -output mast_drdy; // Indicated that either data is available - // during a read, or that the master can accept - // the next data during a write -input mast_wait; // Tells the master to insert wait cycles - // because data can not be accepted/provided - -// Pass Through Interface -input pt_sel; // Pass Through Mode Selected -input [70:0] mast_pt_in; // Grouped WISHBONE inputs -output [34:0] mast_pt_out; // Grouped WISHBONE outputs - -//////////////////////////////////////////////////////////////////// -// -// Local Wires -// - -reg mast_cyc, mast_stb; -reg mast_we_r; -reg [3:0] mast_be; -reg [31:0] mast_dout; - -//////////////////////////////////////////////////////////////////// -// -// Pass-Through Interface -// - -assign {wb_data_o, wb_addr_o, wb_sel_o, wb_we_o, wb_cyc_o, wb_stb_o} = - pt_sel ? mast_pt_in : - {mast_din, mast_adr, mast_be, mast_we_r, mast_cyc, mast_stb}; - -assign mast_pt_out = {wb_data_i, wb_ack_i, wb_err_i, wb_rty_i}; - -//////////////////////////////////////////////////////////////////// -// -// DMA Engine Interface -// - -always @(posedge clk) - if(wb_ack_i) mast_dout <= #1 wb_data_i; - -always @(posedge clk) - mast_be <= #1 4'hf; - -always @(posedge clk) - mast_we_r <= #1 mast_we; - -always @(posedge clk) - mast_cyc <= #1 mast_go; - -always @(posedge clk) - mast_stb <= #1 mast_go & !mast_wait; - -assign mast_drdy = wb_ack_i; -assign mast_err = wb_err_i; - -endmodule Index: trunk/rtl/verilog/wb_dma_wb_slv.v =================================================================== --- trunk/rtl/verilog/wb_dma_wb_slv.v (revision 16) +++ trunk/rtl/verilog/wb_dma_wb_slv.v (nonexistent) @@ -1,176 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// WISHBONE DMA WISHBONE Slave Interface //// -//// //// -//// //// -//// Author: Rudolf Usselmann //// -//// rudi@asics.ws //// -//// //// -//// //// -//// Downloaded from: http://www.opencores.org/cores/wb_dma/ //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000-2002 Rudolf Usselmann //// -//// www.asics.ws //// -//// rudi@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: wb_dma_wb_slv.v,v 1.4 2002-02-01 01:54:45 rudi Exp $ -// -// $Date: 2002-02-01 01:54:45 $ -// $Revision: 1.4 $ -// $Author: rudi $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: not supported by cvs2svn $ -// Revision 1.3 2001/10/19 04:35:04 rudi -// -// - Made the core parameterized -// -// Revision 1.2 2001/08/15 05:40:30 rudi -// -// - Changed IO names to be more clear. -// - Uniquifyed define names to be core specific. -// - Added Section 3.10, describing DMA restart. -// -// Revision 1.1 2001/07/29 08:57:02 rudi -// -// -// 1) Changed Directory Structure -// 2) Added restart signal (REST) -// -// Revision 1.2 2001/06/05 10:22:37 rudi -// -// -// - Added Support of up to 31 channels -// - Added support for 2,4 and 8 priority levels -// - Now can have up to 31 channels -// - Added many configuration items -// - Changed reset to async -// -// Revision 1.1.1.1 2001/03/19 13:10:59 rudi -// Initial Release -// -// -// - -`include "wb_dma_defines.v" - -module wb_dma_wb_slv(clk, rst, - - wb_data_i, wb_data_o, wb_addr_i, wb_sel_i, wb_we_i, wb_cyc_i, - wb_stb_i, wb_ack_o, wb_err_o, wb_rty_o, - - // This is the register File Interface - slv_adr, slv_din, slv_dout, slv_re, slv_we, - - // Pass through Interface - pt_sel, slv_pt_out, slv_pt_in - - ); - -parameter rf_addr = 0; - -input clk, rst; - -// -------------------------------------- -// WISHBONE INTERFACE - -input [31:0] wb_data_i; -output [31:0] wb_data_o; -input [31:0] wb_addr_i; -input [3:0] wb_sel_i; -input wb_we_i; -input wb_cyc_i; -input wb_stb_i; -output wb_ack_o; -output wb_err_o; -output wb_rty_o; - -// This is the register File Interface -output [31:0] slv_adr; // Slave Address -input [31:0] slv_din; // Slave Input Data -output [31:0] slv_dout; // Slave Output Data -output slv_re; // Slave Read Enable -output slv_we; // Slave Write Enable - -// Pass through Interface -output pt_sel; // Pass Through Mode Active -output [70:0] slv_pt_out; // Grouped WISHBONE out signals -input [34:0] slv_pt_in; // Grouped WISHBONE in signals - -//////////////////////////////////////////////////////////////////// -// -// Local Wires -// - -reg slv_re, slv_we; -wire rf_sel; -reg rf_ack; -reg [31:0] slv_adr, slv_dout; - -//////////////////////////////////////////////////////////////////// -// -// Misc Logic -// - -assign rf_sel = `WDMA_REG_SEL ; - -//////////////////////////////////////////////////////////////////// -// -// Pass Through Logic -// - -//assign pt_sel = !rf_sel; -assign pt_sel = !rf_sel & wb_cyc_i; - -assign slv_pt_out = {wb_data_i, wb_addr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i}; -assign {wb_data_o, wb_ack_o, wb_err_o, wb_rty_o} = pt_sel ? slv_pt_in : - {slv_din, rf_ack, 1'b0, 1'b0}; - -//////////////////////////////////////////////////////////////////// -// -// Register File Logic -// - -always @(posedge clk) - slv_adr <= #1 wb_addr_i; - -always @(posedge clk) - slv_re <= #1 rf_sel & wb_cyc_i & wb_stb_i & !wb_we_i & !rf_ack & !slv_re; - -always @(posedge clk) - slv_we <= #1 rf_sel & wb_cyc_i & wb_stb_i & wb_we_i & !rf_ack; - -always @(posedge clk) - slv_dout <= #1 wb_data_i; - -always @(posedge clk) - rf_ack <= #1 (slv_re | slv_we) & wb_cyc_i & wb_stb_i & !rf_ack ; - -endmodule Index: trunk/rtl/verilog/wb_dma_ch_sel.v =================================================================== --- trunk/rtl/verilog/wb_dma_ch_sel.v (revision 16) +++ trunk/rtl/verilog/wb_dma_ch_sel.v (nonexistent) @@ -1,1388 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// WISHBONE DMA Channel Select //// -//// //// -//// //// -//// Author: Rudolf Usselmann //// -//// rudi@asics.ws //// -//// //// -//// //// -//// Downloaded from: http://www.opencores.org/cores/wb_dma/ //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000-2002 Rudolf Usselmann //// -//// www.asics.ws //// -//// rudi@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: wb_dma_ch_sel.v,v 1.4 2002-02-01 01:54:45 rudi Exp $ -// -// $Date: 2002-02-01 01:54:45 $ -// $Revision: 1.4 $ -// $Author: rudi $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: not supported by cvs2svn $ -// Revision 1.3 2001/10/19 04:35:04 rudi -// -// - Made the core parameterized -// -// Revision 1.2 2001/08/15 05:40:30 rudi -// -// - Changed IO names to be more clear. -// - Uniquifyed define names to be core specific. -// - Added Section 3.10, describing DMA restart. -// -// Revision 1.1 2001/07/29 08:57:02 rudi -// -// -// 1) Changed Directory Structure -// 2) Added restart signal (REST) -// -// Revision 1.4 2001/06/14 08:52:00 rudi -// -// -// Changed arbiter module name. -// -// Revision 1.3 2001/06/13 02:26:48 rudi -// -// -// Small changes after running lint. -// -// Revision 1.2 2001/06/05 10:22:36 rudi -// -// -// - Added Support of up to 31 channels -// - Added support for 2,4 and 8 priority levels -// - Now can have up to 31 channels -// - Added many configuration items -// - Changed reset to async -// -// Revision 1.1.1.1 2001/03/19 13:10:35 rudi -// Initial Release -// -// -// - -`include "wb_dma_defines.v" - -module wb_dma_ch_sel(clk, rst, - - // DMA Request Lines - req_i, ack_o, nd_i, - - // DMA Registers Inputs - pointer0, pointer0_s, ch0_csr, ch0_txsz, ch0_adr0, ch0_adr1, ch0_am0, ch0_am1, - pointer1, pointer1_s, ch1_csr, ch1_txsz, ch1_adr0, ch1_adr1, ch1_am0, ch1_am1, - pointer2, pointer2_s, ch2_csr, ch2_txsz, ch2_adr0, ch2_adr1, ch2_am0, ch2_am1, - pointer3, pointer3_s, ch3_csr, ch3_txsz, ch3_adr0, ch3_adr1, ch3_am0, ch3_am1, - pointer4, pointer4_s, ch4_csr, ch4_txsz, ch4_adr0, ch4_adr1, ch4_am0, ch4_am1, - pointer5, pointer5_s, ch5_csr, ch5_txsz, ch5_adr0, ch5_adr1, ch5_am0, ch5_am1, - pointer6, pointer6_s, ch6_csr, ch6_txsz, ch6_adr0, ch6_adr1, ch6_am0, ch6_am1, - pointer7, pointer7_s, ch7_csr, ch7_txsz, ch7_adr0, ch7_adr1, ch7_am0, ch7_am1, - pointer8, pointer8_s, ch8_csr, ch8_txsz, ch8_adr0, ch8_adr1, ch8_am0, ch8_am1, - pointer9, pointer9_s, ch9_csr, ch9_txsz, ch9_adr0, ch9_adr1, ch9_am0, ch9_am1, - pointer10, pointer10_s, ch10_csr, ch10_txsz, ch10_adr0, ch10_adr1, ch10_am0, ch10_am1, - pointer11, pointer11_s, ch11_csr, ch11_txsz, ch11_adr0, ch11_adr1, ch11_am0, ch11_am1, - pointer12, pointer12_s, ch12_csr, ch12_txsz, ch12_adr0, ch12_adr1, ch12_am0, ch12_am1, - pointer13, pointer13_s, ch13_csr, ch13_txsz, ch13_adr0, ch13_adr1, ch13_am0, ch13_am1, - pointer14, pointer14_s, ch14_csr, ch14_txsz, ch14_adr0, ch14_adr1, ch14_am0, ch14_am1, - pointer15, pointer15_s, ch15_csr, ch15_txsz, ch15_adr0, ch15_adr1, ch15_am0, ch15_am1, - pointer16, pointer16_s, ch16_csr, ch16_txsz, ch16_adr0, ch16_adr1, ch16_am0, ch16_am1, - pointer17, pointer17_s, ch17_csr, ch17_txsz, ch17_adr0, ch17_adr1, ch17_am0, ch17_am1, - pointer18, pointer18_s, ch18_csr, ch18_txsz, ch18_adr0, ch18_adr1, ch18_am0, ch18_am1, - pointer19, pointer19_s, ch19_csr, ch19_txsz, ch19_adr0, ch19_adr1, ch19_am0, ch19_am1, - pointer20, pointer20_s, ch20_csr, ch20_txsz, ch20_adr0, ch20_adr1, ch20_am0, ch20_am1, - pointer21, pointer21_s, ch21_csr, ch21_txsz, ch21_adr0, ch21_adr1, ch21_am0, ch21_am1, - pointer22, pointer22_s, ch22_csr, ch22_txsz, ch22_adr0, ch22_adr1, ch22_am0, ch22_am1, - pointer23, pointer23_s, ch23_csr, ch23_txsz, ch23_adr0, ch23_adr1, ch23_am0, ch23_am1, - pointer24, pointer24_s, ch24_csr, ch24_txsz, ch24_adr0, ch24_adr1, ch24_am0, ch24_am1, - pointer25, pointer25_s, ch25_csr, ch25_txsz, ch25_adr0, ch25_adr1, ch25_am0, ch25_am1, - pointer26, pointer26_s, ch26_csr, ch26_txsz, ch26_adr0, ch26_adr1, ch26_am0, ch26_am1, - pointer27, pointer27_s, ch27_csr, ch27_txsz, ch27_adr0, ch27_adr1, ch27_am0, ch27_am1, - pointer28, pointer28_s, ch28_csr, ch28_txsz, ch28_adr0, ch28_adr1, ch28_am0, ch28_am1, - pointer29, pointer29_s, ch29_csr, ch29_txsz, ch29_adr0, ch29_adr1, ch29_am0, ch29_am1, - pointer30, pointer30_s, ch30_csr, ch30_txsz, ch30_adr0, ch30_adr1, ch30_am0, ch30_am1, - - // DMA Registers Write Back Channel Select - ch_sel, ndnr, - - // DMA Engine Interface - de_start, ndr, csr, pointer, txsz, adr0, adr1, am0, am1, - pointer_s, next_ch, de_ack, dma_busy - ); - -//////////////////////////////////////////////////////////////////// -// -// Module Parameters -// - -// chXX_conf = { CBUF, ED, ARS, EN } -parameter [1:0] pri_sel = 2'h0; -parameter [3:0] ch0_conf = 4'h1; -parameter [3:0] ch1_conf = 4'h0; -parameter [3:0] ch2_conf = 4'h0; -parameter [3:0] ch3_conf = 4'h0; -parameter [3:0] ch4_conf = 4'h0; -parameter [3:0] ch5_conf = 4'h0; -parameter [3:0] ch6_conf = 4'h0; -parameter [3:0] ch7_conf = 4'h0; -parameter [3:0] ch8_conf = 4'h0; -parameter [3:0] ch9_conf = 4'h0; -parameter [3:0] ch10_conf = 4'h0; -parameter [3:0] ch11_conf = 4'h0; -parameter [3:0] ch12_conf = 4'h0; -parameter [3:0] ch13_conf = 4'h0; -parameter [3:0] ch14_conf = 4'h0; -parameter [3:0] ch15_conf = 4'h0; -parameter [3:0] ch16_conf = 4'h0; -parameter [3:0] ch17_conf = 4'h0; -parameter [3:0] ch18_conf = 4'h0; -parameter [3:0] ch19_conf = 4'h0; -parameter [3:0] ch20_conf = 4'h0; -parameter [3:0] ch21_conf = 4'h0; -parameter [3:0] ch22_conf = 4'h0; -parameter [3:0] ch23_conf = 4'h0; -parameter [3:0] ch24_conf = 4'h0; -parameter [3:0] ch25_conf = 4'h0; -parameter [3:0] ch26_conf = 4'h0; -parameter [3:0] ch27_conf = 4'h0; -parameter [3:0] ch28_conf = 4'h0; -parameter [3:0] ch29_conf = 4'h0; -parameter [3:0] ch30_conf = 4'h0; - -//////////////////////////////////////////////////////////////////// -// -// Module IOs -// - -input clk, rst; - -// DMA Request Lines -input [30:0] req_i; -output [30:0] ack_o; -input [30:0] nd_i; - -// Channel Registers Inputs -input [31:0] pointer0, pointer0_s, ch0_csr, ch0_txsz, ch0_adr0, ch0_adr1, ch0_am0, ch0_am1; -input [31:0] pointer1, pointer1_s, ch1_csr, ch1_txsz, ch1_adr0, ch1_adr1, ch1_am0, ch1_am1; -input [31:0] pointer2, pointer2_s, ch2_csr, ch2_txsz, ch2_adr0, ch2_adr1, ch2_am0, ch2_am1; -input [31:0] pointer3, pointer3_s, ch3_csr, ch3_txsz, ch3_adr0, ch3_adr1, ch3_am0, ch3_am1; -input [31:0] pointer4, pointer4_s, ch4_csr, ch4_txsz, ch4_adr0, ch4_adr1, ch4_am0, ch4_am1; -input [31:0] pointer5, pointer5_s, ch5_csr, ch5_txsz, ch5_adr0, ch5_adr1, ch5_am0, ch5_am1; -input [31:0] pointer6, pointer6_s, ch6_csr, ch6_txsz, ch6_adr0, ch6_adr1, ch6_am0, ch6_am1; -input [31:0] pointer7, pointer7_s, ch7_csr, ch7_txsz, ch7_adr0, ch7_adr1, ch7_am0, ch7_am1; -input [31:0] pointer8, pointer8_s, ch8_csr, ch8_txsz, ch8_adr0, ch8_adr1, ch8_am0, ch8_am1; -input [31:0] pointer9, pointer9_s, ch9_csr, ch9_txsz, ch9_adr0, ch9_adr1, ch9_am0, ch9_am1; -input [31:0] pointer10, pointer10_s, ch10_csr, ch10_txsz, ch10_adr0, ch10_adr1, ch10_am0, ch10_am1; -input [31:0] pointer11, pointer11_s, ch11_csr, ch11_txsz, ch11_adr0, ch11_adr1, ch11_am0, ch11_am1; -input [31:0] pointer12, pointer12_s, ch12_csr, ch12_txsz, ch12_adr0, ch12_adr1, ch12_am0, ch12_am1; -input [31:0] pointer13, pointer13_s, ch13_csr, ch13_txsz, ch13_adr0, ch13_adr1, ch13_am0, ch13_am1; -input [31:0] pointer14, pointer14_s, ch14_csr, ch14_txsz, ch14_adr0, ch14_adr1, ch14_am0, ch14_am1; -input [31:0] pointer15, pointer15_s, ch15_csr, ch15_txsz, ch15_adr0, ch15_adr1, ch15_am0, ch15_am1; -input [31:0] pointer16, pointer16_s, ch16_csr, ch16_txsz, ch16_adr0, ch16_adr1, ch16_am0, ch16_am1; -input [31:0] pointer17, pointer17_s, ch17_csr, ch17_txsz, ch17_adr0, ch17_adr1, ch17_am0, ch17_am1; -input [31:0] pointer18, pointer18_s, ch18_csr, ch18_txsz, ch18_adr0, ch18_adr1, ch18_am0, ch18_am1; -input [31:0] pointer19, pointer19_s, ch19_csr, ch19_txsz, ch19_adr0, ch19_adr1, ch19_am0, ch19_am1; -input [31:0] pointer20, pointer20_s, ch20_csr, ch20_txsz, ch20_adr0, ch20_adr1, ch20_am0, ch20_am1; -input [31:0] pointer21, pointer21_s, ch21_csr, ch21_txsz, ch21_adr0, ch21_adr1, ch21_am0, ch21_am1; -input [31:0] pointer22, pointer22_s, ch22_csr, ch22_txsz, ch22_adr0, ch22_adr1, ch22_am0, ch22_am1; -input [31:0] pointer23, pointer23_s, ch23_csr, ch23_txsz, ch23_adr0, ch23_adr1, ch23_am0, ch23_am1; -input [31:0] pointer24, pointer24_s, ch24_csr, ch24_txsz, ch24_adr0, ch24_adr1, ch24_am0, ch24_am1; -input [31:0] pointer25, pointer25_s, ch25_csr, ch25_txsz, ch25_adr0, ch25_adr1, ch25_am0, ch25_am1; -input [31:0] pointer26, pointer26_s, ch26_csr, ch26_txsz, ch26_adr0, ch26_adr1, ch26_am0, ch26_am1; -input [31:0] pointer27, pointer27_s, ch27_csr, ch27_txsz, ch27_adr0, ch27_adr1, ch27_am0, ch27_am1; -input [31:0] pointer28, pointer28_s, ch28_csr, ch28_txsz, ch28_adr0, ch28_adr1, ch28_am0, ch28_am1; -input [31:0] pointer29, pointer29_s, ch29_csr, ch29_txsz, ch29_adr0, ch29_adr1, ch29_am0, ch29_am1; -input [31:0] pointer30, pointer30_s, ch30_csr, ch30_txsz, ch30_adr0, ch30_adr1, ch30_am0, ch30_am1; - -output [4:0] ch_sel; // Write Back Channel Select -output [30:0] ndnr; // Next Descriptor No Request - -output de_start; // Start DMA Engine Indicator -output ndr; // Next Descriptor With Request (for current channel) -output [31:0] csr; // Selected Channel CSR -output [31:0] pointer; // LL Descriptor pointer -output [31:0] pointer_s; // LL Descriptor previous pointer -output [31:0] txsz; // Selected Channel Transfer Size -output [31:0] adr0, adr1; // Selected Channel Addresses -output [31:0] am0, am1; // Selected Channel Address Masks - -input next_ch; // Indicates the DMA Engine is done - // with current transfer -input de_ack; // DMA engine ack output - -input dma_busy; - -//////////////////////////////////////////////////////////////////// -// -// Local Wires and Registers -// - -reg [30:0] ack_o; -wire [30:0] valid; // Indicates which channel is valid -reg valid_sel; -reg [30:0] req_r; // Channel Request inputs -reg [30:0] ndr_r; // Next Descriptor Registered (and Request) -reg [30:0] ndnr; // Next Descriptor Registered (and Not Request) -wire [2:0] pri_out; // Highest unserviced priority -wire [2:0] pri0, pri1, pri2, pri3; // Channel Priorities -wire [2:0] pri4, pri5, pri6, pri7; -wire [2:0] pri8, pri9, pri10, pri11; -wire [2:0] pri12, pri13, pri14, pri15; -wire [2:0] pri16, pri17, pri18, pri19; -wire [2:0] pri20, pri21, pri22, pri23; -wire [2:0] pri24, pri25, pri26, pri27; -wire [2:0] pri28, pri29, pri30; -reg [4:0] ch_sel_d; -reg [4:0] ch_sel_r; - -reg ndr; -reg next_start; -reg de_start_r; -reg [31:0] csr; // Selected Channel CSR -reg [31:0] pointer; -reg [31:0] pointer_s; -reg [31:0] txsz; // Selected Channel Transfer Size -reg [31:0] adr0, adr1; // Selected Channel Addresses -reg [31:0] am0, am1; // Selected Channel Address Masks - - // Arbiter Request Inputs -wire [30:0] req_p0, req_p1, req_p2, req_p3; -wire [30:0] req_p4, req_p5, req_p6, req_p7; -wire [30:0] req_p8, req_p9, req_p10, req_p11; -wire [30:0] req_p12, req_p13, req_p14, req_p15; -wire [30:0] req_p16, req_p17, req_p18, req_p19; -wire [30:0] req_p20, req_p21, req_p22, req_p23; -wire [30:0] req_p24, req_p25, req_p26, req_p27; -wire [30:0] req_p28, req_p29, req_p30; - // Arbiter Grant Outputs -wire [4:0] gnt_p0_d, gnt_p1_d, gnt_p2_d, gnt_p3_d; -wire [4:0] gnt_p4_d, gnt_p5_d, gnt_p6_d, gnt_p7_d; -wire [4:0] gnt_p0, gnt_p1, gnt_p2, gnt_p3; -wire [4:0] gnt_p4, gnt_p5, gnt_p6, gnt_p7; -wire [4:0] gnt_p8, gnt_p9, gnt_p10, gnt_p11; -wire [4:0] gnt_p12, gnt_p13, gnt_p14, gnt_p15; -wire [4:0] gnt_p16, gnt_p17, gnt_p18, gnt_p19; -wire [4:0] gnt_p20, gnt_p21, gnt_p22, gnt_p23; -wire [4:0] gnt_p24, gnt_p25, gnt_p26, gnt_p27; -wire [4:0] gnt_p28, gnt_p29, gnt_p30; - - -//////////////////////////////////////////////////////////////////// -// -// Aliases -// - -assign pri0[0] = ch0_csr[13]; -assign pri0[1] = (pri_sel == 2'd0) ? 1'b0 : ch0_csr[14]; -assign pri0[2] = (pri_sel == 2'd2) ? ch0_csr[15] : 1'b0; -assign pri1[0] = ch1_csr[13]; -assign pri1[1] = (pri_sel == 2'd0) ? 1'b0 : ch1_csr[14]; -assign pri1[2] = (pri_sel == 2'd2) ? ch1_csr[15] : 1'b0; -assign pri2[0] = ch2_csr[13]; -assign pri2[1] = (pri_sel == 2'd0) ? 1'b0 : ch2_csr[14]; -assign pri2[2] = (pri_sel == 2'd2) ? ch2_csr[15] : 1'b0; -assign pri3[0] = ch3_csr[13]; -assign pri3[1] = (pri_sel == 2'd0) ? 1'b0 : ch3_csr[14]; -assign pri3[2] = (pri_sel == 2'd2) ? ch3_csr[15] : 1'b0; -assign pri4[0] = ch4_csr[13]; -assign pri4[1] = (pri_sel == 2'd0) ? 1'b0 : ch4_csr[14]; -assign pri4[2] = (pri_sel == 2'd2) ? ch4_csr[15] : 1'b0; -assign pri5[0] = ch5_csr[13]; -assign pri5[1] = (pri_sel == 2'd0) ? 1'b0 : ch5_csr[14]; -assign pri5[2] = (pri_sel == 2'd2) ? ch5_csr[15] : 1'b0; -assign pri6[0] = ch6_csr[13]; -assign pri6[1] = (pri_sel == 2'd0) ? 1'b0 : ch6_csr[14]; -assign pri6[2] = (pri_sel == 2'd2) ? ch6_csr[15] : 1'b0; -assign pri7[0] = ch7_csr[13]; -assign pri7[1] = (pri_sel == 2'd0) ? 1'b0 : ch7_csr[14]; -assign pri7[2] = (pri_sel == 2'd2) ? ch7_csr[15] : 1'b0; -assign pri8[0] = ch8_csr[13]; -assign pri8[1] = (pri_sel == 2'd0) ? 1'b0 : ch8_csr[14]; -assign pri8[2] = (pri_sel == 2'd2) ? ch8_csr[15] : 1'b0; -assign pri9[0] = ch9_csr[13]; -assign pri9[1] = (pri_sel == 2'd0) ? 1'b0 : ch9_csr[14]; -assign pri9[2] = (pri_sel == 2'd2) ? ch9_csr[15] : 1'b0; -assign pri10[0] = ch10_csr[13]; -assign pri10[1] = (pri_sel == 2'd0) ? 1'b0 : ch10_csr[14]; -assign pri10[2] = (pri_sel == 2'd2) ? ch10_csr[15] : 1'b0; -assign pri11[0] = ch11_csr[13]; -assign pri11[1] = (pri_sel == 2'd0) ? 1'b0 : ch11_csr[14]; -assign pri11[2] = (pri_sel == 2'd2) ? ch11_csr[15] : 1'b0; -assign pri12[0] = ch12_csr[13]; -assign pri12[1] = (pri_sel == 2'd0) ? 1'b0 : ch12_csr[14]; -assign pri12[2] = (pri_sel == 2'd2) ? ch12_csr[15] : 1'b0; -assign pri13[0] = ch13_csr[13]; -assign pri13[1] = (pri_sel == 2'd0) ? 1'b0 : ch13_csr[14]; -assign pri13[2] = (pri_sel == 2'd2) ? ch13_csr[15] : 1'b0; -assign pri14[0] = ch14_csr[13]; -assign pri14[1] = (pri_sel == 2'd0) ? 1'b0 : ch14_csr[14]; -assign pri14[2] = (pri_sel == 2'd2) ? ch14_csr[15] : 1'b0; -assign pri15[0] = ch15_csr[13]; -assign pri15[1] = (pri_sel == 2'd0) ? 1'b0 : ch15_csr[14]; -assign pri15[2] = (pri_sel == 2'd2) ? ch15_csr[15] : 1'b0; -assign pri16[0] = ch16_csr[13]; -assign pri16[1] = (pri_sel == 2'd0) ? 1'b0 : ch16_csr[14]; -assign pri16[2] = (pri_sel == 2'd2) ? ch16_csr[15] : 1'b0; -assign pri17[0] = ch17_csr[13]; -assign pri17[1] = (pri_sel == 2'd0) ? 1'b0 : ch17_csr[14]; -assign pri17[2] = (pri_sel == 2'd2) ? ch17_csr[15] : 1'b0; -assign pri18[0] = ch18_csr[13]; -assign pri18[1] = (pri_sel == 2'd0) ? 1'b0 : ch18_csr[14]; -assign pri18[2] = (pri_sel == 2'd2) ? ch18_csr[15] : 1'b0; -assign pri19[0] = ch19_csr[13]; -assign pri19[1] = (pri_sel == 2'd0) ? 1'b0 : ch19_csr[14]; -assign pri19[2] = (pri_sel == 2'd2) ? ch19_csr[15] : 1'b0; -assign pri20[0] = ch20_csr[13]; -assign pri20[1] = (pri_sel == 2'd0) ? 1'b0 : ch20_csr[14]; -assign pri20[2] = (pri_sel == 2'd2) ? ch20_csr[15] : 1'b0; -assign pri21[0] = ch21_csr[13]; -assign pri21[1] = (pri_sel == 2'd0) ? 1'b0 : ch21_csr[14]; -assign pri21[2] = (pri_sel == 2'd2) ? ch21_csr[15] : 1'b0; -assign pri22[0] = ch22_csr[13]; -assign pri22[1] = (pri_sel == 2'd0) ? 1'b0 : ch22_csr[14]; -assign pri22[2] = (pri_sel == 2'd2) ? ch22_csr[15] : 1'b0; -assign pri23[0] = ch23_csr[13]; -assign pri23[1] = (pri_sel == 2'd0) ? 1'b0 : ch23_csr[14]; -assign pri23[2] = (pri_sel == 2'd2) ? ch23_csr[15] : 1'b0; -assign pri24[0] = ch24_csr[13]; -assign pri24[1] = (pri_sel == 2'd0) ? 1'b0 : ch24_csr[14]; -assign pri24[2] = (pri_sel == 2'd2) ? ch24_csr[15] : 1'b0; -assign pri25[0] = ch25_csr[13]; -assign pri25[1] = (pri_sel == 2'd0) ? 1'b0 : ch25_csr[14]; -assign pri25[2] = (pri_sel == 2'd2) ? ch25_csr[15] : 1'b0; -assign pri26[0] = ch26_csr[13]; -assign pri26[1] = (pri_sel == 2'd0) ? 1'b0 : ch26_csr[14]; -assign pri26[2] = (pri_sel == 2'd2) ? ch26_csr[15] : 1'b0; -assign pri27[0] = ch27_csr[13]; -assign pri27[1] = (pri_sel == 2'd0) ? 1'b0 : ch27_csr[14]; -assign pri27[2] = (pri_sel == 2'd2) ? ch27_csr[15] : 1'b0; -assign pri28[0] = ch28_csr[13]; -assign pri28[1] = (pri_sel == 2'd0) ? 1'b0 : ch28_csr[14]; -assign pri28[2] = (pri_sel == 2'd2) ? ch28_csr[15] : 1'b0; -assign pri29[0] = ch29_csr[13]; -assign pri29[1] = (pri_sel == 2'd0) ? 1'b0 : ch29_csr[14]; -assign pri29[2] = (pri_sel == 2'd2) ? ch29_csr[15] : 1'b0; -assign pri30[0] = ch30_csr[13]; -assign pri30[1] = (pri_sel == 2'd0) ? 1'b0 : ch30_csr[14]; -assign pri30[2] = (pri_sel == 2'd2) ? ch30_csr[15] : 1'b0; - -//////////////////////////////////////////////////////////////////// -// -// Misc logic -// - -// Chanel Valid flag -// The valid flag is asserted when the channel is enabled, -// and is either in "normal mode" (software control) or -// "hw handshake mode" (reqN control) -// validN = ch_enabled & (sw_mode | (hw_mode & reqN) ) - -always @(posedge clk) - req_r <= #1 req_i & ~ack_o; - -assign valid[0] = ch0_conf[0] & ch0_csr[`WDMA_CH_EN] & (ch0_csr[`WDMA_MODE] ? (req_r[0] & !ack_o[0]) : 1'b1); -assign valid[1] = ch1_conf[0] & ch1_csr[`WDMA_CH_EN] & (ch1_csr[`WDMA_MODE] ? (req_r[1] & !ack_o[1]) : 1'b1); -assign valid[2] = ch2_conf[0] & ch2_csr[`WDMA_CH_EN] & (ch2_csr[`WDMA_MODE] ? (req_r[2] & !ack_o[2]) : 1'b1); -assign valid[3] = ch3_conf[0] & ch3_csr[`WDMA_CH_EN] & (ch3_csr[`WDMA_MODE] ? (req_r[3] & !ack_o[3]) : 1'b1); -assign valid[4] = ch4_conf[0] & ch4_csr[`WDMA_CH_EN] & (ch4_csr[`WDMA_MODE] ? (req_r[4] & !ack_o[4]) : 1'b1); -assign valid[5] = ch5_conf[0] & ch5_csr[`WDMA_CH_EN] & (ch5_csr[`WDMA_MODE] ? (req_r[5] & !ack_o[5]) : 1'b1); -assign valid[6] = ch6_conf[0] & ch6_csr[`WDMA_CH_EN] & (ch6_csr[`WDMA_MODE] ? (req_r[6] & !ack_o[6]) : 1'b1); -assign valid[7] = ch7_conf[0] & ch7_csr[`WDMA_CH_EN] & (ch7_csr[`WDMA_MODE] ? (req_r[7] & !ack_o[7]) : 1'b1); -assign valid[8] = ch8_conf[0] & ch8_csr[`WDMA_CH_EN] & (ch8_csr[`WDMA_MODE] ? (req_r[8] & !ack_o[8]) : 1'b1); -assign valid[9] = ch9_conf[0] & ch9_csr[`WDMA_CH_EN] & (ch9_csr[`WDMA_MODE] ? (req_r[9] & !ack_o[9]) : 1'b1); -assign valid[10] = ch10_conf[0] & ch10_csr[`WDMA_CH_EN] & (ch10_csr[`WDMA_MODE] ? (req_r[10] & !ack_o[10]) : 1'b1); -assign valid[11] = ch11_conf[0] & ch11_csr[`WDMA_CH_EN] & (ch11_csr[`WDMA_MODE] ? (req_r[11] & !ack_o[11]) : 1'b1); -assign valid[12] = ch12_conf[0] & ch12_csr[`WDMA_CH_EN] & (ch12_csr[`WDMA_MODE] ? (req_r[12] & !ack_o[12]) : 1'b1); -assign valid[13] = ch13_conf[0] & ch13_csr[`WDMA_CH_EN] & (ch13_csr[`WDMA_MODE] ? (req_r[13] & !ack_o[13]) : 1'b1); -assign valid[14] = ch14_conf[0] & ch14_csr[`WDMA_CH_EN] & (ch14_csr[`WDMA_MODE] ? (req_r[14] & !ack_o[14]) : 1'b1); -assign valid[15] = ch15_conf[0] & ch15_csr[`WDMA_CH_EN] & (ch15_csr[`WDMA_MODE] ? (req_r[15] & !ack_o[15]) : 1'b1); -assign valid[16] = ch16_conf[0] & ch16_csr[`WDMA_CH_EN] & (ch16_csr[`WDMA_MODE] ? (req_r[16] & !ack_o[16]) : 1'b1); -assign valid[17] = ch17_conf[0] & ch17_csr[`WDMA_CH_EN] & (ch17_csr[`WDMA_MODE] ? (req_r[17] & !ack_o[17]) : 1'b1); -assign valid[18] = ch18_conf[0] & ch18_csr[`WDMA_CH_EN] & (ch18_csr[`WDMA_MODE] ? (req_r[18] & !ack_o[18]) : 1'b1); -assign valid[19] = ch19_conf[0] & ch19_csr[`WDMA_CH_EN] & (ch19_csr[`WDMA_MODE] ? (req_r[19] & !ack_o[19]) : 1'b1); -assign valid[20] = ch20_conf[0] & ch20_csr[`WDMA_CH_EN] & (ch20_csr[`WDMA_MODE] ? (req_r[20] & !ack_o[20]) : 1'b1); -assign valid[21] = ch21_conf[0] & ch21_csr[`WDMA_CH_EN] & (ch21_csr[`WDMA_MODE] ? (req_r[21] & !ack_o[21]) : 1'b1); -assign valid[22] = ch22_conf[0] & ch22_csr[`WDMA_CH_EN] & (ch22_csr[`WDMA_MODE] ? (req_r[22] & !ack_o[22]) : 1'b1); -assign valid[23] = ch23_conf[0] & ch23_csr[`WDMA_CH_EN] & (ch23_csr[`WDMA_MODE] ? (req_r[23] & !ack_o[23]) : 1'b1); -assign valid[24] = ch24_conf[0] & ch24_csr[`WDMA_CH_EN] & (ch24_csr[`WDMA_MODE] ? (req_r[24] & !ack_o[24]) : 1'b1); -assign valid[25] = ch25_conf[0] & ch25_csr[`WDMA_CH_EN] & (ch25_csr[`WDMA_MODE] ? (req_r[25] & !ack_o[25]) : 1'b1); -assign valid[26] = ch26_conf[0] & ch26_csr[`WDMA_CH_EN] & (ch26_csr[`WDMA_MODE] ? (req_r[26] & !ack_o[26]) : 1'b1); -assign valid[27] = ch27_conf[0] & ch27_csr[`WDMA_CH_EN] & (ch27_csr[`WDMA_MODE] ? (req_r[27] & !ack_o[27]) : 1'b1); -assign valid[28] = ch28_conf[0] & ch28_csr[`WDMA_CH_EN] & (ch28_csr[`WDMA_MODE] ? (req_r[28] & !ack_o[28]) : 1'b1); -assign valid[29] = ch29_conf[0] & ch29_csr[`WDMA_CH_EN] & (ch29_csr[`WDMA_MODE] ? (req_r[29] & !ack_o[29]) : 1'b1); -assign valid[30] = ch30_conf[0] & ch30_csr[`WDMA_CH_EN] & (ch30_csr[`WDMA_MODE] ? (req_r[30] & !ack_o[30]) : 1'b1); - -always @(posedge clk) - ndr_r <= #1 nd_i & req_i; - -always @(posedge clk) - ndnr <= #1 nd_i & ~req_i; - -// Start Signal for DMA engine -assign de_start = (valid_sel & !de_start_r ) | next_start; - -always @(posedge clk) - de_start_r <= #1 valid_sel; - -always @(posedge clk) - next_start <= #1 next_ch & valid_sel; - -// Ack outputs for HW handshake mode -always @(posedge clk) - ack_o[0] <= #1 ch0_conf[0] & (ch_sel == 5'h0) & ch0_csr[`WDMA_MODE] & de_ack; - -always @(posedge clk) - ack_o[1] <= #1 ch1_conf[0] & (ch_sel == 5'h1) & ch1_csr[`WDMA_MODE] & de_ack; - -always @(posedge clk) - ack_o[2] <= #1 ch2_conf[0] & (ch_sel == 5'h2) & ch2_csr[`WDMA_MODE] & de_ack; - -always @(posedge clk) - ack_o[3] <= #1 ch3_conf[0] & (ch_sel == 5'h3) & ch3_csr[`WDMA_MODE] & de_ack; - -always @(posedge clk) - ack_o[4] <= #1 ch4_conf[0] & (ch_sel == 5'h4) & ch4_csr[`WDMA_MODE] & de_ack; - -always @(posedge clk) - ack_o[5] <= #1 ch5_conf[0] & (ch_sel == 5'h5) & ch5_csr[`WDMA_MODE] & de_ack; - -always @(posedge clk) - ack_o[6] <= #1 ch6_conf[0] & (ch_sel == 5'h6) & ch6_csr[`WDMA_MODE] & de_ack; - -always @(posedge clk) - ack_o[7] <= #1 ch7_conf[0] & (ch_sel == 5'h7) & ch7_csr[`WDMA_MODE] & de_ack; - -always @(posedge clk) - ack_o[8] <= #1 ch8_conf[0] & (ch_sel == 5'h8) & ch8_csr[`WDMA_MODE] & de_ack; - -always @(posedge clk) - ack_o[9] <= #1 ch9_conf[0] & (ch_sel == 5'h9) & ch9_csr[`WDMA_MODE] & de_ack; - -always @(posedge clk) - ack_o[10] <= #1 ch10_conf[0] & (ch_sel == 5'ha) & ch10_csr[`WDMA_MODE] & de_ack; - -always @(posedge clk) - ack_o[11] <= #1 ch11_conf[0] & (ch_sel == 5'hb) & ch11_csr[`WDMA_MODE] & de_ack; - -always @(posedge clk) - ack_o[12] <= #1 ch12_conf[0] & (ch_sel == 5'hc) & ch12_csr[`WDMA_MODE] & de_ack; - -always @(posedge clk) - ack_o[13] <= #1 ch13_conf[0] & (ch_sel == 5'hd) & ch13_csr[`WDMA_MODE] & de_ack; - -always @(posedge clk) - ack_o[14] <= #1 ch14_conf[0] & (ch_sel == 5'he) & ch14_csr[`WDMA_MODE] & de_ack; - -always @(posedge clk) - ack_o[15] <= #1 ch15_conf[0] & (ch_sel == 5'hf) & ch15_csr[`WDMA_MODE] & de_ack; - -always @(posedge clk) - ack_o[16] <= #1 ch16_conf[0] & (ch_sel == 5'h10) & ch16_csr[`WDMA_MODE] & de_ack; - -always @(posedge clk) - ack_o[17] <= #1 ch17_conf[0] & (ch_sel == 5'h11) & ch17_csr[`WDMA_MODE] & de_ack; - -always @(posedge clk) - ack_o[18] <= #1 ch18_conf[0] & (ch_sel == 5'h12) & ch18_csr[`WDMA_MODE] & de_ack; - -always @(posedge clk) - ack_o[19] <= #1 ch19_conf[0] & (ch_sel == 5'h13) & ch19_csr[`WDMA_MODE] & de_ack; - -always @(posedge clk) - ack_o[20] <= #1 ch20_conf[0] & (ch_sel == 5'h14) & ch20_csr[`WDMA_MODE] & de_ack; - -always @(posedge clk) - ack_o[21] <= #1 ch21_conf[0] & (ch_sel == 5'h15) & ch21_csr[`WDMA_MODE] & de_ack; - -always @(posedge clk) - ack_o[22] <= #1 ch22_conf[0] & (ch_sel == 5'h16) & ch22_csr[`WDMA_MODE] & de_ack; - -always @(posedge clk) - ack_o[23] <= #1 ch23_conf[0] & (ch_sel == 5'h17) & ch23_csr[`WDMA_MODE] & de_ack; - -always @(posedge clk) - ack_o[24] <= #1 ch24_conf[0] & (ch_sel == 5'h18) & ch24_csr[`WDMA_MODE] & de_ack; - -always @(posedge clk) - ack_o[25] <= #1 ch25_conf[0] & (ch_sel == 5'h19) & ch25_csr[`WDMA_MODE] & de_ack; - -always @(posedge clk) - ack_o[26] <= #1 ch26_conf[0] & (ch_sel == 5'h1a) & ch26_csr[`WDMA_MODE] & de_ack; - -always @(posedge clk) - ack_o[27] <= #1 ch27_conf[0] & (ch_sel == 5'h1b) & ch27_csr[`WDMA_MODE] & de_ack; - -always @(posedge clk) - ack_o[28] <= #1 ch28_conf[0] & (ch_sel == 5'h1c) & ch28_csr[`WDMA_MODE] & de_ack; - -always @(posedge clk) - ack_o[29] <= #1 ch29_conf[0] & (ch_sel == 5'h1d) & ch29_csr[`WDMA_MODE] & de_ack; - -always @(posedge clk) - ack_o[30] <= #1 ch30_conf[0] & (ch_sel == 5'h1e) & ch30_csr[`WDMA_MODE] & de_ack; - -// Channel Select -always @(posedge clk or negedge rst) - if(!rst) ch_sel_r <= #1 0; - else - if(de_start) ch_sel_r <= #1 ch_sel_d; - -assign ch_sel = !dma_busy ? ch_sel_d : ch_sel_r; - -//////////////////////////////////////////////////////////////////// -// -// Select Registers based on arbiter (and priority) outputs -// - -always @(ch_sel or valid) - case(ch_sel) // synopsys parallel_case full_case - 5'h0: valid_sel = valid[0]; - 5'h1: valid_sel = valid[1]; - 5'h2: valid_sel = valid[2]; - 5'h3: valid_sel = valid[3]; - 5'h4: valid_sel = valid[4]; - 5'h5: valid_sel = valid[5]; - 5'h6: valid_sel = valid[6]; - 5'h7: valid_sel = valid[7]; - 5'h8: valid_sel = valid[8]; - 5'h9: valid_sel = valid[9]; - 5'ha: valid_sel = valid[10]; - 5'hb: valid_sel = valid[11]; - 5'hc: valid_sel = valid[12]; - 5'hd: valid_sel = valid[13]; - 5'he: valid_sel = valid[14]; - 5'hf: valid_sel = valid[15]; - 5'h10: valid_sel = valid[16]; - 5'h11: valid_sel = valid[17]; - 5'h12: valid_sel = valid[18]; - 5'h13: valid_sel = valid[19]; - 5'h14: valid_sel = valid[20]; - 5'h15: valid_sel = valid[21]; - 5'h16: valid_sel = valid[22]; - 5'h17: valid_sel = valid[23]; - 5'h18: valid_sel = valid[24]; - 5'h19: valid_sel = valid[25]; - 5'h1a: valid_sel = valid[26]; - 5'h1b: valid_sel = valid[27]; - 5'h1c: valid_sel = valid[28]; - 5'h1d: valid_sel = valid[29]; - 5'h1e: valid_sel = valid[30]; - endcase - -always @(ch_sel or ndr_r) - case(ch_sel) // synopsys parallel_case full_case - 5'h0: ndr = ndr_r[0]; - 5'h1: ndr = ndr_r[1]; - 5'h2: ndr = ndr_r[2]; - 5'h3: ndr = ndr_r[3]; - 5'h4: ndr = ndr_r[4]; - 5'h5: ndr = ndr_r[5]; - 5'h6: ndr = ndr_r[6]; - 5'h7: ndr = ndr_r[7]; - 5'h8: ndr = ndr_r[8]; - 5'h9: ndr = ndr_r[9]; - 5'ha: ndr = ndr_r[10]; - 5'hb: ndr = ndr_r[11]; - 5'hc: ndr = ndr_r[12]; - 5'hd: ndr = ndr_r[13]; - 5'he: ndr = ndr_r[14]; - 5'hf: ndr = ndr_r[15]; - 5'h10: ndr = ndr_r[16]; - 5'h11: ndr = ndr_r[17]; - 5'h12: ndr = ndr_r[18]; - 5'h13: ndr = ndr_r[19]; - 5'h14: ndr = ndr_r[20]; - 5'h15: ndr = ndr_r[21]; - 5'h16: ndr = ndr_r[22]; - 5'h17: ndr = ndr_r[23]; - 5'h18: ndr = ndr_r[24]; - 5'h19: ndr = ndr_r[25]; - 5'h1a: ndr = ndr_r[26]; - 5'h1b: ndr = ndr_r[27]; - 5'h1c: ndr = ndr_r[28]; - 5'h1d: ndr = ndr_r[29]; - 5'h1e: ndr = ndr_r[30]; - endcase - -always @(ch_sel or pointer0 or pointer1 or pointer2 or pointer3 or pointer4 - or pointer5 or pointer6 or pointer7 or pointer8 or pointer9 - or pointer10 or pointer11 or pointer12 or pointer13 or pointer14 - or pointer15 or pointer16 or pointer17 or pointer18 or pointer19 - or pointer20 or pointer21 or pointer22 or pointer23 or pointer24 - or pointer25 or pointer26 or pointer27 or pointer28 or pointer29 - or pointer30 ) - case(ch_sel) // synopsys parallel_case full_case - 5'h0: pointer = pointer0; - 5'h1: pointer = pointer1; - 5'h2: pointer = pointer2; - 5'h3: pointer = pointer3; - 5'h4: pointer = pointer4; - 5'h5: pointer = pointer5; - 5'h6: pointer = pointer6; - 5'h7: pointer = pointer7; - 5'h8: pointer = pointer8; - 5'h9: pointer = pointer9; - 5'ha: pointer = pointer10; - 5'hb: pointer = pointer11; - 5'hc: pointer = pointer12; - 5'hd: pointer = pointer13; - 5'he: pointer = pointer14; - 5'hf: pointer = pointer15; - 5'h10: pointer = pointer16; - 5'h11: pointer = pointer17; - 5'h12: pointer = pointer18; - 5'h13: pointer = pointer19; - 5'h14: pointer = pointer20; - 5'h15: pointer = pointer21; - 5'h16: pointer = pointer22; - 5'h17: pointer = pointer23; - 5'h18: pointer = pointer24; - 5'h19: pointer = pointer25; - 5'h1a: pointer = pointer26; - 5'h1b: pointer = pointer27; - 5'h1c: pointer = pointer28; - 5'h1d: pointer = pointer29; - 5'h1e: pointer = pointer30; - endcase - -always @(ch_sel or pointer0_s or pointer1_s or pointer2_s or pointer3_s or pointer4_s - or pointer5_s or pointer6_s or pointer7_s or pointer8_s or pointer9_s - or pointer10_s or pointer11_s or pointer12_s or pointer13_s or pointer14_s - or pointer15_s or pointer16_s or pointer17_s or pointer18_s or pointer19_s - or pointer20_s or pointer21_s or pointer22_s or pointer23_s or pointer24_s - or pointer25_s or pointer26_s or pointer27_s or pointer28_s or pointer29_s - or pointer30_s ) - case(ch_sel) // synopsys parallel_case full_case - 5'h0: pointer_s = pointer0_s; - 5'h1: pointer_s = pointer1_s; - 5'h2: pointer_s = pointer2_s; - 5'h3: pointer_s = pointer3_s; - 5'h4: pointer_s = pointer4_s; - 5'h5: pointer_s = pointer5_s; - 5'h6: pointer_s = pointer6_s; - 5'h7: pointer_s = pointer7_s; - 5'h8: pointer_s = pointer8_s; - 5'h9: pointer_s = pointer9_s; - 5'ha: pointer_s = pointer10_s; - 5'hb: pointer_s = pointer11_s; - 5'hc: pointer_s = pointer12_s; - 5'hd: pointer_s = pointer13_s; - 5'he: pointer_s = pointer14_s; - 5'hf: pointer_s = pointer15_s; - 5'h10: pointer_s = pointer16_s; - 5'h11: pointer_s = pointer17_s; - 5'h12: pointer_s = pointer18_s; - 5'h13: pointer_s = pointer19_s; - 5'h14: pointer_s = pointer20_s; - 5'h15: pointer_s = pointer21_s; - 5'h16: pointer_s = pointer22_s; - 5'h17: pointer_s = pointer23_s; - 5'h18: pointer_s = pointer24_s; - 5'h19: pointer_s = pointer25_s; - 5'h1a: pointer_s = pointer26_s; - 5'h1b: pointer_s = pointer27_s; - 5'h1c: pointer_s = pointer28_s; - 5'h1d: pointer_s = pointer29_s; - 5'h1e: pointer_s = pointer30_s; - endcase - -always @(ch_sel or ch0_csr or ch1_csr or ch2_csr or ch3_csr or ch4_csr - or ch5_csr or ch6_csr or ch7_csr or ch8_csr or ch9_csr - or ch10_csr or ch11_csr or ch12_csr or ch13_csr or ch14_csr - or ch15_csr or ch16_csr or ch17_csr or ch18_csr or ch19_csr - or ch20_csr or ch21_csr or ch22_csr or ch23_csr or ch24_csr - or ch25_csr or ch26_csr or ch27_csr or ch28_csr or ch29_csr - or ch30_csr ) - case(ch_sel) // synopsys parallel_case full_case - 5'h0: csr = ch0_csr; - 5'h1: csr = ch1_csr; - 5'h2: csr = ch2_csr; - 5'h3: csr = ch3_csr; - 5'h4: csr = ch4_csr; - 5'h5: csr = ch5_csr; - 5'h6: csr = ch6_csr; - 5'h7: csr = ch7_csr; - 5'h8: csr = ch8_csr; - 5'h9: csr = ch9_csr; - 5'ha: csr = ch10_csr; - 5'hb: csr = ch11_csr; - 5'hc: csr = ch12_csr; - 5'hd: csr = ch13_csr; - 5'he: csr = ch14_csr; - 5'hf: csr = ch15_csr; - 5'h10: csr = ch16_csr; - 5'h11: csr = ch17_csr; - 5'h12: csr = ch18_csr; - 5'h13: csr = ch19_csr; - 5'h14: csr = ch20_csr; - 5'h15: csr = ch21_csr; - 5'h16: csr = ch22_csr; - 5'h17: csr = ch23_csr; - 5'h18: csr = ch24_csr; - 5'h19: csr = ch25_csr; - 5'h1a: csr = ch26_csr; - 5'h1b: csr = ch27_csr; - 5'h1c: csr = ch28_csr; - 5'h1d: csr = ch29_csr; - 5'h1e: csr = ch30_csr; - endcase - -always @(ch_sel or ch0_txsz or ch1_txsz or ch2_txsz or ch3_txsz or ch4_txsz - or ch5_txsz or ch6_txsz or ch7_txsz or ch8_txsz or ch9_txsz - or ch10_txsz or ch11_txsz or ch12_txsz or ch13_txsz or ch14_txsz - or ch15_txsz or ch16_txsz or ch17_txsz or ch18_txsz or ch19_txsz - or ch20_txsz or ch21_txsz or ch22_txsz or ch23_txsz or ch24_txsz - or ch25_txsz or ch26_txsz or ch27_txsz or ch28_txsz or ch29_txsz - or ch30_txsz ) - case(ch_sel) // synopsys parallel_case full_case - 5'h0: txsz = ch0_txsz; - 5'h1: txsz = ch1_txsz; - 5'h2: txsz = ch2_txsz; - 5'h3: txsz = ch3_txsz; - 5'h4: txsz = ch4_txsz; - 5'h5: txsz = ch5_txsz; - 5'h6: txsz = ch6_txsz; - 5'h7: txsz = ch7_txsz; - 5'h8: txsz = ch8_txsz; - 5'h9: txsz = ch9_txsz; - 5'ha: txsz = ch10_txsz; - 5'hb: txsz = ch11_txsz; - 5'hc: txsz = ch12_txsz; - 5'hd: txsz = ch13_txsz; - 5'he: txsz = ch14_txsz; - 5'hf: txsz = ch15_txsz; - 5'h10: txsz = ch16_txsz; - 5'h11: txsz = ch17_txsz; - 5'h12: txsz = ch18_txsz; - 5'h13: txsz = ch19_txsz; - 5'h14: txsz = ch20_txsz; - 5'h15: txsz = ch21_txsz; - 5'h16: txsz = ch22_txsz; - 5'h17: txsz = ch23_txsz; - 5'h18: txsz = ch24_txsz; - 5'h19: txsz = ch25_txsz; - 5'h1a: txsz = ch26_txsz; - 5'h1b: txsz = ch27_txsz; - 5'h1c: txsz = ch28_txsz; - 5'h1d: txsz = ch29_txsz; - 5'h1e: txsz = ch30_txsz; - endcase - -always @(ch_sel or ch0_adr0 or ch1_adr0 or ch2_adr0 or ch3_adr0 or ch4_adr0 - or ch5_adr0 or ch6_adr0 or ch7_adr0 or ch8_adr0 or ch9_adr0 - or ch10_adr0 or ch11_adr0 or ch12_adr0 or ch13_adr0 or ch14_adr0 - or ch15_adr0 or ch16_adr0 or ch17_adr0 or ch18_adr0 or ch19_adr0 - or ch20_adr0 or ch21_adr0 or ch22_adr0 or ch23_adr0 or ch24_adr0 - or ch25_adr0 or ch26_adr0 or ch27_adr0 or ch28_adr0 or ch29_adr0 - or ch30_adr0 ) - case(ch_sel) // synopsys parallel_case full_case - 5'h0: adr0 = ch0_adr0; - 5'h1: adr0 = ch1_adr0; - 5'h2: adr0 = ch2_adr0; - 5'h3: adr0 = ch3_adr0; - 5'h4: adr0 = ch4_adr0; - 5'h5: adr0 = ch5_adr0; - 5'h6: adr0 = ch6_adr0; - 5'h7: adr0 = ch7_adr0; - 5'h8: adr0 = ch8_adr0; - 5'h9: adr0 = ch9_adr0; - 5'ha: adr0 = ch10_adr0; - 5'hb: adr0 = ch11_adr0; - 5'hc: adr0 = ch12_adr0; - 5'hd: adr0 = ch13_adr0; - 5'he: adr0 = ch14_adr0; - 5'hf: adr0 = ch15_adr0; - 5'h10: adr0 = ch16_adr0; - 5'h11: adr0 = ch17_adr0; - 5'h12: adr0 = ch18_adr0; - 5'h13: adr0 = ch19_adr0; - 5'h14: adr0 = ch20_adr0; - 5'h15: adr0 = ch21_adr0; - 5'h16: adr0 = ch22_adr0; - 5'h17: adr0 = ch23_adr0; - 5'h18: adr0 = ch24_adr0; - 5'h19: adr0 = ch25_adr0; - 5'h1a: adr0 = ch26_adr0; - 5'h1b: adr0 = ch27_adr0; - 5'h1c: adr0 = ch28_adr0; - 5'h1d: adr0 = ch29_adr0; - 5'h1e: adr0 = ch30_adr0; - endcase - -always @(ch_sel or ch0_adr1 or ch1_adr1 or ch2_adr1 or ch3_adr1 or ch4_adr1 - or ch5_adr1 or ch6_adr1 or ch7_adr1 or ch8_adr1 or ch9_adr1 - or ch10_adr1 or ch11_adr1 or ch12_adr1 or ch13_adr1 or ch14_adr1 - or ch15_adr1 or ch16_adr1 or ch17_adr1 or ch18_adr1 or ch19_adr1 - or ch20_adr1 or ch21_adr1 or ch22_adr1 or ch23_adr1 or ch24_adr1 - or ch25_adr1 or ch26_adr1 or ch27_adr1 or ch28_adr1 or ch29_adr1 - or ch30_adr1 ) - case(ch_sel) // synopsys parallel_case full_case - 5'h0: adr1 = ch0_adr1; - 5'h1: adr1 = ch1_adr1; - 5'h2: adr1 = ch2_adr1; - 5'h3: adr1 = ch3_adr1; - 5'h4: adr1 = ch4_adr1; - 5'h5: adr1 = ch5_adr1; - 5'h6: adr1 = ch6_adr1; - 5'h7: adr1 = ch7_adr1; - 5'h8: adr1 = ch8_adr1; - 5'h9: adr1 = ch9_adr1; - 5'ha: adr1 = ch10_adr1; - 5'hb: adr1 = ch11_adr1; - 5'hc: adr1 = ch12_adr1; - 5'hd: adr1 = ch13_adr1; - 5'he: adr1 = ch14_adr1; - 5'hf: adr1 = ch15_adr1; - 5'h10: adr1 = ch16_adr1; - 5'h11: adr1 = ch17_adr1; - 5'h12: adr1 = ch18_adr1; - 5'h13: adr1 = ch19_adr1; - 5'h14: adr1 = ch20_adr1; - 5'h15: adr1 = ch21_adr1; - 5'h16: adr1 = ch22_adr1; - 5'h17: adr1 = ch23_adr1; - 5'h18: adr1 = ch24_adr1; - 5'h19: adr1 = ch25_adr1; - 5'h1a: adr1 = ch26_adr1; - 5'h1b: adr1 = ch27_adr1; - 5'h1c: adr1 = ch28_adr1; - 5'h1d: adr1 = ch29_adr1; - 5'h1e: adr1 = ch30_adr1; - endcase - -always @(ch_sel or ch0_am0 or ch1_am0 or ch2_am0 or ch3_am0 or ch4_am0 - or ch5_am0 or ch6_am0 or ch7_am0 or ch8_am0 or ch9_am0 - or ch10_am0 or ch11_am0 or ch12_am0 or ch13_am0 or ch14_am0 - or ch15_am0 or ch16_am0 or ch17_am0 or ch18_am0 or ch19_am0 - or ch20_am0 or ch21_am0 or ch22_am0 or ch23_am0 or ch24_am0 - or ch25_am0 or ch26_am0 or ch27_am0 or ch28_am0 or ch29_am0 - or ch30_am0 ) - case(ch_sel) // synopsys parallel_case full_case - 5'h0: am0 = ch0_am0; - 5'h1: am0 = ch1_am0; - 5'h2: am0 = ch2_am0; - 5'h3: am0 = ch3_am0; - 5'h4: am0 = ch4_am0; - 5'h5: am0 = ch5_am0; - 5'h6: am0 = ch6_am0; - 5'h7: am0 = ch7_am0; - 5'h8: am0 = ch8_am0; - 5'h9: am0 = ch9_am0; - 5'ha: am0 = ch10_am0; - 5'hb: am0 = ch11_am0; - 5'hc: am0 = ch12_am0; - 5'hd: am0 = ch13_am0; - 5'he: am0 = ch14_am0; - 5'hf: am0 = ch15_am0; - 5'h10: am0 = ch16_am0; - 5'h11: am0 = ch17_am0; - 5'h12: am0 = ch18_am0; - 5'h13: am0 = ch19_am0; - 5'h14: am0 = ch20_am0; - 5'h15: am0 = ch21_am0; - 5'h16: am0 = ch22_am0; - 5'h17: am0 = ch23_am0; - 5'h18: am0 = ch24_am0; - 5'h19: am0 = ch25_am0; - 5'h1a: am0 = ch26_am0; - 5'h1b: am0 = ch27_am0; - 5'h1c: am0 = ch28_am0; - 5'h1d: am0 = ch29_am0; - 5'h1e: am0 = ch30_am0; - endcase - -always @(ch_sel or ch0_am1 or ch1_am1 or ch2_am1 or ch3_am1 or ch4_am1 - or ch5_am1 or ch6_am1 or ch7_am1 or ch8_am1 or ch9_am1 - or ch10_am1 or ch11_am1 or ch12_am1 or ch13_am1 or ch14_am1 - or ch15_am1 or ch16_am1 or ch17_am1 or ch18_am1 or ch19_am1 - or ch20_am1 or ch21_am1 or ch22_am1 or ch23_am1 or ch24_am1 - or ch25_am1 or ch26_am1 or ch27_am1 or ch28_am1 or ch29_am1 - or ch30_am1 ) - case(ch_sel) // synopsys parallel_case full_case - 5'h0: am1 = ch0_am1; - 5'h1: am1 = ch1_am1; - 5'h2: am1 = ch2_am1; - 5'h3: am1 = ch3_am1; - 5'h4: am1 = ch4_am1; - 5'h5: am1 = ch5_am1; - 5'h6: am1 = ch6_am1; - 5'h7: am1 = ch7_am1; - 5'h8: am1 = ch8_am1; - 5'h9: am1 = ch9_am1; - 5'ha: am1 = ch10_am1; - 5'hb: am1 = ch11_am1; - 5'hc: am1 = ch12_am1; - 5'hd: am1 = ch13_am1; - 5'he: am1 = ch14_am1; - 5'hf: am1 = ch15_am1; - 5'h10: am1 = ch16_am1; - 5'h11: am1 = ch17_am1; - 5'h12: am1 = ch18_am1; - 5'h13: am1 = ch19_am1; - 5'h14: am1 = ch20_am1; - 5'h15: am1 = ch21_am1; - 5'h16: am1 = ch22_am1; - 5'h17: am1 = ch23_am1; - 5'h18: am1 = ch24_am1; - 5'h19: am1 = ch25_am1; - 5'h1a: am1 = ch26_am1; - 5'h1b: am1 = ch27_am1; - 5'h1c: am1 = ch28_am1; - 5'h1d: am1 = ch29_am1; - 5'h1e: am1 = ch30_am1; - endcase - -//////////////////////////////////////////////////////////////////// -// -// Actual Chanel Arbiter and Priority Encoder -// - -// Select the arbiter for current highest priority -always @(pri_out or gnt_p0 or gnt_p1 or gnt_p2 or gnt_p3 or gnt_p4 - or gnt_p5 or gnt_p6 or gnt_p7 ) - case(pri_out) // synopsys parallel_case full_case - 3'h0: ch_sel_d = gnt_p0; - 3'h1: ch_sel_d = gnt_p1; - 3'h2: ch_sel_d = gnt_p2; - 3'h3: ch_sel_d = gnt_p3; - 3'h4: ch_sel_d = gnt_p4; - 3'h5: ch_sel_d = gnt_p5; - 3'h6: ch_sel_d = gnt_p6; - 3'h7: ch_sel_d = gnt_p7; - endcase - - -// Priority Encoder -wb_dma_ch_pri_enc - #( pri_sel, - ch0_conf, - ch1_conf, - ch2_conf, - ch3_conf, - ch4_conf, - ch5_conf, - ch6_conf, - ch7_conf, - ch8_conf, - ch9_conf, - ch10_conf, - ch11_conf, - ch12_conf, - ch13_conf, - ch14_conf, - ch15_conf, - ch16_conf, - ch17_conf, - ch18_conf, - ch19_conf, - ch20_conf, - ch21_conf, - ch22_conf, - ch23_conf, - ch24_conf, - ch25_conf, - ch26_conf, - ch27_conf, - ch28_conf, - ch29_conf, - ch30_conf) - u0( - .clk( clk ), - .valid( valid ), - .pri0( pri0 ), - .pri1( pri1 ), - .pri2( pri2 ), - .pri3( pri3 ), - .pri4( pri4 ), - .pri5( pri5 ), - .pri6( pri6 ), - .pri7( pri7 ), - .pri8( pri8 ), - .pri9( pri9 ), - .pri10( pri10 ), - .pri11( pri11 ), - .pri12( pri12 ), - .pri13( pri13 ), - .pri14( pri14 ), - .pri15( pri15 ), - .pri16( pri16 ), - .pri17( pri17 ), - .pri18( pri18 ), - .pri19( pri19 ), - .pri20( pri20 ), - .pri21( pri21 ), - .pri22( pri22 ), - .pri23( pri23 ), - .pri24( pri24 ), - .pri25( pri25 ), - .pri26( pri26 ), - .pri27( pri27 ), - .pri28( pri28 ), - .pri29( pri29 ), - .pri30( pri30 ), - .pri_out( pri_out ) - ); - -// Arbiter request lines -// Generate request depending on priority and valid bits - -assign req_p0[0] = valid[0] & (pri0==3'h0); -assign req_p0[1] = valid[1] & (pri1==3'h0); -assign req_p0[2] = valid[2] & (pri2==3'h0); -assign req_p0[3] = valid[3] & (pri3==3'h0); -assign req_p0[4] = valid[4] & (pri4==3'h0); -assign req_p0[5] = valid[5] & (pri5==3'h0); -assign req_p0[6] = valid[6] & (pri6==3'h0); -assign req_p0[7] = valid[7] & (pri7==3'h0); -assign req_p0[8] = valid[8] & (pri8==3'h0); -assign req_p0[9] = valid[9] & (pri9==3'h0); -assign req_p0[10] = valid[10] & (pri10==3'h0); -assign req_p0[11] = valid[11] & (pri11==3'h0); -assign req_p0[12] = valid[12] & (pri12==3'h0); -assign req_p0[13] = valid[13] & (pri13==3'h0); -assign req_p0[14] = valid[14] & (pri14==3'h0); -assign req_p0[15] = valid[15] & (pri15==3'h0); -assign req_p0[16] = valid[16] & (pri16==3'h0); -assign req_p0[17] = valid[17] & (pri17==3'h0); -assign req_p0[18] = valid[18] & (pri18==3'h0); -assign req_p0[19] = valid[19] & (pri19==3'h0); -assign req_p0[20] = valid[20] & (pri20==3'h0); -assign req_p0[21] = valid[21] & (pri21==3'h0); -assign req_p0[22] = valid[22] & (pri22==3'h0); -assign req_p0[23] = valid[23] & (pri23==3'h0); -assign req_p0[24] = valid[24] & (pri24==3'h0); -assign req_p0[25] = valid[25] & (pri25==3'h0); -assign req_p0[26] = valid[26] & (pri26==3'h0); -assign req_p0[27] = valid[27] & (pri27==3'h0); -assign req_p0[28] = valid[28] & (pri28==3'h0); -assign req_p0[29] = valid[29] & (pri29==3'h0); -assign req_p0[30] = valid[30] & (pri30==3'h0); - -assign req_p1[0] = valid[0] & (pri0==3'h1); -assign req_p1[1] = valid[1] & (pri1==3'h1); -assign req_p1[2] = valid[2] & (pri2==3'h1); -assign req_p1[3] = valid[3] & (pri3==3'h1); -assign req_p1[4] = valid[4] & (pri4==3'h1); -assign req_p1[5] = valid[5] & (pri5==3'h1); -assign req_p1[6] = valid[6] & (pri6==3'h1); -assign req_p1[7] = valid[7] & (pri7==3'h1); -assign req_p1[8] = valid[8] & (pri8==3'h1); -assign req_p1[9] = valid[9] & (pri9==3'h1); -assign req_p1[10] = valid[10] & (pri10==3'h1); -assign req_p1[11] = valid[11] & (pri11==3'h1); -assign req_p1[12] = valid[12] & (pri12==3'h1); -assign req_p1[13] = valid[13] & (pri13==3'h1); -assign req_p1[14] = valid[14] & (pri14==3'h1); -assign req_p1[15] = valid[15] & (pri15==3'h1); -assign req_p1[16] = valid[16] & (pri16==3'h1); -assign req_p1[17] = valid[17] & (pri17==3'h1); -assign req_p1[18] = valid[18] & (pri18==3'h1); -assign req_p1[19] = valid[19] & (pri19==3'h1); -assign req_p1[20] = valid[20] & (pri20==3'h1); -assign req_p1[21] = valid[21] & (pri21==3'h1); -assign req_p1[22] = valid[22] & (pri22==3'h1); -assign req_p1[23] = valid[23] & (pri23==3'h1); -assign req_p1[24] = valid[24] & (pri24==3'h1); -assign req_p1[25] = valid[25] & (pri25==3'h1); -assign req_p1[26] = valid[26] & (pri26==3'h1); -assign req_p1[27] = valid[27] & (pri27==3'h1); -assign req_p1[28] = valid[28] & (pri28==3'h1); -assign req_p1[29] = valid[29] & (pri29==3'h1); -assign req_p1[30] = valid[30] & (pri30==3'h1); - -assign req_p2[0] = valid[0] & (pri0==3'h2); -assign req_p2[1] = valid[1] & (pri1==3'h2); -assign req_p2[2] = valid[2] & (pri2==3'h2); -assign req_p2[3] = valid[3] & (pri3==3'h2); -assign req_p2[4] = valid[4] & (pri4==3'h2); -assign req_p2[5] = valid[5] & (pri5==3'h2); -assign req_p2[6] = valid[6] & (pri6==3'h2); -assign req_p2[7] = valid[7] & (pri7==3'h2); -assign req_p2[8] = valid[8] & (pri8==3'h2); -assign req_p2[9] = valid[9] & (pri9==3'h2); -assign req_p2[10] = valid[10] & (pri10==3'h2); -assign req_p2[11] = valid[11] & (pri11==3'h2); -assign req_p2[12] = valid[12] & (pri12==3'h2); -assign req_p2[13] = valid[13] & (pri13==3'h2); -assign req_p2[14] = valid[14] & (pri14==3'h2); -assign req_p2[15] = valid[15] & (pri15==3'h2); -assign req_p2[16] = valid[16] & (pri16==3'h2); -assign req_p2[17] = valid[17] & (pri17==3'h2); -assign req_p2[18] = valid[18] & (pri18==3'h2); -assign req_p2[19] = valid[19] & (pri19==3'h2); -assign req_p2[20] = valid[20] & (pri20==3'h2); -assign req_p2[21] = valid[21] & (pri21==3'h2); -assign req_p2[22] = valid[22] & (pri22==3'h2); -assign req_p2[23] = valid[23] & (pri23==3'h2); -assign req_p2[24] = valid[24] & (pri24==3'h2); -assign req_p2[25] = valid[25] & (pri25==3'h2); -assign req_p2[26] = valid[26] & (pri26==3'h2); -assign req_p2[27] = valid[27] & (pri27==3'h2); -assign req_p2[28] = valid[28] & (pri28==3'h2); -assign req_p2[29] = valid[29] & (pri29==3'h2); -assign req_p2[30] = valid[30] & (pri30==3'h2); - -assign req_p3[0] = valid[0] & (pri0==3'h3); -assign req_p3[1] = valid[1] & (pri1==3'h3); -assign req_p3[2] = valid[2] & (pri2==3'h3); -assign req_p3[3] = valid[3] & (pri3==3'h3); -assign req_p3[4] = valid[4] & (pri4==3'h3); -assign req_p3[5] = valid[5] & (pri5==3'h3); -assign req_p3[6] = valid[6] & (pri6==3'h3); -assign req_p3[7] = valid[7] & (pri7==3'h3); -assign req_p3[8] = valid[8] & (pri8==3'h3); -assign req_p3[9] = valid[9] & (pri9==3'h3); -assign req_p3[10] = valid[10] & (pri10==3'h3); -assign req_p3[11] = valid[11] & (pri11==3'h3); -assign req_p3[12] = valid[12] & (pri12==3'h3); -assign req_p3[13] = valid[13] & (pri13==3'h3); -assign req_p3[14] = valid[14] & (pri14==3'h3); -assign req_p3[15] = valid[15] & (pri15==3'h3); -assign req_p3[16] = valid[16] & (pri16==3'h3); -assign req_p3[17] = valid[17] & (pri17==3'h3); -assign req_p3[18] = valid[18] & (pri18==3'h3); -assign req_p3[19] = valid[19] & (pri19==3'h3); -assign req_p3[20] = valid[20] & (pri20==3'h3); -assign req_p3[21] = valid[21] & (pri21==3'h3); -assign req_p3[22] = valid[22] & (pri22==3'h3); -assign req_p3[23] = valid[23] & (pri23==3'h3); -assign req_p3[24] = valid[24] & (pri24==3'h3); -assign req_p3[25] = valid[25] & (pri25==3'h3); -assign req_p3[26] = valid[26] & (pri26==3'h3); -assign req_p3[27] = valid[27] & (pri27==3'h3); -assign req_p3[28] = valid[28] & (pri28==3'h3); -assign req_p3[29] = valid[29] & (pri29==3'h3); -assign req_p3[30] = valid[30] & (pri30==3'h3); - -assign req_p4[0] = valid[0] & (pri0==3'h4); -assign req_p4[1] = valid[1] & (pri1==3'h4); -assign req_p4[2] = valid[2] & (pri2==3'h4); -assign req_p4[3] = valid[3] & (pri3==3'h4); -assign req_p4[4] = valid[4] & (pri4==3'h4); -assign req_p4[5] = valid[5] & (pri5==3'h4); -assign req_p4[6] = valid[6] & (pri6==3'h4); -assign req_p4[7] = valid[7] & (pri7==3'h4); -assign req_p4[8] = valid[8] & (pri8==3'h4); -assign req_p4[9] = valid[9] & (pri9==3'h4); -assign req_p4[10] = valid[10] & (pri10==3'h4); -assign req_p4[11] = valid[11] & (pri11==3'h4); -assign req_p4[12] = valid[12] & (pri12==3'h4); -assign req_p4[13] = valid[13] & (pri13==3'h4); -assign req_p4[14] = valid[14] & (pri14==3'h4); -assign req_p4[15] = valid[15] & (pri15==3'h4); -assign req_p4[16] = valid[16] & (pri16==3'h4); -assign req_p4[17] = valid[17] & (pri17==3'h4); -assign req_p4[18] = valid[18] & (pri18==3'h4); -assign req_p4[19] = valid[19] & (pri19==3'h4); -assign req_p4[20] = valid[20] & (pri20==3'h4); -assign req_p4[21] = valid[21] & (pri21==3'h4); -assign req_p4[22] = valid[22] & (pri22==3'h4); -assign req_p4[23] = valid[23] & (pri23==3'h4); -assign req_p4[24] = valid[24] & (pri24==3'h4); -assign req_p4[25] = valid[25] & (pri25==3'h4); -assign req_p4[26] = valid[26] & (pri26==3'h4); -assign req_p4[27] = valid[27] & (pri27==3'h4); -assign req_p4[28] = valid[28] & (pri28==3'h4); -assign req_p4[29] = valid[29] & (pri29==3'h4); -assign req_p4[30] = valid[30] & (pri30==3'h4); - -assign req_p5[0] = valid[0] & (pri0==3'h5); -assign req_p5[1] = valid[1] & (pri1==3'h5); -assign req_p5[2] = valid[2] & (pri2==3'h5); -assign req_p5[3] = valid[3] & (pri3==3'h5); -assign req_p5[4] = valid[4] & (pri4==3'h5); -assign req_p5[5] = valid[5] & (pri5==3'h5); -assign req_p5[6] = valid[6] & (pri6==3'h5); -assign req_p5[7] = valid[7] & (pri7==3'h5); -assign req_p5[8] = valid[8] & (pri8==3'h5); -assign req_p5[9] = valid[9] & (pri9==3'h5); -assign req_p5[10] = valid[10] & (pri10==3'h5); -assign req_p5[11] = valid[11] & (pri11==3'h5); -assign req_p5[12] = valid[12] & (pri12==3'h5); -assign req_p5[13] = valid[13] & (pri13==3'h5); -assign req_p5[14] = valid[14] & (pri14==3'h5); -assign req_p5[15] = valid[15] & (pri15==3'h5); -assign req_p5[16] = valid[16] & (pri16==3'h5); -assign req_p5[17] = valid[17] & (pri17==3'h5); -assign req_p5[18] = valid[18] & (pri18==3'h5); -assign req_p5[19] = valid[19] & (pri19==3'h5); -assign req_p5[20] = valid[20] & (pri20==3'h5); -assign req_p5[21] = valid[21] & (pri21==3'h5); -assign req_p5[22] = valid[22] & (pri22==3'h5); -assign req_p5[23] = valid[23] & (pri23==3'h5); -assign req_p5[24] = valid[24] & (pri24==3'h5); -assign req_p5[25] = valid[25] & (pri25==3'h5); -assign req_p5[26] = valid[26] & (pri26==3'h5); -assign req_p5[27] = valid[27] & (pri27==3'h5); -assign req_p5[28] = valid[28] & (pri28==3'h5); -assign req_p5[29] = valid[29] & (pri29==3'h5); -assign req_p5[30] = valid[30] & (pri30==3'h5); - -assign req_p6[0] = valid[0] & (pri0==3'h6); -assign req_p6[1] = valid[1] & (pri1==3'h6); -assign req_p6[2] = valid[2] & (pri2==3'h6); -assign req_p6[3] = valid[3] & (pri3==3'h6); -assign req_p6[4] = valid[4] & (pri4==3'h6); -assign req_p6[5] = valid[5] & (pri5==3'h6); -assign req_p6[6] = valid[6] & (pri6==3'h6); -assign req_p6[7] = valid[7] & (pri7==3'h6); -assign req_p6[8] = valid[8] & (pri8==3'h6); -assign req_p6[9] = valid[9] & (pri9==3'h6); -assign req_p6[10] = valid[10] & (pri10==3'h6); -assign req_p6[11] = valid[11] & (pri11==3'h6); -assign req_p6[12] = valid[12] & (pri12==3'h6); -assign req_p6[13] = valid[13] & (pri13==3'h6); -assign req_p6[14] = valid[14] & (pri14==3'h6); -assign req_p6[15] = valid[15] & (pri15==3'h6); -assign req_p6[16] = valid[16] & (pri16==3'h6); -assign req_p6[17] = valid[17] & (pri17==3'h6); -assign req_p6[18] = valid[18] & (pri18==3'h6); -assign req_p6[19] = valid[19] & (pri19==3'h6); -assign req_p6[20] = valid[20] & (pri20==3'h6); -assign req_p6[21] = valid[21] & (pri21==3'h6); -assign req_p6[22] = valid[22] & (pri22==3'h6); -assign req_p6[23] = valid[23] & (pri23==3'h6); -assign req_p6[24] = valid[24] & (pri24==3'h6); -assign req_p6[25] = valid[25] & (pri25==3'h6); -assign req_p6[26] = valid[26] & (pri26==3'h6); -assign req_p6[27] = valid[27] & (pri27==3'h6); -assign req_p6[28] = valid[28] & (pri28==3'h6); -assign req_p6[29] = valid[29] & (pri29==3'h6); -assign req_p6[30] = valid[30] & (pri30==3'h6); - -assign req_p7[0] = valid[0] & (pri0==3'h7); -assign req_p7[1] = valid[1] & (pri1==3'h7); -assign req_p7[2] = valid[2] & (pri2==3'h7); -assign req_p7[3] = valid[3] & (pri3==3'h7); -assign req_p7[4] = valid[4] & (pri4==3'h7); -assign req_p7[5] = valid[5] & (pri5==3'h7); -assign req_p7[6] = valid[6] & (pri6==3'h7); -assign req_p7[7] = valid[7] & (pri7==3'h7); -assign req_p7[8] = valid[8] & (pri8==3'h7); -assign req_p7[9] = valid[9] & (pri9==3'h7); -assign req_p7[10] = valid[10] & (pri10==3'h7); -assign req_p7[11] = valid[11] & (pri11==3'h7); -assign req_p7[12] = valid[12] & (pri12==3'h7); -assign req_p7[13] = valid[13] & (pri13==3'h7); -assign req_p7[14] = valid[14] & (pri14==3'h7); -assign req_p7[15] = valid[15] & (pri15==3'h7); -assign req_p7[16] = valid[16] & (pri16==3'h7); -assign req_p7[17] = valid[17] & (pri17==3'h7); -assign req_p7[18] = valid[18] & (pri18==3'h7); -assign req_p7[19] = valid[19] & (pri19==3'h7); -assign req_p7[20] = valid[20] & (pri20==3'h7); -assign req_p7[21] = valid[21] & (pri21==3'h7); -assign req_p7[22] = valid[22] & (pri22==3'h7); -assign req_p7[23] = valid[23] & (pri23==3'h7); -assign req_p7[24] = valid[24] & (pri24==3'h7); -assign req_p7[25] = valid[25] & (pri25==3'h7); -assign req_p7[26] = valid[26] & (pri26==3'h7); -assign req_p7[27] = valid[27] & (pri27==3'h7); -assign req_p7[28] = valid[28] & (pri28==3'h7); -assign req_p7[29] = valid[29] & (pri29==3'h7); -assign req_p7[30] = valid[30] & (pri30==3'h7); - -// RR Arbiter for priority 0 -wb_dma_ch_arb u1( - .clk( clk ), - .rst( rst ), - .req( req_p0 ), - .gnt( gnt_p0_d ), - .advance( next_ch ) - ); -// RR Arbiter for priority 1 -wb_dma_ch_arb u2( - .clk( clk ), - .rst( rst ), - .req( req_p1 ), - .gnt( gnt_p1_d ), - .advance( next_ch ) - ); - -// RR Arbiter for priority 2 -wb_dma_ch_arb u3( - .clk( clk ), - .rst( rst ), - .req( req_p2 ), - .gnt( gnt_p2_d ), - .advance( next_ch ) - ); -// RR Arbiter for priority 3 -wb_dma_ch_arb u4( - .clk( clk ), - .rst( rst ), - .req( req_p3 ), - .gnt( gnt_p3_d ), - .advance( next_ch ) - ); -// RR Arbiter for priority 4 -wb_dma_ch_arb u5( - .clk( clk ), - .rst( rst ), - .req( req_p4 ), - .gnt( gnt_p4_d ), - .advance( next_ch ) - ); -// RR Arbiter for priority 5 -wb_dma_ch_arb u6( - .clk( clk ), - .rst( rst ), - .req( req_p5 ), - .gnt( gnt_p5_d ), - .advance( next_ch ) - ); -// RR Arbiter for priority 6 -wb_dma_ch_arb u7( - .clk( clk ), - .rst( rst ), - .req( req_p6 ), - .gnt( gnt_p6_d ), - .advance( next_ch ) - ); -// RR Arbiter for priority 7 -wb_dma_ch_arb u8( - .clk( clk ), - .rst( rst ), - .req( req_p7 ), - .gnt( gnt_p7_d ), - .advance( next_ch ) - ); - -// Select grant based on number of priorities -assign gnt_p0 = gnt_p0_d; -assign gnt_p1 = gnt_p1_d; -assign gnt_p2 = (pri_sel==2'd0) ? 5'h0 : gnt_p2_d; -assign gnt_p3 = (pri_sel==2'd0) ? 5'h0 : gnt_p3_d; -assign gnt_p4 = (pri_sel==2'd2) ? gnt_p4_d : 5'h0; -assign gnt_p5 = (pri_sel==2'd2) ? gnt_p5_d : 5'h0; -assign gnt_p6 = (pri_sel==2'd2) ? gnt_p6_d : 5'h0; -assign gnt_p7 = (pri_sel==2'd2) ? gnt_p7_d : 5'h0; - -endmodule Index: trunk/rtl/verilog/wb_dma_defines.v =================================================================== --- trunk/rtl/verilog/wb_dma_defines.v (revision 16) +++ trunk/rtl/verilog/wb_dma_defines.v (nonexistent) @@ -1,116 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// WISHBONE DMA Definitions //// -//// //// -//// //// -//// Author: Rudolf Usselmann //// -//// rudi@asics.ws //// -//// //// -//// //// -//// Downloaded from: http://www.opencores.org/cores/wb_dma/ //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000-2002 Rudolf Usselmann //// -//// www.asics.ws //// -//// rudi@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: wb_dma_defines.v,v 1.5 2002-02-01 01:54:45 rudi Exp $ -// -// $Date: 2002-02-01 01:54:45 $ -// $Revision: 1.5 $ -// $Author: rudi $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: not supported by cvs2svn $ -// Revision 1.4 2001/10/19 04:35:04 rudi -// -// - Made the core parameterized -// -// Revision 1.3 2001/09/07 15:34:38 rudi -// -// Changed reset to active high. -// -// Revision 1.2 2001/08/15 05:40:30 rudi -// -// - Changed IO names to be more clear. -// - Uniquifyed define names to be core specific. -// - Added Section 3.10, describing DMA restart. -// -// Revision 1.1 2001/07/29 08:57:02 rudi -// -// -// 1) Changed Directory Structure -// 2) Added restart signal (REST) -// -// Revision 1.2 2001/06/05 10:22:37 rudi -// -// -// - Added Support of up to 31 channels -// - Added support for 2,4 and 8 priority levels -// - Now can have up to 31 channels -// - Added many configuration items -// - Changed reset to async -// -// Revision 1.1.1.1 2001/03/19 13:11:09 rudi -// Initial Release -// -// -// - -`timescale 1ns / 10ps - -// This define selects how the slave interface determines if -// the internal register file or pass through mode are selected. -// This should be a simple address decoder. "wb_addr_i" is the -// WISHBONE address bus (32 bits wide). -// NOTE: The entire pass-through mode is implemented in combinatorial -// logic only. So the more address lines we look at and compare here -// the higher will be the initial delay when pass-through mode is selected. -// Here we look at the top 8 address bit. If they are all 1, the -// register file is selected. Use this with caution !!! -`define WDMA_REG_SEL (wb_addr_i[31:28] == rf_addr) - - -// DO NOT MODIFY BEYOND THIS POINT -// CSR Bits -`define WDMA_CH_EN 0 -`define WDMA_DST_SEL 1 -`define WDMA_SRC_SEL 2 -`define WDMA_INC_DST 3 -`define WDMA_INC_SRC 4 -`define WDMA_MODE 5 -`define WDMA_ARS 6 -`define WDMA_USE_ED 7 -`define WDMA_WRB 8 -`define WDMA_STOP 9 -`define WDMA_BUSY 10 -`define WDMA_DONE 11 -`define WDMA_ERR 12 -`define WDMA_ED_EOL 20 - Index: trunk/rtl/verilog/wb_dma_ch_arb.v =================================================================== --- trunk/rtl/verilog/wb_dma_ch_arb.v (revision 16) +++ trunk/rtl/verilog/wb_dma_ch_arb.v (nonexistent) @@ -1,2153 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// WISHBONE DMA Channel Arbiter //// -//// //// -//// //// -//// Author: Rudolf Usselmann //// -//// rudi@asics.ws //// -//// //// -//// //// -//// Downloaded from: http://www.opencores.org/cores/wb_dma/ //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000-2002 Rudolf Usselmann //// -//// www.asics.ws //// -//// rudi@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: wb_dma_ch_arb.v,v 1.2 2002-02-01 01:54:44 rudi Exp $ -// -// $Date: 2002-02-01 01:54:44 $ -// $Revision: 1.2 $ -// $Author: rudi $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: not supported by cvs2svn $ -// Revision 1.1 2001/07/29 08:57:02 rudi -// -// -// 1) Changed Directory Structure -// 2) Added restart signal (REST) -// -// Revision 1.4 2001/06/14 08:51:25 rudi -// -// -// Changed Module name to match file name. -// -// Revision 1.3 2001/06/13 02:26:46 rudi -// -// -// Small changes after running lint. -// -// Revision 1.2 2001/06/05 10:22:34 rudi -// -// -// - Added Support of up to 31 channels -// - Added support for 2,4 and 8 priority levels -// - Now can have up to 31 channels -// - Added many configuration items -// - Changed reset to async -// -// Revision 1.1.1.1 2001/03/19 13:10:47 rudi -// Initial Release -// -// -// - -`include "wb_dma_defines.v" - -// Arbiter -// -// Implements a simple round robin arbiter for DMA channels of -// same priority - -module wb_dma_ch_arb(clk, rst, req, gnt, advance); - -input clk; -input rst; -input [30:0] req; // Req input -output [4:0] gnt; // Grant output -input advance; // Next Target - -/////////////////////////////////////////////////////////////////////// -// -// Definitions -// - -parameter [4:0] - grant0 = 5'h0, - grant1 = 5'h1, - grant2 = 5'h2, - grant3 = 5'h3, - grant4 = 5'h4, - grant5 = 5'h5, - grant6 = 5'h6, - grant7 = 5'h7, - grant8 = 5'h8, - grant9 = 5'h9, - grant10 = 5'ha, - grant11 = 5'hb, - grant12 = 5'hc, - grant13 = 5'hd, - grant14 = 5'he, - grant15 = 5'hf, - grant16 = 5'h10, - grant17 = 5'h11, - grant18 = 5'h12, - grant19 = 5'h13, - grant20 = 5'h14, - grant21 = 5'h15, - grant22 = 5'h16, - grant23 = 5'h17, - grant24 = 5'h18, - grant25 = 5'h19, - grant26 = 5'h1a, - grant27 = 5'h1b, - grant28 = 5'h1c, - grant29 = 5'h1d, - grant30 = 5'h1e; - -/////////////////////////////////////////////////////////////////////// -// -// Local Registers and Wires -// - -reg [4:0] state, next_state; - -/////////////////////////////////////////////////////////////////////// -// -// Misc Logic -// - -assign gnt = state; - -always@(posedge clk or negedge rst) - if(!rst) state <= #1 grant0; - else state <= #1 next_state; - -/////////////////////////////////////////////////////////////////////// -// -// Next State Logic -// - implements round robin arbitration algorithm -// - switches grant if current req is dropped or next is asserted -// - parks at last grant -// - -always@(state or req or advance) - begin - next_state = state; // Default Keep State - case(state) // synopsys parallel_case full_case - grant0: - // if this req is dropped or next is asserted, check for other req's - if(!req[0] | advance) - begin - if(req[1]) next_state = grant1; - else - if(req[2]) next_state = grant2; - else - if(req[3]) next_state = grant3; - else - if(req[4]) next_state = grant4; - else - if(req[5]) next_state = grant5; - else - if(req[6]) next_state = grant6; - else - if(req[7]) next_state = grant7; - else - if(req[8]) next_state = grant8; - else - if(req[9]) next_state = grant9; - else - if(req[10]) next_state = grant10; - else - if(req[11]) next_state = grant11; - else - if(req[12]) next_state = grant12; - else - if(req[13]) next_state = grant13; - else - if(req[14]) next_state = grant14; - else - if(req[15]) next_state = grant15; - else - if(req[16]) next_state = grant16; - else - if(req[17]) next_state = grant17; - else - if(req[18]) next_state = grant18; - else - if(req[19]) next_state = grant19; - else - if(req[20]) next_state = grant20; - else - if(req[21]) next_state = grant21; - else - if(req[22]) next_state = grant22; - else - if(req[23]) next_state = grant23; - else - if(req[24]) next_state = grant24; - else - if(req[25]) next_state = grant25; - else - if(req[26]) next_state = grant26; - else - if(req[27]) next_state = grant27; - else - if(req[28]) next_state = grant28; - else - if(req[29]) next_state = grant29; - else - if(req[30]) next_state = grant30; - end - grant1: - // if this req is dropped or next is asserted, check for other req's - if(!req[1] | advance) - begin - if(req[2]) next_state = grant2; - else - if(req[3]) next_state = grant3; - else - if(req[4]) next_state = grant4; - else - if(req[5]) next_state = grant5; - else - if(req[6]) next_state = grant6; - else - if(req[7]) next_state = grant7; - else - if(req[8]) next_state = grant8; - else - if(req[9]) next_state = grant9; - else - if(req[10]) next_state = grant10; - else - if(req[11]) next_state = grant11; - else - if(req[12]) next_state = grant12; - else - if(req[13]) next_state = grant13; - else - if(req[14]) next_state = grant14; - else - if(req[15]) next_state = grant15; - else - if(req[16]) next_state = grant16; - else - if(req[17]) next_state = grant17; - else - if(req[18]) next_state = grant18; - else - if(req[19]) next_state = grant19; - else - if(req[20]) next_state = grant20; - else - if(req[21]) next_state = grant21; - else - if(req[22]) next_state = grant22; - else - if(req[23]) next_state = grant23; - else - if(req[24]) next_state = grant24; - else - if(req[25]) next_state = grant25; - else - if(req[26]) next_state = grant26; - else - if(req[27]) next_state = grant27; - else - if(req[28]) next_state = grant28; - else - if(req[29]) next_state = grant29; - else - if(req[30]) next_state = grant30; - else - if(req[0]) next_state = grant0; - end - grant2: - // if this req is dropped or next is asserted, check for other req's - if(!req[2] | advance) - begin - if(req[3]) next_state = grant3; - else - if(req[4]) next_state = grant4; - else - if(req[5]) next_state = grant5; - else - if(req[6]) next_state = grant6; - else - if(req[7]) next_state = grant7; - else - if(req[8]) next_state = grant8; - else - if(req[9]) next_state = grant9; - else - if(req[10]) next_state = grant10; - else - if(req[11]) next_state = grant11; - else - if(req[12]) next_state = grant12; - else - if(req[13]) next_state = grant13; - else - if(req[14]) next_state = grant14; - else - if(req[15]) next_state = grant15; - else - if(req[16]) next_state = grant16; - else - if(req[17]) next_state = grant17; - else - if(req[18]) next_state = grant18; - else - if(req[19]) next_state = grant19; - else - if(req[20]) next_state = grant20; - else - if(req[21]) next_state = grant21; - else - if(req[22]) next_state = grant22; - else - if(req[23]) next_state = grant23; - else - if(req[24]) next_state = grant24; - else - if(req[25]) next_state = grant25; - else - if(req[26]) next_state = grant26; - else - if(req[27]) next_state = grant27; - else - if(req[28]) next_state = grant28; - else - if(req[29]) next_state = grant29; - else - if(req[30]) next_state = grant30; - else - if(req[0]) next_state = grant0; - else - if(req[1]) next_state = grant1; - end - grant3: - // if this req is dropped or next is asserted, check for other req's - if(!req[3] | advance) - begin - if(req[4]) next_state = grant4; - else - if(req[5]) next_state = grant5; - else - if(req[6]) next_state = grant6; - else - if(req[7]) next_state = grant7; - else - if(req[8]) next_state = grant8; - else - if(req[9]) next_state = grant9; - else - if(req[10]) next_state = grant10; - else - if(req[11]) next_state = grant11; - else - if(req[12]) next_state = grant12; - else - if(req[13]) next_state = grant13; - else - if(req[14]) next_state = grant14; - else - if(req[15]) next_state = grant15; - else - if(req[16]) next_state = grant16; - else - if(req[17]) next_state = grant17; - else - if(req[18]) next_state = grant18; - else - if(req[19]) next_state = grant19; - else - if(req[20]) next_state = grant20; - else - if(req[21]) next_state = grant21; - else - if(req[22]) next_state = grant22; - else - if(req[23]) next_state = grant23; - else - if(req[24]) next_state = grant24; - else - if(req[25]) next_state = grant25; - else - if(req[26]) next_state = grant26; - else - if(req[27]) next_state = grant27; - else - if(req[28]) next_state = grant28; - else - if(req[29]) next_state = grant29; - else - if(req[30]) next_state = grant30; - else - if(req[0]) next_state = grant0; - else - if(req[1]) next_state = grant1; - else - if(req[2]) next_state = grant2; - end - grant4: - // if this req is dropped or next is asserted, check for other req's - if(!req[4] | advance) - begin - if(req[5]) next_state = grant5; - else - if(req[6]) next_state = grant6; - else - if(req[7]) next_state = grant7; - else - if(req[8]) next_state = grant8; - else - if(req[9]) next_state = grant9; - else - if(req[10]) next_state = grant10; - else - if(req[11]) next_state = grant11; - else - if(req[12]) next_state = grant12; - else - if(req[13]) next_state = grant13; - else - if(req[14]) next_state = grant14; - else - if(req[15]) next_state = grant15; - else - if(req[16]) next_state = grant16; - else - if(req[17]) next_state = grant17; - else - if(req[18]) next_state = grant18; - else - if(req[19]) next_state = grant19; - else - if(req[20]) next_state = grant20; - else - if(req[21]) next_state = grant21; - else - if(req[22]) next_state = grant22; - else - if(req[23]) next_state = grant23; - else - if(req[24]) next_state = grant24; - else - if(req[25]) next_state = grant25; - else - if(req[26]) next_state = grant26; - else - if(req[27]) next_state = grant27; - else - if(req[28]) next_state = grant28; - else - if(req[29]) next_state = grant29; - else - if(req[30]) next_state = grant30; - else - if(req[0]) next_state = grant0; - else - if(req[1]) next_state = grant1; - else - if(req[2]) next_state = grant2; - else - if(req[3]) next_state = grant3; - end - grant5: - // if this req is dropped or next is asserted, check for other req's - if(!req[5] | advance) - begin - if(req[6]) next_state = grant6; - else - if(req[7]) next_state = grant7; - else - if(req[8]) next_state = grant8; - else - if(req[9]) next_state = grant9; - else - if(req[10]) next_state = grant10; - else - if(req[11]) next_state = grant11; - else - if(req[12]) next_state = grant12; - else - if(req[13]) next_state = grant13; - else - if(req[14]) next_state = grant14; - else - if(req[15]) next_state = grant15; - else - if(req[16]) next_state = grant16; - else - if(req[17]) next_state = grant17; - else - if(req[18]) next_state = grant18; - else - if(req[19]) next_state = grant19; - else - if(req[20]) next_state = grant20; - else - if(req[21]) next_state = grant21; - else - if(req[22]) next_state = grant22; - else - if(req[23]) next_state = grant23; - else - if(req[24]) next_state = grant24; - else - if(req[25]) next_state = grant25; - else - if(req[26]) next_state = grant26; - else - if(req[27]) next_state = grant27; - else - if(req[28]) next_state = grant28; - else - if(req[29]) next_state = grant29; - else - if(req[30]) next_state = grant30; - else - if(req[0]) next_state = grant0; - else - if(req[1]) next_state = grant1; - else - if(req[2]) next_state = grant2; - else - if(req[3]) next_state = grant3; - else - if(req[4]) next_state = grant4; - end - grant6: - // if this req is dropped or next is asserted, check for other req's - if(!req[6] | advance) - begin - if(req[7]) next_state = grant7; - else - if(req[8]) next_state = grant8; - else - if(req[9]) next_state = grant9; - else - if(req[10]) next_state = grant10; - else - if(req[11]) next_state = grant11; - else - if(req[12]) next_state = grant12; - else - if(req[13]) next_state = grant13; - else - if(req[14]) next_state = grant14; - else - if(req[15]) next_state = grant15; - else - if(req[16]) next_state = grant16; - else - if(req[17]) next_state = grant17; - else - if(req[18]) next_state = grant18; - else - if(req[19]) next_state = grant19; - else - if(req[20]) next_state = grant20; - else - if(req[21]) next_state = grant21; - else - if(req[22]) next_state = grant22; - else - if(req[23]) next_state = grant23; - else - if(req[24]) next_state = grant24; - else - if(req[25]) next_state = grant25; - else - if(req[26]) next_state = grant26; - else - if(req[27]) next_state = grant27; - else - if(req[28]) next_state = grant28; - else - if(req[29]) next_state = grant29; - else - if(req[30]) next_state = grant30; - else - if(req[0]) next_state = grant0; - else - if(req[1]) next_state = grant1; - else - if(req[2]) next_state = grant2; - else - if(req[3]) next_state = grant3; - else - if(req[4]) next_state = grant4; - else - if(req[5]) next_state = grant5; - end - grant7: - // if this req is dropped or next is asserted, check for other req's - if(!req[7] | advance) - begin - if(req[8]) next_state = grant8; - else - if(req[9]) next_state = grant9; - else - if(req[10]) next_state = grant10; - else - if(req[11]) next_state = grant11; - else - if(req[12]) next_state = grant12; - else - if(req[13]) next_state = grant13; - else - if(req[14]) next_state = grant14; - else - if(req[15]) next_state = grant15; - else - if(req[16]) next_state = grant16; - else - if(req[17]) next_state = grant17; - else - if(req[18]) next_state = grant18; - else - if(req[19]) next_state = grant19; - else - if(req[20]) next_state = grant20; - else - if(req[21]) next_state = grant21; - else - if(req[22]) next_state = grant22; - else - if(req[23]) next_state = grant23; - else - if(req[24]) next_state = grant24; - else - if(req[25]) next_state = grant25; - else - if(req[26]) next_state = grant26; - else - if(req[27]) next_state = grant27; - else - if(req[28]) next_state = grant28; - else - if(req[29]) next_state = grant29; - else - if(req[30]) next_state = grant30; - else - if(req[0]) next_state = grant0; - else - if(req[1]) next_state = grant1; - else - if(req[2]) next_state = grant2; - else - if(req[3]) next_state = grant3; - else - if(req[4]) next_state = grant4; - else - if(req[5]) next_state = grant5; - else - if(req[6]) next_state = grant6; - end - grant8: - // if this req is dropped or next is asserted, check for other req's - if(!req[8] | advance) - begin - if(req[9]) next_state = grant9; - else - if(req[10]) next_state = grant10; - else - if(req[11]) next_state = grant11; - else - if(req[12]) next_state = grant12; - else - if(req[13]) next_state = grant13; - else - if(req[14]) next_state = grant14; - else - if(req[15]) next_state = grant15; - else - if(req[16]) next_state = grant16; - else - if(req[17]) next_state = grant17; - else - if(req[18]) next_state = grant18; - else - if(req[19]) next_state = grant19; - else - if(req[20]) next_state = grant20; - else - if(req[21]) next_state = grant21; - else - if(req[22]) next_state = grant22; - else - if(req[23]) next_state = grant23; - else - if(req[24]) next_state = grant24; - else - if(req[25]) next_state = grant25; - else - if(req[26]) next_state = grant26; - else - if(req[27]) next_state = grant27; - else - if(req[28]) next_state = grant28; - else - if(req[29]) next_state = grant29; - else - if(req[30]) next_state = grant30; - else - if(req[0]) next_state = grant0; - else - if(req[1]) next_state = grant1; - else - if(req[2]) next_state = grant2; - else - if(req[3]) next_state = grant3; - else - if(req[4]) next_state = grant4; - else - if(req[5]) next_state = grant5; - else - if(req[6]) next_state = grant6; - else - if(req[7]) next_state = grant7; - end - grant9: - // if this req is dropped or next is asserted, check for other req's - if(!req[9] | advance) - begin - if(req[10]) next_state = grant10; - else - if(req[11]) next_state = grant11; - else - if(req[12]) next_state = grant12; - else - if(req[13]) next_state = grant13; - else - if(req[14]) next_state = grant14; - else - if(req[15]) next_state = grant15; - else - if(req[16]) next_state = grant16; - else - if(req[17]) next_state = grant17; - else - if(req[18]) next_state = grant18; - else - if(req[19]) next_state = grant19; - else - if(req[20]) next_state = grant20; - else - if(req[21]) next_state = grant21; - else - if(req[22]) next_state = grant22; - else - if(req[23]) next_state = grant23; - else - if(req[24]) next_state = grant24; - else - if(req[25]) next_state = grant25; - else - if(req[26]) next_state = grant26; - else - if(req[27]) next_state = grant27; - else - if(req[28]) next_state = grant28; - else - if(req[29]) next_state = grant29; - else - if(req[30]) next_state = grant30; - else - if(req[0]) next_state = grant0; - else - if(req[1]) next_state = grant1; - else - if(req[2]) next_state = grant2; - else - if(req[3]) next_state = grant3; - else - if(req[4]) next_state = grant4; - else - if(req[5]) next_state = grant5; - else - if(req[6]) next_state = grant6; - else - if(req[7]) next_state = grant7; - else - if(req[8]) next_state = grant8; - end - grant10: - // if this req is dropped or next is asserted, check for other req's - if(!req[10] | advance) - begin - if(req[11]) next_state = grant11; - else - if(req[12]) next_state = grant12; - else - if(req[13]) next_state = grant13; - else - if(req[14]) next_state = grant14; - else - if(req[15]) next_state = grant15; - else - if(req[16]) next_state = grant16; - else - if(req[17]) next_state = grant17; - else - if(req[18]) next_state = grant18; - else - if(req[19]) next_state = grant19; - else - if(req[20]) next_state = grant20; - else - if(req[21]) next_state = grant21; - else - if(req[22]) next_state = grant22; - else - if(req[23]) next_state = grant23; - else - if(req[24]) next_state = grant24; - else - if(req[25]) next_state = grant25; - else - if(req[26]) next_state = grant26; - else - if(req[27]) next_state = grant27; - else - if(req[28]) next_state = grant28; - else - if(req[29]) next_state = grant29; - else - if(req[30]) next_state = grant30; - else - if(req[0]) next_state = grant0; - else - if(req[1]) next_state = grant1; - else - if(req[2]) next_state = grant2; - else - if(req[3]) next_state = grant3; - else - if(req[4]) next_state = grant4; - else - if(req[5]) next_state = grant5; - else - if(req[6]) next_state = grant6; - else - if(req[7]) next_state = grant7; - else - if(req[8]) next_state = grant8; - else - if(req[9]) next_state = grant9; - end - grant11: - // if this req is dropped or next is asserted, check for other req's - if(!req[11] | advance) - begin - if(req[12]) next_state = grant12; - else - if(req[13]) next_state = grant13; - else - if(req[14]) next_state = grant14; - else - if(req[15]) next_state = grant15; - else - if(req[16]) next_state = grant16; - else - if(req[17]) next_state = grant17; - else - if(req[18]) next_state = grant18; - else - if(req[19]) next_state = grant19; - else - if(req[20]) next_state = grant20; - else - if(req[21]) next_state = grant21; - else - if(req[22]) next_state = grant22; - else - if(req[23]) next_state = grant23; - else - if(req[24]) next_state = grant24; - else - if(req[25]) next_state = grant25; - else - if(req[26]) next_state = grant26; - else - if(req[27]) next_state = grant27; - else - if(req[28]) next_state = grant28; - else - if(req[29]) next_state = grant29; - else - if(req[30]) next_state = grant30; - else - if(req[0]) next_state = grant0; - else - if(req[1]) next_state = grant1; - else - if(req[2]) next_state = grant2; - else - if(req[3]) next_state = grant3; - else - if(req[4]) next_state = grant4; - else - if(req[5]) next_state = grant5; - else - if(req[6]) next_state = grant6; - else - if(req[7]) next_state = grant7; - else - if(req[8]) next_state = grant8; - else - if(req[9]) next_state = grant9; - else - if(req[10]) next_state = grant10; - end - grant12: - // if this req is dropped or next is asserted, check for other req's - if(!req[12] | advance) - begin - if(req[13]) next_state = grant13; - else - if(req[14]) next_state = grant14; - else - if(req[15]) next_state = grant15; - else - if(req[16]) next_state = grant16; - else - if(req[17]) next_state = grant17; - else - if(req[18]) next_state = grant18; - else - if(req[19]) next_state = grant19; - else - if(req[20]) next_state = grant20; - else - if(req[21]) next_state = grant21; - else - if(req[22]) next_state = grant22; - else - if(req[23]) next_state = grant23; - else - if(req[24]) next_state = grant24; - else - if(req[25]) next_state = grant25; - else - if(req[26]) next_state = grant26; - else - if(req[27]) next_state = grant27; - else - if(req[28]) next_state = grant28; - else - if(req[29]) next_state = grant29; - else - if(req[30]) next_state = grant30; - else - if(req[0]) next_state = grant0; - else - if(req[1]) next_state = grant1; - else - if(req[2]) next_state = grant2; - else - if(req[3]) next_state = grant3; - else - if(req[4]) next_state = grant4; - else - if(req[5]) next_state = grant5; - else - if(req[6]) next_state = grant6; - else - if(req[7]) next_state = grant7; - else - if(req[8]) next_state = grant8; - else - if(req[9]) next_state = grant9; - else - if(req[10]) next_state = grant10; - else - if(req[11]) next_state = grant11; - end - grant13: - // if this req is dropped or next is asserted, check for other req's - if(!req[13] | advance) - begin - if(req[14]) next_state = grant14; - else - if(req[15]) next_state = grant15; - else - if(req[16]) next_state = grant16; - else - if(req[17]) next_state = grant17; - else - if(req[18]) next_state = grant18; - else - if(req[19]) next_state = grant19; - else - if(req[20]) next_state = grant20; - else - if(req[21]) next_state = grant21; - else - if(req[22]) next_state = grant22; - else - if(req[23]) next_state = grant23; - else - if(req[24]) next_state = grant24; - else - if(req[25]) next_state = grant25; - else - if(req[26]) next_state = grant26; - else - if(req[27]) next_state = grant27; - else - if(req[28]) next_state = grant28; - else - if(req[29]) next_state = grant29; - else - if(req[30]) next_state = grant30; - else - if(req[0]) next_state = grant0; - else - if(req[1]) next_state = grant1; - else - if(req[2]) next_state = grant2; - else - if(req[3]) next_state = grant3; - else - if(req[4]) next_state = grant4; - else - if(req[5]) next_state = grant5; - else - if(req[6]) next_state = grant6; - else - if(req[7]) next_state = grant7; - else - if(req[8]) next_state = grant8; - else - if(req[9]) next_state = grant9; - else - if(req[10]) next_state = grant10; - else - if(req[11]) next_state = grant11; - else - if(req[12]) next_state = grant12; - end - grant14: - // if this req is dropped or next is asserted, check for other req's - if(!req[14] | advance) - begin - if(req[15]) next_state = grant15; - else - if(req[16]) next_state = grant16; - else - if(req[17]) next_state = grant17; - else - if(req[18]) next_state = grant18; - else - if(req[19]) next_state = grant19; - else - if(req[20]) next_state = grant20; - else - if(req[21]) next_state = grant21; - else - if(req[22]) next_state = grant22; - else - if(req[23]) next_state = grant23; - else - if(req[24]) next_state = grant24; - else - if(req[25]) next_state = grant25; - else - if(req[26]) next_state = grant26; - else - if(req[27]) next_state = grant27; - else - if(req[28]) next_state = grant28; - else - if(req[29]) next_state = grant29; - else - if(req[30]) next_state = grant30; - else - if(req[0]) next_state = grant0; - else - if(req[1]) next_state = grant1; - else - if(req[2]) next_state = grant2; - else - if(req[3]) next_state = grant3; - else - if(req[4]) next_state = grant4; - else - if(req[5]) next_state = grant5; - else - if(req[6]) next_state = grant6; - else - if(req[7]) next_state = grant7; - else - if(req[8]) next_state = grant8; - else - if(req[9]) next_state = grant9; - else - if(req[10]) next_state = grant10; - else - if(req[11]) next_state = grant11; - else - if(req[12]) next_state = grant12; - else - if(req[13]) next_state = grant13; - end - grant15: - // if this req is dropped or next is asserted, check for other req's - if(!req[15] | advance) - begin - if(req[16]) next_state = grant16; - else - if(req[17]) next_state = grant17; - else - if(req[18]) next_state = grant18; - else - if(req[19]) next_state = grant19; - else - if(req[20]) next_state = grant20; - else - if(req[21]) next_state = grant21; - else - if(req[22]) next_state = grant22; - else - if(req[23]) next_state = grant23; - else - if(req[24]) next_state = grant24; - else - if(req[25]) next_state = grant25; - else - if(req[26]) next_state = grant26; - else - if(req[27]) next_state = grant27; - else - if(req[28]) next_state = grant28; - else - if(req[29]) next_state = grant29; - else - if(req[30]) next_state = grant30; - else - if(req[0]) next_state = grant0; - else - if(req[1]) next_state = grant1; - else - if(req[2]) next_state = grant2; - else - if(req[3]) next_state = grant3; - else - if(req[4]) next_state = grant4; - else - if(req[5]) next_state = grant5; - else - if(req[6]) next_state = grant6; - else - if(req[7]) next_state = grant7; - else - if(req[8]) next_state = grant8; - else - if(req[9]) next_state = grant9; - else - if(req[10]) next_state = grant10; - else - if(req[11]) next_state = grant11; - else - if(req[12]) next_state = grant12; - else - if(req[13]) next_state = grant13; - else - if(req[14]) next_state = grant14; - end - grant16: - // if this req is dropped or next is asserted, check for other req's - if(!req[16] | advance) - begin - if(req[17]) next_state = grant17; - else - if(req[18]) next_state = grant18; - else - if(req[19]) next_state = grant19; - else - if(req[20]) next_state = grant20; - else - if(req[21]) next_state = grant21; - else - if(req[22]) next_state = grant22; - else - if(req[23]) next_state = grant23; - else - if(req[24]) next_state = grant24; - else - if(req[25]) next_state = grant25; - else - if(req[26]) next_state = grant26; - else - if(req[27]) next_state = grant27; - else - if(req[28]) next_state = grant28; - else - if(req[29]) next_state = grant29; - else - if(req[30]) next_state = grant30; - else - if(req[0]) next_state = grant0; - else - if(req[1]) next_state = grant1; - else - if(req[2]) next_state = grant2; - else - if(req[3]) next_state = grant3; - else - if(req[4]) next_state = grant4; - else - if(req[5]) next_state = grant5; - else - if(req[6]) next_state = grant6; - else - if(req[7]) next_state = grant7; - else - if(req[8]) next_state = grant8; - else - if(req[9]) next_state = grant9; - else - if(req[10]) next_state = grant10; - else - if(req[11]) next_state = grant11; - else - if(req[12]) next_state = grant12; - else - if(req[13]) next_state = grant13; - else - if(req[14]) next_state = grant14; - else - if(req[15]) next_state = grant15; - end - grant17: - // if this req is dropped or next is asserted, check for other req's - if(!req[17] | advance) - begin - if(req[18]) next_state = grant18; - else - if(req[19]) next_state = grant19; - else - if(req[20]) next_state = grant20; - else - if(req[21]) next_state = grant21; - else - if(req[22]) next_state = grant22; - else - if(req[23]) next_state = grant23; - else - if(req[24]) next_state = grant24; - else - if(req[25]) next_state = grant25; - else - if(req[26]) next_state = grant26; - else - if(req[27]) next_state = grant27; - else - if(req[28]) next_state = grant28; - else - if(req[29]) next_state = grant29; - else - if(req[30]) next_state = grant30; - else - if(req[0]) next_state = grant0; - else - if(req[1]) next_state = grant1; - else - if(req[2]) next_state = grant2; - else - if(req[3]) next_state = grant3; - else - if(req[4]) next_state = grant4; - else - if(req[5]) next_state = grant5; - else - if(req[6]) next_state = grant6; - else - if(req[7]) next_state = grant7; - else - if(req[8]) next_state = grant8; - else - if(req[9]) next_state = grant9; - else - if(req[10]) next_state = grant10; - else - if(req[11]) next_state = grant11; - else - if(req[12]) next_state = grant12; - else - if(req[13]) next_state = grant13; - else - if(req[14]) next_state = grant14; - else - if(req[15]) next_state = grant15; - else - if(req[16]) next_state = grant16; - end - grant18: - // if this req is dropped or next is asserted, check for other req's - if(!req[18] | advance) - begin - if(req[19]) next_state = grant19; - else - if(req[20]) next_state = grant20; - else - if(req[21]) next_state = grant21; - else - if(req[22]) next_state = grant22; - else - if(req[23]) next_state = grant23; - else - if(req[24]) next_state = grant24; - else - if(req[25]) next_state = grant25; - else - if(req[26]) next_state = grant26; - else - if(req[27]) next_state = grant27; - else - if(req[28]) next_state = grant28; - else - if(req[29]) next_state = grant29; - else - if(req[30]) next_state = grant30; - else - if(req[0]) next_state = grant0; - else - if(req[1]) next_state = grant1; - else - if(req[2]) next_state = grant2; - else - if(req[3]) next_state = grant3; - else - if(req[4]) next_state = grant4; - else - if(req[5]) next_state = grant5; - else - if(req[6]) next_state = grant6; - else - if(req[7]) next_state = grant7; - else - if(req[8]) next_state = grant8; - else - if(req[9]) next_state = grant9; - else - if(req[10]) next_state = grant10; - else - if(req[11]) next_state = grant11; - else - if(req[12]) next_state = grant12; - else - if(req[13]) next_state = grant13; - else - if(req[14]) next_state = grant14; - else - if(req[15]) next_state = grant15; - else - if(req[16]) next_state = grant16; - else - if(req[17]) next_state = grant17; - end - grant19: - // if this req is dropped or next is asserted, check for other req's - if(!req[19] | advance) - begin - if(req[20]) next_state = grant20; - else - if(req[21]) next_state = grant21; - else - if(req[22]) next_state = grant22; - else - if(req[23]) next_state = grant23; - else - if(req[24]) next_state = grant24; - else - if(req[25]) next_state = grant25; - else - if(req[26]) next_state = grant26; - else - if(req[27]) next_state = grant27; - else - if(req[28]) next_state = grant28; - else - if(req[29]) next_state = grant29; - else - if(req[30]) next_state = grant30; - else - if(req[0]) next_state = grant0; - else - if(req[1]) next_state = grant1; - else - if(req[2]) next_state = grant2; - else - if(req[3]) next_state = grant3; - else - if(req[4]) next_state = grant4; - else - if(req[5]) next_state = grant5; - else - if(req[6]) next_state = grant6; - else - if(req[7]) next_state = grant7; - else - if(req[8]) next_state = grant8; - else - if(req[9]) next_state = grant9; - else - if(req[10]) next_state = grant10; - else - if(req[11]) next_state = grant11; - else - if(req[12]) next_state = grant12; - else - if(req[13]) next_state = grant13; - else - if(req[14]) next_state = grant14; - else - if(req[15]) next_state = grant15; - else - if(req[16]) next_state = grant16; - else - if(req[17]) next_state = grant17; - else - if(req[18]) next_state = grant18; - end - grant20: - // if this req is dropped or next is asserted, check for other req's - if(!req[20] | advance) - begin - if(req[21]) next_state = grant21; - else - if(req[22]) next_state = grant22; - else - if(req[23]) next_state = grant23; - else - if(req[24]) next_state = grant24; - else - if(req[25]) next_state = grant25; - else - if(req[26]) next_state = grant26; - else - if(req[27]) next_state = grant27; - else - if(req[28]) next_state = grant28; - else - if(req[29]) next_state = grant29; - else - if(req[30]) next_state = grant30; - else - if(req[0]) next_state = grant0; - else - if(req[1]) next_state = grant1; - else - if(req[2]) next_state = grant2; - else - if(req[3]) next_state = grant3; - else - if(req[4]) next_state = grant4; - else - if(req[5]) next_state = grant5; - else - if(req[6]) next_state = grant6; - else - if(req[7]) next_state = grant7; - else - if(req[8]) next_state = grant8; - else - if(req[9]) next_state = grant9; - else - if(req[10]) next_state = grant10; - else - if(req[11]) next_state = grant11; - else - if(req[12]) next_state = grant12; - else - if(req[13]) next_state = grant13; - else - if(req[14]) next_state = grant14; - else - if(req[15]) next_state = grant15; - else - if(req[16]) next_state = grant16; - else - if(req[17]) next_state = grant17; - else - if(req[18]) next_state = grant18; - else - if(req[19]) next_state = grant19; - end - grant21: - // if this req is dropped or next is asserted, check for other req's - if(!req[21] | advance) - begin - if(req[22]) next_state = grant22; - else - if(req[23]) next_state = grant23; - else - if(req[24]) next_state = grant24; - else - if(req[25]) next_state = grant25; - else - if(req[26]) next_state = grant26; - else - if(req[27]) next_state = grant27; - else - if(req[28]) next_state = grant28; - else - if(req[29]) next_state = grant29; - else - if(req[30]) next_state = grant30; - else - if(req[0]) next_state = grant0; - else - if(req[1]) next_state = grant1; - else - if(req[2]) next_state = grant2; - else - if(req[3]) next_state = grant3; - else - if(req[4]) next_state = grant4; - else - if(req[5]) next_state = grant5; - else - if(req[6]) next_state = grant6; - else - if(req[7]) next_state = grant7; - else - if(req[8]) next_state = grant8; - else - if(req[9]) next_state = grant9; - else - if(req[10]) next_state = grant10; - else - if(req[11]) next_state = grant11; - else - if(req[12]) next_state = grant12; - else - if(req[13]) next_state = grant13; - else - if(req[14]) next_state = grant14; - else - if(req[15]) next_state = grant15; - else - if(req[16]) next_state = grant16; - else - if(req[17]) next_state = grant17; - else - if(req[18]) next_state = grant18; - else - if(req[19]) next_state = grant19; - else - if(req[20]) next_state = grant20; - end - grant22: - // if this req is dropped or next is asserted, check for other req's - if(!req[22] | advance) - begin - if(req[23]) next_state = grant23; - else - if(req[24]) next_state = grant24; - else - if(req[25]) next_state = grant25; - else - if(req[26]) next_state = grant26; - else - if(req[27]) next_state = grant27; - else - if(req[28]) next_state = grant28; - else - if(req[29]) next_state = grant29; - else - if(req[30]) next_state = grant30; - else - if(req[0]) next_state = grant0; - else - if(req[1]) next_state = grant1; - else - if(req[2]) next_state = grant2; - else - if(req[3]) next_state = grant3; - else - if(req[4]) next_state = grant4; - else - if(req[5]) next_state = grant5; - else - if(req[6]) next_state = grant6; - else - if(req[7]) next_state = grant7; - else - if(req[8]) next_state = grant8; - else - if(req[9]) next_state = grant9; - else - if(req[10]) next_state = grant10; - else - if(req[11]) next_state = grant11; - else - if(req[12]) next_state = grant12; - else - if(req[13]) next_state = grant13; - else - if(req[14]) next_state = grant14; - else - if(req[15]) next_state = grant15; - else - if(req[16]) next_state = grant16; - else - if(req[17]) next_state = grant17; - else - if(req[18]) next_state = grant18; - else - if(req[19]) next_state = grant19; - else - if(req[20]) next_state = grant20; - else - if(req[21]) next_state = grant21; - end - grant23: - // if this req is dropped or next is asserted, check for other req's - if(!req[23] | advance) - begin - if(req[24]) next_state = grant24; - else - if(req[25]) next_state = grant25; - else - if(req[26]) next_state = grant26; - else - if(req[27]) next_state = grant27; - else - if(req[28]) next_state = grant28; - else - if(req[29]) next_state = grant29; - else - if(req[30]) next_state = grant30; - else - if(req[0]) next_state = grant0; - else - if(req[1]) next_state = grant1; - else - if(req[2]) next_state = grant2; - else - if(req[3]) next_state = grant3; - else - if(req[4]) next_state = grant4; - else - if(req[5]) next_state = grant5; - else - if(req[6]) next_state = grant6; - else - if(req[7]) next_state = grant7; - else - if(req[8]) next_state = grant8; - else - if(req[9]) next_state = grant9; - else - if(req[10]) next_state = grant10; - else - if(req[11]) next_state = grant11; - else - if(req[12]) next_state = grant12; - else - if(req[13]) next_state = grant13; - else - if(req[14]) next_state = grant14; - else - if(req[15]) next_state = grant15; - else - if(req[16]) next_state = grant16; - else - if(req[17]) next_state = grant17; - else - if(req[18]) next_state = grant18; - else - if(req[19]) next_state = grant19; - else - if(req[20]) next_state = grant20; - else - if(req[21]) next_state = grant21; - else - if(req[22]) next_state = grant22; - end - grant24: - // if this req is dropped or next is asserted, check for other req's - if(!req[24] | advance) - begin - if(req[25]) next_state = grant25; - else - if(req[26]) next_state = grant26; - else - if(req[27]) next_state = grant27; - else - if(req[28]) next_state = grant28; - else - if(req[29]) next_state = grant29; - else - if(req[30]) next_state = grant30; - else - if(req[0]) next_state = grant0; - else - if(req[1]) next_state = grant1; - else - if(req[2]) next_state = grant2; - else - if(req[3]) next_state = grant3; - else - if(req[4]) next_state = grant4; - else - if(req[5]) next_state = grant5; - else - if(req[6]) next_state = grant6; - else - if(req[7]) next_state = grant7; - else - if(req[8]) next_state = grant8; - else - if(req[9]) next_state = grant9; - else - if(req[10]) next_state = grant10; - else - if(req[11]) next_state = grant11; - else - if(req[12]) next_state = grant12; - else - if(req[13]) next_state = grant13; - else - if(req[14]) next_state = grant14; - else - if(req[15]) next_state = grant15; - else - if(req[16]) next_state = grant16; - else - if(req[17]) next_state = grant17; - else - if(req[18]) next_state = grant18; - else - if(req[19]) next_state = grant19; - else - if(req[20]) next_state = grant20; - else - if(req[21]) next_state = grant21; - else - if(req[22]) next_state = grant22; - else - if(req[23]) next_state = grant23; - end - grant25: - // if this req is dropped or next is asserted, check for other req's - if(!req[25] | advance) - begin - if(req[26]) next_state = grant26; - else - if(req[27]) next_state = grant27; - else - if(req[28]) next_state = grant28; - else - if(req[29]) next_state = grant29; - else - if(req[30]) next_state = grant30; - else - if(req[0]) next_state = grant0; - else - if(req[1]) next_state = grant1; - else - if(req[2]) next_state = grant2; - else - if(req[3]) next_state = grant3; - else - if(req[4]) next_state = grant4; - else - if(req[5]) next_state = grant5; - else - if(req[6]) next_state = grant6; - else - if(req[7]) next_state = grant7; - else - if(req[8]) next_state = grant8; - else - if(req[9]) next_state = grant9; - else - if(req[10]) next_state = grant10; - else - if(req[11]) next_state = grant11; - else - if(req[12]) next_state = grant12; - else - if(req[13]) next_state = grant13; - else - if(req[14]) next_state = grant14; - else - if(req[15]) next_state = grant15; - else - if(req[16]) next_state = grant16; - else - if(req[17]) next_state = grant17; - else - if(req[18]) next_state = grant18; - else - if(req[19]) next_state = grant19; - else - if(req[20]) next_state = grant20; - else - if(req[21]) next_state = grant21; - else - if(req[22]) next_state = grant22; - else - if(req[23]) next_state = grant23; - else - if(req[24]) next_state = grant24; - end - grant26: - // if this req is dropped or next is asserted, check for other req's - if(!req[26] | advance) - begin - if(req[27]) next_state = grant27; - else - if(req[28]) next_state = grant28; - else - if(req[29]) next_state = grant29; - else - if(req[30]) next_state = grant30; - else - if(req[0]) next_state = grant0; - else - if(req[1]) next_state = grant1; - else - if(req[2]) next_state = grant2; - else - if(req[3]) next_state = grant3; - else - if(req[4]) next_state = grant4; - else - if(req[5]) next_state = grant5; - else - if(req[6]) next_state = grant6; - else - if(req[7]) next_state = grant7; - else - if(req[8]) next_state = grant8; - else - if(req[9]) next_state = grant9; - else - if(req[10]) next_state = grant10; - else - if(req[11]) next_state = grant11; - else - if(req[12]) next_state = grant12; - else - if(req[13]) next_state = grant13; - else - if(req[14]) next_state = grant14; - else - if(req[15]) next_state = grant15; - else - if(req[16]) next_state = grant16; - else - if(req[17]) next_state = grant17; - else - if(req[18]) next_state = grant18; - else - if(req[19]) next_state = grant19; - else - if(req[20]) next_state = grant20; - else - if(req[21]) next_state = grant21; - else - if(req[22]) next_state = grant22; - else - if(req[23]) next_state = grant23; - else - if(req[24]) next_state = grant24; - else - if(req[25]) next_state = grant25; - end - grant27: - // if this req is dropped or next is asserted, check for other req's - if(!req[27] | advance) - begin - if(req[28]) next_state = grant28; - else - if(req[29]) next_state = grant29; - else - if(req[30]) next_state = grant30; - else - if(req[0]) next_state = grant0; - else - if(req[1]) next_state = grant1; - else - if(req[2]) next_state = grant2; - else - if(req[3]) next_state = grant3; - else - if(req[4]) next_state = grant4; - else - if(req[5]) next_state = grant5; - else - if(req[6]) next_state = grant6; - else - if(req[7]) next_state = grant7; - else - if(req[8]) next_state = grant8; - else - if(req[9]) next_state = grant9; - else - if(req[10]) next_state = grant10; - else - if(req[11]) next_state = grant11; - else - if(req[12]) next_state = grant12; - else - if(req[13]) next_state = grant13; - else - if(req[14]) next_state = grant14; - else - if(req[15]) next_state = grant15; - else - if(req[16]) next_state = grant16; - else - if(req[17]) next_state = grant17; - else - if(req[18]) next_state = grant18; - else - if(req[19]) next_state = grant19; - else - if(req[20]) next_state = grant20; - else - if(req[21]) next_state = grant21; - else - if(req[22]) next_state = grant22; - else - if(req[23]) next_state = grant23; - else - if(req[24]) next_state = grant24; - else - if(req[25]) next_state = grant25; - else - if(req[26]) next_state = grant26; - end - grant28: - // if this req is dropped or next is asserted, check for other req's - if(!req[28] | advance) - begin - if(req[29]) next_state = grant29; - else - if(req[30]) next_state = grant30; - else - if(req[0]) next_state = grant0; - else - if(req[1]) next_state = grant1; - else - if(req[2]) next_state = grant2; - else - if(req[3]) next_state = grant3; - else - if(req[4]) next_state = grant4; - else - if(req[5]) next_state = grant5; - else - if(req[6]) next_state = grant6; - else - if(req[7]) next_state = grant7; - else - if(req[8]) next_state = grant8; - else - if(req[9]) next_state = grant9; - else - if(req[10]) next_state = grant10; - else - if(req[11]) next_state = grant11; - else - if(req[12]) next_state = grant12; - else - if(req[13]) next_state = grant13; - else - if(req[14]) next_state = grant14; - else - if(req[15]) next_state = grant15; - else - if(req[16]) next_state = grant16; - else - if(req[17]) next_state = grant17; - else - if(req[18]) next_state = grant18; - else - if(req[19]) next_state = grant19; - else - if(req[20]) next_state = grant20; - else - if(req[21]) next_state = grant21; - else - if(req[22]) next_state = grant22; - else - if(req[23]) next_state = grant23; - else - if(req[24]) next_state = grant24; - else - if(req[25]) next_state = grant25; - else - if(req[26]) next_state = grant26; - else - if(req[27]) next_state = grant27; - end - grant29: - // if this req is dropped or next is asserted, check for other req's - if(!req[29] | advance) - begin - if(req[30]) next_state = grant30; - else - if(req[0]) next_state = grant0; - else - if(req[1]) next_state = grant1; - else - if(req[2]) next_state = grant2; - else - if(req[3]) next_state = grant3; - else - if(req[4]) next_state = grant4; - else - if(req[5]) next_state = grant5; - else - if(req[6]) next_state = grant6; - else - if(req[7]) next_state = grant7; - else - if(req[8]) next_state = grant8; - else - if(req[9]) next_state = grant9; - else - if(req[10]) next_state = grant10; - else - if(req[11]) next_state = grant11; - else - if(req[12]) next_state = grant12; - else - if(req[13]) next_state = grant13; - else - if(req[14]) next_state = grant14; - else - if(req[15]) next_state = grant15; - else - if(req[16]) next_state = grant16; - else - if(req[17]) next_state = grant17; - else - if(req[18]) next_state = grant18; - else - if(req[19]) next_state = grant19; - else - if(req[20]) next_state = grant20; - else - if(req[21]) next_state = grant21; - else - if(req[22]) next_state = grant22; - else - if(req[23]) next_state = grant23; - else - if(req[24]) next_state = grant24; - else - if(req[25]) next_state = grant25; - else - if(req[26]) next_state = grant26; - else - if(req[27]) next_state = grant27; - else - if(req[28]) next_state = grant28; - end - grant30: - // if this req is dropped or next is asserted, check for other req's - if(!req[30] | advance) - begin - if(req[0]) next_state = grant0; - else - if(req[1]) next_state = grant1; - else - if(req[2]) next_state = grant2; - else - if(req[3]) next_state = grant3; - else - if(req[4]) next_state = grant4; - else - if(req[5]) next_state = grant5; - else - if(req[6]) next_state = grant6; - else - if(req[7]) next_state = grant7; - else - if(req[8]) next_state = grant8; - else - if(req[9]) next_state = grant9; - else - if(req[10]) next_state = grant10; - else - if(req[11]) next_state = grant11; - else - if(req[12]) next_state = grant12; - else - if(req[13]) next_state = grant13; - else - if(req[14]) next_state = grant14; - else - if(req[15]) next_state = grant15; - else - if(req[16]) next_state = grant16; - else - if(req[17]) next_state = grant17; - else - if(req[18]) next_state = grant18; - else - if(req[19]) next_state = grant19; - else - if(req[20]) next_state = grant20; - else - if(req[21]) next_state = grant21; - else - if(req[22]) next_state = grant22; - else - if(req[23]) next_state = grant23; - else - if(req[24]) next_state = grant24; - else - if(req[25]) next_state = grant25; - else - if(req[26]) next_state = grant26; - else - if(req[27]) next_state = grant27; - else - if(req[28]) next_state = grant28; - else - if(req[29]) next_state = grant29; - end - endcase - end - -endmodule - Index: trunk/rtl/verilog/wb_dma_inc30r.v =================================================================== --- trunk/rtl/verilog/wb_dma_inc30r.v (revision 16) +++ trunk/rtl/verilog/wb_dma_inc30r.v (nonexistent) @@ -1,92 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// WISHBONE DMA Primitives //// -//// //// -//// //// -//// Author: Rudolf Usselmann //// -//// rudi@asics.ws //// -//// //// -//// //// -//// Downloaded from: http://www.opencores.org/cores/wb_dma/ //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000-2002 Rudolf Usselmann //// -//// www.asics.ws //// -//// rudi@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: wb_dma_inc30r.v,v 1.2 2002-02-01 01:54:45 rudi Exp $ -// -// $Date: 2002-02-01 01:54:45 $ -// $Revision: 1.2 $ -// $Author: rudi $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: not supported by cvs2svn $ -// Revision 1.1 2001/07/29 08:57:02 rudi -// -// -// 1) Changed Directory Structure -// 2) Added restart signal (REST) -// -// Revision 1.2 2001/06/05 10:22:37 rudi -// -// -// - Added Support of up to 31 channels -// - Added support for 2,4 and 8 priority levels -// - Now can have up to 31 channels -// - Added many configuration items -// - Changed reset to async -// -// Revision 1.1.1.1 2001/03/19 13:11:12 rudi -// Initial Release -// -// -// - -`include "wb_dma_defines.v" - -module wb_dma_inc30r(clk, in, out); -input clk; -input [29:0] in; -output [29:0] out; - -// INC30_CENTER indicates the center bit of the 30 bit incrementor -// so it can be easily manually optimized for best performance -parameter INC30_CENTER = 16; - -reg [INC30_CENTER:0] out_r; - -always @(posedge clk) - out_r <= #1 in[(INC30_CENTER - 1):0] + 1; - -assign out[29:INC30_CENTER] = in[29:INC30_CENTER] + out_r[INC30_CENTER]; -assign out[(INC30_CENTER - 1):0] = out_r; - -endmodule - Index: trunk/rtl/verilog/wb_dma_ch_rf.v =================================================================== --- trunk/rtl/verilog/wb_dma_ch_rf.v (revision 16) +++ trunk/rtl/verilog/wb_dma_ch_rf.v (nonexistent) @@ -1,583 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// WISHBONE DMA One Channel Register File //// -//// //// -//// //// -//// Author: Rudolf Usselmann //// -//// rudi@asics.ws //// -//// //// -//// //// -//// Downloaded from: http://www.opencores.org/cores/wb_dma/ //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000-2002 Rudolf Usselmann //// -//// www.asics.ws //// -//// rudi@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: wb_dma_ch_rf.v,v 1.5 2002-02-01 01:54:45 rudi Exp $ -// -// $Date: 2002-02-01 01:54:45 $ -// $Revision: 1.5 $ -// $Author: rudi $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: not supported by cvs2svn $ -// Revision 1.4 2001/10/30 02:06:17 rudi -// -// - Fixed problem where synthesis tools would instantiate latches instead of flip-flops -// -// Revision 1.3 2001/10/19 04:35:04 rudi -// -// - Made the core parameterized -// -// Revision 1.2 2001/08/15 05:40:30 rudi -// -// - Changed IO names to be more clear. -// - Uniquifyed define names to be core specific. -// - Added Section 3.10, describing DMA restart. -// -// Revision 1.1 2001/07/29 08:57:02 rudi -// -// -// 1) Changed Directory Structure -// 2) Added restart signal (REST) -// -// Revision 1.3 2001/06/14 08:50:01 rudi -// -// Changed Module Name to match file name. -// -// Revision 1.2 2001/06/13 02:26:48 rudi -// -// -// Small changes after running lint. -// -// Revision 1.1 2001/06/05 10:25:27 rudi -// -// -// Initial checkin of register file for one channel. -// -// -// -// - -`include "wb_dma_defines.v" - -module wb_dma_ch_rf( clk, rst, - pointer, pointer_s, ch_csr, ch_txsz, ch_adr0, ch_adr1, - ch_am0, ch_am1, sw_pointer, ch_stop, ch_dis, int, - - wb_rf_din, wb_rf_adr, wb_rf_we, wb_rf_re, - - // DMA Registers Write Back Channel Select - ch_sel, ndnr, - - // DMA Engine Status - dma_busy, dma_err, dma_done, dma_done_all, - - // DMA Engine Reg File Update ctrl signals - de_csr, de_txsz, de_adr0, de_adr1, - de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we, - de_fetch_descr, dma_rest, - ptr_set - - ); - -parameter [4:0] CH_NO = 5'h0; // This Instances Channel ID -parameter [0:0] CH_EN = 1'b1; // This channel exists -parameter [0:0] HAVE_ARS = 1'b1; // 1=this Instance Supports ARS -parameter [0:0] HAVE_ED = 1'b1; // 1=this Instance Supports External Descriptors -parameter [0:0] HAVE_CBUF= 1'b1; // 1=this Instance Supports Cyclic Buffers - -input clk, rst; - -output [31:0] pointer; -output [31:0] pointer_s; -output [31:0] ch_csr; -output [31:0] ch_txsz; -output [31:0] ch_adr0; -output [31:0] ch_adr1; -output [31:0] ch_am0; -output [31:0] ch_am1; -output [31:0] sw_pointer; -output ch_stop; -output ch_dis; -output int; - -input [31:0] wb_rf_din; -input [7:0] wb_rf_adr; -input wb_rf_we; -input wb_rf_re; - -input [4:0] ch_sel; -input ndnr; - -// DMA Engine Status -input dma_busy, dma_err, dma_done, dma_done_all; - -// DMA Engine Reg File Update ctrl signals -input [31:0] de_csr; -input [11:0] de_txsz; -input [31:0] de_adr0; -input [31:0] de_adr1; -input de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we, ptr_set; -input de_fetch_descr; -input dma_rest; - -//////////////////////////////////////////////////////////////////// -// -// Local Wires and Registers -// - -wire [31:0] pointer; -reg [27:0] pointer_r; -reg [27:0] pointer_sr; -reg ptr_valid; -reg ch_eol; - -wire [31:0] ch_csr, ch_txsz; - -reg [8:0] ch_csr_r; -reg [2:0] ch_csr_r2; -reg [2:0] ch_csr_r3; -reg [2:0] int_src_r; -reg ch_err_r; -reg ch_stop; -reg ch_busy; -reg ch_done; -reg ch_err; -reg rest_en; - -reg [10:0] ch_chk_sz_r; -reg [11:0] ch_tot_sz_r; -reg [22:0] ch_txsz_s; -reg ch_sz_inf; - -wire [31:0] ch_adr0, ch_adr1; -reg [29:0] ch_adr0_r, ch_adr1_r; -wire [31:0] ch_am0, ch_am1; -reg [27:0] ch_am0_r, ch_am1_r; - -reg [29:0] ch_adr0_s, ch_adr1_s; - -reg [29:0] sw_pointer_r; -wire sw_pointer_we; -wire [28:0] cmp_adr; -reg ch_dis; -wire ch_enable; - -wire pointer_we; -wire ch_csr_we, ch_csr_re, ch_txsz_we, ch_adr0_we, ch_adr1_we; -wire ch_am0_we, ch_am1_we; -reg ch_rl; -wire ch_done_we; -wire ch_err_we; -wire chunk_done_we; - -wire ch_csr_dewe, ch_txsz_dewe, ch_adr0_dewe, ch_adr1_dewe; - -wire this_ptr_set; -wire ptr_inv; - -//////////////////////////////////////////////////////////////////// -// -// Aliases -// - -assign ch_adr0 = CH_EN ? {ch_adr0_r, 2'h0} : 32'h0; -assign ch_adr1 = CH_EN ? {ch_adr1_r, 2'h0} : 32'h0; -assign ch_am0 = (CH_EN & HAVE_CBUF) ? {ch_am0_r, 4'h0} : 32'hffff_fff0; -assign ch_am1 = (CH_EN & HAVE_CBUF) ? {ch_am1_r, 4'h0} : 32'hffff_fff0; -assign sw_pointer = (CH_EN & HAVE_CBUF) ? {sw_pointer_r,2'h0} : 32'h0; - -assign pointer = CH_EN ? {pointer_r, 3'h0, ptr_valid} : 32'h0; -assign pointer_s = CH_EN ? {pointer_sr, 4'h0} : 32'h0; -assign ch_csr = CH_EN ? {9'h0, int_src_r, ch_csr_r3, rest_en, ch_csr_r2, - ch_err, ch_done, ch_busy, 1'b0, ch_csr_r[8:1], ch_enable} : 32'h0; -assign ch_txsz = CH_EN ? {5'h0, ch_chk_sz_r, ch_sz_inf, 3'h0, ch_tot_sz_r} : 32'h0; - -assign ch_enable = CH_EN ? (ch_csr_r[`WDMA_CH_EN] & (HAVE_CBUF ? !ch_dis : 1'b1) ) : 1'b0; - -//////////////////////////////////////////////////////////////////// -// -// CH0 control signals -// - -parameter [4:0] CH_ADR = CH_NO + 5'h1; - -assign ch_csr_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h0); -assign ch_csr_re = CH_EN & wb_rf_re & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h0); -assign ch_txsz_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h1); -assign ch_adr0_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h2); -assign ch_am0_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h3); -assign ch_adr1_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h4); -assign ch_am1_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h5); -assign pointer_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h6); -assign sw_pointer_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h7); - -assign ch_done_we = CH_EN & (((ch_sel==CH_NO) & dma_done_all) | ndnr) & - (ch_csr[`WDMA_USE_ED] ? ch_eol : !ch_csr[`WDMA_ARS]); -assign chunk_done_we = CH_EN & (ch_sel==CH_NO) & dma_done; -assign ch_err_we = CH_EN & (ch_sel==CH_NO) & dma_err; -assign ch_csr_dewe = CH_EN & de_csr_we & (ch_sel==CH_NO); -assign ch_txsz_dewe = CH_EN & de_txsz_we & (ch_sel==CH_NO); -assign ch_adr0_dewe = CH_EN & de_adr0_we & (ch_sel==CH_NO); -assign ch_adr1_dewe = CH_EN & de_adr1_we & (ch_sel==CH_NO); - -assign ptr_inv = CH_EN & ((ch_sel==CH_NO) & dma_done_all) | ndnr; -assign this_ptr_set = CH_EN & ptr_set & (ch_sel==CH_NO); - -always @(posedge clk) - ch_rl <= #1 CH_EN & HAVE_ARS & ( - (rest_en & dma_rest) | - ((ch_sel==CH_NO) & dma_done_all & ch_csr[`WDMA_ARS] & !ch_csr[`WDMA_USE_ED]) - ); - -// --------------------------------------------------- -// Pointers - -always @(posedge clk or negedge rst) - if(!rst) ptr_valid <= #1 1'b0; - else - if(CH_EN & HAVE_ED) - begin - if( this_ptr_set | (rest_en & dma_rest) ) - ptr_valid <= #1 1'b1; - else - if(ptr_inv) ptr_valid <= #1 1'b0; - end - else ptr_valid <= #1 1'b0; - -always @(posedge clk or negedge rst) - if(!rst) ch_eol <= #1 1'b0; - else - if(CH_EN & HAVE_ED) - begin - if(ch_csr_dewe) ch_eol <= #1 de_csr[`WDMA_ED_EOL]; - else - if(ch_done_we) ch_eol <= #1 1'b0; - end - else ch_eol <= #1 1'b0; - -always @(posedge clk) - if(CH_EN & HAVE_ED) - begin - if(pointer_we) pointer_r <= #1 wb_rf_din[31:4]; - else - if(this_ptr_set) pointer_r <= #1 de_csr[31:4]; - end - else pointer_r <= #1 1'b0; - -always @(posedge clk) - if(CH_EN & HAVE_ED) - begin - if(this_ptr_set) pointer_sr <= #1 pointer_r; - end - else pointer_sr <= #1 1'b0; - -// --------------------------------------------------- -// CSR - -always @(posedge clk or negedge rst) - if(!rst) ch_csr_r <= #1 1'b0; - else - if(CH_EN) - begin - if(ch_csr_we) ch_csr_r <= #1 wb_rf_din[8:0]; - else - begin - if(ch_done_we) ch_csr_r[`WDMA_CH_EN] <= #1 1'b0; - if(ch_csr_dewe) ch_csr_r[4:1] <= #1 de_csr[19:16]; - end - end - -// done bit -always @(posedge clk or negedge rst) - if(!rst) ch_done <= #1 1'b0; - else - if(CH_EN) - begin - if(ch_csr_we) ch_done <= #1 !wb_rf_din[`WDMA_CH_EN]; - else - if(ch_done_we) ch_done <= #1 1'b1; - end - -// busy bit -always @(posedge clk) - ch_busy <= #1 CH_EN & (ch_sel==CH_NO) & dma_busy; - -// stop bit -always @(posedge clk) - ch_stop <= #1 CH_EN & ch_csr_we & wb_rf_din[`WDMA_STOP]; - -// error bit -always @(posedge clk or negedge rst) - if(!rst) ch_err <= #1 1'b0; - else - if(CH_EN) - begin - if(ch_err_we) ch_err <= #1 1'b1; - else - if(ch_csr_re) ch_err <= #1 1'b0; - end - -// Priority Bits -always @(posedge clk or negedge rst) - if(!rst) ch_csr_r2 <= #1 3'h0; - else - if(CH_EN & ch_csr_we) ch_csr_r2 <= #1 wb_rf_din[15:13]; - -// Restart Enable Bit (REST) -always @(posedge clk or negedge rst) - if(!rst) rest_en <= #1 1'b0; - else - if(CH_EN & ch_csr_we) rest_en <= #1 wb_rf_din[16]; - -// INT Mask -always @(posedge clk or negedge rst) - if(!rst) ch_csr_r3 <= #1 3'h0; - else - if(CH_EN & ch_csr_we) ch_csr_r3 <= #1 wb_rf_din[19:17]; - -// INT Source -always @(posedge clk or negedge rst) - if(!rst) int_src_r[2] <= #1 1'b0; - else - if(CH_EN) - begin - if(chunk_done_we) int_src_r[2] <= #1 1'b1; - else - if(ch_csr_re) int_src_r[2] <= #1 1'b0; - end - -always @(posedge clk or negedge rst) - if(!rst) int_src_r[1] <= #1 1'b0; - else - if(CH_EN) - begin - if(ch_done_we) int_src_r[1] <= #1 1'b1; - else - if(ch_csr_re) int_src_r[1] <= #1 1'b0; - end - -always @(posedge clk or negedge rst) - if(!rst) int_src_r[0] <= #1 1'b0; - else - if(CH_EN) - begin - if(ch_err_we) int_src_r[0] <= #1 1'b1; - else - if(ch_csr_re) int_src_r[0] <= #1 1'b0; - end - -// Interrupt Output -assign int = |(int_src_r & ch_csr_r3) & CH_EN; - -// --------------------------------------------------- -// TXZS -always @(posedge clk) - if(CH_EN) - begin - if(ch_txsz_we) - {ch_chk_sz_r, ch_tot_sz_r} <= #1 {wb_rf_din[26:16], wb_rf_din[11:0]}; - else - if(ch_txsz_dewe) - ch_tot_sz_r <= #1 de_txsz; - else - if(ch_rl) - {ch_chk_sz_r, ch_tot_sz_r} <= #1 ch_txsz_s; - end - -// txsz shadow register -always @(posedge clk) - if(CH_EN & HAVE_ARS) - begin - - if(ch_txsz_we) ch_txsz_s <= #1 {wb_rf_din[26:16], wb_rf_din[11:0]}; - else - if(rest_en & ch_txsz_dewe & de_fetch_descr) - ch_txsz_s[11:0] <= #1 de_txsz[11:0]; - end - -// Infinite Size indicator -always @(posedge clk) - if(CH_EN) - begin - if(ch_txsz_we) ch_sz_inf <= #1 wb_rf_din[15]; - end - -// --------------------------------------------------- -// ADR0 -always @(posedge clk) - if(CH_EN) - begin - if(ch_adr0_we) ch_adr0_r <= #1 wb_rf_din[31:2]; - else - if(ch_adr0_dewe) ch_adr0_r <= #1 de_adr0[31:2]; - else - if(ch_rl) ch_adr0_r <= #1 ch_adr0_s; - end - -// Adr0 shadow register -always @(posedge clk) - if(CH_EN & HAVE_ARS) - begin - if(ch_adr0_we) ch_adr0_s <= #1 wb_rf_din[31:2]; - else - if(rest_en & ch_adr0_dewe & de_fetch_descr) - ch_adr0_s <= #1 de_adr0[31:2]; - end - -// --------------------------------------------------- -// AM0 -always @(posedge clk or negedge rst) - if(!rst) ch_am0_r <= #1 28'hfffffff; - else - if(ch_am0_we) ch_am0_r <= #1 wb_rf_din[31:4]; - -// --------------------------------------------------- -// ADR1 -always @(posedge clk) - if(CH_EN) - begin - if(ch_adr1_we) ch_adr1_r <= #1 wb_rf_din[31:2]; - else - if(ch_adr1_dewe) ch_adr1_r <= #1 de_adr1[31:2]; - else - if(ch_rl) ch_adr1_r <= #1 ch_adr1_s; - end - -// Adr1 shadow register -always @(posedge clk) - if(CH_EN & HAVE_ARS) - begin - if(ch_adr1_we) ch_adr1_s <= #1 wb_rf_din[31:2]; - else - if(rest_en & ch_adr1_dewe & de_fetch_descr) - ch_adr1_s <= #1 de_adr1[31:2]; - end - -// --------------------------------------------------- -// AM1 -always @(posedge clk or negedge rst) - if(!rst) ch_am1_r <= #1 28'hfffffff; - else - if(ch_am1_we & CH_EN & HAVE_CBUF) ch_am1_r <= #1 wb_rf_din[31:4]; - -// --------------------------------------------------- -// Software Pointer -always @(posedge clk or negedge rst) - if(!rst) sw_pointer_r <= #1 28'h0; - else - if(sw_pointer_we & CH_EN & HAVE_CBUF) sw_pointer_r <= #1 wb_rf_din[31:4]; - -// --------------------------------------------------- -// Software Pointer Match logic - -assign cmp_adr = ch_csr[2] ? ch_adr1[30:2] : ch_adr0[30:2]; - -always @(posedge clk) - ch_dis <= #1 CH_EN & HAVE_CBUF & (sw_pointer[30:2] == cmp_adr) & sw_pointer[31]; - -endmodule - - -module wb_dma_ch_rf_dummy(clk, rst, - pointer, pointer_s, ch_csr, ch_txsz, ch_adr0, ch_adr1, - ch_am0, ch_am1, sw_pointer, ch_stop, ch_dis, int, - - wb_rf_din, wb_rf_adr, wb_rf_we, wb_rf_re, - - // DMA Registers Write Back Channel Select - ch_sel, ndnr, - - // DMA Engine Status - dma_busy, dma_err, dma_done, dma_done_all, - - // DMA Engine Reg File Update ctrl signals - de_csr, de_txsz, de_adr0, de_adr1, - de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we, - de_fetch_descr, dma_rest, - ptr_set - - ); - -parameter CH_NO = 0; -parameter HAVE_ARS = 1; -parameter HAVE_ED = 1; -parameter HAVE_CBUF= 1; - -input clk, rst; - -output [31:0] pointer; -output [31:0] pointer_s; -output [31:0] ch_csr; -output [31:0] ch_txsz; -output [31:0] ch_adr0; -output [31:0] ch_adr1; -output [31:0] ch_am0; -output [31:0] ch_am1; -output [31:0] sw_pointer; -output ch_stop; -output ch_dis; -output int; - -input [31:0] wb_rf_din; -input [7:0] wb_rf_adr; -input wb_rf_we; -input wb_rf_re; - -input [4:0] ch_sel; -input ndnr; - -// DMA Engine Status -input dma_busy, dma_err, dma_done, dma_done_all; - -// DMA Engine Reg File Update ctrl signals -input [31:0] de_csr; -input [11:0] de_txsz; -input [31:0] de_adr0; -input [31:0] de_adr1; -input de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we, ptr_set; -input de_fetch_descr; -input dma_rest; - -assign pointer = 32'h0; -assign pointer_s = 32'h0; -assign ch_csr = 32'h0; -assign ch_txsz = 32'h0; -assign ch_adr0 = 32'h0; -assign ch_adr1 = 32'h0; -assign ch_am0 = 32'h0; -assign ch_am1 = 32'h0; -assign sw_pointer = 32'h0; -assign ch_stop = 1'b0; -assign ch_dis = 1'b0; -assign int = 1'b0; - -endmodule Index: trunk/rtl/verilog/wb_dma_top.v =================================================================== --- trunk/rtl/verilog/wb_dma_top.v (revision 16) +++ trunk/rtl/verilog/wb_dma_top.v (nonexistent) @@ -1,1122 +0,0 @@ -///////////////////////////////////////////////////////////////////// -//// //// -//// WISHBONE DMA Top Level //// -//// //// -//// //// -//// Author: Rudolf Usselmann //// -//// rudi@asics.ws //// -//// //// -//// //// -//// Downloaded from: http://www.opencores.org/cores/wb_dma/ //// -//// //// -///////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000-2002 Rudolf Usselmann //// -//// www.asics.ws //// -//// rudi@asics.ws //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer.//// -//// //// -//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// -//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// -//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// -//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// -//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// -//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// -//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// -//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// -//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// -//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// -//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// -//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// -//// POSSIBILITY OF SUCH DAMAGE. //// -//// //// -///////////////////////////////////////////////////////////////////// - -// CVS Log -// -// $Id: wb_dma_top.v,v 1.5 2002-02-01 01:54:45 rudi Exp $ -// -// $Date: 2002-02-01 01:54:45 $ -// $Revision: 1.5 $ -// $Author: rudi $ -// $Locker: $ -// $State: Exp $ -// -// Change History: -// $Log: not supported by cvs2svn $ -// Revision 1.4 2001/10/19 04:35:04 rudi -// -// - Made the core parameterized -// -// Revision 1.3 2001/09/07 15:34:38 rudi -// -// Changed reset to active high. -// -// Revision 1.2 2001/08/15 05:40:30 rudi -// -// - Changed IO names to be more clear. -// - Uniquifyed define names to be core specific. -// - Added Section 3.10, describing DMA restart. -// -// Revision 1.1 2001/07/29 08:57:02 rudi -// -// -// 1) Changed Directory Structure -// 2) Added restart signal (REST) -// -// Revision 1.3 2001/06/13 02:26:50 rudi -// -// -// Small changes after running lint. -// -// Revision 1.2 2001/06/05 10:22:37 rudi -// -// -// - Added Support of up to 31 channels -// - Added support for 2,4 and 8 priority levels -// - Now can have up to 31 channels -// - Added many configuration items -// - Changed reset to async -// -// Revision 1.1.1.1 2001/03/19 13:10:23 rudi -// Initial Release -// -// -// - -`include "wb_dma_defines.v" - -module wb_dma_top(clk_i, rst_i, - - wb0s_data_i, wb0s_data_o, wb0_addr_i, wb0_sel_i, wb0_we_i, wb0_cyc_i, - wb0_stb_i, wb0_ack_o, wb0_err_o, wb0_rty_o, - wb0m_data_i, wb0m_data_o, wb0_addr_o, wb0_sel_o, wb0_we_o, wb0_cyc_o, - wb0_stb_o, wb0_ack_i, wb0_err_i, wb0_rty_i, - - wb1s_data_i, wb1s_data_o, wb1_addr_i, wb1_sel_i, wb1_we_i, wb1_cyc_i, - wb1_stb_i, wb1_ack_o, wb1_err_o, wb1_rty_o, - wb1m_data_i, wb1m_data_o, wb1_addr_o, wb1_sel_o, wb1_we_o, wb1_cyc_o, - wb1_stb_o, wb1_ack_i, wb1_err_i, wb1_rty_i, - - dma_req_i, dma_ack_o, dma_nd_i, dma_rest_i, - - inta_o, intb_o - ); - -//////////////////////////////////////////////////////////////////// -// -// Module Parameters -// - -// chXX_conf = { CBUF, ED, ARS, EN } -parameter rf_addr = 0; -parameter [1:0] pri_sel = 2'h0; -parameter ch_count = 1; -parameter [3:0] ch0_conf = 4'h1; -parameter [3:0] ch1_conf = 4'h0; -parameter [3:0] ch2_conf = 4'h0; -parameter [3:0] ch3_conf = 4'h0; -parameter [3:0] ch4_conf = 4'h0; -parameter [3:0] ch5_conf = 4'h0; -parameter [3:0] ch6_conf = 4'h0; -parameter [3:0] ch7_conf = 4'h0; -parameter [3:0] ch8_conf = 4'h0; -parameter [3:0] ch9_conf = 4'h0; -parameter [3:0] ch10_conf = 4'h0; -parameter [3:0] ch11_conf = 4'h0; -parameter [3:0] ch12_conf = 4'h0; -parameter [3:0] ch13_conf = 4'h0; -parameter [3:0] ch14_conf = 4'h0; -parameter [3:0] ch15_conf = 4'h0; -parameter [3:0] ch16_conf = 4'h0; -parameter [3:0] ch17_conf = 4'h0; -parameter [3:0] ch18_conf = 4'h0; -parameter [3:0] ch19_conf = 4'h0; -parameter [3:0] ch20_conf = 4'h0; -parameter [3:0] ch21_conf = 4'h0; -parameter [3:0] ch22_conf = 4'h0; -parameter [3:0] ch23_conf = 4'h0; -parameter [3:0] ch24_conf = 4'h0; -parameter [3:0] ch25_conf = 4'h0; -parameter [3:0] ch26_conf = 4'h0; -parameter [3:0] ch27_conf = 4'h0; -parameter [3:0] ch28_conf = 4'h0; -parameter [3:0] ch29_conf = 4'h0; -parameter [3:0] ch30_conf = 4'h0; - -//////////////////////////////////////////////////////////////////// -// -// Module IOs -// - -input clk_i, rst_i; - -// -------------------------------------- -// WISHBONE INTERFACE 0 - -// Slave Interface -input [31:0] wb0s_data_i; -output [31:0] wb0s_data_o; -input [31:0] wb0_addr_i; -input [3:0] wb0_sel_i; -input wb0_we_i; -input wb0_cyc_i; -input wb0_stb_i; -output wb0_ack_o; -output wb0_err_o; -output wb0_rty_o; - -// Master Interface -input [31:0] wb0m_data_i; -output [31:0] wb0m_data_o; -output [31:0] wb0_addr_o; -output [3:0] wb0_sel_o; -output wb0_we_o; -output wb0_cyc_o; -output wb0_stb_o; -input wb0_ack_i; -input wb0_err_i; -input wb0_rty_i; - -// -------------------------------------- -// WISHBONE INTERFACE 1 - -// Slave Interface -input [31:0] wb1s_data_i; -output [31:0] wb1s_data_o; -input [31:0] wb1_addr_i; -input [3:0] wb1_sel_i; -input wb1_we_i; -input wb1_cyc_i; -input wb1_stb_i; -output wb1_ack_o; -output wb1_err_o; -output wb1_rty_o; - -// Master Interface -input [31:0] wb1m_data_i; -output [31:0] wb1m_data_o; -output [31:0] wb1_addr_o; -output [3:0] wb1_sel_o; -output wb1_we_o; -output wb1_cyc_o; -output wb1_stb_o; -input wb1_ack_i; -input wb1_err_i; -input wb1_rty_i; - -// -------------------------------------- -// Misc Signals -input [ch_count-1:0] dma_req_i; -input [ch_count-1:0] dma_nd_i; -output [ch_count-1:0] dma_ack_o; -input [ch_count-1:0] dma_rest_i; -output inta_o; -output intb_o; - -//////////////////////////////////////////////////////////////////// -// -// Local Wires -// - -wire [31:0] pointer0, pointer0_s, ch0_csr, ch0_txsz, ch0_adr0, ch0_adr1, ch0_am0, ch0_am1; -wire [31:0] pointer1, pointer1_s, ch1_csr, ch1_txsz, ch1_adr0, ch1_adr1, ch1_am0, ch1_am1; -wire [31:0] pointer2, pointer2_s, ch2_csr, ch2_txsz, ch2_adr0, ch2_adr1, ch2_am0, ch2_am1; -wire [31:0] pointer3, pointer3_s, ch3_csr, ch3_txsz, ch3_adr0, ch3_adr1, ch3_am0, ch3_am1; -wire [31:0] pointer4, pointer4_s, ch4_csr, ch4_txsz, ch4_adr0, ch4_adr1, ch4_am0, ch4_am1; -wire [31:0] pointer5, pointer5_s, ch5_csr, ch5_txsz, ch5_adr0, ch5_adr1, ch5_am0, ch5_am1; -wire [31:0] pointer6, pointer6_s, ch6_csr, ch6_txsz, ch6_adr0, ch6_adr1, ch6_am0, ch6_am1; -wire [31:0] pointer7, pointer7_s, ch7_csr, ch7_txsz, ch7_adr0, ch7_adr1, ch7_am0, ch7_am1; -wire [31:0] pointer8, pointer8_s, ch8_csr, ch8_txsz, ch8_adr0, ch8_adr1, ch8_am0, ch8_am1; -wire [31:0] pointer9, pointer9_s, ch9_csr, ch9_txsz, ch9_adr0, ch9_adr1, ch9_am0, ch9_am1; -wire [31:0] pointer10, pointer10_s, ch10_csr, ch10_txsz, ch10_adr0, ch10_adr1, ch10_am0, ch10_am1; -wire [31:0] pointer11, pointer11_s, ch11_csr, ch11_txsz, ch11_adr0, ch11_adr1, ch11_am0, ch11_am1; -wire [31:0] pointer12, pointer12_s, ch12_csr, ch12_txsz, ch12_adr0, ch12_adr1, ch12_am0, ch12_am1; -wire [31:0] pointer13, pointer13_s, ch13_csr, ch13_txsz, ch13_adr0, ch13_adr1, ch13_am0, ch13_am1; -wire [31:0] pointer14, pointer14_s, ch14_csr, ch14_txsz, ch14_adr0, ch14_adr1, ch14_am0, ch14_am1; -wire [31:0] pointer15, pointer15_s, ch15_csr, ch15_txsz, ch15_adr0, ch15_adr1, ch15_am0, ch15_am1; -wire [31:0] pointer16, pointer16_s, ch16_csr, ch16_txsz, ch16_adr0, ch16_adr1, ch16_am0, ch16_am1; -wire [31:0] pointer17, pointer17_s, ch17_csr, ch17_txsz, ch17_adr0, ch17_adr1, ch17_am0, ch17_am1; -wire [31:0] pointer18, pointer18_s, ch18_csr, ch18_txsz, ch18_adr0, ch18_adr1, ch18_am0, ch18_am1; -wire [31:0] pointer19, pointer19_s, ch19_csr, ch19_txsz, ch19_adr0, ch19_adr1, ch19_am0, ch19_am1; -wire [31:0] pointer20, pointer20_s, ch20_csr, ch20_txsz, ch20_adr0, ch20_adr1, ch20_am0, ch20_am1; -wire [31:0] pointer21, pointer21_s, ch21_csr, ch21_txsz, ch21_adr0, ch21_adr1, ch21_am0, ch21_am1; -wire [31:0] pointer22, pointer22_s, ch22_csr, ch22_txsz, ch22_adr0, ch22_adr1, ch22_am0, ch22_am1; -wire [31:0] pointer23, pointer23_s, ch23_csr, ch23_txsz, ch23_adr0, ch23_adr1, ch23_am0, ch23_am1; -wire [31:0] pointer24, pointer24_s, ch24_csr, ch24_txsz, ch24_adr0, ch24_adr1, ch24_am0, ch24_am1; -wire [31:0] pointer25, pointer25_s, ch25_csr, ch25_txsz, ch25_adr0, ch25_adr1, ch25_am0, ch25_am1; -wire [31:0] pointer26, pointer26_s, ch26_csr, ch26_txsz, ch26_adr0, ch26_adr1, ch26_am0, ch26_am1; -wire [31:0] pointer27, pointer27_s, ch27_csr, ch27_txsz, ch27_adr0, ch27_adr1, ch27_am0, ch27_am1; -wire [31:0] pointer28, pointer28_s, ch28_csr, ch28_txsz, ch28_adr0, ch28_adr1, ch28_am0, ch28_am1; -wire [31:0] pointer29, pointer29_s, ch29_csr, ch29_txsz, ch29_adr0, ch29_adr1, ch29_am0, ch29_am1; -wire [31:0] pointer30, pointer30_s, ch30_csr, ch30_txsz, ch30_adr0, ch30_adr1, ch30_am0, ch30_am1; - -wire [4:0] ch_sel; // Write Back Channel Select -wire [30:0] ndnr; // Next Descriptor No Request -wire de_start; // Start DMA Engine -wire ndr; // Next Descriptor With Request -wire [31:0] csr; // Selected Channel CSR -wire [31:0] pointer; -wire [31:0] pointer_s; -wire [31:0] txsz; // Selected Channel Transfer Size -wire [31:0] adr0, adr1; // Selected Channel Addresses -wire [31:0] am0, am1; // Selected Channel Address Masks -wire next_ch; // Indicates the DMA Engine is done - -wire inta_o, intb_o; -wire dma_abort; -wire dma_busy, dma_err, dma_done, dma_done_all; -wire [31:0] de_csr; -wire [11:0] de_txsz; -wire [31:0] de_adr0; -wire [31:0] de_adr1; -wire de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we; -wire de_fetch_descr; -wire ptr_set; -wire de_ack; -wire pause_req; -wire paused; - -wire mast0_go; // Perform a Master Cycle (as long as this -wire mast0_we; // Read/Write -wire [31:0] mast0_adr; // Address for the transfer -wire [31:0] mast0_din; // Internal Input Data -wire [31:0] mast0_dout; // Internal Output Data -wire mast0_err; // Indicates an error has occurred -wire mast0_drdy; // Indicated that either data is available -wire mast0_wait; // Tells the master to insert wait cycles - -wire [31:0] slv0_adr; // Slave Address -wire [31:0] slv0_din; // Slave Input Data -wire [31:0] slv0_dout; // Slave Output Data -wire slv0_re; // Slave Read Enable -wire slv0_we; // Slave Write Enable - -wire pt0_sel_i; // Pass Through Mode Selected -wire [70:0] mast0_pt_in; // Grouped WISHBONE inputs -wire [34:0] mast0_pt_out; // Grouped WISHBONE outputs - -wire pt0_sel_o; // Pass Through Mode Active -wire [70:0] slv0_pt_out; // Grouped WISHBONE out signals -wire [34:0] slv0_pt_in; // Grouped WISHBONE in signals - -wire mast1_go; // Perform a Master Cycle (as long as this -wire mast1_we; // Read/Write -wire [31:0] mast1_adr; // Address for the transfer -wire [31:0] mast1_din; // Internal Input Data -wire [31:0] mast1_dout; // Internal Output Data -wire mast1_err; // Indicates an error has occurred -wire mast1_drdy; // Indicated that either data is available -wire mast1_wait; // Tells the master to insert wait cycles - -wire [31:0] slv1_adr; // Slave Address -wire [31:0] slv1_dout; // Slave Output Data -wire slv1_re; // Slave Read Enable -wire slv1_we; // Slave Write Enable - -wire pt1_sel_i; // Pass Through Mode Selected -wire [70:0] mast1_pt_in; // Grouped WISHBONE inputs -wire [34:0] mast1_pt_out; // Grouped WISHBONE outputs - -wire pt1_sel_o; // Pass Through Mode Active -wire [70:0] slv1_pt_out; // Grouped WISHBONE out signals -wire [34:0] slv1_pt_in; // Grouped WISHBONE in signals - -wire [30:0] dma_req; -wire [30:0] dma_nd; -wire [30:0] dma_ack; -wire [30:0] dma_rest; - -//////////////////////////////////////////////////////////////////// -// -// Misc Logic -// - -wire [31:0] tmp_gnd = 32'h0; - -assign dma_req[ch_count-1:0] = dma_req_i; -assign dma_nd[ch_count-1:0] = dma_nd_i; -assign dma_rest[ch_count-1:0] = dma_rest_i; -assign dma_ack_o = {tmp_gnd[31-ch_count:0], dma_ack[ch_count-1:0]}; - -// -------------------------------------------------- -// This should go in to a separate Pass Through Block -assign pt1_sel_i = pt0_sel_o; -assign pt0_sel_i = pt1_sel_o; -assign mast1_pt_in = slv0_pt_out; -assign slv0_pt_in = mast1_pt_out; -assign mast0_pt_in = slv1_pt_out; -assign slv1_pt_in = mast0_pt_out; -// -------------------------------------------------- - -//////////////////////////////////////////////////////////////////// -// -// Modules -// - -// DMA Register File -wb_dma_rf #( ch0_conf, - ch1_conf, - ch2_conf, - ch3_conf, - ch4_conf, - ch5_conf, - ch6_conf, - ch7_conf, - ch8_conf, - ch9_conf, - ch10_conf, - ch11_conf, - ch12_conf, - ch13_conf, - ch14_conf, - ch15_conf, - ch16_conf, - ch17_conf, - ch18_conf, - ch19_conf, - ch20_conf, - ch21_conf, - ch22_conf, - ch23_conf, - ch24_conf, - ch25_conf, - ch26_conf, - ch27_conf, - ch28_conf, - ch29_conf, - ch30_conf) - u0( - .clk( clk_i ), - .rst( ~rst_i ), - .wb_rf_adr( slv0_adr[9:2] ), - .wb_rf_din( slv0_dout ), - .wb_rf_dout( slv0_din ), - .wb_rf_re( slv0_re ), - .wb_rf_we( slv0_we ), - .inta_o( inta_o ), - .intb_o( intb_o ), - .pointer0( pointer0 ), - .pointer0_s( pointer0_s ), - .ch0_csr( ch0_csr ), - .ch0_txsz( ch0_txsz ), - .ch0_adr0( ch0_adr0 ), - .ch0_adr1( ch0_adr1 ), - .ch0_am0( ch0_am0 ), - .ch0_am1( ch0_am1 ), - .pointer1( pointer1 ), - .pointer1_s( pointer1_s ), - .ch1_csr( ch1_csr ), - .ch1_txsz( ch1_txsz ), - .ch1_adr0( ch1_adr0 ), - .ch1_adr1( ch1_adr1 ), - .ch1_am0( ch1_am0 ), - .ch1_am1( ch1_am1 ), - .pointer2( pointer2 ), - .pointer2_s( pointer2_s ), - .ch2_csr( ch2_csr ), - .ch2_txsz( ch2_txsz ), - .ch2_adr0( ch2_adr0 ), - .ch2_adr1( ch2_adr1 ), - .ch2_am0( ch2_am0 ), - .ch2_am1( ch2_am1 ), - .pointer3( pointer3 ), - .pointer3_s( pointer3_s ), - .ch3_csr( ch3_csr ), - .ch3_txsz( ch3_txsz ), - .ch3_adr0( ch3_adr0 ), - .ch3_adr1( ch3_adr1 ), - .ch3_am0( ch3_am0 ), - .ch3_am1( ch3_am1 ), - .pointer4( pointer4 ), - .pointer4_s( pointer4_s ), - .ch4_csr( ch4_csr ), - .ch4_txsz( ch4_txsz ), - .ch4_adr0( ch4_adr0 ), - .ch4_adr1( ch4_adr1 ), - .ch4_am0( ch4_am0 ), - .ch4_am1( ch4_am1 ), - .pointer5( pointer5 ), - .pointer5_s( pointer5_s ), - .ch5_csr( ch5_csr ), - .ch5_txsz( ch5_txsz ), - .ch5_adr0( ch5_adr0 ), - .ch5_adr1( ch5_adr1 ), - .ch5_am0( ch5_am0 ), - .ch5_am1( ch5_am1 ), - .pointer6( pointer6 ), - .pointer6_s( pointer6_s ), - .ch6_csr( ch6_csr ), - .ch6_txsz( ch6_txsz ), - .ch6_adr0( ch6_adr0 ), - .ch6_adr1( ch6_adr1 ), - .ch6_am0( ch6_am0 ), - .ch6_am1( ch6_am1 ), - .pointer7( pointer7 ), - .pointer7_s( pointer7_s ), - .ch7_csr( ch7_csr ), - .ch7_txsz( ch7_txsz ), - .ch7_adr0( ch7_adr0 ), - .ch7_adr1( ch7_adr1 ), - .ch7_am0( ch7_am0 ), - .ch7_am1( ch7_am1 ), - .pointer8( pointer8 ), - .pointer8_s( pointer8_s ), - .ch8_csr( ch8_csr ), - .ch8_txsz( ch8_txsz ), - .ch8_adr0( ch8_adr0 ), - .ch8_adr1( ch8_adr1 ), - .ch8_am0( ch8_am0 ), - .ch8_am1( ch8_am1 ), - .pointer9( pointer9 ), - .pointer9_s( pointer9_s ), - .ch9_csr( ch9_csr ), - .ch9_txsz( ch9_txsz ), - .ch9_adr0( ch9_adr0 ), - .ch9_adr1( ch9_adr1 ), - .ch9_am0( ch9_am0 ), - .ch9_am1( ch9_am1 ), - .pointer10( pointer10 ), - .pointer10_s( pointer10_s ), - .ch10_csr( ch10_csr ), - .ch10_txsz( ch10_txsz ), - .ch10_adr0( ch10_adr0 ), - .ch10_adr1( ch10_adr1 ), - .ch10_am0( ch10_am0 ), - .ch10_am1( ch10_am1 ), - .pointer11( pointer11 ), - .pointer11_s( pointer11_s ), - .ch11_csr( ch11_csr ), - .ch11_txsz( ch11_txsz ), - .ch11_adr0( ch11_adr0 ), - .ch11_adr1( ch11_adr1 ), - .ch11_am0( ch11_am0 ), - .ch11_am1( ch11_am1 ), - .pointer12( pointer12 ), - .pointer12_s( pointer12_s ), - .ch12_csr( ch12_csr ), - .ch12_txsz( ch12_txsz ), - .ch12_adr0( ch12_adr0 ), - .ch12_adr1( ch12_adr1 ), - .ch12_am0( ch12_am0 ), - .ch12_am1( ch12_am1 ), - .pointer13( pointer13 ), - .pointer13_s( pointer13_s ), - .ch13_csr( ch13_csr ), - .ch13_txsz( ch13_txsz ), - .ch13_adr0( ch13_adr0 ), - .ch13_adr1( ch13_adr1 ), - .ch13_am0( ch13_am0 ), - .ch13_am1( ch13_am1 ), - .pointer14( pointer14 ), - .pointer14_s( pointer14_s ), - .ch14_csr( ch14_csr ), - .ch14_txsz( ch14_txsz ), - .ch14_adr0( ch14_adr0 ), - .ch14_adr1( ch14_adr1 ), - .ch14_am0( ch14_am0 ), - .ch14_am1( ch14_am1 ), - .pointer15( pointer15 ), - .pointer15_s( pointer15_s ), - .ch15_csr( ch15_csr ), - .ch15_txsz( ch15_txsz ), - .ch15_adr0( ch15_adr0 ), - .ch15_adr1( ch15_adr1 ), - .ch15_am0( ch15_am0 ), - .ch15_am1( ch15_am1 ), - .pointer16( pointer16 ), - .pointer16_s( pointer16_s ), - .ch16_csr( ch16_csr ), - .ch16_txsz( ch16_txsz ), - .ch16_adr0( ch16_adr0 ), - .ch16_adr1( ch16_adr1 ), - .ch16_am0( ch16_am0 ), - .ch16_am1( ch16_am1 ), - .pointer17( pointer17 ), - .pointer17_s( pointer17_s ), - .ch17_csr( ch17_csr ), - .ch17_txsz( ch17_txsz ), - .ch17_adr0( ch17_adr0 ), - .ch17_adr1( ch17_adr1 ), - .ch17_am0( ch17_am0 ), - .ch17_am1( ch17_am1 ), - .pointer18( pointer18 ), - .pointer18_s( pointer18_s ), - .ch18_csr( ch18_csr ), - .ch18_txsz( ch18_txsz ), - .ch18_adr0( ch18_adr0 ), - .ch18_adr1( ch18_adr1 ), - .ch18_am0( ch18_am0 ), - .ch18_am1( ch18_am1 ), - .pointer19( pointer19 ), - .pointer19_s( pointer19_s ), - .ch19_csr( ch19_csr ), - .ch19_txsz( ch19_txsz ), - .ch19_adr0( ch19_adr0 ), - .ch19_adr1( ch19_adr1 ), - .ch19_am0( ch19_am0 ), - .ch19_am1( ch19_am1 ), - .pointer20( pointer20 ), - .pointer20_s( pointer20_s ), - .ch20_csr( ch20_csr ), - .ch20_txsz( ch20_txsz ), - .ch20_adr0( ch20_adr0 ), - .ch20_adr1( ch20_adr1 ), - .ch20_am0( ch20_am0 ), - .ch20_am1( ch20_am1 ), - .pointer21( pointer21 ), - .pointer21_s( pointer21_s ), - .ch21_csr( ch21_csr ), - .ch21_txsz( ch21_txsz ), - .ch21_adr0( ch21_adr0 ), - .ch21_adr1( ch21_adr1 ), - .ch21_am0( ch21_am0 ), - .ch21_am1( ch21_am1 ), - .pointer22( pointer22 ), - .pointer22_s( pointer22_s ), - .ch22_csr( ch22_csr ), - .ch22_txsz( ch22_txsz ), - .ch22_adr0( ch22_adr0 ), - .ch22_adr1( ch22_adr1 ), - .ch22_am0( ch22_am0 ), - .ch22_am1( ch22_am1 ), - .pointer23( pointer23 ), - .pointer23_s( pointer23_s ), - .ch23_csr( ch23_csr ), - .ch23_txsz( ch23_txsz ), - .ch23_adr0( ch23_adr0 ), - .ch23_adr1( ch23_adr1 ), - .ch23_am0( ch23_am0 ), - .ch23_am1( ch23_am1 ), - .pointer24( pointer24 ), - .pointer24_s( pointer24_s ), - .ch24_csr( ch24_csr ), - .ch24_txsz( ch24_txsz ), - .ch24_adr0( ch24_adr0 ), - .ch24_adr1( ch24_adr1 ), - .ch24_am0( ch24_am0 ), - .ch24_am1( ch24_am1 ), - .pointer25( pointer25 ), - .pointer25_s( pointer25_s ), - .ch25_csr( ch25_csr ), - .ch25_txsz( ch25_txsz ), - .ch25_adr0( ch25_adr0 ), - .ch25_adr1( ch25_adr1 ), - .ch25_am0( ch25_am0 ), - .ch25_am1( ch25_am1 ), - .pointer26( pointer26 ), - .pointer26_s( pointer26_s ), - .ch26_csr( ch26_csr ), - .ch26_txsz( ch26_txsz ), - .ch26_adr0( ch26_adr0 ), - .ch26_adr1( ch26_adr1 ), - .ch26_am0( ch26_am0 ), - .ch26_am1( ch26_am1 ), - .pointer27( pointer27 ), - .pointer27_s( pointer27_s ), - .ch27_csr( ch27_csr ), - .ch27_txsz( ch27_txsz ), - .ch27_adr0( ch27_adr0 ), - .ch27_adr1( ch27_adr1 ), - .ch27_am0( ch27_am0 ), - .ch27_am1( ch27_am1 ), - .pointer28( pointer28 ), - .pointer28_s( pointer28_s ), - .ch28_csr( ch28_csr ), - .ch28_txsz( ch28_txsz ), - .ch28_adr0( ch28_adr0 ), - .ch28_adr1( ch28_adr1 ), - .ch28_am0( ch28_am0 ), - .ch28_am1( ch28_am1 ), - .pointer29( pointer29 ), - .pointer29_s( pointer29_s ), - .ch29_csr( ch29_csr ), - .ch29_txsz( ch29_txsz ), - .ch29_adr0( ch29_adr0 ), - .ch29_adr1( ch29_adr1 ), - .ch29_am0( ch29_am0 ), - .ch29_am1( ch29_am1 ), - .pointer30( pointer30 ), - .pointer30_s( pointer30_s ), - .ch30_csr( ch30_csr ), - .ch30_txsz( ch30_txsz ), - .ch30_adr0( ch30_adr0 ), - .ch30_adr1( ch30_adr1 ), - .ch30_am0( ch30_am0 ), - .ch30_am1( ch30_am1 ), - .ch_sel( ch_sel ), - .ndnr( ndnr ), - .pause_req( pause_req ), - .paused( paused ), - .dma_abort( dma_abort ), - .dma_busy( dma_busy ), - .dma_err( dma_err ), - .dma_done( dma_done ), - .dma_done_all( dma_done_all ), - .de_csr( de_csr ), - .de_txsz( de_txsz ), - .de_adr0( de_adr0 ), - .de_adr1( de_adr1 ), - .de_csr_we( de_csr_we ), - .de_txsz_we( de_txsz_we ), - .de_adr0_we( de_adr0_we ), - .de_adr1_we( de_adr1_we ), - .de_fetch_descr(de_fetch_descr ), - .dma_rest( dma_rest ), - .ptr_set( ptr_set ) - ); - -// Channel Select -wb_dma_ch_sel #(pri_sel, - ch0_conf, - ch1_conf, - ch2_conf, - ch3_conf, - ch4_conf, - ch5_conf, - ch6_conf, - ch7_conf, - ch8_conf, - ch9_conf, - ch10_conf, - ch11_conf, - ch12_conf, - ch13_conf, - ch14_conf, - ch15_conf, - ch16_conf, - ch17_conf, - ch18_conf, - ch19_conf, - ch20_conf, - ch21_conf, - ch22_conf, - ch23_conf, - ch24_conf, - ch25_conf, - ch26_conf, - ch27_conf, - ch28_conf, - ch29_conf, - ch30_conf) - u1( - .clk( clk_i ), - .rst( ~rst_i ), - .req_i( dma_req ), - .ack_o( dma_ack ), - .nd_i( dma_nd ), - - .pointer0( pointer0 ), - .pointer0_s( pointer0_s ), - .ch0_csr( ch0_csr ), - .ch0_txsz( ch0_txsz ), - .ch0_adr0( ch0_adr0 ), - .ch0_adr1( ch0_adr1 ), - .ch0_am0( ch0_am0 ), - .ch0_am1( ch0_am1 ), - .pointer1( pointer1 ), - .pointer1_s( pointer1_s ), - .ch1_csr( ch1_csr ), - .ch1_txsz( ch1_txsz ), - .ch1_adr0( ch1_adr0 ), - .ch1_adr1( ch1_adr1 ), - .ch1_am0( ch1_am0 ), - .ch1_am1( ch1_am1 ), - .pointer2( pointer2 ), - .pointer2_s( pointer2_s ), - .ch2_csr( ch2_csr ), - .ch2_txsz( ch2_txsz ), - .ch2_adr0( ch2_adr0 ), - .ch2_adr1( ch2_adr1 ), - .ch2_am0( ch2_am0 ), - .ch2_am1( ch2_am1 ), - .pointer3( pointer3 ), - .pointer3_s( pointer3_s ), - .ch3_csr( ch3_csr ), - .ch3_txsz( ch3_txsz ), - .ch3_adr0( ch3_adr0 ), - .ch3_adr1( ch3_adr1 ), - .ch3_am0( ch3_am0 ), - .ch3_am1( ch3_am1 ), - .pointer4( pointer4 ), - .pointer4_s( pointer4_s ), - .ch4_csr( ch4_csr ), - .ch4_txsz( ch4_txsz ), - .ch4_adr0( ch4_adr0 ), - .ch4_adr1( ch4_adr1 ), - .ch4_am0( ch4_am0 ), - .ch4_am1( ch4_am1 ), - .pointer5( pointer5 ), - .pointer5_s( pointer5_s ), - .ch5_csr( ch5_csr ), - .ch5_txsz( ch5_txsz ), - .ch5_adr0( ch5_adr0 ), - .ch5_adr1( ch5_adr1 ), - .ch5_am0( ch5_am0 ), - .ch5_am1( ch5_am1 ), - .pointer6( pointer6 ), - .pointer6_s( pointer6_s ), - .ch6_csr( ch6_csr ), - .ch6_txsz( ch6_txsz ), - .ch6_adr0( ch6_adr0 ), - .ch6_adr1( ch6_adr1 ), - .ch6_am0( ch6_am0 ), - .ch6_am1( ch6_am1 ), - .pointer7( pointer7 ), - .pointer7_s( pointer7_s ), - .ch7_csr( ch7_csr ), - .ch7_txsz( ch7_txsz ), - .ch7_adr0( ch7_adr0 ), - .ch7_adr1( ch7_adr1 ), - .ch7_am0( ch7_am0 ), - .ch7_am1( ch7_am1 ), - .pointer8( pointer8 ), - .pointer8_s( pointer8_s ), - .ch8_csr( ch8_csr ), - .ch8_txsz( ch8_txsz ), - .ch8_adr0( ch8_adr0 ), - .ch8_adr1( ch8_adr1 ), - .ch8_am0( ch8_am0 ), - .ch8_am1( ch8_am1 ), - .pointer9( pointer9 ), - .pointer9_s( pointer9_s ), - .ch9_csr( ch9_csr ), - .ch9_txsz( ch9_txsz ), - .ch9_adr0( ch9_adr0 ), - .ch9_adr1( ch9_adr1 ), - .ch9_am0( ch9_am0 ), - .ch9_am1( ch9_am1 ), - .pointer10( pointer10 ), - .pointer10_s( pointer10_s ), - .ch10_csr( ch10_csr ), - .ch10_txsz( ch10_txsz ), - .ch10_adr0( ch10_adr0 ), - .ch10_adr1( ch10_adr1 ), - .ch10_am0( ch10_am0 ), - .ch10_am1( ch10_am1 ), - .pointer11( pointer11 ), - .pointer11_s( pointer11_s ), - .ch11_csr( ch11_csr ), - .ch11_txsz( ch11_txsz ), - .ch11_adr0( ch11_adr0 ), - .ch11_adr1( ch11_adr1 ), - .ch11_am0( ch11_am0 ), - .ch11_am1( ch11_am1 ), - .pointer12( pointer12 ), - .pointer12_s( pointer12_s ), - .ch12_csr( ch12_csr ), - .ch12_txsz( ch12_txsz ), - .ch12_adr0( ch12_adr0 ), - .ch12_adr1( ch12_adr1 ), - .ch12_am0( ch12_am0 ), - .ch12_am1( ch12_am1 ), - .pointer13( pointer13 ), - .pointer13_s( pointer13_s ), - .ch13_csr( ch13_csr ), - .ch13_txsz( ch13_txsz ), - .ch13_adr0( ch13_adr0 ), - .ch13_adr1( ch13_adr1 ), - .ch13_am0( ch13_am0 ), - .ch13_am1( ch13_am1 ), - .pointer14( pointer14 ), - .pointer14_s( pointer14_s ), - .ch14_csr( ch14_csr ), - .ch14_txsz( ch14_txsz ), - .ch14_adr0( ch14_adr0 ), - .ch14_adr1( ch14_adr1 ), - .ch14_am0( ch14_am0 ), - .ch14_am1( ch14_am1 ), - .pointer15( pointer15 ), - .pointer15_s( pointer15_s ), - .ch15_csr( ch15_csr ), - .ch15_txsz( ch15_txsz ), - .ch15_adr0( ch15_adr0 ), - .ch15_adr1( ch15_adr1 ), - .ch15_am0( ch15_am0 ), - .ch15_am1( ch15_am1 ), - .pointer16( pointer16 ), - .pointer16_s( pointer16_s ), - .ch16_csr( ch16_csr ), - .ch16_txsz( ch16_txsz ), - .ch16_adr0( ch16_adr0 ), - .ch16_adr1( ch16_adr1 ), - .ch16_am0( ch16_am0 ), - .ch16_am1( ch16_am1 ), - .pointer17( pointer17 ), - .pointer17_s( pointer17_s ), - .ch17_csr( ch17_csr ), - .ch17_txsz( ch17_txsz ), - .ch17_adr0( ch17_adr0 ), - .ch17_adr1( ch17_adr1 ), - .ch17_am0( ch17_am0 ), - .ch17_am1( ch17_am1 ), - .pointer18( pointer18 ), - .pointer18_s( pointer18_s ), - .ch18_csr( ch18_csr ), - .ch18_txsz( ch18_txsz ), - .ch18_adr0( ch18_adr0 ), - .ch18_adr1( ch18_adr1 ), - .ch18_am0( ch18_am0 ), - .ch18_am1( ch18_am1 ), - .pointer19( pointer19 ), - .pointer19_s( pointer19_s ), - .ch19_csr( ch19_csr ), - .ch19_txsz( ch19_txsz ), - .ch19_adr0( ch19_adr0 ), - .ch19_adr1( ch19_adr1 ), - .ch19_am0( ch19_am0 ), - .ch19_am1( ch19_am1 ), - .pointer20( pointer20 ), - .pointer20_s( pointer20_s ), - .ch20_csr( ch20_csr ), - .ch20_txsz( ch20_txsz ), - .ch20_adr0( ch20_adr0 ), - .ch20_adr1( ch20_adr1 ), - .ch20_am0( ch20_am0 ), - .ch20_am1( ch20_am1 ), - .pointer21( pointer21 ), - .pointer21_s( pointer21_s ), - .ch21_csr( ch21_csr ), - .ch21_txsz( ch21_txsz ), - .ch21_adr0( ch21_adr0 ), - .ch21_adr1( ch21_adr1 ), - .ch21_am0( ch21_am0 ), - .ch21_am1( ch21_am1 ), - .pointer22( pointer22 ), - .pointer22_s( pointer22_s ), - .ch22_csr( ch22_csr ), - .ch22_txsz( ch22_txsz ), - .ch22_adr0( ch22_adr0 ), - .ch22_adr1( ch22_adr1 ), - .ch22_am0( ch22_am0 ), - .ch22_am1( ch22_am1 ), - .pointer23( pointer23 ), - .pointer23_s( pointer23_s ), - .ch23_csr( ch23_csr ), - .ch23_txsz( ch23_txsz ), - .ch23_adr0( ch23_adr0 ), - .ch23_adr1( ch23_adr1 ), - .ch23_am0( ch23_am0 ), - .ch23_am1( ch23_am1 ), - .pointer24( pointer24 ), - .pointer24_s( pointer24_s ), - .ch24_csr( ch24_csr ), - .ch24_txsz( ch24_txsz ), - .ch24_adr0( ch24_adr0 ), - .ch24_adr1( ch24_adr1 ), - .ch24_am0( ch24_am0 ), - .ch24_am1( ch24_am1 ), - .pointer25( pointer25 ), - .pointer25_s( pointer25_s ), - .ch25_csr( ch25_csr ), - .ch25_txsz( ch25_txsz ), - .ch25_adr0( ch25_adr0 ), - .ch25_adr1( ch25_adr1 ), - .ch25_am0( ch25_am0 ), - .ch25_am1( ch25_am1 ), - .pointer26( pointer26 ), - .pointer26_s( pointer26_s ), - .ch26_csr( ch26_csr ), - .ch26_txsz( ch26_txsz ), - .ch26_adr0( ch26_adr0 ), - .ch26_adr1( ch26_adr1 ), - .ch26_am0( ch26_am0 ), - .ch26_am1( ch26_am1 ), - .pointer27( pointer27 ), - .pointer27_s( pointer27_s ), - .ch27_csr( ch27_csr ), - .ch27_txsz( ch27_txsz ), - .ch27_adr0( ch27_adr0 ), - .ch27_adr1( ch27_adr1 ), - .ch27_am0( ch27_am0 ), - .ch27_am1( ch27_am1 ), - .pointer28( pointer28 ), - .pointer28_s( pointer28_s ), - .ch28_csr( ch28_csr ), - .ch28_txsz( ch28_txsz ), - .ch28_adr0( ch28_adr0 ), - .ch28_adr1( ch28_adr1 ), - .ch28_am0( ch28_am0 ), - .ch28_am1( ch28_am1 ), - .pointer29( pointer29 ), - .pointer29_s( pointer29_s ), - .ch29_csr( ch29_csr ), - .ch29_txsz( ch29_txsz ), - .ch29_adr0( ch29_adr0 ), - .ch29_adr1( ch29_adr1 ), - .ch29_am0( ch29_am0 ), - .ch29_am1( ch29_am1 ), - .pointer30( pointer30 ), - .pointer30_s( pointer30_s ), - .ch30_csr( ch30_csr ), - .ch30_txsz( ch30_txsz ), - .ch30_adr0( ch30_adr0 ), - .ch30_adr1( ch30_adr1 ), - .ch30_am0( ch30_am0 ), - .ch30_am1( ch30_am1 ), - - .ch_sel( ch_sel ), - .ndnr( ndnr ), - .de_start( de_start ), - .ndr( ndr ), - .csr( csr ), - .pointer( pointer ), - .txsz( txsz ), - .adr0( adr0 ), - .adr1( adr1 ), - .am0( am0 ), - .am1( am1 ), - .pointer_s( pointer_s ), - .next_ch( next_ch ), - .de_ack( de_ack ), - .dma_busy( dma_busy ) - ); - - -// DMA Engine -wb_dma_de u2( - .clk( clk_i ), - .rst( ~rst_i ), - .mast0_go( mast0_go ), - .mast0_we( mast0_we ), - .mast0_adr( mast0_adr ), - .mast0_din( mast0_dout ), - .mast0_dout( mast0_din ), - .mast0_err( mast0_err ), - .mast0_drdy( mast0_drdy ), - .mast0_wait( mast0_wait ), - .mast1_go( mast1_go ), - .mast1_we( mast1_we ), - .mast1_adr( mast1_adr ), - .mast1_din( mast1_dout ), - .mast1_dout( mast1_din ), - .mast1_err( mast1_err ), - .mast1_drdy( mast1_drdy ), - .mast1_wait( mast1_wait ), - .de_start( de_start ), - .nd( ndr ), - .csr( csr ), - .pointer( pointer ), - .pointer_s( pointer_s ), - .txsz( txsz ), - .adr0( adr0 ), - .adr1( adr1 ), - .am0( am0 ), - .am1( am1 ), - .de_csr_we( de_csr_we ), - .de_txsz_we( de_txsz_we ), - .de_adr0_we( de_adr0_we ), - .de_adr1_we( de_adr1_we ), - .de_fetch_descr(de_fetch_descr ), - .ptr_set( ptr_set ), - .de_csr( de_csr ), - .de_txsz( de_txsz ), - .de_adr0( de_adr0 ), - .de_adr1( de_adr1 ), - .next_ch( next_ch ), - .de_ack( de_ack ), - .pause_req( pause_req ), - .paused( paused ), - .dma_abort( dma_abort ), - .dma_busy( dma_busy ), - .dma_err( dma_err ), - .dma_done( dma_done ), - .dma_done_all( dma_done_all ) - ); - -// Wishbone Interface 0 -wb_dma_wb_if #(rf_addr) u3( - .clk( clk_i ), - .rst( ~rst_i ), - .wbs_data_i( wb0s_data_i ), - .wbs_data_o( wb0s_data_o ), - .wb_addr_i( wb0_addr_i ), - .wb_sel_i( wb0_sel_i ), - .wb_we_i( wb0_we_i ), - .wb_cyc_i( wb0_cyc_i ), - .wb_stb_i( wb0_stb_i ), - .wb_ack_o( wb0_ack_o ), - .wb_err_o( wb0_err_o ), - .wb_rty_o( wb0_rty_o ), - .wbm_data_i( wb0m_data_i ), - .wbm_data_o( wb0m_data_o ), - .wb_addr_o( wb0_addr_o ), - .wb_sel_o( wb0_sel_o ), - .wb_we_o( wb0_we_o ), - .wb_cyc_o( wb0_cyc_o ), - .wb_stb_o( wb0_stb_o ), - .wb_ack_i( wb0_ack_i ), - .wb_err_i( wb0_err_i ), - .wb_rty_i( wb0_rty_i ), - .mast_go( mast0_go ), - .mast_we( mast0_we ), - .mast_adr( mast0_adr ), - .mast_din( mast0_din ), - .mast_dout( mast0_dout ), - .mast_err( mast0_err ), - .mast_drdy( mast0_drdy ), - .mast_wait( mast0_wait ), - .pt_sel_i( pt0_sel_i ), - .mast_pt_in( mast0_pt_in ), - .mast_pt_out( mast0_pt_out ), - .slv_adr( slv0_adr ), - .slv_din( slv0_din ), - .slv_dout( slv0_dout ), - .slv_re( slv0_re ), - .slv_we( slv0_we ), - .pt_sel_o( pt0_sel_o ), - .slv_pt_out( slv0_pt_out ), - .slv_pt_in( slv0_pt_in ) - ); - -// Wishbone Interface 1 -wb_dma_wb_if #(rf_addr) u4( - .clk( clk_i ), - .rst( ~rst_i ), - .wbs_data_i( wb1s_data_i ), - .wbs_data_o( wb1s_data_o ), - .wb_addr_i( wb1_addr_i ), - .wb_sel_i( wb1_sel_i ), - .wb_we_i( wb1_we_i ), - .wb_cyc_i( wb1_cyc_i ), - .wb_stb_i( wb1_stb_i ), - .wb_ack_o( wb1_ack_o ), - .wb_err_o( wb1_err_o ), - .wb_rty_o( wb1_rty_o ), - .wbm_data_i( wb1m_data_i ), - .wbm_data_o( wb1m_data_o ), - .wb_addr_o( wb1_addr_o ), - .wb_sel_o( wb1_sel_o ), - .wb_we_o( wb1_we_o ), - .wb_cyc_o( wb1_cyc_o ), - .wb_stb_o( wb1_stb_o ), - .wb_ack_i( wb1_ack_i ), - .wb_err_i( wb1_err_i ), - .wb_rty_i( wb1_rty_i ), - .mast_go( mast1_go ), - .mast_we( mast1_we ), - .mast_adr( mast1_adr ), - .mast_din( mast1_din ), - .mast_dout( mast1_dout ), - .mast_err( mast1_err ), - .mast_drdy( mast1_drdy ), - .mast_wait( mast1_wait ), - .pt_sel_i( pt1_sel_i ), - .mast_pt_in( mast1_pt_in ), - .mast_pt_out( mast1_pt_out ), - .slv_adr( slv1_adr ), - .slv_din( 32'h0 ), // Not Connected - .slv_dout( slv1_dout ), // Not Connected - .slv_re( slv1_re ), // Not Connected - .slv_we( slv1_we ), // Not Connected - .pt_sel_o( pt1_sel_o ), - .slv_pt_out( slv1_pt_out ), - .slv_pt_in( slv1_pt_in ) - ); - - -endmodule Index: wb_dma/trunk/sim/rtl_sim/bin/Makefile =================================================================== --- wb_dma/trunk/sim/rtl_sim/bin/Makefile (nonexistent) +++ wb_dma/trunk/sim/rtl_sim/bin/Makefile (revision 17) @@ -0,0 +1,93 @@ + +all: sim +SHELL = /bin/sh +MS=-s + +########################################################################## +# +# DUT Sources +# +########################################################################## +DUT_SRC_DIR=../../../rtl/verilog +_TARGETS_= $(DUT_SRC_DIR)/wb_dma_ch_pri_enc.v \ + $(DUT_SRC_DIR)/wb_dma_ch_arb.v \ + $(DUT_SRC_DIR)/wb_dma_pri_enc_sub.v \ + $(DUT_SRC_DIR)/wb_dma_ch_sel.v \ + $(DUT_SRC_DIR)/wb_dma_top.v \ + $(DUT_SRC_DIR)/wb_dma_ch_rf.v \ + $(DUT_SRC_DIR)/wb_dma_rf.v \ + $(DUT_SRC_DIR)/wb_dma_wb_if.v \ + $(DUT_SRC_DIR)/wb_dma_wb_mast.v \ + $(DUT_SRC_DIR)/wb_dma_wb_slv.v \ + $(DUT_SRC_DIR)/wb_dma_de.v \ + $(DUT_SRC_DIR)/wb_dma_inc30r.v + +########################################################################## +# +# Test Bench Sources +# +########################################################################## +_TOP_=test +TB_SRC_DIR=../../../bench/verilog +_TB_= $(TB_SRC_DIR)/test_bench_top.v \ + $(TB_SRC_DIR)/wb_slv_model.v \ + $(TB_SRC_DIR)/wb_mast_model.v + +########################################################################## +# +# Misc Variables +# +########################################################################## + +#INCDIR="-INCDIR ./$(DUT_SRC_DIR)/ -INCDIR ./$(TB_SRC_DIR)/" +#LOGF=-LOGFILE .nclog +#NCCOMMON=-CDSLIB ncwork/cds.lib -HDLVAR ncwork/hdl.var -NOCOPYRIGHT + +INCDIR=+incdir+./$(DUT_SRC_DIR)/ +incdir+./$(TB_SRC_DIR)/ +LOGF=-l .nclog + +UMC_LIB=/tools/dc_libraries/virtual_silicon/umc_lib.v +GATE_NETLIST = ../../../syn/out/wb_dma_top_ps.v + +########################################################################## +# +# Make Targets +# +########################################################################## + +ss: + signalscan -do waves/waves.do -waves waves/waves.trn & + +simxl: + verilog +incdir+$(DUT_SRC_DIR) +incdir+$(TB_SRC_DIR) \ + $(_TARGETS_) $(_TB_) + +simw: + @$(MAKE) -s sim ACCESS="+access+r " WAVES="+define+WAVES" + +sim: + ncverilog -q +define+RUDIS_TB $(_TARGETS_) $(_TB_) \ + $(INCDIR) $(WAVES) $(ACCESS) $(LOGF) +ncstatus \ + +ncuid+`hostname` + +gatew: + @$(MAKE) -s gate ACCESS="+access+r" WAVES="+define+WAVES" + +gate: + ncverilog -q +define+RUDIS_TB $(_TB_) $(UMC_LIB) \ + $(GATE_NETLIST) $(INCDIR) $(WAVES) $(ACCESS) \ + $(LOGF) +ncstatus +ncuid+`hostname` + +hal: + @echo "" + @echo "----- Running HAL ... ----------" + @hal -NOP -NOS -nocheck STYVAL:USEPRT:NOBLKN:DLNBLK \ + +incdir+$(DUT_SRC_DIR) $(_TARGETS_) + @echo "----- DONE ... ----------" + +clean: + rm -rf ./waves/*.dsn ./waves/*.trn \ + ncwork/inc* ncwork/.inc* ncverilog.key \ + ./verilog.* .nclog hal.log INCA_libs + +##########################################################################

wb_dma/trunk/sim/rtl_sim/bin/Makefile Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: wb_dma/trunk/bench/verilog/wb_mast_model.v =================================================================== --- wb_dma/trunk/bench/verilog/wb_mast_model.v (nonexistent) +++ wb_dma/trunk/bench/verilog/wb_mast_model.v (revision 17) @@ -0,0 +1,687 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Master Model //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/wb_dma/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: wb_mast_model.v,v 1.3 2002-02-01 01:55:44 rudi Exp $ +// +// $Date: 2002-02-01 01:55:44 $ +// $Revision: 1.3 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.2 2001/09/07 15:34:36 rudi +// +// Changed reset to active high. +// +// Revision 1.1 2001/07/29 08:57:02 rudi +// +// +// 1) Changed Directory Structure +// 2) Added restart signal (REST) +// +// Revision 1.1.1.1 2001/03/19 13:11:34 rudi +// Initial Release +// +// +// + +`include "wb_model_defines.v" + +module wb_mast(clk, rst, adr, din, dout, cyc, stb, sel, we, ack, err, rty); + +input clk, rst; +output [31:0] adr; +input [31:0] din; +output [31:0] dout; +output cyc, stb; +output [3:0] sel; +output we; +input ack, err, rty; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +parameter mem_size = 4096; + +reg [31:0] adr; +reg [31:0] dout; +reg cyc, stb; +reg [3:0] sel; +reg we; + +reg [31:0] rd_mem[mem_size:0]; +reg [31:0] wr_mem[mem_size:0]; +integer rd_cnt; +integer wr_cnt; + +//////////////////////////////////////////////////////////////////// +// +// Memory Logic +// + +initial + begin + //adr = 32'hxxxx_xxxx; + //adr = 0; + adr = 32'hffff_ffff; + dout = 32'hxxxx_xxxx; + cyc = 0; + stb = 0; + sel = 4'hx; + we = 1'hx; + rd_cnt = 0; + wr_cnt = 0; + #1; + $display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n"); + end + + + +task mem_fill; + +integer n; +begin +rd_cnt = 0; +wr_cnt = 0; +for(n=0;n5000) + begin + $display("\n\n*************************************\n"); + $display("ERROR: Watch Dog Counter Expired\n"); + $display("*************************************\n\n\n"); + $finish; + end + +always #5 clk = ~clk; + +///////////////////////////////////////////////////////////////////// +// +// WISHBONE DMA IP Core +// + + +// Module Prototype + +wb_dma_top + #( 4'hb, // register file address + 2'd1, // Number of priorities (4) + `CH_COUNT, // Number of channels + 4'hf, + 4'hf, + 4'hf, + 4'hf, + 4'hf, + 4'hf, + 4'hf, + 4'hf + ) + u0( + .clk_i( clk ), + .rst_i( rst ), + .wb0s_data_i( wb0s_data_i ), + .wb0s_data_o( wb0s_data_o ), + .wb0_addr_i( wb0_addr_i ), + .wb0_sel_i( wb0_sel_i ), + .wb0_we_i( wb0_we_i ), + .wb0_cyc_i( wb0_cyc_i ), + .wb0_stb_i( wb0_stb_i ), + .wb0_ack_o( wb0_ack_o ), + .wb0_err_o( wb0_err_o ), + .wb0_rty_o( wb0_rty_o ), + .wb0m_data_i( wb0m_data_i ), + .wb0m_data_o( wb0m_data_o ), + .wb0_addr_o( wb0_addr_o ), + .wb0_sel_o( wb0_sel_o ), + .wb0_we_o( wb0_we_o ), + .wb0_cyc_o( wb0_cyc_o ), + .wb0_stb_o( wb0_stb_o ), + .wb0_ack_i( wb0_ack_i ), + .wb0_err_i( wb0_err_i ), + .wb0_rty_i( wb0_rty_i ), + .wb1s_data_i( wb1s_data_i ), + .wb1s_data_o( wb1s_data_o ), + .wb1_addr_i( wb1_addr_i ), + .wb1_sel_i( wb1_sel_i ), + .wb1_we_i( wb1_we_i ), + .wb1_cyc_i( wb1_cyc_i ), + .wb1_stb_i( wb1_stb_i ), + .wb1_ack_o( wb1_ack_o ), + .wb1_err_o( wb1_err_o ), + .wb1_rty_o( wb1_rty_o ), + .wb1m_data_i( wb1m_data_i ), + .wb1m_data_o( wb1m_data_o ), + .wb1_addr_o( wb1_addr_o ), + .wb1_sel_o( wb1_sel_o ), + .wb1_we_o( wb1_we_o ), + .wb1_cyc_o( wb1_cyc_o ), + .wb1_stb_o( wb1_stb_o ), + .wb1_ack_i( wb1_ack_i ), + .wb1_err_i( wb1_err_i ), + .wb1_rty_i( wb1_rty_i ), + .dma_req_i( req_i ), + .dma_ack_o( ack_o ), + .dma_nd_i( nd_i ), + .dma_rest_i( rest_i ), + .inta_o( inta_o ), + .intb_o( intb_o ) + ); + +wb_slv #(14) s0( + .clk( clk ), + .rst( ~rst ), + .adr( wb0_addr_o ), + .din( wb0s_data_o ), + .dout( wb0s_data_i ), + .cyc( wb0_cyc_o ), + .stb( wb0_stb_o ), + .sel( wb0_sel_o ), + .we( wb0_we_o ), + .ack( wb0_ack_i ), + .err( wb0_err_i ), + .rty( wb0_rty_i ) + ); + +wb_slv #(14) s1( + .clk( clk ), + .rst( ~rst ), + .adr( wb1_addr_o ), + .din( wb1s_data_o ), + .dout( wb1s_data_i ), + .cyc( wb1_cyc_o ), + .stb( wb1_stb_o ), + .sel( wb1_sel_o ), + .we( wb1_we_o ), + .ack( wb1_ack_i ), + .err( wb1_err_i ), + .rty( wb1_rty_i ) + ); + +wb_mast m0( + .clk( clk ), + .rst( ~rst ), + .adr( wb0_addr_i ), + .din( wb0m_data_o ), + .dout( wb0m_data_i ), + .cyc( wb0_cyc_i ), + .stb( wb0_stb_i ), + .sel( wb0_sel_i ), + .we( wb0_we_i ), + .ack( wb0_ack_o ), + .err( wb0_err_o ), + .rty( wb0_rty_o ) + ); + +wb_mast m1( + .clk( clk ), + .rst( ~rst ), + .adr( wb1_addr_i ), + .din( wb1m_data_o ), + .dout( wb1m_data_i ), + .cyc( wb1_cyc_i ), + .stb( wb1_stb_i ), + .sel( wb1_sel_i ), + .we( wb1_we_i ), + .ack( wb1_ack_o ), + .err( wb1_err_o ), + .rty( wb1_rty_o ) + ); + +`include "tests.v" + +endmodule + Index: wb_dma/trunk/bench/verilog/wb_model_defines.v =================================================================== --- wb_dma/trunk/bench/verilog/wb_model_defines.v (nonexistent) +++ wb_dma/trunk/bench/verilog/wb_model_defines.v (revision 17) @@ -0,0 +1,63 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Model Definitions //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/wb_dma/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: wb_model_defines.v,v 1.2 2002-02-01 01:55:44 rudi Exp $ +// +// $Date: 2002-02-01 01:55:44 $ +// $Revision: 1.2 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.1 2001/07/29 08:57:02 rudi +// +// +// 1) Changed Directory Structure +// 2) Added restart signal (REST) +// +// Revision 1.1.1.1 2001/03/19 13:12:48 rudi +// Initial Release +// +// +// + +`timescale 1ns / 10ps Index: wb_dma/trunk/bench/verilog/tests.v =================================================================== --- wb_dma/trunk/bench/verilog/tests.v (nonexistent) +++ wb_dma/trunk/bench/verilog/tests.v (revision 17) @@ -0,0 +1,2502 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// DMA Test Cases //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/wb_dma/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: tests.v,v 1.3 2001-09-07 15:34:36 rudi Exp $ +// +// $Date: 2001-09-07 15:34:36 $ +// $Revision: 1.3 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.2 2001/08/15 05:40:29 rudi +// +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// - Added Section 3.10, describing DMA restart. +// +// Revision 1.1 2001/07/29 08:57:02 rudi +// +// +// 1) Changed Directory Structure +// 2) Added restart signal (REST) +// +// Revision 1.1.1.1 2001/03/19 13:12:39 rudi +// Initial Release +// +// +// + +task sw_ext_desc1; +input quick; + +integer quick, tot_sz_max, chunk_sz_max, del_max; + +reg [7:0] mode; +reg [15:0] tot_sz; +reg [15:0] chunk_sz; +integer ii, n,del; +reg [31:0] int_src, d0, d1; + +begin +$display("\n\n"); +$display("*****************************************************"); +$display("*** SW DMA No Buffer Ext. Descr LL ... ***"); +$display("*****************************************************\n"); + +rst = 1; +repeat(10) @(posedge clk); +rst = 0; +repeat(10) @(posedge clk); + +if(quick) + begin + tot_sz_max = 32; + del_max = 2; + chunk_sz_max = 4; + end +else + begin + tot_sz_max = 128; + del_max = 6; + chunk_sz_max = 8; + end + + +mode = 1; +tot_sz = 64; +chunk_sz=3; +del = 0; + +for(del=0;del8) tot_sz = tot_sz + 2; +if(tot_sz>16) tot_sz = tot_sz + 2; +if(tot_sz>32) tot_sz = tot_sz + 12; + + +for(chunk_sz=0;chunk_sz0, "); + 1: $write("Mode: 0->1, "); + 2: $write("Mode: 1->0, "); + 3: $write("Mode: 1->1, "); + endcase + $display("Total Size: %0d, Chunk Size: %0d, Slave Delay: %0d", + tot_sz, chunk_sz, del); + + ack_cnt_clr = 1; + @(posedge clk); + ack_cnt_clr = 0; + + s0.delay = del; + s1.delay = del; + + s0.fill_mem(1); + s1.fill_mem(1); + + s0.mem[0] = (32'h000c_0000 | (mode[1:0]<<16)) + tot_sz; + s0.mem[1] = 32'h0000_0100; + s0.mem[2] = 32'h0000_0400; + s0.mem[3] = 32'h0000_0010; + + s0.mem[4] = (32'h001c_0000 | (mode[1:0]<<16)) + tot_sz; + s0.mem[5] = 32'h0000_0100 + (tot_sz * 4); + s0.mem[6] = 32'h0000_0400 + (tot_sz * 4); + s0.mem[7] = 32'h0000_0000; + + + s0.mem[8] = (32'h000c_0000 | (mode[1:0]<<16)) + tot_sz; + s0.mem[9] = 32'h0000_0800; + s0.mem[10] = 32'h0000_0c00; + s0.mem[11] = 32'h0000_0030; + + s0.mem[12] = (32'h001c_0000 | (mode[1:0]<<16)) + tot_sz; + s0.mem[13] = 32'h0000_0800 + (tot_sz * 4); + s0.mem[14] = 32'h0000_0c00 + (tot_sz * 4); + s0.mem[15] = 32'h0000_0000; + + + m0.wb_wr1(`REG_BASE + `INT_MASKA,4'hf,32'hffff_ffff); + + m0.wb_wr1(`REG_BASE + `PTR0, 4'hf, 32'h0000_0020); + m0.wb_wr1(`REG_BASE + `CH0_TXSZ,4'hf, {chunk_sz, 12'h0}); + m0.wb_wr1(`REG_BASE + `CH0_ADR0,4'hf,32'h0000_0080); + m0.wb_wr1(`REG_BASE + `CH0_ADR1,4'hf,32'h0000_4000); + + m0.wb_wr1(`REG_BASE + `CH0_CSR,4'hf, + {15'h0002, 3'b000, 1'b0, 6'h1, 4'b0011, 2'b00, 1'b1}); + + + m0.wb_wr1(`REG_BASE + `PTR1, 4'hf, 32'h0000_0000); + m0.wb_wr1(`REG_BASE + `CH1_TXSZ,4'hf, {chunk_sz, 12'h0}); + m0.wb_wr1(`REG_BASE + `CH1_ADR0,4'hf,32'h0000_0080); + m0.wb_wr1(`REG_BASE + `CH1_ADR1,4'hf,32'h0000_4000); + + m0.wb_wr1(`REG_BASE + `CH1_CSR,4'hf, + {15'h0002, 3'b000, 1'b0, 6'h1, 4'b0011, 2'b00, 1'b1}); + + +for(ii=0;ii<2;ii=ii+1) +begin + repeat(5) @(posedge clk); + while(!inta_o) @(posedge clk); + + m0.wb_rd1(`REG_BASE + `INT_SRCA, 4'hf, int_src); + + if(int_src[0]) + begin + for(n=0;n>2) + n ]; + else d0=s0.mem[(s0.mem[9]>>2) + n ]; + if(mode[0]) d1=s1.mem[(s0.mem[10]>>2) + n ]; + else d1=s0.mem[(s0.mem[10]>>2) + n ]; + + if( d1 !== d0 ) + begin + $display("ERROR: CH0: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)", + n, d0, d1, $time); + error_cnt = error_cnt + 1; + end + end + m0.wb_rd1(`REG_BASE + `CH0_CSR, 4'hf, d1); + d0 = {24'h0064_089, 1'b1, mode[1:0], 1'b0}; + if( d1 !== d0 ) + begin + $display("ERROR: CH0_CSR Mismatch: Expected: %x, Got: %x (%0t)", + d0, d1, $time); + error_cnt = error_cnt + 1; + end + end + + + if(int_src[1]) + begin + for(n=0;n>2) + n ]; + else d0=s0.mem[(s0.mem[1]>>2) + n ]; + if(mode[0]) d1=s1.mem[(s0.mem[2]>>2) + n ]; + else d1=s0.mem[(s0.mem[2]>>2) + n ]; + + if( d1 !== d0 ) + begin + $display("ERROR: CH1: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)", + n, d0, d1, $time); + error_cnt = error_cnt + 1; + end + end + m0.wb_rd1(`REG_BASE + `CH1_CSR, 4'hf, d1); + d0 = {24'h0064_089, 1'b1, mode[1:0], 1'b0}; + if( d1 !== d0 ) + begin + $display("ERROR: CH1_CSR Mismatch: Expected: %x, Got: %x (%0t)", + d0, d1, $time); + error_cnt = error_cnt + 1; + end + end + +end + + if(ack_cnt != ((tot_sz*4)+(4*2))*2 ) + begin + $display("ERROR: ACK count Mismatch: Expected: %0d, Got: %0d (%0t)", + ((tot_sz*4)+(4*2)), ack_cnt, $time); + error_cnt = error_cnt + 1; + end + + repeat(5) @(posedge clk); + +end +end + +show_errors; +$display("*****************************************************"); +$display("*** Test DONE ... ***"); +$display("*****************************************************\n\n"); +end + + +endtask + + + +task arb_test1; + +reg [7:0] mode; +reg [15:0] tot_sz; +reg [15:0] chunk_sz0; +reg [15:0] chunk_sz1; +reg [15:0] chunk_sz2; +reg [15:0] chunk_sz3; +integer a,n,ptr; +reg [31:0] d0,d1; +reg [7:0] pri, order, finish; + +begin +$display("\n\n"); +$display("*****************************************************"); +$display("*** SW DMA No Buffer 4 ch pri ... ***"); +$display("*****************************************************\n"); + +mode = 0; +tot_sz = 32; +chunk_sz0=4; +chunk_sz1=4; +chunk_sz2=4; +chunk_sz3=4; +a=0; + +m0.wb_wr1(`REG_BASE + `CH0_CSR,4'hf, 32'h0); +m0.wb_wr1(`REG_BASE + `CH1_CSR,4'hf, 32'h0); +m0.wb_wr1(`REG_BASE + `CH2_CSR,4'hf, 32'h0); +m0.wb_wr1(`REG_BASE + `CH3_CSR,4'hf, 32'h0); + +m0.wb_rd1(`REG_BASE + `INT_SRCA, 4'hf, d0); + +for(mode=0;mode<4;mode=mode+1) +for(a=0;a<17;a=a+1) +begin + + chunk_sz0=4; + chunk_sz1=4; + chunk_sz2=4; + chunk_sz3=4; + + s0.delay = 0; + s1.delay = 0; + + case(a) // ch3 ch2 ch1 ch0 + 0: + begin + pri = 8'b10_10_10_10; // All equal 0,1,2,3 + order = {2'd0, 2'd1, 2'd2, 2'd3}; + end + + // One channel with High Priority + // The other depend oon the ARB state + 1: + begin + pri = 8'b00_00_00_10; // 3,1,0,2 + order = {2'b0, 2'd3, 2'd1, 2'd2}; + end + 2: + begin + pri = 8'b00_00_10_00; // 2,3,0,1 + order = {2'd1, 2'd0, 2'd2, 2'd3}; + end + 3: + begin + pri = 8'b00_10_00_00; // 1,0,2,3 + order = {2'd2, 2'd0, 2'd1, 2'd3}; + end + 4: + begin + pri = 8'b10_00_00_00; // 0,3,1,2 + order = {2'd3, 2'd0, 2'd1, 2'd2}; + end + + // Specific order for all Channels + 5: + begin + pri = 8'b10_00_01_11; // 3,0,2,1 + order = {2'd0, 2'd3, 2'd1, 2'd2}; + end + + 6: + begin + pri = 8'b00_10_11_01; // 2,1,3,0 + order = {2'd1, 2'd2, 2'd0, 2'd3}; + end + + 7: + begin + pri = 8'b00_11_01_10; // 1,3,2,0 + order = {2'd2, 2'd0, 2'd1, 2'd3}; + end + + 8: + begin + pri = 8'b00_01_10_11; // 3,2,1,0 + order = {2'd0, 2'd1, 2'd2, 2'd3}; + end + + // One channel with High Priority + // The other depend oon the ARB state + // Chunk Size varies + // First channel small chunkc size + 9: + begin + pri = 8'b00_00_00_10; // 3,1,0,2 + order = {2'd0, 2'd1, 2'd2, 2'd3}; + chunk_sz3=1; + end + 10: + begin + pri = 8'b00_00_10_00; // 2,0,1,3 + order = {2'd1, 2'd0, 2'd3, 2'd2}; + chunk_sz2=1; + end + 11: + begin + pri = 8'b00_10_00_00; // 1,0,2,3 + order = {2'd2, 2'd0, 2'd3, 2'd1}; + chunk_sz1=1; + end + 12: + begin + pri = 8'b10_00_00_00; // 0,2,3,1 + order = {2'd3, 2'd1, 2'd2, 2'd0}; + chunk_sz0=1; + end + + // First channel large chunkc size + 13: + begin + pri = 8'b00_00_00_10; // 3,0,2,1 + order = {2'd0, 2'd3, 2'd1, 2'd2}; + chunk_sz3=8; + end + 14: + begin + pri = 8'b00_00_10_00; // 2,0,3,1 + order = {2'd1, 2'd2, 2'd0, 2'd3}; + chunk_sz2=8; + end + 15: + begin + pri = 8'b00_10_00_00; // 1,0,3,2 + order = {2'd2, 2'd1, 2'd0, 2'd3}; + chunk_sz1=8; + end + 16: + begin + pri = 8'b10_00_00_00; // 0,2,3,1 + order = {2'd3, 2'd0, 2'd1, 2'd2}; + chunk_sz0=8; + end + + endcase + +case(mode) + 0: $write("Mode: 0->0, "); + 1: $write("Mode: 0->1, "); + 2: $write("Mode: 1->0, "); + 3: $write("Mode: 1->1, "); +endcase +$display("a: %0d", a); + + ack_cnt_clr = 1; + @(posedge clk); + ack_cnt_clr = 0; + + s0.fill_mem(1); + s1.fill_mem(1); + + m0.wb_wr1(`REG_BASE + `CH0_CSR,4'hf, + {17'h00000, pri[1:0], 6'h0, 4'b0011, mode[1:0], 1'b0}); + + m0.wb_wr1(`REG_BASE + `CH1_CSR,4'hf, + {17'h00000, pri[3:2], 6'h0, 4'b0011, mode[1:0], 1'b0}); + + m0.wb_wr1(`REG_BASE + `CH2_CSR,4'hf, + {17'h00000, pri[5:4], 6'h0, 4'b0011, mode[1:0], 1'b0}); + + m0.wb_wr1(`REG_BASE + `CH3_CSR,4'hf, + {17'h00000, pri[7:6], 6'h0, 4'b0011, mode[1:0], 1'b0}); + + m0.wb_wr1(`REG_BASE + `INT_MASKA,4'hf,32'hffff_ffff); + + m0.wb_wr1(`REG_BASE + `CH0_TXSZ,4'hf, {chunk_sz0, tot_sz}); + m0.wb_wr1(`REG_BASE + `CH0_ADR0,4'hf,32'h0000_0000); + m0.wb_wr1(`REG_BASE + `CH0_ADR1,4'hf,32'h0000_4000); + + m0.wb_wr1(`REG_BASE + `CH1_TXSZ,4'hf, {chunk_sz1, tot_sz}); + m0.wb_wr1(`REG_BASE + `CH1_ADR0,4'hf,32'h0000_0080); + m0.wb_wr1(`REG_BASE + `CH1_ADR1,4'hf,32'h0000_4080); + + m0.wb_wr1(`REG_BASE + `CH2_TXSZ,4'hf, {chunk_sz2, tot_sz}); + m0.wb_wr1(`REG_BASE + `CH2_ADR0,4'hf,32'h0000_0100); + m0.wb_wr1(`REG_BASE + `CH2_ADR1,4'hf,32'h0000_4100); + + m0.wb_wr1(`REG_BASE + `CH3_TXSZ,4'hf, {chunk_sz3, tot_sz}); + m0.wb_wr1(`REG_BASE + `CH3_ADR0,4'hf,32'h0000_0180); + m0.wb_wr1(`REG_BASE + `CH3_ADR1,4'hf,32'h0000_4180); + + + m0.wb_wr1(`REG_BASE + `CH0_CSR,4'hf, + {12'h000, 3'b010, 1'b0, 1'b0, pri[1:0], 6'h0, 4'b0011, mode[1:0], 1'b1}); + + //{15'h0002, 3'b000, 1'b0, 6'h1, 4'b0011, 2'b00, 1'b1}); + + m0.wb_wr1(`REG_BASE + `CH1_CSR,4'hf, + {12'h000, 3'b010, 1'b0, 1'b0, pri[3:2], 6'h0, 4'b0011, mode[1:0], 1'b1}); + + m0.wb_wr1(`REG_BASE + `CH2_CSR,4'hf, + {12'h000, 3'b010, 1'b0, 1'b0, pri[5:4], 6'h0, 4'b0011, mode[1:0], 1'b1}); + + + + m0.wb_wr1(`REG_BASE + `CH3_CSR,4'hf, + {12'h0000, 3'b010, 1'b0, 1'b0, pri[7:6], 6'h0, 4'b0011, mode[1:0], 1'b1}); + + repeat(1) @(posedge clk); + + // Wait for interrupt, Check completion order + + ptr=0; + finish = 8'hxx; + + while(ptr!=4) + begin + while(!inta_o) @(posedge clk); + m0.wb_rd1(`REG_BASE + `INT_SRCA, 4'hf, d0); + + if(d0[0]) d0[1:0] = 0; + else + if(d0[1]) d0[1:0] = 1; + else + if(d0[2]) d0[1:0] = 2; + else + if(d0[3]) d0[1:0] = 3; + + case(ptr) + 0: finish[7:6] = d0[1:0]; + 1: finish[5:4] = d0[1:0]; + 2: finish[3:2] = d0[1:0]; + 3: finish[1:0] = d0[1:0]; + endcase + + case(d0[1:0]) + 0: m0.wb_rd1(`REG_BASE + `CH0_CSR, 4'hf, d0); + 1: m0.wb_rd1(`REG_BASE + `CH1_CSR, 4'hf, d0); + 2: m0.wb_rd1(`REG_BASE + `CH2_CSR, 4'hf, d0); + 3: m0.wb_rd1(`REG_BASE + `CH3_CSR, 4'hf, d0); + endcase + + ptr=ptr+1; + repeat(4) @(posedge clk); + end + + + if(finish !== order) + begin + $display("ERROR: Completion Order[%0d] Mismatch: Expected: %b, Got: %b (%0t)", + a, order, finish, $time); + error_cnt = error_cnt + 1; + end + + + for(n=0;n0, chunk_size: %0d", chunk_sz); + 1: $display("Mode: 0->1, chunk_size: %0d", chunk_sz); + 2: $display("Mode: 1->0, chunk_size: %0d", chunk_sz); + 3: $display("Mode: 1->1, chunk_size: %0d", chunk_sz); +endcase + +for(rep=0;rep<4;rep=rep+1) + begin + ack_cnt_clr = 1; + @(posedge clk); + ack_cnt_clr = 0; + + if(del==4) del = 10; + + s0.delay = del; + s1.delay = del; + + if(chunk_sz==0) k = 1; + else + begin + k = tot_sz/chunk_sz; + if((k*chunk_sz) != tot_sz) k = k + 1; + end + + s0.fill_mem(1); + s1.fill_mem(1); + + fork + begin + + for(m=0;m < k;m=m+1) + begin + repeat(del) @(posedge clk); + #1; + req_i[0] = 1; + while(!ack_o[0]) @(posedge clk); + #1; + req_i[0] = 0; + end + + end + + begin + repeat(1) @(posedge clk); + while(!u0.dma_done_all) @(posedge clk); + +/* + repeat(5) @(posedge clk); + while(!inta_o) @(posedge clk); + + m0.wb_rd1(`REG_BASE + `INT_SRCA, 4'hf, d1); + d0 = 32'h0000_0002; + if( d1 !== d0 ) + begin + $display("ERROR: INT_SRC Mismatch: Expected: %x, Got: %x (%0t)", + d0, d1, $time); + error_cnt = error_cnt + 1; + end + + m0.wb_rd1(`REG_BASE + `CH0_CSR, 4'hf, d1); + d0 = {24'h0000_081, 1'b1, mode[1:0], 1'b0}; + if( d1 !== d0 ) + begin + $display("ERROR: CH0_CSR Mismatch: Expected: %x, Got: %x (%0t)", + d0, d1, $time); + error_cnt = error_cnt + 1; + end +*/ + + + for(n=0;n4) tot_sz = tot_sz + 4; +if(tot_sz>16) tot_sz = tot_sz + 12; +if(tot_sz>64) tot_sz = tot_sz + 48; + +for(del=0;del0, chunk_size: %0d", chunk_sz); + 1: $display("Mode: 0->1, chunk_size: %0d", chunk_sz); + 2: $display("Mode: 1->0, chunk_size: %0d", chunk_sz); + 3: $display("Mode: 1->1, chunk_size: %0d", chunk_sz); + endcase + + ack_cnt_clr = 1; + @(posedge clk); + ack_cnt_clr = 0; + + if(chunk_sz==0) k = 1; + else + begin + k = tot_sz/chunk_sz; + if((k*chunk_sz) != tot_sz) k = k + 1; + end + + k = k * 2; + + fork + begin + repeat(5) @(posedge clk); + for(m0=0;m0 < k;m0=m0+1) + begin + repeat(del) @(posedge clk); + #1; + req_i[0] = 1; + while(!ack_o[0]) @(posedge clk); + #1; + req_i[0] = 0; + end + end + + begin + repeat(5) @(posedge clk); + for(m1=0;m1 < k;m1=m1+1) + begin + repeat(del) @(posedge clk); + #1; + req_i[1] = 1; + while(!ack_o[1]) @(posedge clk); + #1; + req_i[1] = 0; + end + end + + begin + repeat(5) @(posedge clk); + for(m2=0;m2 < k;m2=m2+1) + begin + repeat(del) @(posedge clk); + #1; + req_i[2] = 1; + while(!ack_o[2]) @(posedge clk); + #1; + req_i[2] = 0; + end + end + + begin + repeat(5) @(posedge clk); + for(m3=0;m3 < k;m3=m3+1) + begin + repeat(del) @(posedge clk); + #1; + req_i[3] = 1; + while(!ack_o[3]) @(posedge clk); + #1; + req_i[3] = 0; + end + end + + for(i=0;i<4;i=i) + begin + repeat(5) @(posedge clk); + while(!inta_o) @(posedge clk); + m0.wb_rd1(`REG_BASE + `INT_SRCA, 4'hf, int_src); + + if(int_src[0]) + begin + m0.wb_rd1(`REG_BASE + `CH0_CSR, 4'hf, d0); + i=i+1; + for(n=0;n>2) + n ]; + else d0=s0.mem[(s0.mem[1]>>2) + n ]; + if(mode[0]) d1=s1.mem[(s0.mem[2]>>2) + n ]; + else d1=s0.mem[(s0.mem[2]>>2) + n ]; + + if( d1 !== d0 ) + begin + $display("ERROR: CH0: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)", + n, d0, d1, $time); + error_cnt = error_cnt + 1; + end + end + end + + if(int_src[1]) + begin + m0.wb_rd1(`REG_BASE + `CH1_CSR, 4'hf, d0); + i=i+1; + for(n=0;n>2) + n ]; + else d0=s0.mem[(s0.mem[9]>>2) + n ]; + if(mode[0]) d1=s1.mem[(s0.mem[10]>>2) + n ]; + else d1=s0.mem[(s0.mem[10]>>2) + n ]; + + if( d1 !== d0 ) + begin + $display("ERROR: CH1: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)", + n, d0, d1, $time); + error_cnt = error_cnt + 1; + end + end + end + + if(int_src[2]) + begin + m0.wb_rd1(`REG_BASE + `CH2_CSR, 4'hf, d0); + i=i+1; + for(n=0;n>2) + n ]; + else d0=s0.mem[(s0.mem[17]>>2) + n ]; + if(mode[0]) d1=s1.mem[(s0.mem[18]>>2) + n ]; + else d1=s0.mem[(s0.mem[18]>>2) + n ]; + + if( d1 !== d0 ) + begin + $display("ERROR: CH2: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)", + n, d0, d1, $time); + error_cnt = error_cnt + 1; + end + end + end + + if(int_src[3]) + begin + m0.wb_rd1(`REG_BASE + `CH3_CSR, 4'hf, d0); + i=i+1; + for(n=0;n>2) + n ]; + else d0=s0.mem[(s0.mem[25]>>2) + n ]; + if(mode[0]) d1=s1.mem[(s0.mem[26]>>2) + n ]; + else d1=s0.mem[(s0.mem[26]>>2) + n ]; + + if( d1 !== d0 ) + begin + $display("ERROR: CH3: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)", + n, d0, d1, $time); + error_cnt = error_cnt + 1; + end + end + end + + end + + join + + + if(ack_cnt != ((tot_sz*2*4*2)+(4*4*2)) ) + begin + $display("ERROR: ACK count Mismatch: Expected: %0d, Got: %0d (%0t)", + ((tot_sz*2*4*2)+(4*4*2)), ack_cnt, $time); + error_cnt = error_cnt + 1; + end + + repeat(5) @(posedge clk); + +end +end + + s0.delay = 0; + s1.delay = 0; + +show_errors; +$display("*****************************************************"); +$display("*** Test DONE ... ***"); +$display("*****************************************************\n\n"); +end + +endtask + + + + + + +task hw_dma3; +input quick; + +integer quick, tot_sz_max, chunk_sz_max, del_max; + +reg [7:0] mode; +reg [15:0] chunk_sz, tot_sz; +integer odd, i, iz, n,m0, m1, m2, m3, k, k1, rep,del; +reg [31:0] int_src, d0,d1; + +begin +$display("\n\n"); +$display("*****************************************************"); +$display("*** HW DMA Ext Descr. 4 Channels ND Test ... ***"); +$display("*****************************************************\n"); + +case(quick) + default: + begin + del_max = 6; + chunk_sz_max = 8; + end + 1: + begin + del_max = 4; + chunk_sz_max = 4; + end + 2: + begin + del_max = 3; + chunk_sz_max = 4; + end +endcase + +mode = 0; +tot_sz = 64; +chunk_sz=4; +del = 0; + +m0.wb_wr1(`REG_BASE + `CH0_CSR,4'hf, 32'h0); +m0.wb_wr1(`REG_BASE + `CH1_CSR,4'hf, 32'h0); +m0.wb_wr1(`REG_BASE + `CH2_CSR,4'hf, 32'h0); +m0.wb_wr1(`REG_BASE + `CH3_CSR,4'hf, 32'h0); + +m0.wb_rd1(`REG_BASE + `INT_SRCA, 4'hf, int_src); + + +for(del=0;del0, chunk_size: %0d", chunk_sz); + 1: $display("Mode: 0->1, chunk_size: %0d", chunk_sz); + 2: $display("Mode: 1->0, chunk_size: %0d", chunk_sz); + 3: $display("Mode: 1->1, chunk_size: %0d", chunk_sz); + endcase + + ack_cnt_clr = 1; + @(posedge clk); + ack_cnt_clr = 0; + + if(chunk_sz==0) k = 1; + else + begin + k = tot_sz/chunk_sz; + if((k*chunk_sz) != tot_sz) k = k + 1; + if((k*chunk_sz) != tot_sz) odd = 1; + else odd = 0; + end + + if(chunk_sz==0) k1 = 4; + else + begin + k1 = tot_sz/chunk_sz; + if((k1*chunk_sz) != tot_sz) k1 = k1 + 1; + k1 = k1 * 4; + end + + k1 = k * 4; + iz = k; + + fork + begin + repeat(5) @(posedge clk); + for(m0=0;m0 < k1+1;m0=m0+1) + begin + repeat(del) @(posedge clk); + #1; + + if(m0==iz) nd_i[0] = 1; + else + if(m0==(iz*2)) nd_i[0] = 1; + else + if(m0==(iz*3)) nd_i[0] = 1; + else + if(m0==(iz*4)) nd_i[0] = 1; + else req_i[0] = 1; + + if(nd_i[0]==1) + begin + @(posedge clk); + #1; + nd_i[0] = 0; + repeat(1) @(posedge clk); + #1; + req_i[0] = 1; + end + + while(!ack_o[0] & (m0 < k1)) @(posedge clk); + #1; + req_i[0] = 0; + nd_i[0] = 0; + end + end + + begin + repeat(5) @(posedge clk); + for(m1=0;m1 < k1;m1=m1+1) + begin + repeat(del) @(posedge clk); + #1; + if(m1==k-1) nd_i[1] = 1; + if(m1==(k*2)-1) nd_i[1] = 1; + if(m1==(k*3)-1) nd_i[1] = 1; + if(m1==(k*4)-1) nd_i[1] = 1; + req_i[1] = 1; + while(!ack_o[1]) @(posedge clk); + #1; + req_i[1] = 0; + nd_i[1] = 0; + end + end + + begin + repeat(5) @(posedge clk); + for(m2=0;m2 < k1+1;m2=m2+1) + begin + repeat(del) @(posedge clk); + #1; + + if(m2==k) nd_i[2] = 1; + else + if(m2==(k*2)) nd_i[2] = 1; + else + if(m2==(k*3)) nd_i[2] = 1; + else + if(m2==(k*4)) nd_i[2] = 1; + else req_i[2] = 1; + + if(nd_i[2]==1) + begin + @(posedge clk); + #1; + nd_i[2] = 0; + repeat(1) @(posedge clk); + #1; + req_i[2] = 1; + end + + while(!ack_o[2] & (m2 < k1)) @(posedge clk); + #1; + req_i[2] = 0; + nd_i[2] = 0; + end + end + + + begin + repeat(5) @(posedge clk); + for(m3=0;m3 < k1;m3=m3+1) + begin + repeat(del) @(posedge clk); + #1; + if(m3==k-1) nd_i[3] = 1; + if(m3==(k*2)-1) nd_i[3] = 1; + if(m3==(k*3)-1) nd_i[3] = 1; + if(m3==(k*4)-1) nd_i[3] = 1; + req_i[3] = 1; + while(!ack_o[3]) @(posedge clk); + #1; + req_i[3] = 0; + nd_i[3] = 0; + end + end + + + for(i=0;i<4;i=i) + begin + repeat(5) @(posedge clk); + while(!inta_o) @(posedge clk); + m0.wb_rd1(`REG_BASE + `INT_SRCA, 4'hf, int_src); + + if(int_src[0]) + begin + i=i+1; + for(n=0;n>2) + n ]; + else d0=s0.mem[(s0.mem[1]>>2) + n ]; + if(mode[0]) d1=s1.mem[(s0.mem[2]>>2) + n ]; + else d1=s0.mem[(s0.mem[2]>>2) + n ]; + + if( d1 !== d0 ) + begin + $display("ERROR: CH0: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)", + n, d0, d1, $time); + error_cnt = error_cnt + 1; + end + end + repeat(1) @(posedge clk); + d1 = {28'h0064_09b, 1'b1, mode[1:0], 1'b0}; + m0.wb_rd1(`REG_BASE + `CH0_CSR, 4'hf, d0); + repeat(1) @(posedge clk); + if( d1 !== d0 ) + begin + $display("ERROR: CH0: CSR Mismatch: Expected: %x, Got: %x (%0t)", + d1, d0, $time); + error_cnt = error_cnt + 1; + end + end + + if(int_src[1]) + begin + i=i+1; + for(n=0;n>2) + n ]; + else d0=s0.mem[(s0.mem[17]>>2) + n ]; + if(mode[0]) d1=s1.mem[(s0.mem[18]>>2) + n ]; + else d1=s0.mem[(s0.mem[18]>>2) + n ]; + + if( d1 !== d0 ) + begin + $display("ERROR: CH1: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)", + n, d0, d1, $time); + error_cnt = error_cnt + 1; + end + end + repeat(1) @(posedge clk); + d1 = {28'h0064_09b, 1'b1, mode[1:0], 1'b0}; + m0.wb_rd1(`REG_BASE + `CH1_CSR, 4'hf, d0); + repeat(1) @(posedge clk); + if( d1 !== d0 ) + begin + $display("ERROR: CH1: CSR Mismatch: Expected: %x, Got: %x (%0t)", + d1, d0, $time); + error_cnt = error_cnt + 1; + end + repeat(1) @(posedge clk); + case(chunk_sz) + default: d1 = 32'h0000_00c0; + 3: d1 = 32'h0000_00be; + 5: d1 = 32'h0000_00bf; + 6: d1 = 32'h0000_00be; + 7: d1 = 32'h0000_00ba; + endcase + d0 = s0.mem[16]; + repeat(1) @(posedge clk); + if( d1 !== d0 ) + begin + $display("ERROR: CH1: DESC_CSR Mismatch: Expected: %x, Got: %x (%0t)", + d1, d0, $time); + error_cnt = error_cnt + 1; + end + end + + if(int_src[2]) + begin + i=i+1; + for(n=0;n>2) + n ]; + else d0=s0.mem[(s0.mem[33]>>2) + n ]; + if(mode[0]) d1=s1.mem[(s0.mem[34]>>2) + n ]; + else d1=s0.mem[(s0.mem[34]>>2) + n ]; + + if( d1 !== d0 ) + begin + $display("ERROR: CH2: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)", + n, d0, d1, $time); + error_cnt = error_cnt + 1; + end + end + repeat(1) @(posedge clk); + d1 = {28'h0064_09b, 1'b1, mode[1:0], 1'b0}; + m0.wb_rd1(`REG_BASE + `CH2_CSR, 4'hf, d0); + repeat(1) @(posedge clk); + if( d1 !== d0 ) + begin + $display("ERROR: CH2: CSR Mismatch: Expected: %x, Got: %x (%0t)", + d1, d0, $time); + error_cnt = error_cnt + 1; + end + end + + if(int_src[3]) + begin + i=i+1; + for(n=0;n>2) + n ]; + else d0=s0.mem[(s0.mem[49]>>2) + n ]; + if(mode[0]) d1=s1.mem[(s0.mem[50]>>2) + n ]; + else d1=s0.mem[(s0.mem[50]>>2) + n ]; + + if( d1 !== d0 ) + begin + $display("ERROR: CH3: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)", + n, d0, d1, $time); + error_cnt = error_cnt + 1; + end + end + repeat(1) @(posedge clk); + d1 = {28'h0064_09b, 1'b1, mode[1:0], 1'b0}; + m0.wb_rd1(`REG_BASE + `CH3_CSR, 4'hf, d0); + repeat(1) @(posedge clk); + if( d1 !== d0 ) + begin + $display("ERROR: CH3: CSR Mismatch: Expected: %x, Got: %x (%0t)", + d1, d0, $time); + error_cnt = error_cnt + 1; + end + repeat(1) @(posedge clk); + case(chunk_sz) + default: d1 = 32'h0000_00c0; + 3: d1 = 32'h0000_00be; + 5: d1 = 32'h0000_00bf; + 6: d1 = 32'h0000_00be; + 7: d1 = 32'h0000_00ba; + endcase + d0 = s0.mem[48]; + repeat(1) @(posedge clk); + if( d1 !== d0 ) + begin + $display("ERROR: CH3: DESC_CSR Mismatch: Expected: %x, Got: %x (%0t)", + d1, d0, $time); + error_cnt = error_cnt + 1; + end + + end + + end + join + + // CH0: 528 Acks + // CH1: 532 Acks + // CH2: 528 Acks + // CH3: 532 Acks + + case(chunk_sz) + default: k = 2120; + 3: k = 2184; + 5: k = 2152; + 6: k = 2184; + 7: k = 2312; + endcase + + if(ack_cnt != k ) + begin + $display("ERROR: ACK count Mismatch: Expected: %0d, Got: %0d (%0t)", + k, ack_cnt, $time); + error_cnt = error_cnt + 1; + end + + repeat(5) @(posedge clk); + +end + +s0.delay = 0; +s1.delay = 0; + +show_errors; +$display("*****************************************************"); +$display("*** Test DONE ... ***"); +$display("*****************************************************\n\n"); +end + +endtask + + + + + +task sw_dma1; +input quick; + +integer quick, tot_sz_max, chunk_sz_max; +reg [7:0] mode; +reg [15:0] chunk_sz, tot_sz; +integer n; +reg [31:0] d0,d1; + +begin +$display("\n\n"); +$display("*****************************************************"); +$display("*** SW DMA No Buffer (tx & chunk size test) ... ***"); +$display("*****************************************************\n"); + +case(quick) + default: + begin + tot_sz_max = 1024; + chunk_sz_max = 256; + end + 1: + begin + tot_sz_max = 128; + chunk_sz_max = 64; + end + 2: + begin + tot_sz_max = 32; + chunk_sz_max = 4; + end +endcase + +mode = 1; +tot_sz = 2048; +tot_sz = 16; +chunk_sz=4; + +for(mode=0;mode<4;mode=mode+1) +for(tot_sz=1;tot_sz64) tot_sz=tot_sz+4; +if(tot_sz>128) tot_sz=tot_sz+12; +case(mode) + 0: $display("Mode: 0->0, tot_size: %0d", tot_sz); + 1: $display("Mode: 0->1, tot_size: %0d", tot_sz); + 2: $display("Mode: 1->0, tot_size: %0d", tot_sz); + 3: $display("Mode: 1->1, tot_size: %0d", tot_sz); +endcase + +for(chunk_sz=0;chunk_sz128) tot_sz=tot_sz+4; + +$write("Slv 0 delay: %0d, Slv 1 Delay: %0d - ",del0, del1); +case(mode) + 0: $display("Mode: 0->0, tot_size: %0d", tot_sz); + 1: $display("Mode: 0->1, tot_size: %0d", tot_sz); + 2: $display("Mode: 1->0, tot_size: %0d", tot_sz); + 3: $display("Mode: 1->1, tot_size: %0d", tot_sz); +endcase + +for(chunk_sz=0;chunk_sz 4)) chunk_sz = chunk_sz + 1; + + s0.delay = del0; + s1.delay = del1; + + ack_cnt_clr = 1; + @(posedge clk); + ack_cnt_clr = 0; + + s0.fill_mem(1); + s1.fill_mem(1); + m0.wb_wr1(`REG_BASE + `INT_MASKB,4'hf,32'hffff_ffff); + m0.wb_wr1(`REG_BASE + `CH0_TXSZ,4'hf, {chunk_sz, tot_sz}); + m0.wb_wr1(`REG_BASE + `CH0_ADR0,4'hf,32'h0000_0000); + m0.wb_wr1(`REG_BASE + `CH0_ADR1,4'hf,32'h0000_4000); + m0.wb_wr1(`REG_BASE + `CH0_CSR,4'hf, + {12'h0000, 3'b010, 1'b0, 11'h000, 2'b11, mode[1:0], 1'b1}); + + repeat(5) @(posedge clk); + while(!intb_o) @(posedge clk); + + m0.wb_rd1(`REG_BASE + `INT_SRCB, 4'hf, d1); + d0 = 32'h0000_0001; + if( d1 !== d0 ) + begin + $display("ERROR: INT_SRC Mismatch: Expected: %x, Got: %x (%0t)", + d0, d1, $time); + error_cnt = error_cnt + 1; + end + + m0.wb_rd1(`REG_BASE + `CH0_CSR, 4'hf, d1); + d0 = {24'h0064_081, 1'b1, mode[1:0], 1'b0}; + if( d1 !== d0 ) + begin + $display("ERROR: CH0_CSR Mismatch: Expected: %x, Got: %x (%0t)", + d0, d1, $time); + error_cnt = error_cnt + 1; + end + + for(n=0;n0 Read Test .... ***"); +$display("*****************************************************\n"); + +s0.fill_mem(1); +s1.fill_mem(1); +d=0; +n=16; + +for(d=0;d<16;d=d+1) + begin + $display("INFO: PT10 RD4, delay %0d",d); + for(n=0;n<512;n=n+4) + begin + m0.wb_rd4(n<<2,4'hf,d,d0,d1,d2,d3); + + if( (s1.mem[n+0] !== d0) | (s1.mem[n+1] !== d1) | + (s1.mem[n+2] !== d2) | (s1.mem[n+3] !== d3) ) + begin + $display("ERROR: Memory Read Data (%0d) Mismatch: (%0t)",n,$time); + $display("D0: Expected: %x, Got %x", s1.mem[n+0], d0); + $display("D1: Expected: %x, Got %x", s1.mem[n+1], d1); + $display("D2: Expected: %x, Got %x", s1.mem[n+2], d2); + $display("D3: Expected: %x, Got %x", s1.mem[n+3], d3); + error_cnt = error_cnt + 1; + end + end + end + + +$display("\nINFO: PT10 RD1"); + for(n=0;n<512;n=n+1) + begin + m0.wb_rd1(n<<2,4'hf,d0); + + if( s1.mem[n] !== d0 ) + begin + $display("ERROR: Memory Read Data (%0d) Mismatch: (%0t)",n,$time); + $display("D0: Expected: %x, Got %x", s1.mem[n], d0); + error_cnt = error_cnt + 1; + end + end + + +show_errors; +$display("*****************************************************"); +$display("*** Test DONE ... ***"); +$display("*****************************************************\n"); +end +endtask + + +task pt01_rd; + +// Misc Variables +reg [31:0] d0,d1,d2,d3; +integer d,n; + +begin +$display("\n"); +$display("*****************************************************"); +$display("*** Running Path Through 0->1 Read Test .... ***"); +$display("*****************************************************\n"); + +s0.fill_mem(1); +s1.fill_mem(1); + +d=1; +n=0; +for(d=0;d<16;d=d+1) + begin + $display("INFO: PT01 RD4, delay %0d",d); + for(n=0;n<512;n=n+4) + begin + m1.wb_rd4(n<<2,4'hf,d,d0,d1,d2,d3); + @(posedge clk); + + if( (s0.mem[n+0] !== d0) | (s0.mem[n+1] !== d1) | + (s0.mem[n+2] !== d2) | (s0.mem[n+3] !== d3) ) + begin + $display("ERROR: Memory Read Data (%0d) Mismatch: (%0t)",n,$time); + $display("D0: Expected: %x, Got %x", s0.mem[n+0], d0); + $display("D1: Expected: %x, Got %x", s0.mem[n+1], d1); + $display("D2: Expected: %x, Got %x", s0.mem[n+2], d2); + $display("D3: Expected: %x, Got %x", s0.mem[n+3], d3); + error_cnt = error_cnt + 1; + end + end + end + +$display("\nINFO: PT01 RD1"); + for(n=0;n<512;n=n+1) + begin + m1.wb_rd1(n<<2,4'hf,d0); + + if( s0.mem[n+0] !== d0 ) + begin + $display("ERROR: Memory Read Data (%0d) Mismatch: (%0t)",n,$time); + $display("D0: Expected: %x, Got %x", s0.mem[n+0], d0); + error_cnt = error_cnt + 1; + end + end + +show_errors; +$display("*****************************************************"); +$display("*** Test DONE ... ***"); +$display("*****************************************************\n"); +end +endtask + + + + +task pt10_wr; + +// Misc Variables +reg [31:0] d0,d1,d2,d3; +integer d,n; + +begin + +$display("\n"); +$display("*****************************************************"); +$display("*** Running Path Through 1->0 Write Test .... ***"); +$display("*****************************************************\n"); + + +s0.fill_mem(1); +s1.fill_mem(1); +d=1; +n=0; +for(d=0;d<16;d=d+1) + begin + $display("INFO: PT10 WR4, delay %0d",d); + for(n=0;n<512;n=n+4) + begin + + d0 = $random; + d1 = $random; + d2 = $random; + d3 = $random; + m0.wb_wr4(n<<2,4'hf,d,d0,d1,d2,d3); + @(posedge clk); + + if( (s1.mem[n+0] !== d0) | (s1.mem[n+1] !== d1) | + (s1.mem[n+2] !== d2) | (s1.mem[n+3] !== d3) ) + begin + $display("ERROR: Memory Write Data (%0d) Mismatch: (%0t)",n,$time); + $display("D0: Expected: %x, Got %x", s1.mem[n+0], d0); + $display("D1: Expected: %x, Got %x", s1.mem[n+1], d1); + $display("D2: Expected: %x, Got %x", s1.mem[n+2], d2); + $display("D3: Expected: %x, Got %x", s1.mem[n+3], d3); + error_cnt = error_cnt + 1; + end + end + end + +$display("\nINFO: PT10 WR1"); + for(n=0;n<512;n=n+1) + begin + d0 = $random; + m0.wb_wr1(n<<2,4'hf,d0); + @(posedge clk); + + if( s1.mem[n+0] !== d0 ) + begin + $display("ERROR: Memory Write Data (%0d) Mismatch: (%0t)",n,$time); + $display("D0: Expected: %x, Got %x", s1.mem[n+0], d0); + error_cnt = error_cnt + 1; + end + end + +show_errors; +$display("*****************************************************"); +$display("*** Test DONE ... ***"); +$display("*****************************************************\n"); +end +endtask + + + +task pt01_wr; + +// Misc Variables +reg [31:0] d0,d1,d2,d3; +integer d,n; + +begin + +$display("\n"); +$display("*****************************************************"); +$display("*** Running Path Through 0->1 Write Test .... ***"); +$display("*****************************************************\n"); + + +s0.fill_mem(1); +s1.fill_mem(1); + +d=1; +n=0; +for(d=0;d<16;d=d+1) + begin + $display("INFO: PT01 WR4, delay %0d",d); + for(n=0;n<512;n=n+4) + begin + + d0 = $random; + d1 = $random; + d2 = $random; + d3 = $random; + m1.wb_wr4(n<<2,4'hf,d,d0,d1,d2,d3); + @(posedge clk); + + if( (s0.mem[n+0] !== d0) | (s0.mem[n+1] !== d1) | + (s0.mem[n+2] !== d2) | (s0.mem[n+3] !== d3) ) + begin + $display("ERROR: Memory Write Data (%0d) Mismatch: (%0t)",n,$time); + $display("D0: Expected: %x, Got %x", s0.mem[n+0], d0); + $display("D1: Expected: %x, Got %x", s0.mem[n+1], d1); + $display("D2: Expected: %x, Got %x", s0.mem[n+2], d2); + $display("D3: Expected: %x, Got %x", s0.mem[n+3], d3); + error_cnt = error_cnt + 1; + end + end + end + + $display("\nINFO: PT01 WR1"); + for(n=0;n<512;n=n+1) + begin + d0 = $random; + m1.wb_wr1(n<<2,4'hf,d0); + @(posedge clk); + + if( s0.mem[n+0] !== d0 ) + begin + $display("ERROR: Memory Write Data (%0d) Mismatch: (%0t)",n,$time); + $display("D0: Expected: %x, Got %x", s0.mem[n+0], d0); + error_cnt = error_cnt + 1; + end + end + +show_errors; +$display("*****************************************************"); +$display("*** Test DONE ... ***"); +$display("*****************************************************\n"); +end +endtask + + + + + + + +task show_errors; + +begin + +$display("\n"); +$display(" +--------------------+"); +$display(" | Total ERRORS: %0d |", error_cnt); +$display(" +--------------------+"); + +end +endtask + + + +task hw_dma4; +input quick; + +integer quick, tot_sz_max, chunk_sz_max, del_max; + +reg [7:0] mode; +reg [15:0] chunk_sz, tot_sz; +integer i, n,m0, m1, m2, m3, k,rep,del; +reg [31:0] int_src, d0,d1; +reg do_rest; +integer rest_del; +integer rest_del_t; + +begin +$display("\n\n"); +$display("*****************************************************"); +$display("*** HW DMA No Buffer Ext Descr. REST Test ... ***"); +$display("*****************************************************\n"); + +case(quick) + default: + begin + del_max = 6; + tot_sz_max = 200; + chunk_sz_max = 8; + end + 1: + begin + del_max = 4; + tot_sz_max = 128; + chunk_sz_max = 4; + end + 2: + begin + del_max = 3; + tot_sz_max = 32; + chunk_sz_max = 4; + end +endcase + +mode = 1; +tot_sz = 32; +chunk_sz=7; +del = 0; +do_rest = 1; +rest_del = 7; + + m0.wb_wr1(`REG_BASE + `CH0_CSR,4'hf, 32'h0); + m0.wb_wr1(`REG_BASE + `CH1_CSR,4'hf, 32'h0); + m0.wb_wr1(`REG_BASE + `CH2_CSR,4'hf, 32'h0); + m0.wb_wr1(`REG_BASE + `CH3_CSR,4'hf, 32'h0); + + m0.wb_rd1(`REG_BASE + `INT_SRCA, 4'hf, int_src); + +for(tot_sz=1;tot_sz4) tot_sz = tot_sz + 4; +if(tot_sz>16) tot_sz = tot_sz + 12; +if(tot_sz>64) tot_sz = tot_sz + 48; + +for(del=0;del= k) rest_del_t = k - 1; + else rest_del_t = rest_del; + + k = k * 2; + + + $write("Total Size: %0d, Delay: %0d REST_del: %0d ",tot_sz, del, rest_del_t); + case(mode) + 0: $display("Mode: 0->0, chunk_size: %0d", chunk_sz); + 1: $display("Mode: 0->1, chunk_size: %0d", chunk_sz); + 2: $display("Mode: 1->0, chunk_size: %0d", chunk_sz); + 3: $display("Mode: 1->1, chunk_size: %0d", chunk_sz); + endcase + + + +//$display("k=%0d",k); + + fork + begin // Hardware Handshake Channel 0 + repeat(5) @(posedge clk); + for(m0=0;m0 < k;m0=m0+1) + begin + repeat(del) @(posedge clk); + #1; + req_i[0] = 1; + while(!ack_o[0]) @(posedge clk); + #1; + req_i[0] = 0; + end + end + + begin // Hardware Handshake Channel 1 + repeat(5) @(posedge clk); + for(m1=0;m1 < (k + rest_del_t + 1);m1=m1+1) + begin + repeat(del) @(posedge clk); + #1; + req_i[1] = 1; + while(!ack_o[1]) @(posedge clk); + #1; + req_i[1] = 0; +//$display("m1=%0d",m1); + if( (do_rest==1) & (m1==rest_del_t) ) + //if( do_rest==1 ) + begin +//$display("Asserting Restart ..."); + @(posedge clk); + #1; + rest_i[1] = 1; + @(posedge clk); + #1; + rest_i[1] = 0; + do_rest = 0; + @(posedge clk); + @(posedge clk); + end + + end + end + + begin // Hardware Handshake Channel 2 + repeat(5) @(posedge clk); + for(m2=0;m2 < k;m2=m2+1) + begin + repeat(del) @(posedge clk); + #1; + req_i[2] = 1; + while(!ack_o[2]) @(posedge clk); + #1; + req_i[2] = 0; + end + end + + begin // Hardware Handshake Channel 3 + repeat(5) @(posedge clk); + for(m3=0;m3 < k;m3=m3+1) + begin + repeat(del) @(posedge clk); + #1; + req_i[3] = 1; + while(!ack_o[3]) @(posedge clk); + #1; + req_i[3] = 0; + end + end + + for(i=0;i<4;i=i) + begin + repeat(5) @(posedge clk); + while(!inta_o) @(posedge clk); + m0.wb_rd1(`REG_BASE + `INT_SRCA, 4'hf, int_src); + + if(int_src[0]) + begin + m0.wb_rd1(`REG_BASE + `CH0_CSR, 4'hf, d0); + i=i+1; + for(n=0;n>2) + n ]; + else d0=s0.mem[(s0.mem[1]>>2) + n ]; + if(mode[0]) d1=s1.mem[(s0.mem[2]>>2) + n ]; + else d1=s0.mem[(s0.mem[2]>>2) + n ]; + + if( d1 !== d0 ) + begin + $display("ERROR: CH0: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)", + n, d0, d1, $time); + error_cnt = error_cnt + 1; + end + end + end + + if(int_src[1]) + begin + m0.wb_rd1(`REG_BASE + `CH1_CSR, 4'hf, d0); + i=i+1; + for(n=0;n>2) + n ]; + else d0=s0.mem[(s0.mem[9]>>2) + n ]; + if(mode[0]) d1=s1.mem[(s0.mem[10]>>2) + n ]; + else d1=s0.mem[(s0.mem[10]>>2) + n ]; + + if( d1 !== d0 ) + begin + $display("ERROR: CH1: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)", + n, d0, d1, $time); + error_cnt = error_cnt + 1; + end + end + end + + if(int_src[2]) + begin + m0.wb_rd1(`REG_BASE + `CH2_CSR, 4'hf, d0); + i=i+1; + for(n=0;n>2) + n ]; + else d0=s0.mem[(s0.mem[17]>>2) + n ]; + if(mode[0]) d1=s1.mem[(s0.mem[18]>>2) + n ]; + else d1=s0.mem[(s0.mem[18]>>2) + n ]; + + if( d1 !== d0 ) + begin + $display("ERROR: CH2: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)", + n, d0, d1, $time); + error_cnt = error_cnt + 1; + end + end + end + + if(int_src[3]) + begin + m0.wb_rd1(`REG_BASE + `CH3_CSR, 4'hf, d0); + i=i+1; + for(n=0;n>2) + n ]; + else d0=s0.mem[(s0.mem[25]>>2) + n ]; + if(mode[0]) d1=s1.mem[(s0.mem[26]>>2) + n ]; + else d1=s0.mem[(s0.mem[26]>>2) + n ]; + + if( d1 !== d0 ) + begin + $display("ERROR: CH3: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)", + n, d0, d1, $time); + error_cnt = error_cnt + 1; + end + end + end + + end + + join + + +/* + if(ack_cnt != ((tot_sz*2*4*2)+(4*4*2)) ) + begin + $display("ERROR: ACK count Mismatch: Expected: %0d, Got: %0d (%0t)", + ((tot_sz*2*4*2)+(4*4*2)), ack_cnt, $time); + error_cnt = error_cnt + 1; + end +*/ + + repeat(5) @(posedge clk); + +end +end + + s0.delay = 0; + s1.delay = 0; + +show_errors; +$display("*****************************************************"); +$display("*** Test DONE ... ***"); +$display("*****************************************************\n\n"); +end + +endtask + + + + Index: wb_dma/trunk/rtl/verilog/wb_dma_top.v =================================================================== --- wb_dma/trunk/rtl/verilog/wb_dma_top.v (nonexistent) +++ wb_dma/trunk/rtl/verilog/wb_dma_top.v (revision 17) @@ -0,0 +1,1122 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE DMA Top Level //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/wb_dma/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: wb_dma_top.v,v 1.5 2002-02-01 01:54:45 rudi Exp $ +// +// $Date: 2002-02-01 01:54:45 $ +// $Revision: 1.5 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.4 2001/10/19 04:35:04 rudi +// +// - Made the core parameterized +// +// Revision 1.3 2001/09/07 15:34:38 rudi +// +// Changed reset to active high. +// +// Revision 1.2 2001/08/15 05:40:30 rudi +// +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// - Added Section 3.10, describing DMA restart. +// +// Revision 1.1 2001/07/29 08:57:02 rudi +// +// +// 1) Changed Directory Structure +// 2) Added restart signal (REST) +// +// Revision 1.3 2001/06/13 02:26:50 rudi +// +// +// Small changes after running lint. +// +// Revision 1.2 2001/06/05 10:22:37 rudi +// +// +// - Added Support of up to 31 channels +// - Added support for 2,4 and 8 priority levels +// - Now can have up to 31 channels +// - Added many configuration items +// - Changed reset to async +// +// Revision 1.1.1.1 2001/03/19 13:10:23 rudi +// Initial Release +// +// +// + +`include "wb_dma_defines.v" + +module wb_dma_top(clk_i, rst_i, + + wb0s_data_i, wb0s_data_o, wb0_addr_i, wb0_sel_i, wb0_we_i, wb0_cyc_i, + wb0_stb_i, wb0_ack_o, wb0_err_o, wb0_rty_o, + wb0m_data_i, wb0m_data_o, wb0_addr_o, wb0_sel_o, wb0_we_o, wb0_cyc_o, + wb0_stb_o, wb0_ack_i, wb0_err_i, wb0_rty_i, + + wb1s_data_i, wb1s_data_o, wb1_addr_i, wb1_sel_i, wb1_we_i, wb1_cyc_i, + wb1_stb_i, wb1_ack_o, wb1_err_o, wb1_rty_o, + wb1m_data_i, wb1m_data_o, wb1_addr_o, wb1_sel_o, wb1_we_o, wb1_cyc_o, + wb1_stb_o, wb1_ack_i, wb1_err_i, wb1_rty_i, + + dma_req_i, dma_ack_o, dma_nd_i, dma_rest_i, + + inta_o, intb_o + ); + +//////////////////////////////////////////////////////////////////// +// +// Module Parameters +// + +// chXX_conf = { CBUF, ED, ARS, EN } +parameter rf_addr = 0; +parameter [1:0] pri_sel = 2'h0; +parameter ch_count = 1; +parameter [3:0] ch0_conf = 4'h1; +parameter [3:0] ch1_conf = 4'h0; +parameter [3:0] ch2_conf = 4'h0; +parameter [3:0] ch3_conf = 4'h0; +parameter [3:0] ch4_conf = 4'h0; +parameter [3:0] ch5_conf = 4'h0; +parameter [3:0] ch6_conf = 4'h0; +parameter [3:0] ch7_conf = 4'h0; +parameter [3:0] ch8_conf = 4'h0; +parameter [3:0] ch9_conf = 4'h0; +parameter [3:0] ch10_conf = 4'h0; +parameter [3:0] ch11_conf = 4'h0; +parameter [3:0] ch12_conf = 4'h0; +parameter [3:0] ch13_conf = 4'h0; +parameter [3:0] ch14_conf = 4'h0; +parameter [3:0] ch15_conf = 4'h0; +parameter [3:0] ch16_conf = 4'h0; +parameter [3:0] ch17_conf = 4'h0; +parameter [3:0] ch18_conf = 4'h0; +parameter [3:0] ch19_conf = 4'h0; +parameter [3:0] ch20_conf = 4'h0; +parameter [3:0] ch21_conf = 4'h0; +parameter [3:0] ch22_conf = 4'h0; +parameter [3:0] ch23_conf = 4'h0; +parameter [3:0] ch24_conf = 4'h0; +parameter [3:0] ch25_conf = 4'h0; +parameter [3:0] ch26_conf = 4'h0; +parameter [3:0] ch27_conf = 4'h0; +parameter [3:0] ch28_conf = 4'h0; +parameter [3:0] ch29_conf = 4'h0; +parameter [3:0] ch30_conf = 4'h0; + +//////////////////////////////////////////////////////////////////// +// +// Module IOs +// + +input clk_i, rst_i; + +// -------------------------------------- +// WISHBONE INTERFACE 0 + +// Slave Interface +input [31:0] wb0s_data_i; +output [31:0] wb0s_data_o; +input [31:0] wb0_addr_i; +input [3:0] wb0_sel_i; +input wb0_we_i; +input wb0_cyc_i; +input wb0_stb_i; +output wb0_ack_o; +output wb0_err_o; +output wb0_rty_o; + +// Master Interface +input [31:0] wb0m_data_i; +output [31:0] wb0m_data_o; +output [31:0] wb0_addr_o; +output [3:0] wb0_sel_o; +output wb0_we_o; +output wb0_cyc_o; +output wb0_stb_o; +input wb0_ack_i; +input wb0_err_i; +input wb0_rty_i; + +// -------------------------------------- +// WISHBONE INTERFACE 1 + +// Slave Interface +input [31:0] wb1s_data_i; +output [31:0] wb1s_data_o; +input [31:0] wb1_addr_i; +input [3:0] wb1_sel_i; +input wb1_we_i; +input wb1_cyc_i; +input wb1_stb_i; +output wb1_ack_o; +output wb1_err_o; +output wb1_rty_o; + +// Master Interface +input [31:0] wb1m_data_i; +output [31:0] wb1m_data_o; +output [31:0] wb1_addr_o; +output [3:0] wb1_sel_o; +output wb1_we_o; +output wb1_cyc_o; +output wb1_stb_o; +input wb1_ack_i; +input wb1_err_i; +input wb1_rty_i; + +// -------------------------------------- +// Misc Signals +input [ch_count-1:0] dma_req_i; +input [ch_count-1:0] dma_nd_i; +output [ch_count-1:0] dma_ack_o; +input [ch_count-1:0] dma_rest_i; +output inta_o; +output intb_o; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +wire [31:0] pointer0, pointer0_s, ch0_csr, ch0_txsz, ch0_adr0, ch0_adr1, ch0_am0, ch0_am1; +wire [31:0] pointer1, pointer1_s, ch1_csr, ch1_txsz, ch1_adr0, ch1_adr1, ch1_am0, ch1_am1; +wire [31:0] pointer2, pointer2_s, ch2_csr, ch2_txsz, ch2_adr0, ch2_adr1, ch2_am0, ch2_am1; +wire [31:0] pointer3, pointer3_s, ch3_csr, ch3_txsz, ch3_adr0, ch3_adr1, ch3_am0, ch3_am1; +wire [31:0] pointer4, pointer4_s, ch4_csr, ch4_txsz, ch4_adr0, ch4_adr1, ch4_am0, ch4_am1; +wire [31:0] pointer5, pointer5_s, ch5_csr, ch5_txsz, ch5_adr0, ch5_adr1, ch5_am0, ch5_am1; +wire [31:0] pointer6, pointer6_s, ch6_csr, ch6_txsz, ch6_adr0, ch6_adr1, ch6_am0, ch6_am1; +wire [31:0] pointer7, pointer7_s, ch7_csr, ch7_txsz, ch7_adr0, ch7_adr1, ch7_am0, ch7_am1; +wire [31:0] pointer8, pointer8_s, ch8_csr, ch8_txsz, ch8_adr0, ch8_adr1, ch8_am0, ch8_am1; +wire [31:0] pointer9, pointer9_s, ch9_csr, ch9_txsz, ch9_adr0, ch9_adr1, ch9_am0, ch9_am1; +wire [31:0] pointer10, pointer10_s, ch10_csr, ch10_txsz, ch10_adr0, ch10_adr1, ch10_am0, ch10_am1; +wire [31:0] pointer11, pointer11_s, ch11_csr, ch11_txsz, ch11_adr0, ch11_adr1, ch11_am0, ch11_am1; +wire [31:0] pointer12, pointer12_s, ch12_csr, ch12_txsz, ch12_adr0, ch12_adr1, ch12_am0, ch12_am1; +wire [31:0] pointer13, pointer13_s, ch13_csr, ch13_txsz, ch13_adr0, ch13_adr1, ch13_am0, ch13_am1; +wire [31:0] pointer14, pointer14_s, ch14_csr, ch14_txsz, ch14_adr0, ch14_adr1, ch14_am0, ch14_am1; +wire [31:0] pointer15, pointer15_s, ch15_csr, ch15_txsz, ch15_adr0, ch15_adr1, ch15_am0, ch15_am1; +wire [31:0] pointer16, pointer16_s, ch16_csr, ch16_txsz, ch16_adr0, ch16_adr1, ch16_am0, ch16_am1; +wire [31:0] pointer17, pointer17_s, ch17_csr, ch17_txsz, ch17_adr0, ch17_adr1, ch17_am0, ch17_am1; +wire [31:0] pointer18, pointer18_s, ch18_csr, ch18_txsz, ch18_adr0, ch18_adr1, ch18_am0, ch18_am1; +wire [31:0] pointer19, pointer19_s, ch19_csr, ch19_txsz, ch19_adr0, ch19_adr1, ch19_am0, ch19_am1; +wire [31:0] pointer20, pointer20_s, ch20_csr, ch20_txsz, ch20_adr0, ch20_adr1, ch20_am0, ch20_am1; +wire [31:0] pointer21, pointer21_s, ch21_csr, ch21_txsz, ch21_adr0, ch21_adr1, ch21_am0, ch21_am1; +wire [31:0] pointer22, pointer22_s, ch22_csr, ch22_txsz, ch22_adr0, ch22_adr1, ch22_am0, ch22_am1; +wire [31:0] pointer23, pointer23_s, ch23_csr, ch23_txsz, ch23_adr0, ch23_adr1, ch23_am0, ch23_am1; +wire [31:0] pointer24, pointer24_s, ch24_csr, ch24_txsz, ch24_adr0, ch24_adr1, ch24_am0, ch24_am1; +wire [31:0] pointer25, pointer25_s, ch25_csr, ch25_txsz, ch25_adr0, ch25_adr1, ch25_am0, ch25_am1; +wire [31:0] pointer26, pointer26_s, ch26_csr, ch26_txsz, ch26_adr0, ch26_adr1, ch26_am0, ch26_am1; +wire [31:0] pointer27, pointer27_s, ch27_csr, ch27_txsz, ch27_adr0, ch27_adr1, ch27_am0, ch27_am1; +wire [31:0] pointer28, pointer28_s, ch28_csr, ch28_txsz, ch28_adr0, ch28_adr1, ch28_am0, ch28_am1; +wire [31:0] pointer29, pointer29_s, ch29_csr, ch29_txsz, ch29_adr0, ch29_adr1, ch29_am0, ch29_am1; +wire [31:0] pointer30, pointer30_s, ch30_csr, ch30_txsz, ch30_adr0, ch30_adr1, ch30_am0, ch30_am1; + +wire [4:0] ch_sel; // Write Back Channel Select +wire [30:0] ndnr; // Next Descriptor No Request +wire de_start; // Start DMA Engine +wire ndr; // Next Descriptor With Request +wire [31:0] csr; // Selected Channel CSR +wire [31:0] pointer; +wire [31:0] pointer_s; +wire [31:0] txsz; // Selected Channel Transfer Size +wire [31:0] adr0, adr1; // Selected Channel Addresses +wire [31:0] am0, am1; // Selected Channel Address Masks +wire next_ch; // Indicates the DMA Engine is done + +wire inta_o, intb_o; +wire dma_abort; +wire dma_busy, dma_err, dma_done, dma_done_all; +wire [31:0] de_csr; +wire [11:0] de_txsz; +wire [31:0] de_adr0; +wire [31:0] de_adr1; +wire de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we; +wire de_fetch_descr; +wire ptr_set; +wire de_ack; +wire pause_req; +wire paused; + +wire mast0_go; // Perform a Master Cycle (as long as this +wire mast0_we; // Read/Write +wire [31:0] mast0_adr; // Address for the transfer +wire [31:0] mast0_din; // Internal Input Data +wire [31:0] mast0_dout; // Internal Output Data +wire mast0_err; // Indicates an error has occurred +wire mast0_drdy; // Indicated that either data is available +wire mast0_wait; // Tells the master to insert wait cycles + +wire [31:0] slv0_adr; // Slave Address +wire [31:0] slv0_din; // Slave Input Data +wire [31:0] slv0_dout; // Slave Output Data +wire slv0_re; // Slave Read Enable +wire slv0_we; // Slave Write Enable + +wire pt0_sel_i; // Pass Through Mode Selected +wire [70:0] mast0_pt_in; // Grouped WISHBONE inputs +wire [34:0] mast0_pt_out; // Grouped WISHBONE outputs + +wire pt0_sel_o; // Pass Through Mode Active +wire [70:0] slv0_pt_out; // Grouped WISHBONE out signals +wire [34:0] slv0_pt_in; // Grouped WISHBONE in signals + +wire mast1_go; // Perform a Master Cycle (as long as this +wire mast1_we; // Read/Write +wire [31:0] mast1_adr; // Address for the transfer +wire [31:0] mast1_din; // Internal Input Data +wire [31:0] mast1_dout; // Internal Output Data +wire mast1_err; // Indicates an error has occurred +wire mast1_drdy; // Indicated that either data is available +wire mast1_wait; // Tells the master to insert wait cycles + +wire [31:0] slv1_adr; // Slave Address +wire [31:0] slv1_dout; // Slave Output Data +wire slv1_re; // Slave Read Enable +wire slv1_we; // Slave Write Enable + +wire pt1_sel_i; // Pass Through Mode Selected +wire [70:0] mast1_pt_in; // Grouped WISHBONE inputs +wire [34:0] mast1_pt_out; // Grouped WISHBONE outputs + +wire pt1_sel_o; // Pass Through Mode Active +wire [70:0] slv1_pt_out; // Grouped WISHBONE out signals +wire [34:0] slv1_pt_in; // Grouped WISHBONE in signals + +wire [30:0] dma_req; +wire [30:0] dma_nd; +wire [30:0] dma_ack; +wire [30:0] dma_rest; + +//////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +wire [31:0] tmp_gnd = 32'h0; + +assign dma_req[ch_count-1:0] = dma_req_i; +assign dma_nd[ch_count-1:0] = dma_nd_i; +assign dma_rest[ch_count-1:0] = dma_rest_i; +assign dma_ack_o = {tmp_gnd[31-ch_count:0], dma_ack[ch_count-1:0]}; + +// -------------------------------------------------- +// This should go in to a separate Pass Through Block +assign pt1_sel_i = pt0_sel_o; +assign pt0_sel_i = pt1_sel_o; +assign mast1_pt_in = slv0_pt_out; +assign slv0_pt_in = mast1_pt_out; +assign mast0_pt_in = slv1_pt_out; +assign slv1_pt_in = mast0_pt_out; +// -------------------------------------------------- + +//////////////////////////////////////////////////////////////////// +// +// Modules +// + +// DMA Register File +wb_dma_rf #( ch0_conf, + ch1_conf, + ch2_conf, + ch3_conf, + ch4_conf, + ch5_conf, + ch6_conf, + ch7_conf, + ch8_conf, + ch9_conf, + ch10_conf, + ch11_conf, + ch12_conf, + ch13_conf, + ch14_conf, + ch15_conf, + ch16_conf, + ch17_conf, + ch18_conf, + ch19_conf, + ch20_conf, + ch21_conf, + ch22_conf, + ch23_conf, + ch24_conf, + ch25_conf, + ch26_conf, + ch27_conf, + ch28_conf, + ch29_conf, + ch30_conf) + u0( + .clk( clk_i ), + .rst( ~rst_i ), + .wb_rf_adr( slv0_adr[9:2] ), + .wb_rf_din( slv0_dout ), + .wb_rf_dout( slv0_din ), + .wb_rf_re( slv0_re ), + .wb_rf_we( slv0_we ), + .inta_o( inta_o ), + .intb_o( intb_o ), + .pointer0( pointer0 ), + .pointer0_s( pointer0_s ), + .ch0_csr( ch0_csr ), + .ch0_txsz( ch0_txsz ), + .ch0_adr0( ch0_adr0 ), + .ch0_adr1( ch0_adr1 ), + .ch0_am0( ch0_am0 ), + .ch0_am1( ch0_am1 ), + .pointer1( pointer1 ), + .pointer1_s( pointer1_s ), + .ch1_csr( ch1_csr ), + .ch1_txsz( ch1_txsz ), + .ch1_adr0( ch1_adr0 ), + .ch1_adr1( ch1_adr1 ), + .ch1_am0( ch1_am0 ), + .ch1_am1( ch1_am1 ), + .pointer2( pointer2 ), + .pointer2_s( pointer2_s ), + .ch2_csr( ch2_csr ), + .ch2_txsz( ch2_txsz ), + .ch2_adr0( ch2_adr0 ), + .ch2_adr1( ch2_adr1 ), + .ch2_am0( ch2_am0 ), + .ch2_am1( ch2_am1 ), + .pointer3( pointer3 ), + .pointer3_s( pointer3_s ), + .ch3_csr( ch3_csr ), + .ch3_txsz( ch3_txsz ), + .ch3_adr0( ch3_adr0 ), + .ch3_adr1( ch3_adr1 ), + .ch3_am0( ch3_am0 ), + .ch3_am1( ch3_am1 ), + .pointer4( pointer4 ), + .pointer4_s( pointer4_s ), + .ch4_csr( ch4_csr ), + .ch4_txsz( ch4_txsz ), + .ch4_adr0( ch4_adr0 ), + .ch4_adr1( ch4_adr1 ), + .ch4_am0( ch4_am0 ), + .ch4_am1( ch4_am1 ), + .pointer5( pointer5 ), + .pointer5_s( pointer5_s ), + .ch5_csr( ch5_csr ), + .ch5_txsz( ch5_txsz ), + .ch5_adr0( ch5_adr0 ), + .ch5_adr1( ch5_adr1 ), + .ch5_am0( ch5_am0 ), + .ch5_am1( ch5_am1 ), + .pointer6( pointer6 ), + .pointer6_s( pointer6_s ), + .ch6_csr( ch6_csr ), + .ch6_txsz( ch6_txsz ), + .ch6_adr0( ch6_adr0 ), + .ch6_adr1( ch6_adr1 ), + .ch6_am0( ch6_am0 ), + .ch6_am1( ch6_am1 ), + .pointer7( pointer7 ), + .pointer7_s( pointer7_s ), + .ch7_csr( ch7_csr ), + .ch7_txsz( ch7_txsz ), + .ch7_adr0( ch7_adr0 ), + .ch7_adr1( ch7_adr1 ), + .ch7_am0( ch7_am0 ), + .ch7_am1( ch7_am1 ), + .pointer8( pointer8 ), + .pointer8_s( pointer8_s ), + .ch8_csr( ch8_csr ), + .ch8_txsz( ch8_txsz ), + .ch8_adr0( ch8_adr0 ), + .ch8_adr1( ch8_adr1 ), + .ch8_am0( ch8_am0 ), + .ch8_am1( ch8_am1 ), + .pointer9( pointer9 ), + .pointer9_s( pointer9_s ), + .ch9_csr( ch9_csr ), + .ch9_txsz( ch9_txsz ), + .ch9_adr0( ch9_adr0 ), + .ch9_adr1( ch9_adr1 ), + .ch9_am0( ch9_am0 ), + .ch9_am1( ch9_am1 ), + .pointer10( pointer10 ), + .pointer10_s( pointer10_s ), + .ch10_csr( ch10_csr ), + .ch10_txsz( ch10_txsz ), + .ch10_adr0( ch10_adr0 ), + .ch10_adr1( ch10_adr1 ), + .ch10_am0( ch10_am0 ), + .ch10_am1( ch10_am1 ), + .pointer11( pointer11 ), + .pointer11_s( pointer11_s ), + .ch11_csr( ch11_csr ), + .ch11_txsz( ch11_txsz ), + .ch11_adr0( ch11_adr0 ), + .ch11_adr1( ch11_adr1 ), + .ch11_am0( ch11_am0 ), + .ch11_am1( ch11_am1 ), + .pointer12( pointer12 ), + .pointer12_s( pointer12_s ), + .ch12_csr( ch12_csr ), + .ch12_txsz( ch12_txsz ), + .ch12_adr0( ch12_adr0 ), + .ch12_adr1( ch12_adr1 ), + .ch12_am0( ch12_am0 ), + .ch12_am1( ch12_am1 ), + .pointer13( pointer13 ), + .pointer13_s( pointer13_s ), + .ch13_csr( ch13_csr ), + .ch13_txsz( ch13_txsz ), + .ch13_adr0( ch13_adr0 ), + .ch13_adr1( ch13_adr1 ), + .ch13_am0( ch13_am0 ), + .ch13_am1( ch13_am1 ), + .pointer14( pointer14 ), + .pointer14_s( pointer14_s ), + .ch14_csr( ch14_csr ), + .ch14_txsz( ch14_txsz ), + .ch14_adr0( ch14_adr0 ), + .ch14_adr1( ch14_adr1 ), + .ch14_am0( ch14_am0 ), + .ch14_am1( ch14_am1 ), + .pointer15( pointer15 ), + .pointer15_s( pointer15_s ), + .ch15_csr( ch15_csr ), + .ch15_txsz( ch15_txsz ), + .ch15_adr0( ch15_adr0 ), + .ch15_adr1( ch15_adr1 ), + .ch15_am0( ch15_am0 ), + .ch15_am1( ch15_am1 ), + .pointer16( pointer16 ), + .pointer16_s( pointer16_s ), + .ch16_csr( ch16_csr ), + .ch16_txsz( ch16_txsz ), + .ch16_adr0( ch16_adr0 ), + .ch16_adr1( ch16_adr1 ), + .ch16_am0( ch16_am0 ), + .ch16_am1( ch16_am1 ), + .pointer17( pointer17 ), + .pointer17_s( pointer17_s ), + .ch17_csr( ch17_csr ), + .ch17_txsz( ch17_txsz ), + .ch17_adr0( ch17_adr0 ), + .ch17_adr1( ch17_adr1 ), + .ch17_am0( ch17_am0 ), + .ch17_am1( ch17_am1 ), + .pointer18( pointer18 ), + .pointer18_s( pointer18_s ), + .ch18_csr( ch18_csr ), + .ch18_txsz( ch18_txsz ), + .ch18_adr0( ch18_adr0 ), + .ch18_adr1( ch18_adr1 ), + .ch18_am0( ch18_am0 ), + .ch18_am1( ch18_am1 ), + .pointer19( pointer19 ), + .pointer19_s( pointer19_s ), + .ch19_csr( ch19_csr ), + .ch19_txsz( ch19_txsz ), + .ch19_adr0( ch19_adr0 ), + .ch19_adr1( ch19_adr1 ), + .ch19_am0( ch19_am0 ), + .ch19_am1( ch19_am1 ), + .pointer20( pointer20 ), + .pointer20_s( pointer20_s ), + .ch20_csr( ch20_csr ), + .ch20_txsz( ch20_txsz ), + .ch20_adr0( ch20_adr0 ), + .ch20_adr1( ch20_adr1 ), + .ch20_am0( ch20_am0 ), + .ch20_am1( ch20_am1 ), + .pointer21( pointer21 ), + .pointer21_s( pointer21_s ), + .ch21_csr( ch21_csr ), + .ch21_txsz( ch21_txsz ), + .ch21_adr0( ch21_adr0 ), + .ch21_adr1( ch21_adr1 ), + .ch21_am0( ch21_am0 ), + .ch21_am1( ch21_am1 ), + .pointer22( pointer22 ), + .pointer22_s( pointer22_s ), + .ch22_csr( ch22_csr ), + .ch22_txsz( ch22_txsz ), + .ch22_adr0( ch22_adr0 ), + .ch22_adr1( ch22_adr1 ), + .ch22_am0( ch22_am0 ), + .ch22_am1( ch22_am1 ), + .pointer23( pointer23 ), + .pointer23_s( pointer23_s ), + .ch23_csr( ch23_csr ), + .ch23_txsz( ch23_txsz ), + .ch23_adr0( ch23_adr0 ), + .ch23_adr1( ch23_adr1 ), + .ch23_am0( ch23_am0 ), + .ch23_am1( ch23_am1 ), + .pointer24( pointer24 ), + .pointer24_s( pointer24_s ), + .ch24_csr( ch24_csr ), + .ch24_txsz( ch24_txsz ), + .ch24_adr0( ch24_adr0 ), + .ch24_adr1( ch24_adr1 ), + .ch24_am0( ch24_am0 ), + .ch24_am1( ch24_am1 ), + .pointer25( pointer25 ), + .pointer25_s( pointer25_s ), + .ch25_csr( ch25_csr ), + .ch25_txsz( ch25_txsz ), + .ch25_adr0( ch25_adr0 ), + .ch25_adr1( ch25_adr1 ), + .ch25_am0( ch25_am0 ), + .ch25_am1( ch25_am1 ), + .pointer26( pointer26 ), + .pointer26_s( pointer26_s ), + .ch26_csr( ch26_csr ), + .ch26_txsz( ch26_txsz ), + .ch26_adr0( ch26_adr0 ), + .ch26_adr1( ch26_adr1 ), + .ch26_am0( ch26_am0 ), + .ch26_am1( ch26_am1 ), + .pointer27( pointer27 ), + .pointer27_s( pointer27_s ), + .ch27_csr( ch27_csr ), + .ch27_txsz( ch27_txsz ), + .ch27_adr0( ch27_adr0 ), + .ch27_adr1( ch27_adr1 ), + .ch27_am0( ch27_am0 ), + .ch27_am1( ch27_am1 ), + .pointer28( pointer28 ), + .pointer28_s( pointer28_s ), + .ch28_csr( ch28_csr ), + .ch28_txsz( ch28_txsz ), + .ch28_adr0( ch28_adr0 ), + .ch28_adr1( ch28_adr1 ), + .ch28_am0( ch28_am0 ), + .ch28_am1( ch28_am1 ), + .pointer29( pointer29 ), + .pointer29_s( pointer29_s ), + .ch29_csr( ch29_csr ), + .ch29_txsz( ch29_txsz ), + .ch29_adr0( ch29_adr0 ), + .ch29_adr1( ch29_adr1 ), + .ch29_am0( ch29_am0 ), + .ch29_am1( ch29_am1 ), + .pointer30( pointer30 ), + .pointer30_s( pointer30_s ), + .ch30_csr( ch30_csr ), + .ch30_txsz( ch30_txsz ), + .ch30_adr0( ch30_adr0 ), + .ch30_adr1( ch30_adr1 ), + .ch30_am0( ch30_am0 ), + .ch30_am1( ch30_am1 ), + .ch_sel( ch_sel ), + .ndnr( ndnr ), + .pause_req( pause_req ), + .paused( paused ), + .dma_abort( dma_abort ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest ), + .ptr_set( ptr_set ) + ); + +// Channel Select +wb_dma_ch_sel #(pri_sel, + ch0_conf, + ch1_conf, + ch2_conf, + ch3_conf, + ch4_conf, + ch5_conf, + ch6_conf, + ch7_conf, + ch8_conf, + ch9_conf, + ch10_conf, + ch11_conf, + ch12_conf, + ch13_conf, + ch14_conf, + ch15_conf, + ch16_conf, + ch17_conf, + ch18_conf, + ch19_conf, + ch20_conf, + ch21_conf, + ch22_conf, + ch23_conf, + ch24_conf, + ch25_conf, + ch26_conf, + ch27_conf, + ch28_conf, + ch29_conf, + ch30_conf) + u1( + .clk( clk_i ), + .rst( ~rst_i ), + .req_i( dma_req ), + .ack_o( dma_ack ), + .nd_i( dma_nd ), + + .pointer0( pointer0 ), + .pointer0_s( pointer0_s ), + .ch0_csr( ch0_csr ), + .ch0_txsz( ch0_txsz ), + .ch0_adr0( ch0_adr0 ), + .ch0_adr1( ch0_adr1 ), + .ch0_am0( ch0_am0 ), + .ch0_am1( ch0_am1 ), + .pointer1( pointer1 ), + .pointer1_s( pointer1_s ), + .ch1_csr( ch1_csr ), + .ch1_txsz( ch1_txsz ), + .ch1_adr0( ch1_adr0 ), + .ch1_adr1( ch1_adr1 ), + .ch1_am0( ch1_am0 ), + .ch1_am1( ch1_am1 ), + .pointer2( pointer2 ), + .pointer2_s( pointer2_s ), + .ch2_csr( ch2_csr ), + .ch2_txsz( ch2_txsz ), + .ch2_adr0( ch2_adr0 ), + .ch2_adr1( ch2_adr1 ), + .ch2_am0( ch2_am0 ), + .ch2_am1( ch2_am1 ), + .pointer3( pointer3 ), + .pointer3_s( pointer3_s ), + .ch3_csr( ch3_csr ), + .ch3_txsz( ch3_txsz ), + .ch3_adr0( ch3_adr0 ), + .ch3_adr1( ch3_adr1 ), + .ch3_am0( ch3_am0 ), + .ch3_am1( ch3_am1 ), + .pointer4( pointer4 ), + .pointer4_s( pointer4_s ), + .ch4_csr( ch4_csr ), + .ch4_txsz( ch4_txsz ), + .ch4_adr0( ch4_adr0 ), + .ch4_adr1( ch4_adr1 ), + .ch4_am0( ch4_am0 ), + .ch4_am1( ch4_am1 ), + .pointer5( pointer5 ), + .pointer5_s( pointer5_s ), + .ch5_csr( ch5_csr ), + .ch5_txsz( ch5_txsz ), + .ch5_adr0( ch5_adr0 ), + .ch5_adr1( ch5_adr1 ), + .ch5_am0( ch5_am0 ), + .ch5_am1( ch5_am1 ), + .pointer6( pointer6 ), + .pointer6_s( pointer6_s ), + .ch6_csr( ch6_csr ), + .ch6_txsz( ch6_txsz ), + .ch6_adr0( ch6_adr0 ), + .ch6_adr1( ch6_adr1 ), + .ch6_am0( ch6_am0 ), + .ch6_am1( ch6_am1 ), + .pointer7( pointer7 ), + .pointer7_s( pointer7_s ), + .ch7_csr( ch7_csr ), + .ch7_txsz( ch7_txsz ), + .ch7_adr0( ch7_adr0 ), + .ch7_adr1( ch7_adr1 ), + .ch7_am0( ch7_am0 ), + .ch7_am1( ch7_am1 ), + .pointer8( pointer8 ), + .pointer8_s( pointer8_s ), + .ch8_csr( ch8_csr ), + .ch8_txsz( ch8_txsz ), + .ch8_adr0( ch8_adr0 ), + .ch8_adr1( ch8_adr1 ), + .ch8_am0( ch8_am0 ), + .ch8_am1( ch8_am1 ), + .pointer9( pointer9 ), + .pointer9_s( pointer9_s ), + .ch9_csr( ch9_csr ), + .ch9_txsz( ch9_txsz ), + .ch9_adr0( ch9_adr0 ), + .ch9_adr1( ch9_adr1 ), + .ch9_am0( ch9_am0 ), + .ch9_am1( ch9_am1 ), + .pointer10( pointer10 ), + .pointer10_s( pointer10_s ), + .ch10_csr( ch10_csr ), + .ch10_txsz( ch10_txsz ), + .ch10_adr0( ch10_adr0 ), + .ch10_adr1( ch10_adr1 ), + .ch10_am0( ch10_am0 ), + .ch10_am1( ch10_am1 ), + .pointer11( pointer11 ), + .pointer11_s( pointer11_s ), + .ch11_csr( ch11_csr ), + .ch11_txsz( ch11_txsz ), + .ch11_adr0( ch11_adr0 ), + .ch11_adr1( ch11_adr1 ), + .ch11_am0( ch11_am0 ), + .ch11_am1( ch11_am1 ), + .pointer12( pointer12 ), + .pointer12_s( pointer12_s ), + .ch12_csr( ch12_csr ), + .ch12_txsz( ch12_txsz ), + .ch12_adr0( ch12_adr0 ), + .ch12_adr1( ch12_adr1 ), + .ch12_am0( ch12_am0 ), + .ch12_am1( ch12_am1 ), + .pointer13( pointer13 ), + .pointer13_s( pointer13_s ), + .ch13_csr( ch13_csr ), + .ch13_txsz( ch13_txsz ), + .ch13_adr0( ch13_adr0 ), + .ch13_adr1( ch13_adr1 ), + .ch13_am0( ch13_am0 ), + .ch13_am1( ch13_am1 ), + .pointer14( pointer14 ), + .pointer14_s( pointer14_s ), + .ch14_csr( ch14_csr ), + .ch14_txsz( ch14_txsz ), + .ch14_adr0( ch14_adr0 ), + .ch14_adr1( ch14_adr1 ), + .ch14_am0( ch14_am0 ), + .ch14_am1( ch14_am1 ), + .pointer15( pointer15 ), + .pointer15_s( pointer15_s ), + .ch15_csr( ch15_csr ), + .ch15_txsz( ch15_txsz ), + .ch15_adr0( ch15_adr0 ), + .ch15_adr1( ch15_adr1 ), + .ch15_am0( ch15_am0 ), + .ch15_am1( ch15_am1 ), + .pointer16( pointer16 ), + .pointer16_s( pointer16_s ), + .ch16_csr( ch16_csr ), + .ch16_txsz( ch16_txsz ), + .ch16_adr0( ch16_adr0 ), + .ch16_adr1( ch16_adr1 ), + .ch16_am0( ch16_am0 ), + .ch16_am1( ch16_am1 ), + .pointer17( pointer17 ), + .pointer17_s( pointer17_s ), + .ch17_csr( ch17_csr ), + .ch17_txsz( ch17_txsz ), + .ch17_adr0( ch17_adr0 ), + .ch17_adr1( ch17_adr1 ), + .ch17_am0( ch17_am0 ), + .ch17_am1( ch17_am1 ), + .pointer18( pointer18 ), + .pointer18_s( pointer18_s ), + .ch18_csr( ch18_csr ), + .ch18_txsz( ch18_txsz ), + .ch18_adr0( ch18_adr0 ), + .ch18_adr1( ch18_adr1 ), + .ch18_am0( ch18_am0 ), + .ch18_am1( ch18_am1 ), + .pointer19( pointer19 ), + .pointer19_s( pointer19_s ), + .ch19_csr( ch19_csr ), + .ch19_txsz( ch19_txsz ), + .ch19_adr0( ch19_adr0 ), + .ch19_adr1( ch19_adr1 ), + .ch19_am0( ch19_am0 ), + .ch19_am1( ch19_am1 ), + .pointer20( pointer20 ), + .pointer20_s( pointer20_s ), + .ch20_csr( ch20_csr ), + .ch20_txsz( ch20_txsz ), + .ch20_adr0( ch20_adr0 ), + .ch20_adr1( ch20_adr1 ), + .ch20_am0( ch20_am0 ), + .ch20_am1( ch20_am1 ), + .pointer21( pointer21 ), + .pointer21_s( pointer21_s ), + .ch21_csr( ch21_csr ), + .ch21_txsz( ch21_txsz ), + .ch21_adr0( ch21_adr0 ), + .ch21_adr1( ch21_adr1 ), + .ch21_am0( ch21_am0 ), + .ch21_am1( ch21_am1 ), + .pointer22( pointer22 ), + .pointer22_s( pointer22_s ), + .ch22_csr( ch22_csr ), + .ch22_txsz( ch22_txsz ), + .ch22_adr0( ch22_adr0 ), + .ch22_adr1( ch22_adr1 ), + .ch22_am0( ch22_am0 ), + .ch22_am1( ch22_am1 ), + .pointer23( pointer23 ), + .pointer23_s( pointer23_s ), + .ch23_csr( ch23_csr ), + .ch23_txsz( ch23_txsz ), + .ch23_adr0( ch23_adr0 ), + .ch23_adr1( ch23_adr1 ), + .ch23_am0( ch23_am0 ), + .ch23_am1( ch23_am1 ), + .pointer24( pointer24 ), + .pointer24_s( pointer24_s ), + .ch24_csr( ch24_csr ), + .ch24_txsz( ch24_txsz ), + .ch24_adr0( ch24_adr0 ), + .ch24_adr1( ch24_adr1 ), + .ch24_am0( ch24_am0 ), + .ch24_am1( ch24_am1 ), + .pointer25( pointer25 ), + .pointer25_s( pointer25_s ), + .ch25_csr( ch25_csr ), + .ch25_txsz( ch25_txsz ), + .ch25_adr0( ch25_adr0 ), + .ch25_adr1( ch25_adr1 ), + .ch25_am0( ch25_am0 ), + .ch25_am1( ch25_am1 ), + .pointer26( pointer26 ), + .pointer26_s( pointer26_s ), + .ch26_csr( ch26_csr ), + .ch26_txsz( ch26_txsz ), + .ch26_adr0( ch26_adr0 ), + .ch26_adr1( ch26_adr1 ), + .ch26_am0( ch26_am0 ), + .ch26_am1( ch26_am1 ), + .pointer27( pointer27 ), + .pointer27_s( pointer27_s ), + .ch27_csr( ch27_csr ), + .ch27_txsz( ch27_txsz ), + .ch27_adr0( ch27_adr0 ), + .ch27_adr1( ch27_adr1 ), + .ch27_am0( ch27_am0 ), + .ch27_am1( ch27_am1 ), + .pointer28( pointer28 ), + .pointer28_s( pointer28_s ), + .ch28_csr( ch28_csr ), + .ch28_txsz( ch28_txsz ), + .ch28_adr0( ch28_adr0 ), + .ch28_adr1( ch28_adr1 ), + .ch28_am0( ch28_am0 ), + .ch28_am1( ch28_am1 ), + .pointer29( pointer29 ), + .pointer29_s( pointer29_s ), + .ch29_csr( ch29_csr ), + .ch29_txsz( ch29_txsz ), + .ch29_adr0( ch29_adr0 ), + .ch29_adr1( ch29_adr1 ), + .ch29_am0( ch29_am0 ), + .ch29_am1( ch29_am1 ), + .pointer30( pointer30 ), + .pointer30_s( pointer30_s ), + .ch30_csr( ch30_csr ), + .ch30_txsz( ch30_txsz ), + .ch30_adr0( ch30_adr0 ), + .ch30_adr1( ch30_adr1 ), + .ch30_am0( ch30_am0 ), + .ch30_am1( ch30_am1 ), + + .ch_sel( ch_sel ), + .ndnr( ndnr ), + .de_start( de_start ), + .ndr( ndr ), + .csr( csr ), + .pointer( pointer ), + .txsz( txsz ), + .adr0( adr0 ), + .adr1( adr1 ), + .am0( am0 ), + .am1( am1 ), + .pointer_s( pointer_s ), + .next_ch( next_ch ), + .de_ack( de_ack ), + .dma_busy( dma_busy ) + ); + + +// DMA Engine +wb_dma_de u2( + .clk( clk_i ), + .rst( ~rst_i ), + .mast0_go( mast0_go ), + .mast0_we( mast0_we ), + .mast0_adr( mast0_adr ), + .mast0_din( mast0_dout ), + .mast0_dout( mast0_din ), + .mast0_err( mast0_err ), + .mast0_drdy( mast0_drdy ), + .mast0_wait( mast0_wait ), + .mast1_go( mast1_go ), + .mast1_we( mast1_we ), + .mast1_adr( mast1_adr ), + .mast1_din( mast1_dout ), + .mast1_dout( mast1_din ), + .mast1_err( mast1_err ), + .mast1_drdy( mast1_drdy ), + .mast1_wait( mast1_wait ), + .de_start( de_start ), + .nd( ndr ), + .csr( csr ), + .pointer( pointer ), + .pointer_s( pointer_s ), + .txsz( txsz ), + .adr0( adr0 ), + .adr1( adr1 ), + .am0( am0 ), + .am1( am1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .ptr_set( ptr_set ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .next_ch( next_ch ), + .de_ack( de_ack ), + .pause_req( pause_req ), + .paused( paused ), + .dma_abort( dma_abort ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ) + ); + +// Wishbone Interface 0 +wb_dma_wb_if #(rf_addr) u3( + .clk( clk_i ), + .rst( ~rst_i ), + .wbs_data_i( wb0s_data_i ), + .wbs_data_o( wb0s_data_o ), + .wb_addr_i( wb0_addr_i ), + .wb_sel_i( wb0_sel_i ), + .wb_we_i( wb0_we_i ), + .wb_cyc_i( wb0_cyc_i ), + .wb_stb_i( wb0_stb_i ), + .wb_ack_o( wb0_ack_o ), + .wb_err_o( wb0_err_o ), + .wb_rty_o( wb0_rty_o ), + .wbm_data_i( wb0m_data_i ), + .wbm_data_o( wb0m_data_o ), + .wb_addr_o( wb0_addr_o ), + .wb_sel_o( wb0_sel_o ), + .wb_we_o( wb0_we_o ), + .wb_cyc_o( wb0_cyc_o ), + .wb_stb_o( wb0_stb_o ), + .wb_ack_i( wb0_ack_i ), + .wb_err_i( wb0_err_i ), + .wb_rty_i( wb0_rty_i ), + .mast_go( mast0_go ), + .mast_we( mast0_we ), + .mast_adr( mast0_adr ), + .mast_din( mast0_din ), + .mast_dout( mast0_dout ), + .mast_err( mast0_err ), + .mast_drdy( mast0_drdy ), + .mast_wait( mast0_wait ), + .pt_sel_i( pt0_sel_i ), + .mast_pt_in( mast0_pt_in ), + .mast_pt_out( mast0_pt_out ), + .slv_adr( slv0_adr ), + .slv_din( slv0_din ), + .slv_dout( slv0_dout ), + .slv_re( slv0_re ), + .slv_we( slv0_we ), + .pt_sel_o( pt0_sel_o ), + .slv_pt_out( slv0_pt_out ), + .slv_pt_in( slv0_pt_in ) + ); + +// Wishbone Interface 1 +wb_dma_wb_if #(rf_addr) u4( + .clk( clk_i ), + .rst( ~rst_i ), + .wbs_data_i( wb1s_data_i ), + .wbs_data_o( wb1s_data_o ), + .wb_addr_i( wb1_addr_i ), + .wb_sel_i( wb1_sel_i ), + .wb_we_i( wb1_we_i ), + .wb_cyc_i( wb1_cyc_i ), + .wb_stb_i( wb1_stb_i ), + .wb_ack_o( wb1_ack_o ), + .wb_err_o( wb1_err_o ), + .wb_rty_o( wb1_rty_o ), + .wbm_data_i( wb1m_data_i ), + .wbm_data_o( wb1m_data_o ), + .wb_addr_o( wb1_addr_o ), + .wb_sel_o( wb1_sel_o ), + .wb_we_o( wb1_we_o ), + .wb_cyc_o( wb1_cyc_o ), + .wb_stb_o( wb1_stb_o ), + .wb_ack_i( wb1_ack_i ), + .wb_err_i( wb1_err_i ), + .wb_rty_i( wb1_rty_i ), + .mast_go( mast1_go ), + .mast_we( mast1_we ), + .mast_adr( mast1_adr ), + .mast_din( mast1_din ), + .mast_dout( mast1_dout ), + .mast_err( mast1_err ), + .mast_drdy( mast1_drdy ), + .mast_wait( mast1_wait ), + .pt_sel_i( pt1_sel_i ), + .mast_pt_in( mast1_pt_in ), + .mast_pt_out( mast1_pt_out ), + .slv_adr( slv1_adr ), + .slv_din( 32'h0 ), // Not Connected + .slv_dout( slv1_dout ), // Not Connected + .slv_re( slv1_re ), // Not Connected + .slv_we( slv1_we ), // Not Connected + .pt_sel_o( pt1_sel_o ), + .slv_pt_out( slv1_pt_out ), + .slv_pt_in( slv1_pt_in ) + ); + + +endmodule Index: wb_dma/trunk/rtl/verilog/wb_dma_wb_if.v =================================================================== --- wb_dma/trunk/rtl/verilog/wb_dma_wb_if.v (nonexistent) +++ wb_dma/trunk/rtl/verilog/wb_dma_wb_if.v (revision 17) @@ -0,0 +1,219 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE DMA WISHBONE Interface //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/wb_dma/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: wb_dma_wb_if.v,v 1.3 2002-02-01 01:54:45 rudi Exp $ +// +// $Date: 2002-02-01 01:54:45 $ +// $Revision: 1.3 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.2 2001/10/19 04:35:04 rudi +// +// - Made the core parameterized +// +// Revision 1.1 2001/07/29 08:57:02 rudi +// +// +// 1) Changed Directory Structure +// 2) Added restart signal (REST) +// +// Revision 1.2 2001/06/05 10:22:37 rudi +// +// +// - Added Support of up to 31 channels +// - Added support for 2,4 and 8 priority levels +// - Now can have up to 31 channels +// - Added many configuration items +// - Changed reset to async +// +// Revision 1.1.1.1 2001/03/19 13:10:54 rudi +// Initial Release +// +// +// + +`include "wb_dma_defines.v" + +module wb_dma_wb_if(clk, rst, + + // Wishbone + wbs_data_i, wbs_data_o, wb_addr_i, wb_sel_i, wb_we_i, wb_cyc_i, + wb_stb_i, wb_ack_o, wb_err_o, wb_rty_o, + wbm_data_i, wbm_data_o, wb_addr_o, wb_sel_o, wb_we_o, wb_cyc_o, + wb_stb_o, wb_ack_i, wb_err_i, wb_rty_i, + + // Master + mast_go, mast_we, mast_adr, mast_din, mast_dout, mast_err, + mast_drdy, mast_wait, pt_sel_i, mast_pt_in, mast_pt_out, + + // Slave + slv_adr, slv_din, slv_dout, slv_re, slv_we, + pt_sel_o, slv_pt_out, slv_pt_in + + ); + +parameter rf_addr = 0; + +input clk, rst; + +// -------------------------------------- +// WISHBONE INTERFACE + +// Slave Interface +input [31:0] wbs_data_i; +output [31:0] wbs_data_o; +input [31:0] wb_addr_i; +input [3:0] wb_sel_i; +input wb_we_i; +input wb_cyc_i; +input wb_stb_i; +output wb_ack_o; +output wb_err_o; +output wb_rty_o; + +// Master Interface +input [31:0] wbm_data_i; +output [31:0] wbm_data_o; +output [31:0] wb_addr_o; +output [3:0] wb_sel_o; +output wb_we_o; +output wb_cyc_o; +output wb_stb_o; +input wb_ack_i; +input wb_err_i; +input wb_rty_i; + +// -------------------------------------- +// MASTER INTERFACE +input mast_go; // Perform a Master Cycle (as long as this + // line is asserted) +input mast_we; // Read/Write +input [31:0] mast_adr; // Address for the transfer +input [31:0] mast_din; // Internal Input Data +output [31:0] mast_dout; // Internal Output Data +output mast_err; // Indicates an error has occurred + +output mast_drdy; // Indicated that either data is available + // during a read, or that the master can accept + // the next data during a write +input mast_wait; // Tells the master to insert wait cycles + // because data can not be accepted/provided + +// Pass Through Interface +input pt_sel_i; // Pass Through Mode Selected +input [70:0] mast_pt_in; // Grouped WISHBONE inputs +output [34:0] mast_pt_out; // Grouped WISHBONE outputs + +// -------------------------------------- +// Slave INTERFACE + +// This is the register File Interface +output [31:0] slv_adr; // Slave Address +input [31:0] slv_din; // Slave Input Data +output [31:0] slv_dout; // Slave Output Data +output slv_re; // Slave Read Enable +output slv_we; // Slave Write Enable + +// Pass through Interface +output pt_sel_o; // Pass Through Mode Active +output [70:0] slv_pt_out; // Grouped WISHBONE out signals +input [34:0] slv_pt_in; // Grouped WISHBONE in signals + +//////////////////////////////////////////////////////////////////// +// +// Modules +// + +wb_dma_wb_mast u0( + .clk( clk ), + .rst( rst ), + .wb_data_i( wbs_data_i ), + .wb_data_o( wbs_data_o ), + .wb_addr_o( wb_addr_o ), + .wb_sel_o( wb_sel_o ), + .wb_we_o( wb_we_o ), + .wb_cyc_o( wb_cyc_o ), + .wb_stb_o( wb_stb_o ), + .wb_ack_i( wb_ack_i ), + .wb_err_i( wb_err_i ), + .wb_rty_i( wb_rty_i ), + .mast_go( mast_go ), + .mast_we( mast_we ), + .mast_adr( mast_adr ), + .mast_din( mast_din ), + .mast_dout( mast_dout ), + .mast_err( mast_err ), + .mast_drdy( mast_drdy ), + .mast_wait( mast_wait ), + .pt_sel( pt_sel_i ), + .mast_pt_in( mast_pt_in ), + .mast_pt_out( mast_pt_out ) + ); + + +wb_dma_wb_slv #(rf_addr) u1( + .clk( clk ), + .rst( rst ), + .wb_data_i( wbm_data_i ), + .wb_data_o( wbm_data_o ), + .wb_addr_i( wb_addr_i ), + .wb_sel_i( wb_sel_i ), + .wb_we_i( wb_we_i ), + .wb_cyc_i( wb_cyc_i ), + .wb_stb_i( wb_stb_i ), + .wb_ack_o( wb_ack_o ), + .wb_err_o( wb_err_o ), + .wb_rty_o( wb_rty_o ), + .slv_adr( slv_adr ), + .slv_din( slv_din ), + .slv_dout( slv_dout ), + .slv_re( slv_re ), + .slv_we( slv_we ), + .pt_sel( pt_sel_o ), + .slv_pt_out( slv_pt_out ), + .slv_pt_in( slv_pt_in ) + ); + + +endmodule Index: wb_dma/trunk/rtl/verilog/wb_dma_rf.v =================================================================== --- wb_dma/trunk/rtl/verilog/wb_dma_rf.v (nonexistent) +++ wb_dma/trunk/rtl/verilog/wb_dma_rf.v (revision 17) @@ -0,0 +1,1856 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE DMA Register File //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/wb_dma/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: wb_dma_rf.v,v 1.4 2002-02-01 01:54:45 rudi Exp $ +// +// $Date: 2002-02-01 01:54:45 $ +// $Revision: 1.4 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.3 2001/10/19 04:35:04 rudi +// +// - Made the core parameterized +// +// Revision 1.2 2001/08/15 05:40:30 rudi +// +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// - Added Section 3.10, describing DMA restart. +// +// Revision 1.1 2001/07/29 08:57:02 rudi +// +// +// 1) Changed Directory Structure +// 2) Added restart signal (REST) +// +// Revision 1.4 2001/06/14 08:50:46 rudi +// +// Changed name of channel register file module. +// +// Revision 1.3 2001/06/13 02:26:48 rudi +// +// +// Small changes after running lint. +// +// Revision 1.2 2001/06/05 10:22:37 rudi +// +// +// - Added Support of up to 31 channels +// - Added support for 2,4 and 8 priority levels +// - Now can have up to 31 channels +// - Added many configuration items +// - Changed reset to async +// +// Revision 1.1.1.1 2001/03/19 13:10:11 rudi +// Initial Release +// +// +// + +`include "wb_dma_defines.v" + +module wb_dma_rf(clk, rst, + + // WISHBONE Access + wb_rf_adr, wb_rf_din, wb_rf_dout, wb_rf_re, wb_rf_we, + + // WISHBONE Interrupt outputs + inta_o, intb_o, + + // DMA Registers Outputs + pointer0, pointer0_s, ch0_csr, ch0_txsz, ch0_adr0, ch0_adr1, ch0_am0, ch0_am1, + pointer1, pointer1_s, ch1_csr, ch1_txsz, ch1_adr0, ch1_adr1, ch1_am0, ch1_am1, + pointer2, pointer2_s, ch2_csr, ch2_txsz, ch2_adr0, ch2_adr1, ch2_am0, ch2_am1, + pointer3, pointer3_s, ch3_csr, ch3_txsz, ch3_adr0, ch3_adr1, ch3_am0, ch3_am1, + pointer4, pointer4_s, ch4_csr, ch4_txsz, ch4_adr0, ch4_adr1, ch4_am0, ch4_am1, + pointer5, pointer5_s, ch5_csr, ch5_txsz, ch5_adr0, ch5_adr1, ch5_am0, ch5_am1, + pointer6, pointer6_s, ch6_csr, ch6_txsz, ch6_adr0, ch6_adr1, ch6_am0, ch6_am1, + pointer7, pointer7_s, ch7_csr, ch7_txsz, ch7_adr0, ch7_adr1, ch7_am0, ch7_am1, + pointer8, pointer8_s, ch8_csr, ch8_txsz, ch8_adr0, ch8_adr1, ch8_am0, ch8_am1, + pointer9, pointer9_s, ch9_csr, ch9_txsz, ch9_adr0, ch9_adr1, ch9_am0, ch9_am1, + pointer10, pointer10_s, ch10_csr, ch10_txsz, ch10_adr0, ch10_adr1, ch10_am0, ch10_am1, + pointer11, pointer11_s, ch11_csr, ch11_txsz, ch11_adr0, ch11_adr1, ch11_am0, ch11_am1, + pointer12, pointer12_s, ch12_csr, ch12_txsz, ch12_adr0, ch12_adr1, ch12_am0, ch12_am1, + pointer13, pointer13_s, ch13_csr, ch13_txsz, ch13_adr0, ch13_adr1, ch13_am0, ch13_am1, + pointer14, pointer14_s, ch14_csr, ch14_txsz, ch14_adr0, ch14_adr1, ch14_am0, ch14_am1, + pointer15, pointer15_s, ch15_csr, ch15_txsz, ch15_adr0, ch15_adr1, ch15_am0, ch15_am1, + pointer16, pointer16_s, ch16_csr, ch16_txsz, ch16_adr0, ch16_adr1, ch16_am0, ch16_am1, + pointer17, pointer17_s, ch17_csr, ch17_txsz, ch17_adr0, ch17_adr1, ch17_am0, ch17_am1, + pointer18, pointer18_s, ch18_csr, ch18_txsz, ch18_adr0, ch18_adr1, ch18_am0, ch18_am1, + pointer19, pointer19_s, ch19_csr, ch19_txsz, ch19_adr0, ch19_adr1, ch19_am0, ch19_am1, + pointer20, pointer20_s, ch20_csr, ch20_txsz, ch20_adr0, ch20_adr1, ch20_am0, ch20_am1, + pointer21, pointer21_s, ch21_csr, ch21_txsz, ch21_adr0, ch21_adr1, ch21_am0, ch21_am1, + pointer22, pointer22_s, ch22_csr, ch22_txsz, ch22_adr0, ch22_adr1, ch22_am0, ch22_am1, + pointer23, pointer23_s, ch23_csr, ch23_txsz, ch23_adr0, ch23_adr1, ch23_am0, ch23_am1, + pointer24, pointer24_s, ch24_csr, ch24_txsz, ch24_adr0, ch24_adr1, ch24_am0, ch24_am1, + pointer25, pointer25_s, ch25_csr, ch25_txsz, ch25_adr0, ch25_adr1, ch25_am0, ch25_am1, + pointer26, pointer26_s, ch26_csr, ch26_txsz, ch26_adr0, ch26_adr1, ch26_am0, ch26_am1, + pointer27, pointer27_s, ch27_csr, ch27_txsz, ch27_adr0, ch27_adr1, ch27_am0, ch27_am1, + pointer28, pointer28_s, ch28_csr, ch28_txsz, ch28_adr0, ch28_adr1, ch28_am0, ch28_am1, + pointer29, pointer29_s, ch29_csr, ch29_txsz, ch29_adr0, ch29_adr1, ch29_am0, ch29_am1, + pointer30, pointer30_s, ch30_csr, ch30_txsz, ch30_adr0, ch30_adr1, ch30_am0, ch30_am1, + + // DMA Registers Write Back Channel Select + ch_sel, ndnr, + + // DMA Engine Status + pause_req, paused, dma_abort, dma_busy, dma_err, dma_done, dma_done_all, + + // DMA Engine Reg File Update ctrl signals + de_csr, de_txsz, de_adr0, de_adr1, + de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we, de_fetch_descr, dma_rest, + ptr_set + ); + +//////////////////////////////////////////////////////////////////// +// +// Module Parameters +// + +// chXX_conf = { CBUF, ED, ARS, EN } +parameter [3:0] ch0_conf = 4'h1; +parameter [3:0] ch1_conf = 4'h0; +parameter [3:0] ch2_conf = 4'h0; +parameter [3:0] ch3_conf = 4'h0; +parameter [3:0] ch4_conf = 4'h0; +parameter [3:0] ch5_conf = 4'h0; +parameter [3:0] ch6_conf = 4'h0; +parameter [3:0] ch7_conf = 4'h0; +parameter [3:0] ch8_conf = 4'h0; +parameter [3:0] ch9_conf = 4'h0; +parameter [3:0] ch10_conf = 4'h0; +parameter [3:0] ch11_conf = 4'h0; +parameter [3:0] ch12_conf = 4'h0; +parameter [3:0] ch13_conf = 4'h0; +parameter [3:0] ch14_conf = 4'h0; +parameter [3:0] ch15_conf = 4'h0; +parameter [3:0] ch16_conf = 4'h0; +parameter [3:0] ch17_conf = 4'h0; +parameter [3:0] ch18_conf = 4'h0; +parameter [3:0] ch19_conf = 4'h0; +parameter [3:0] ch20_conf = 4'h0; +parameter [3:0] ch21_conf = 4'h0; +parameter [3:0] ch22_conf = 4'h0; +parameter [3:0] ch23_conf = 4'h0; +parameter [3:0] ch24_conf = 4'h0; +parameter [3:0] ch25_conf = 4'h0; +parameter [3:0] ch26_conf = 4'h0; +parameter [3:0] ch27_conf = 4'h0; +parameter [3:0] ch28_conf = 4'h0; +parameter [3:0] ch29_conf = 4'h0; +parameter [3:0] ch30_conf = 4'h0; + +//////////////////////////////////////////////////////////////////// +// +// Module IOs +// + +input clk, rst; + +// WISHBONE Access +input [7:0] wb_rf_adr; +input [31:0] wb_rf_din; +output [31:0] wb_rf_dout; +input wb_rf_re; +input wb_rf_we; + +// WISHBONE Interrupt outputs +output inta_o, intb_o; + +// Channel Registers Inputs +output [31:0] pointer0, pointer0_s, ch0_csr, ch0_txsz, ch0_adr0, ch0_adr1, ch0_am0, ch0_am1; +output [31:0] pointer1, pointer1_s, ch1_csr, ch1_txsz, ch1_adr0, ch1_adr1, ch1_am0, ch1_am1; +output [31:0] pointer2, pointer2_s, ch2_csr, ch2_txsz, ch2_adr0, ch2_adr1, ch2_am0, ch2_am1; +output [31:0] pointer3, pointer3_s, ch3_csr, ch3_txsz, ch3_adr0, ch3_adr1, ch3_am0, ch3_am1; +output [31:0] pointer4, pointer4_s, ch4_csr, ch4_txsz, ch4_adr0, ch4_adr1, ch4_am0, ch4_am1; +output [31:0] pointer5, pointer5_s, ch5_csr, ch5_txsz, ch5_adr0, ch5_adr1, ch5_am0, ch5_am1; +output [31:0] pointer6, pointer6_s, ch6_csr, ch6_txsz, ch6_adr0, ch6_adr1, ch6_am0, ch6_am1; +output [31:0] pointer7, pointer7_s, ch7_csr, ch7_txsz, ch7_adr0, ch7_adr1, ch7_am0, ch7_am1; +output [31:0] pointer8, pointer8_s, ch8_csr, ch8_txsz, ch8_adr0, ch8_adr1, ch8_am0, ch8_am1; +output [31:0] pointer9, pointer9_s, ch9_csr, ch9_txsz, ch9_adr0, ch9_adr1, ch9_am0, ch9_am1; +output [31:0] pointer10, pointer10_s, ch10_csr, ch10_txsz, ch10_adr0, ch10_adr1, ch10_am0, ch10_am1; +output [31:0] pointer11, pointer11_s, ch11_csr, ch11_txsz, ch11_adr0, ch11_adr1, ch11_am0, ch11_am1; +output [31:0] pointer12, pointer12_s, ch12_csr, ch12_txsz, ch12_adr0, ch12_adr1, ch12_am0, ch12_am1; +output [31:0] pointer13, pointer13_s, ch13_csr, ch13_txsz, ch13_adr0, ch13_adr1, ch13_am0, ch13_am1; +output [31:0] pointer14, pointer14_s, ch14_csr, ch14_txsz, ch14_adr0, ch14_adr1, ch14_am0, ch14_am1; +output [31:0] pointer15, pointer15_s, ch15_csr, ch15_txsz, ch15_adr0, ch15_adr1, ch15_am0, ch15_am1; +output [31:0] pointer16, pointer16_s, ch16_csr, ch16_txsz, ch16_adr0, ch16_adr1, ch16_am0, ch16_am1; +output [31:0] pointer17, pointer17_s, ch17_csr, ch17_txsz, ch17_adr0, ch17_adr1, ch17_am0, ch17_am1; +output [31:0] pointer18, pointer18_s, ch18_csr, ch18_txsz, ch18_adr0, ch18_adr1, ch18_am0, ch18_am1; +output [31:0] pointer19, pointer19_s, ch19_csr, ch19_txsz, ch19_adr0, ch19_adr1, ch19_am0, ch19_am1; +output [31:0] pointer20, pointer20_s, ch20_csr, ch20_txsz, ch20_adr0, ch20_adr1, ch20_am0, ch20_am1; +output [31:0] pointer21, pointer21_s, ch21_csr, ch21_txsz, ch21_adr0, ch21_adr1, ch21_am0, ch21_am1; +output [31:0] pointer22, pointer22_s, ch22_csr, ch22_txsz, ch22_adr0, ch22_adr1, ch22_am0, ch22_am1; +output [31:0] pointer23, pointer23_s, ch23_csr, ch23_txsz, ch23_adr0, ch23_adr1, ch23_am0, ch23_am1; +output [31:0] pointer24, pointer24_s, ch24_csr, ch24_txsz, ch24_adr0, ch24_adr1, ch24_am0, ch24_am1; +output [31:0] pointer25, pointer25_s, ch25_csr, ch25_txsz, ch25_adr0, ch25_adr1, ch25_am0, ch25_am1; +output [31:0] pointer26, pointer26_s, ch26_csr, ch26_txsz, ch26_adr0, ch26_adr1, ch26_am0, ch26_am1; +output [31:0] pointer27, pointer27_s, ch27_csr, ch27_txsz, ch27_adr0, ch27_adr1, ch27_am0, ch27_am1; +output [31:0] pointer28, pointer28_s, ch28_csr, ch28_txsz, ch28_adr0, ch28_adr1, ch28_am0, ch28_am1; +output [31:0] pointer29, pointer29_s, ch29_csr, ch29_txsz, ch29_adr0, ch29_adr1, ch29_am0, ch29_am1; +output [31:0] pointer30, pointer30_s, ch30_csr, ch30_txsz, ch30_adr0, ch30_adr1, ch30_am0, ch30_am1; + +input [4:0] ch_sel; // Write Back Channel Select +input [30:0] ndnr; // Next Descriptor No Request + +// DMA Engine Abort +output dma_abort; + +// DMA Engine Status +output pause_req; +input paused; +input dma_busy, dma_err, dma_done, dma_done_all; + +// DMA Engine Reg File Update ctrl signals +input [31:0] de_csr; +input [11:0] de_txsz; +input [31:0] de_adr0; +input [31:0] de_adr1; +input de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we, ptr_set; +input de_fetch_descr; +input [30:0] dma_rest; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires and Registers +// + +reg [31:0] wb_rf_dout; +reg inta_o, intb_o; +reg [30:0] int_maska_r, int_maskb_r; +wire [31:0] int_maska, int_maskb; +wire [31:0] int_srca, int_srcb; +wire int_maska_we, int_maskb_we; +wire [30:0] ch_int; +wire csr_we; +wire [31:0] csr; +reg [7:0] csr_r; + +wire [30:0] ch_stop; +wire [30:0] ch_dis; + +wire [31:0] ch0_csr, ch0_txsz, ch0_adr0, ch0_adr1, ch0_am0, ch0_am1; +wire [31:0] ch1_csr, ch1_txsz, ch1_adr0, ch1_adr1, ch1_am0, ch1_am1; +wire [31:0] ch2_csr, ch2_txsz, ch2_adr0, ch2_adr1, ch2_am0, ch2_am1; +wire [31:0] ch3_csr, ch3_txsz, ch3_adr0, ch3_adr1, ch3_am0, ch3_am1; +wire [31:0] ch4_csr, ch4_txsz, ch4_adr0, ch4_adr1, ch4_am0, ch4_am1; +wire [31:0] ch5_csr, ch5_txsz, ch5_adr0, ch5_adr1, ch5_am0, ch5_am1; +wire [31:0] ch6_csr, ch6_txsz, ch6_adr0, ch6_adr1, ch6_am0, ch6_am1; +wire [31:0] ch7_csr, ch7_txsz, ch7_adr0, ch7_adr1, ch7_am0, ch7_am1; +wire [31:0] ch8_csr, ch8_txsz, ch8_adr0, ch8_adr1, ch8_am0, ch8_am1; +wire [31:0] ch9_csr, ch9_txsz, ch9_adr0, ch9_adr1, ch9_am0, ch9_am1; +wire [31:0] ch10_csr, ch10_txsz, ch10_adr0, ch10_adr1, ch10_am0, ch10_am1; +wire [31:0] ch11_csr, ch11_txsz, ch11_adr0, ch11_adr1, ch11_am0, ch11_am1; +wire [31:0] ch12_csr, ch12_txsz, ch12_adr0, ch12_adr1, ch12_am0, ch12_am1; +wire [31:0] ch13_csr, ch13_txsz, ch13_adr0, ch13_adr1, ch13_am0, ch13_am1; +wire [31:0] ch14_csr, ch14_txsz, ch14_adr0, ch14_adr1, ch14_am0, ch14_am1; +wire [31:0] ch15_csr, ch15_txsz, ch15_adr0, ch15_adr1, ch15_am0, ch15_am1; +wire [31:0] ch16_csr, ch16_txsz, ch16_adr0, ch16_adr1, ch16_am0, ch16_am1; +wire [31:0] ch17_csr, ch17_txsz, ch17_adr0, ch17_adr1, ch17_am0, ch17_am1; +wire [31:0] ch18_csr, ch18_txsz, ch18_adr0, ch18_adr1, ch18_am0, ch18_am1; +wire [31:0] ch19_csr, ch19_txsz, ch19_adr0, ch19_adr1, ch19_am0, ch19_am1; +wire [31:0] ch20_csr, ch20_txsz, ch20_adr0, ch20_adr1, ch20_am0, ch20_am1; +wire [31:0] ch21_csr, ch21_txsz, ch21_adr0, ch21_adr1, ch21_am0, ch21_am1; +wire [31:0] ch22_csr, ch22_txsz, ch22_adr0, ch22_adr1, ch22_am0, ch22_am1; +wire [31:0] ch23_csr, ch23_txsz, ch23_adr0, ch23_adr1, ch23_am0, ch23_am1; +wire [31:0] ch24_csr, ch24_txsz, ch24_adr0, ch24_adr1, ch24_am0, ch24_am1; +wire [31:0] ch25_csr, ch25_txsz, ch25_adr0, ch25_adr1, ch25_am0, ch25_am1; +wire [31:0] ch26_csr, ch26_txsz, ch26_adr0, ch26_adr1, ch26_am0, ch26_am1; +wire [31:0] ch27_csr, ch27_txsz, ch27_adr0, ch27_adr1, ch27_am0, ch27_am1; +wire [31:0] ch28_csr, ch28_txsz, ch28_adr0, ch28_adr1, ch28_am0, ch28_am1; +wire [31:0] ch29_csr, ch29_txsz, ch29_adr0, ch29_adr1, ch29_am0, ch29_am1; +wire [31:0] ch30_csr, ch30_txsz, ch30_adr0, ch30_adr1, ch30_am0, ch30_am1; + +wire [31:0] sw_pointer0, sw_pointer1, sw_pointer2, sw_pointer3; +wire [31:0] sw_pointer4, sw_pointer5, sw_pointer6, sw_pointer7; +wire [31:0] sw_pointer8, sw_pointer9, sw_pointer10, sw_pointer11; +wire [31:0] sw_pointer12, sw_pointer13, sw_pointer14, sw_pointer15; +wire [31:0] sw_pointer16, sw_pointer17, sw_pointer18, sw_pointer19; +wire [31:0] sw_pointer20, sw_pointer21, sw_pointer22, sw_pointer23; +wire [31:0] sw_pointer24, sw_pointer25, sw_pointer26, sw_pointer27; +wire [31:0] sw_pointer28, sw_pointer29, sw_pointer30; + +//////////////////////////////////////////////////////////////////// +// +// Aliases +// + +assign int_maska = {1'h0, int_maska_r}; +assign int_maskb = {1'h0, int_maskb_r}; +assign csr = {31'h0, paused}; + +//////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +assign dma_abort = |ch_stop; +assign pause_req = csr_r[0]; + +//////////////////////////////////////////////////////////////////// +// +// WISHBONE Register Read Logic +// + +always @(posedge clk) + case(wb_rf_adr) // synopsys parallel_case full_case + 8'h0: wb_rf_dout <= #1 csr; + 8'h1: wb_rf_dout <= #1 int_maska; + 8'h2: wb_rf_dout <= #1 int_maskb; + 8'h3: wb_rf_dout <= #1 int_srca; + 8'h4: wb_rf_dout <= #1 int_srcb; + + 8'h8: wb_rf_dout <= #1 ch0_csr; + 8'h9: wb_rf_dout <= #1 ch0_txsz; + 8'ha: wb_rf_dout <= #1 ch0_adr0; + 8'hb: wb_rf_dout <= #1 ch0_am0; + 8'hc: wb_rf_dout <= #1 ch0_adr1; + 8'hd: wb_rf_dout <= #1 ch0_am1; + 8'he: wb_rf_dout <= #1 pointer0; + 8'hf: wb_rf_dout <= #1 sw_pointer0; + + 8'h10: wb_rf_dout <= #1 ch1_conf[0] ? ch1_csr : 32'h0; + 8'h11: wb_rf_dout <= #1 ch1_conf[0] ? ch1_txsz : 32'h0; + 8'h12: wb_rf_dout <= #1 ch1_conf[0] ? ch1_adr0 : 32'h0; + 8'h13: wb_rf_dout <= #1 ch1_conf[0] ? ch1_am0 : 32'h0; + 8'h14: wb_rf_dout <= #1 ch1_conf[0] ? ch1_adr1 : 32'h0; + 8'h15: wb_rf_dout <= #1 ch1_conf[0] ? ch1_am1 : 32'h0; + 8'h16: wb_rf_dout <= #1 ch1_conf[0] ? pointer1 : 32'h0; + 8'h17: wb_rf_dout <= #1 ch1_conf[0] ? sw_pointer1 : 32'h0; + + 8'h18: wb_rf_dout <= #1 ch2_conf[0] ? ch2_csr : 32'h0; + 8'h19: wb_rf_dout <= #1 ch2_conf[0] ? ch2_txsz : 32'h0; + 8'h1a: wb_rf_dout <= #1 ch2_conf[0] ? ch2_adr0 : 32'h0; + 8'h1b: wb_rf_dout <= #1 ch2_conf[0] ? ch2_am0 : 32'h0; + 8'h1c: wb_rf_dout <= #1 ch2_conf[0] ? ch2_adr1 : 32'h0; + 8'h1d: wb_rf_dout <= #1 ch2_conf[0] ? ch2_am1 : 32'h0; + 8'h1e: wb_rf_dout <= #1 ch2_conf[0] ? pointer2 : 32'h0; + 8'h1f: wb_rf_dout <= #1 ch2_conf[0] ? sw_pointer2 : 32'h0; + + 8'h20: wb_rf_dout <= #1 ch3_conf[0] ? ch3_csr : 32'h0; + 8'h21: wb_rf_dout <= #1 ch3_conf[0] ? ch3_txsz : 32'h0; + 8'h22: wb_rf_dout <= #1 ch3_conf[0] ? ch3_adr0 : 32'h0; + 8'h23: wb_rf_dout <= #1 ch3_conf[0] ? ch3_am0 : 32'h0; + 8'h24: wb_rf_dout <= #1 ch3_conf[0] ? ch3_adr1 : 32'h0; + 8'h25: wb_rf_dout <= #1 ch3_conf[0] ? ch3_am1 : 32'h0; + 8'h26: wb_rf_dout <= #1 ch3_conf[0] ? pointer3 : 32'h0; + 8'h27: wb_rf_dout <= #1 ch3_conf[0] ? sw_pointer3 : 32'h0; + + 8'h28: wb_rf_dout <= #1 ch4_conf[0] ? ch4_csr : 32'h0; + 8'h29: wb_rf_dout <= #1 ch4_conf[0] ? ch4_txsz : 32'h0; + 8'h2a: wb_rf_dout <= #1 ch4_conf[0] ? ch4_adr0 : 32'h0; + 8'h2b: wb_rf_dout <= #1 ch4_conf[0] ? ch4_am0 : 32'h0; + 8'h2c: wb_rf_dout <= #1 ch4_conf[0] ? ch4_adr1 : 32'h0; + 8'h2d: wb_rf_dout <= #1 ch4_conf[0] ? ch4_am1 : 32'h0; + 8'h2e: wb_rf_dout <= #1 ch4_conf[0] ? pointer4 : 32'h0; + 8'h2f: wb_rf_dout <= #1 ch4_conf[0] ? sw_pointer4 : 32'h0; + + 8'h30: wb_rf_dout <= #1 ch5_conf[0] ? ch5_csr : 32'h0; + 8'h31: wb_rf_dout <= #1 ch5_conf[0] ? ch5_txsz : 32'h0; + 8'h32: wb_rf_dout <= #1 ch5_conf[0] ? ch5_adr0 : 32'h0; + 8'h33: wb_rf_dout <= #1 ch5_conf[0] ? ch5_am0 : 32'h0; + 8'h34: wb_rf_dout <= #1 ch5_conf[0] ? ch5_adr1 : 32'h0; + 8'h35: wb_rf_dout <= #1 ch5_conf[0] ? ch5_am1 : 32'h0; + 8'h36: wb_rf_dout <= #1 ch5_conf[0] ? pointer5 : 32'h0; + 8'h37: wb_rf_dout <= #1 ch5_conf[0] ? sw_pointer5 : 32'h0; + + 8'h38: wb_rf_dout <= #1 ch6_conf[0] ? ch6_csr : 32'h0; + 8'h39: wb_rf_dout <= #1 ch6_conf[0] ? ch6_txsz : 32'h0; + 8'h3a: wb_rf_dout <= #1 ch6_conf[0] ? ch6_adr0 : 32'h0; + 8'h3b: wb_rf_dout <= #1 ch6_conf[0] ? ch6_am0 : 32'h0; + 8'h3c: wb_rf_dout <= #1 ch6_conf[0] ? ch6_adr1 : 32'h0; + 8'h3d: wb_rf_dout <= #1 ch6_conf[0] ? ch6_am1 : 32'h0; + 8'h3e: wb_rf_dout <= #1 ch6_conf[0] ? pointer6 : 32'h0; + 8'h3f: wb_rf_dout <= #1 ch6_conf[0] ? sw_pointer6 : 32'h0; + + 8'h40: wb_rf_dout <= #1 ch7_conf[0] ? ch7_csr : 32'h0; + 8'h41: wb_rf_dout <= #1 ch7_conf[0] ? ch7_txsz : 32'h0; + 8'h42: wb_rf_dout <= #1 ch7_conf[0] ? ch7_adr0 : 32'h0; + 8'h43: wb_rf_dout <= #1 ch7_conf[0] ? ch7_am0 : 32'h0; + 8'h44: wb_rf_dout <= #1 ch7_conf[0] ? ch7_adr1 : 32'h0; + 8'h45: wb_rf_dout <= #1 ch7_conf[0] ? ch7_am1 : 32'h0; + 8'h46: wb_rf_dout <= #1 ch7_conf[0] ? pointer7 : 32'h0; + 8'h47: wb_rf_dout <= #1 ch7_conf[0] ? sw_pointer7 : 32'h0; + + 8'h48: wb_rf_dout <= #1 ch8_conf[0] ? ch8_csr : 32'h0; + 8'h49: wb_rf_dout <= #1 ch8_conf[0] ? ch8_txsz : 32'h0; + 8'h4a: wb_rf_dout <= #1 ch8_conf[0] ? ch8_adr0 : 32'h0; + 8'h4b: wb_rf_dout <= #1 ch8_conf[0] ? ch8_am0 : 32'h0; + 8'h4c: wb_rf_dout <= #1 ch8_conf[0] ? ch8_adr1 : 32'h0; + 8'h4d: wb_rf_dout <= #1 ch8_conf[0] ? ch8_am1 : 32'h0; + 8'h4e: wb_rf_dout <= #1 ch8_conf[0] ? pointer8 : 32'h0; + 8'h4f: wb_rf_dout <= #1 ch8_conf[0] ? sw_pointer8 : 32'h0; + + 8'h50: wb_rf_dout <= #1 ch9_conf[0] ? ch9_csr : 32'h0; + 8'h51: wb_rf_dout <= #1 ch9_conf[0] ? ch9_txsz : 32'h0; + 8'h52: wb_rf_dout <= #1 ch9_conf[0] ? ch9_adr0 : 32'h0; + 8'h53: wb_rf_dout <= #1 ch9_conf[0] ? ch9_am0 : 32'h0; + 8'h54: wb_rf_dout <= #1 ch9_conf[0] ? ch9_adr1 : 32'h0; + 8'h55: wb_rf_dout <= #1 ch9_conf[0] ? ch9_am1 : 32'h0; + 8'h56: wb_rf_dout <= #1 ch9_conf[0] ? pointer9 : 32'h0; + 8'h57: wb_rf_dout <= #1 ch9_conf[0] ? sw_pointer9 : 32'h0; + + 8'h58: wb_rf_dout <= #1 ch10_conf[0] ? ch10_csr : 32'h0; + 8'h59: wb_rf_dout <= #1 ch10_conf[0] ? ch10_txsz : 32'h0; + 8'h5a: wb_rf_dout <= #1 ch10_conf[0] ? ch10_adr0 : 32'h0; + 8'h5b: wb_rf_dout <= #1 ch10_conf[0] ? ch10_am0 : 32'h0; + 8'h5c: wb_rf_dout <= #1 ch10_conf[0] ? ch10_adr1 : 32'h0; + 8'h5d: wb_rf_dout <= #1 ch10_conf[0] ? ch10_am1 : 32'h0; + 8'h5e: wb_rf_dout <= #1 ch10_conf[0] ? pointer10 : 32'h0; + 8'h5f: wb_rf_dout <= #1 ch10_conf[0] ? sw_pointer10 : 32'h0; + + 8'h60: wb_rf_dout <= #1 ch11_conf[0] ? ch11_csr : 32'h0; + 8'h61: wb_rf_dout <= #1 ch11_conf[0] ? ch11_txsz : 32'h0; + 8'h62: wb_rf_dout <= #1 ch11_conf[0] ? ch11_adr0 : 32'h0; + 8'h63: wb_rf_dout <= #1 ch11_conf[0] ? ch11_am0 : 32'h0; + 8'h64: wb_rf_dout <= #1 ch11_conf[0] ? ch11_adr1 : 32'h0; + 8'h65: wb_rf_dout <= #1 ch11_conf[0] ? ch11_am1 : 32'h0; + 8'h66: wb_rf_dout <= #1 ch11_conf[0] ? pointer11 : 32'h0; + 8'h67: wb_rf_dout <= #1 ch11_conf[0] ? sw_pointer11 : 32'h0; + + 8'h68: wb_rf_dout <= #1 ch12_conf[0] ? ch12_csr : 32'h0; + 8'h69: wb_rf_dout <= #1 ch12_conf[0] ? ch12_txsz : 32'h0; + 8'h6a: wb_rf_dout <= #1 ch12_conf[0] ? ch12_adr0 : 32'h0; + 8'h6b: wb_rf_dout <= #1 ch12_conf[0] ? ch12_am0 : 32'h0; + 8'h6c: wb_rf_dout <= #1 ch12_conf[0] ? ch12_adr1 : 32'h0; + 8'h6d: wb_rf_dout <= #1 ch12_conf[0] ? ch12_am1 : 32'h0; + 8'h6e: wb_rf_dout <= #1 ch12_conf[0] ? pointer12 : 32'h0; + 8'h6f: wb_rf_dout <= #1 ch12_conf[0] ? sw_pointer12 : 32'h0; + + 8'h70: wb_rf_dout <= #1 ch13_conf[0] ? ch13_csr : 32'h0; + 8'h71: wb_rf_dout <= #1 ch13_conf[0] ? ch13_txsz : 32'h0; + 8'h72: wb_rf_dout <= #1 ch13_conf[0] ? ch13_adr0 : 32'h0; + 8'h73: wb_rf_dout <= #1 ch13_conf[0] ? ch13_am0 : 32'h0; + 8'h74: wb_rf_dout <= #1 ch13_conf[0] ? ch13_adr1 : 32'h0; + 8'h75: wb_rf_dout <= #1 ch13_conf[0] ? ch13_am1 : 32'h0; + 8'h76: wb_rf_dout <= #1 ch13_conf[0] ? pointer13 : 32'h0; + 8'h77: wb_rf_dout <= #1 ch13_conf[0] ? sw_pointer13 : 32'h0; + + 8'h78: wb_rf_dout <= #1 ch14_conf[0] ? ch14_csr : 32'h0; + 8'h79: wb_rf_dout <= #1 ch14_conf[0] ? ch14_txsz : 32'h0; + 8'h7a: wb_rf_dout <= #1 ch14_conf[0] ? ch14_adr0 : 32'h0; + 8'h7b: wb_rf_dout <= #1 ch14_conf[0] ? ch14_am0 : 32'h0; + 8'h7c: wb_rf_dout <= #1 ch14_conf[0] ? ch14_adr1 : 32'h0; + 8'h7d: wb_rf_dout <= #1 ch14_conf[0] ? ch14_am1 : 32'h0; + 8'h7e: wb_rf_dout <= #1 ch14_conf[0] ? pointer14 : 32'h0; + 8'h7f: wb_rf_dout <= #1 ch14_conf[0] ? sw_pointer14 : 32'h0; + + 8'h80: wb_rf_dout <= #1 ch15_conf[0] ? ch15_csr : 32'h0; + 8'h81: wb_rf_dout <= #1 ch15_conf[0] ? ch15_txsz : 32'h0; + 8'h82: wb_rf_dout <= #1 ch15_conf[0] ? ch15_adr0 : 32'h0; + 8'h83: wb_rf_dout <= #1 ch15_conf[0] ? ch15_am0 : 32'h0; + 8'h84: wb_rf_dout <= #1 ch15_conf[0] ? ch15_adr1 : 32'h0; + 8'h85: wb_rf_dout <= #1 ch15_conf[0] ? ch15_am1 : 32'h0; + 8'h86: wb_rf_dout <= #1 ch15_conf[0] ? pointer15 : 32'h0; + 8'h87: wb_rf_dout <= #1 ch15_conf[0] ? sw_pointer15 : 32'h0; + + 8'h88: wb_rf_dout <= #1 ch16_conf[0] ? ch16_csr : 32'h0; + 8'h89: wb_rf_dout <= #1 ch16_conf[0] ? ch16_txsz : 32'h0; + 8'h8a: wb_rf_dout <= #1 ch16_conf[0] ? ch16_adr0 : 32'h0; + 8'h8b: wb_rf_dout <= #1 ch16_conf[0] ? ch16_am0 : 32'h0; + 8'h8c: wb_rf_dout <= #1 ch16_conf[0] ? ch16_adr1 : 32'h0; + 8'h8d: wb_rf_dout <= #1 ch16_conf[0] ? ch16_am1 : 32'h0; + 8'h8e: wb_rf_dout <= #1 ch16_conf[0] ? pointer16 : 32'h0; + 8'h8f: wb_rf_dout <= #1 ch16_conf[0] ? sw_pointer16 : 32'h0; + + 8'h90: wb_rf_dout <= #1 ch17_conf[0] ? ch17_csr : 32'h0; + 8'h91: wb_rf_dout <= #1 ch17_conf[0] ? ch17_txsz : 32'h0; + 8'h92: wb_rf_dout <= #1 ch17_conf[0] ? ch17_adr0 : 32'h0; + 8'h93: wb_rf_dout <= #1 ch17_conf[0] ? ch17_am0 : 32'h0; + 8'h94: wb_rf_dout <= #1 ch17_conf[0] ? ch17_adr1 : 32'h0; + 8'h95: wb_rf_dout <= #1 ch17_conf[0] ? ch17_am1 : 32'h0; + 8'h96: wb_rf_dout <= #1 ch17_conf[0] ? pointer17 : 32'h0; + 8'h97: wb_rf_dout <= #1 ch17_conf[0] ? sw_pointer17 : 32'h0; + + 8'h98: wb_rf_dout <= #1 ch18_conf[0] ? ch18_csr : 32'h0; + 8'h99: wb_rf_dout <= #1 ch18_conf[0] ? ch18_txsz : 32'h0; + 8'h9a: wb_rf_dout <= #1 ch18_conf[0] ? ch18_adr0 : 32'h0; + 8'h9b: wb_rf_dout <= #1 ch18_conf[0] ? ch18_am0 : 32'h0; + 8'h9c: wb_rf_dout <= #1 ch18_conf[0] ? ch18_adr1 : 32'h0; + 8'h9d: wb_rf_dout <= #1 ch18_conf[0] ? ch18_am1 : 32'h0; + 8'h9e: wb_rf_dout <= #1 ch18_conf[0] ? pointer18 : 32'h0; + 8'h9f: wb_rf_dout <= #1 ch18_conf[0] ? sw_pointer18 : 32'h0; + + 8'ha0: wb_rf_dout <= #1 ch19_conf[0] ? ch19_csr : 32'h0; + 8'ha1: wb_rf_dout <= #1 ch19_conf[0] ? ch19_txsz : 32'h0; + 8'ha2: wb_rf_dout <= #1 ch19_conf[0] ? ch19_adr0 : 32'h0; + 8'ha3: wb_rf_dout <= #1 ch19_conf[0] ? ch19_am0 : 32'h0; + 8'ha4: wb_rf_dout <= #1 ch19_conf[0] ? ch19_adr1 : 32'h0; + 8'ha5: wb_rf_dout <= #1 ch19_conf[0] ? ch19_am1 : 32'h0; + 8'ha6: wb_rf_dout <= #1 ch19_conf[0] ? pointer19 : 32'h0; + 8'ha7: wb_rf_dout <= #1 ch19_conf[0] ? sw_pointer19 : 32'h0; + + 8'ha8: wb_rf_dout <= #1 ch20_conf[0] ? ch20_csr : 32'h0; + 8'ha9: wb_rf_dout <= #1 ch20_conf[0] ? ch20_txsz : 32'h0; + 8'haa: wb_rf_dout <= #1 ch20_conf[0] ? ch20_adr0 : 32'h0; + 8'hab: wb_rf_dout <= #1 ch20_conf[0] ? ch20_am0 : 32'h0; + 8'hac: wb_rf_dout <= #1 ch20_conf[0] ? ch20_adr1 : 32'h0; + 8'had: wb_rf_dout <= #1 ch20_conf[0] ? ch20_am1 : 32'h0; + 8'hae: wb_rf_dout <= #1 ch20_conf[0] ? pointer20 : 32'h0; + 8'haf: wb_rf_dout <= #1 ch20_conf[0] ? sw_pointer20 : 32'h0; + + 8'hb0: wb_rf_dout <= #1 ch21_conf[0] ? ch21_csr : 32'h0; + 8'hb1: wb_rf_dout <= #1 ch21_conf[0] ? ch21_txsz : 32'h0; + 8'hb2: wb_rf_dout <= #1 ch21_conf[0] ? ch21_adr0 : 32'h0; + 8'hb3: wb_rf_dout <= #1 ch21_conf[0] ? ch21_am0 : 32'h0; + 8'hb4: wb_rf_dout <= #1 ch21_conf[0] ? ch21_adr1 : 32'h0; + 8'hb5: wb_rf_dout <= #1 ch21_conf[0] ? ch21_am1 : 32'h0; + 8'hb6: wb_rf_dout <= #1 ch21_conf[0] ? pointer21 : 32'h0; + 8'hb7: wb_rf_dout <= #1 ch21_conf[0] ? sw_pointer21 : 32'h0; + + 8'hb8: wb_rf_dout <= #1 ch22_conf[0] ? ch22_csr : 32'h0; + 8'hb9: wb_rf_dout <= #1 ch22_conf[0] ? ch22_txsz : 32'h0; + 8'hba: wb_rf_dout <= #1 ch22_conf[0] ? ch22_adr0 : 32'h0; + 8'hbb: wb_rf_dout <= #1 ch22_conf[0] ? ch22_am0 : 32'h0; + 8'hbc: wb_rf_dout <= #1 ch22_conf[0] ? ch22_adr1 : 32'h0; + 8'hbd: wb_rf_dout <= #1 ch22_conf[0] ? ch22_am1 : 32'h0; + 8'hbe: wb_rf_dout <= #1 ch22_conf[0] ? pointer22 : 32'h0; + 8'hbf: wb_rf_dout <= #1 ch22_conf[0] ? sw_pointer22 : 32'h0; + + 8'hc0: wb_rf_dout <= #1 ch23_conf[0] ? ch23_csr : 32'h0; + 8'hc1: wb_rf_dout <= #1 ch23_conf[0] ? ch23_txsz : 32'h0; + 8'hc2: wb_rf_dout <= #1 ch23_conf[0] ? ch23_adr0 : 32'h0; + 8'hc3: wb_rf_dout <= #1 ch23_conf[0] ? ch23_am0 : 32'h0; + 8'hc4: wb_rf_dout <= #1 ch23_conf[0] ? ch23_adr1 : 32'h0; + 8'hc5: wb_rf_dout <= #1 ch23_conf[0] ? ch23_am1 : 32'h0; + 8'hc6: wb_rf_dout <= #1 ch23_conf[0] ? pointer23 : 32'h0; + 8'hc7: wb_rf_dout <= #1 ch23_conf[0] ? sw_pointer23 : 32'h0; + + 8'hc8: wb_rf_dout <= #1 ch24_conf[0] ? ch24_csr : 32'h0; + 8'hc9: wb_rf_dout <= #1 ch24_conf[0] ? ch24_txsz : 32'h0; + 8'hca: wb_rf_dout <= #1 ch24_conf[0] ? ch24_adr0 : 32'h0; + 8'hcb: wb_rf_dout <= #1 ch24_conf[0] ? ch24_am0 : 32'h0; + 8'hcc: wb_rf_dout <= #1 ch24_conf[0] ? ch24_adr1 : 32'h0; + 8'hcd: wb_rf_dout <= #1 ch24_conf[0] ? ch24_am1 : 32'h0; + 8'hce: wb_rf_dout <= #1 ch24_conf[0] ? pointer24 : 32'h0; + 8'hcf: wb_rf_dout <= #1 ch24_conf[0] ? sw_pointer24 : 32'h0; + + 8'hd0: wb_rf_dout <= #1 ch25_conf[0] ? ch25_csr : 32'h0; + 8'hd1: wb_rf_dout <= #1 ch25_conf[0] ? ch25_txsz : 32'h0; + 8'hd2: wb_rf_dout <= #1 ch25_conf[0] ? ch25_adr0 : 32'h0; + 8'hd3: wb_rf_dout <= #1 ch25_conf[0] ? ch25_am0 : 32'h0; + 8'hd4: wb_rf_dout <= #1 ch25_conf[0] ? ch25_adr1 : 32'h0; + 8'hd5: wb_rf_dout <= #1 ch25_conf[0] ? ch25_am1 : 32'h0; + 8'hd6: wb_rf_dout <= #1 ch25_conf[0] ? pointer25 : 32'h0; + 8'hd7: wb_rf_dout <= #1 ch25_conf[0] ? sw_pointer25 : 32'h0; + + 8'hd8: wb_rf_dout <= #1 ch26_conf[0] ? ch26_csr : 32'h0; + 8'hd9: wb_rf_dout <= #1 ch26_conf[0] ? ch26_txsz : 32'h0; + 8'hda: wb_rf_dout <= #1 ch26_conf[0] ? ch26_adr0 : 32'h0; + 8'hdb: wb_rf_dout <= #1 ch26_conf[0] ? ch26_am0 : 32'h0; + 8'hdc: wb_rf_dout <= #1 ch26_conf[0] ? ch26_adr1 : 32'h0; + 8'hdd: wb_rf_dout <= #1 ch26_conf[0] ? ch26_am1 : 32'h0; + 8'hde: wb_rf_dout <= #1 ch26_conf[0] ? pointer26 : 32'h0; + 8'hdf: wb_rf_dout <= #1 ch26_conf[0] ? sw_pointer26 : 32'h0; + + 8'he0: wb_rf_dout <= #1 ch27_conf[0] ? ch27_csr : 32'h0; + 8'he1: wb_rf_dout <= #1 ch27_conf[0] ? ch27_txsz : 32'h0; + 8'he2: wb_rf_dout <= #1 ch27_conf[0] ? ch27_adr0 : 32'h0; + 8'he3: wb_rf_dout <= #1 ch27_conf[0] ? ch27_am0 : 32'h0; + 8'he4: wb_rf_dout <= #1 ch27_conf[0] ? ch27_adr1 : 32'h0; + 8'he5: wb_rf_dout <= #1 ch27_conf[0] ? ch27_am1 : 32'h0; + 8'he6: wb_rf_dout <= #1 ch27_conf[0] ? pointer27 : 32'h0; + 8'he7: wb_rf_dout <= #1 ch27_conf[0] ? sw_pointer27 : 32'h0; + + 8'he8: wb_rf_dout <= #1 ch28_conf[0] ? ch28_csr : 32'h0; + 8'he9: wb_rf_dout <= #1 ch28_conf[0] ? ch28_txsz : 32'h0; + 8'hea: wb_rf_dout <= #1 ch28_conf[0] ? ch28_adr0 : 32'h0; + 8'heb: wb_rf_dout <= #1 ch28_conf[0] ? ch28_am0 : 32'h0; + 8'hec: wb_rf_dout <= #1 ch28_conf[0] ? ch28_adr1 : 32'h0; + 8'hed: wb_rf_dout <= #1 ch28_conf[0] ? ch28_am1 : 32'h0; + 8'hee: wb_rf_dout <= #1 ch28_conf[0] ? pointer28 : 32'h0; + 8'hef: wb_rf_dout <= #1 ch28_conf[0] ? sw_pointer28 : 32'h0; + + 8'hf0: wb_rf_dout <= #1 ch29_conf[0] ? ch29_csr : 32'h0; + 8'hf1: wb_rf_dout <= #1 ch29_conf[0] ? ch29_txsz : 32'h0; + 8'hf2: wb_rf_dout <= #1 ch29_conf[0] ? ch29_adr0 : 32'h0; + 8'hf3: wb_rf_dout <= #1 ch29_conf[0] ? ch29_am0 : 32'h0; + 8'hf4: wb_rf_dout <= #1 ch29_conf[0] ? ch29_adr1 : 32'h0; + 8'hf5: wb_rf_dout <= #1 ch29_conf[0] ? ch29_am1 : 32'h0; + 8'hf6: wb_rf_dout <= #1 ch29_conf[0] ? pointer29 : 32'h0; + 8'hf7: wb_rf_dout <= #1 ch29_conf[0] ? sw_pointer29 : 32'h0; + + 8'hf8: wb_rf_dout <= #1 ch30_conf[0] ? ch30_csr : 32'h0; + 8'hf9: wb_rf_dout <= #1 ch30_conf[0] ? ch30_txsz : 32'h0; + 8'hfa: wb_rf_dout <= #1 ch30_conf[0] ? ch30_adr0 : 32'h0; + 8'hfb: wb_rf_dout <= #1 ch30_conf[0] ? ch30_am0 : 32'h0; + 8'hfc: wb_rf_dout <= #1 ch30_conf[0] ? ch30_adr1 : 32'h0; + 8'hfd: wb_rf_dout <= #1 ch30_conf[0] ? ch30_am1 : 32'h0; + 8'hfe: wb_rf_dout <= #1 ch30_conf[0] ? pointer30 : 32'h0; + 8'hff: wb_rf_dout <= #1 ch30_conf[0] ? sw_pointer30 : 32'h0; + + endcase + + +//////////////////////////////////////////////////////////////////// +// +// WISHBONE Register Write Logic +// And DMA Engine register Update Logic +// + +// Global Registers +assign csr_we = wb_rf_we & (wb_rf_adr == 8'h0); +assign int_maska_we = wb_rf_we & (wb_rf_adr == 8'h1); +assign int_maskb_we = wb_rf_we & (wb_rf_adr == 8'h2); + +// --------------------------------------------------- + +always @(posedge clk or negedge rst) + if(!rst) csr_r <= #1 8'h0; + else + if(csr_we) csr_r <= #1 wb_rf_din[7:0]; + +// --------------------------------------------------- +// INT_MASK +always @(posedge clk or negedge rst) + if(!rst) int_maska_r <= #1 31'h0; + else + if(int_maska_we) int_maska_r <= #1 wb_rf_din[30:0]; + +always @(posedge clk or negedge rst) + if(!rst) int_maskb_r <= #1 31'h0; + else + if(int_maskb_we) int_maskb_r <= #1 wb_rf_din[30:0]; + +//////////////////////////////////////////////////////////////////// +// +// Interrupts +// + +assign int_srca = {1'b0, (int_maska_r & ch_int) }; +assign int_srcb = {1'b0, (int_maskb_r & ch_int) }; + +// Interrupt Outputs +always @(posedge clk) + inta_o <= #1 |int_srca; + +always @(posedge clk) + intb_o <= #1 |int_srcb; + +//////////////////////////////////////////////////////////////////// +// +// Channel Register File +// + +// chXX_conf = { CBUF, ED, ARS, EN } + +wb_dma_ch_rf #(0, ch0_conf[0], ch0_conf[1], ch0_conf[2], ch0_conf[3]) u0( + .clk( clk ), + .rst( rst ), + .pointer( pointer0 ), + .pointer_s( pointer0_s ), + .ch_csr( ch0_csr ), + .ch_txsz( ch0_txsz ), + .ch_adr0( ch0_adr0 ), + .ch_adr1( ch0_adr1 ), + .ch_am0( ch0_am0 ), + .ch_am1( ch0_am1 ), + .sw_pointer( sw_pointer0 ), + .ch_stop( ch_stop[0] ), + .ch_dis( ch_dis[0] ), + .int( ch_int[0] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[0] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[0] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(1, ch1_conf[0], ch1_conf[1], ch1_conf[2], ch1_conf[3]) u1( + .clk( clk ), + .rst( rst ), + .pointer( pointer1 ), + .pointer_s( pointer1_s ), + .ch_csr( ch1_csr ), + .ch_txsz( ch1_txsz ), + .ch_adr0( ch1_adr0 ), + .ch_adr1( ch1_adr1 ), + .ch_am0( ch1_am0 ), + .ch_am1( ch1_am1 ), + .sw_pointer( sw_pointer1 ), + .ch_stop( ch_stop[1] ), + .ch_dis( ch_dis[1] ), + .int( ch_int[1] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[1] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[1] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(2, ch2_conf[0], ch2_conf[1], ch2_conf[2], ch2_conf[3]) u2( + .clk( clk ), + .rst( rst ), + .pointer( pointer2 ), + .pointer_s( pointer2_s ), + .ch_csr( ch2_csr ), + .ch_txsz( ch2_txsz ), + .ch_adr0( ch2_adr0 ), + .ch_adr1( ch2_adr1 ), + .ch_am0( ch2_am0 ), + .ch_am1( ch2_am1 ), + .sw_pointer( sw_pointer2 ), + .ch_stop( ch_stop[2] ), + .ch_dis( ch_dis[2] ), + .int( ch_int[2] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[2] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[2] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(3, ch3_conf[0], ch3_conf[1], ch3_conf[2], ch3_conf[3]) u3( + .clk( clk ), + .rst( rst ), + .pointer( pointer3 ), + .pointer_s( pointer3_s ), + .ch_csr( ch3_csr ), + .ch_txsz( ch3_txsz ), + .ch_adr0( ch3_adr0 ), + .ch_adr1( ch3_adr1 ), + .ch_am0( ch3_am0 ), + .ch_am1( ch3_am1 ), + .sw_pointer( sw_pointer3 ), + .ch_stop( ch_stop[3] ), + .ch_dis( ch_dis[3] ), + .int( ch_int[3] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[3] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[3] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(4, ch4_conf[0], ch4_conf[1], ch4_conf[2], ch4_conf[3]) u4( + .clk( clk ), + .rst( rst ), + .pointer( pointer4 ), + .pointer_s( pointer4_s ), + .ch_csr( ch4_csr ), + .ch_txsz( ch4_txsz ), + .ch_adr0( ch4_adr0 ), + .ch_adr1( ch4_adr1 ), + .ch_am0( ch4_am0 ), + .ch_am1( ch4_am1 ), + .sw_pointer( sw_pointer4 ), + .ch_stop( ch_stop[4] ), + .ch_dis( ch_dis[4] ), + .int( ch_int[4] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[4] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[4] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(5, ch5_conf[0], ch5_conf[1], ch5_conf[2], ch5_conf[3]) u5( + .clk( clk ), + .rst( rst ), + .pointer( pointer5 ), + .pointer_s( pointer5_s ), + .ch_csr( ch5_csr ), + .ch_txsz( ch5_txsz ), + .ch_adr0( ch5_adr0 ), + .ch_adr1( ch5_adr1 ), + .ch_am0( ch5_am0 ), + .ch_am1( ch5_am1 ), + .sw_pointer( sw_pointer5 ), + .ch_stop( ch_stop[5] ), + .ch_dis( ch_dis[5] ), + .int( ch_int[5] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[5] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[5] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(6, ch6_conf[0], ch6_conf[1], ch6_conf[2], ch6_conf[3]) u6( + .clk( clk ), + .rst( rst ), + .pointer( pointer6 ), + .pointer_s( pointer6_s ), + .ch_csr( ch6_csr ), + .ch_txsz( ch6_txsz ), + .ch_adr0( ch6_adr0 ), + .ch_adr1( ch6_adr1 ), + .ch_am0( ch6_am0 ), + .ch_am1( ch6_am1 ), + .sw_pointer( sw_pointer6 ), + .ch_stop( ch_stop[6] ), + .ch_dis( ch_dis[6] ), + .int( ch_int[6] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[6] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[6] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(7, ch7_conf[0], ch7_conf[1], ch7_conf[2], ch7_conf[3]) u7( + .clk( clk ), + .rst( rst ), + .pointer( pointer7 ), + .pointer_s( pointer7_s ), + .ch_csr( ch7_csr ), + .ch_txsz( ch7_txsz ), + .ch_adr0( ch7_adr0 ), + .ch_adr1( ch7_adr1 ), + .ch_am0( ch7_am0 ), + .ch_am1( ch7_am1 ), + .sw_pointer( sw_pointer7 ), + .ch_stop( ch_stop[7] ), + .ch_dis( ch_dis[7] ), + .int( ch_int[7] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[7] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[7] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(8, ch8_conf[0], ch8_conf[1], ch8_conf[2], ch8_conf[3]) u8( + .clk( clk ), + .rst( rst ), + .pointer( pointer8 ), + .pointer_s( pointer8_s ), + .ch_csr( ch8_csr ), + .ch_txsz( ch8_txsz ), + .ch_adr0( ch8_adr0 ), + .ch_adr1( ch8_adr1 ), + .ch_am0( ch8_am0 ), + .ch_am1( ch8_am1 ), + .sw_pointer( sw_pointer8 ), + .ch_stop( ch_stop[8] ), + .ch_dis( ch_dis[8] ), + .int( ch_int[8] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[8] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[8] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(9, ch9_conf[0], ch9_conf[1], ch9_conf[2], ch9_conf[3]) u9( + .clk( clk ), + .rst( rst ), + .pointer( pointer9 ), + .pointer_s( pointer9_s ), + .ch_csr( ch9_csr ), + .ch_txsz( ch9_txsz ), + .ch_adr0( ch9_adr0 ), + .ch_adr1( ch9_adr1 ), + .ch_am0( ch9_am0 ), + .ch_am1( ch9_am1 ), + .sw_pointer( sw_pointer9 ), + .ch_stop( ch_stop[9] ), + .ch_dis( ch_dis[9] ), + .int( ch_int[9] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[9] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[9] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(10, ch10_conf[0], ch10_conf[1], ch10_conf[2], ch10_conf[3]) u10( + .clk( clk ), + .rst( rst ), + .pointer( pointer10 ), + .pointer_s( pointer10_s ), + .ch_csr( ch10_csr ), + .ch_txsz( ch10_txsz ), + .ch_adr0( ch10_adr0 ), + .ch_adr1( ch10_adr1 ), + .ch_am0( ch10_am0 ), + .ch_am1( ch10_am1 ), + .sw_pointer( sw_pointer10 ), + .ch_stop( ch_stop[10] ), + .ch_dis( ch_dis[10] ), + .int( ch_int[10] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[10] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[10] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(11, ch11_conf[0], ch11_conf[1], ch11_conf[2], ch11_conf[3]) u11( + .clk( clk ), + .rst( rst ), + .pointer( pointer11 ), + .pointer_s( pointer11_s ), + .ch_csr( ch11_csr ), + .ch_txsz( ch11_txsz ), + .ch_adr0( ch11_adr0 ), + .ch_adr1( ch11_adr1 ), + .ch_am0( ch11_am0 ), + .ch_am1( ch11_am1 ), + .sw_pointer( sw_pointer11 ), + .ch_stop( ch_stop[11] ), + .ch_dis( ch_dis[11] ), + .int( ch_int[11] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[11] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[11] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(12, ch12_conf[0], ch12_conf[1], ch12_conf[2], ch12_conf[3]) u12( + .clk( clk ), + .rst( rst ), + .pointer( pointer12 ), + .pointer_s( pointer12_s ), + .ch_csr( ch12_csr ), + .ch_txsz( ch12_txsz ), + .ch_adr0( ch12_adr0 ), + .ch_adr1( ch12_adr1 ), + .ch_am0( ch12_am0 ), + .ch_am1( ch12_am1 ), + .sw_pointer( sw_pointer12 ), + .ch_stop( ch_stop[12] ), + .ch_dis( ch_dis[12] ), + .int( ch_int[12] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[12] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[12] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(13, ch13_conf[0], ch13_conf[1], ch13_conf[2], ch13_conf[3]) u13( + .clk( clk ), + .rst( rst ), + .pointer( pointer13 ), + .pointer_s( pointer13_s ), + .ch_csr( ch13_csr ), + .ch_txsz( ch13_txsz ), + .ch_adr0( ch13_adr0 ), + .ch_adr1( ch13_adr1 ), + .ch_am0( ch13_am0 ), + .ch_am1( ch13_am1 ), + .sw_pointer( sw_pointer13 ), + .ch_stop( ch_stop[13] ), + .ch_dis( ch_dis[13] ), + .int( ch_int[13] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[13] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[13] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(14, ch14_conf[0], ch14_conf[1], ch14_conf[2], ch14_conf[3]) u14( + .clk( clk ), + .rst( rst ), + .pointer( pointer14 ), + .pointer_s( pointer14_s ), + .ch_csr( ch14_csr ), + .ch_txsz( ch14_txsz ), + .ch_adr0( ch14_adr0 ), + .ch_adr1( ch14_adr1 ), + .ch_am0( ch14_am0 ), + .ch_am1( ch14_am1 ), + .sw_pointer( sw_pointer14 ), + .ch_stop( ch_stop[14] ), + .ch_dis( ch_dis[14] ), + .int( ch_int[14] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[14] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[14] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(15, ch15_conf[0], ch15_conf[1], ch15_conf[2], ch15_conf[3]) u15( + .clk( clk ), + .rst( rst ), + .pointer( pointer15 ), + .pointer_s( pointer15_s ), + .ch_csr( ch15_csr ), + .ch_txsz( ch15_txsz ), + .ch_adr0( ch15_adr0 ), + .ch_adr1( ch15_adr1 ), + .ch_am0( ch15_am0 ), + .ch_am1( ch15_am1 ), + .sw_pointer( sw_pointer15 ), + .ch_stop( ch_stop[15] ), + .ch_dis( ch_dis[15] ), + .int( ch_int[15] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[15] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[15] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(16, ch16_conf[0], ch16_conf[1], ch16_conf[2], ch16_conf[3]) u16( + .clk( clk ), + .rst( rst ), + .pointer( pointer16 ), + .pointer_s( pointer16_s ), + .ch_csr( ch16_csr ), + .ch_txsz( ch16_txsz ), + .ch_adr0( ch16_adr0 ), + .ch_adr1( ch16_adr1 ), + .ch_am0( ch16_am0 ), + .ch_am1( ch16_am1 ), + .sw_pointer( sw_pointer16 ), + .ch_stop( ch_stop[16] ), + .ch_dis( ch_dis[16] ), + .int( ch_int[16] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[16] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[16] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(17, ch17_conf[0], ch17_conf[1], ch17_conf[2], ch17_conf[3]) u17( + .clk( clk ), + .rst( rst ), + .pointer( pointer17 ), + .pointer_s( pointer17_s ), + .ch_csr( ch17_csr ), + .ch_txsz( ch17_txsz ), + .ch_adr0( ch17_adr0 ), + .ch_adr1( ch17_adr1 ), + .ch_am0( ch17_am0 ), + .ch_am1( ch17_am1 ), + .sw_pointer( sw_pointer17 ), + .ch_stop( ch_stop[17] ), + .ch_dis( ch_dis[17] ), + .int( ch_int[17] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[17] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[17] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(18, ch18_conf[0], ch18_conf[1], ch18_conf[2], ch18_conf[3]) u18( + .clk( clk ), + .rst( rst ), + .pointer( pointer18 ), + .pointer_s( pointer18_s ), + .ch_csr( ch18_csr ), + .ch_txsz( ch18_txsz ), + .ch_adr0( ch18_adr0 ), + .ch_adr1( ch18_adr1 ), + .ch_am0( ch18_am0 ), + .ch_am1( ch18_am1 ), + .sw_pointer( sw_pointer18 ), + .ch_stop( ch_stop[18] ), + .ch_dis( ch_dis[18] ), + .int( ch_int[18] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[18] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[18] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(19, ch19_conf[0], ch19_conf[1], ch19_conf[2], ch19_conf[3]) u19( + .clk( clk ), + .rst( rst ), + .pointer( pointer19 ), + .pointer_s( pointer19_s ), + .ch_csr( ch19_csr ), + .ch_txsz( ch19_txsz ), + .ch_adr0( ch19_adr0 ), + .ch_adr1( ch19_adr1 ), + .ch_am0( ch19_am0 ), + .ch_am1( ch19_am1 ), + .sw_pointer( sw_pointer19 ), + .ch_stop( ch_stop[19] ), + .ch_dis( ch_dis[19] ), + .int( ch_int[19] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[19] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[19] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(20, ch20_conf[0], ch20_conf[1], ch20_conf[2], ch20_conf[3]) u20( + .clk( clk ), + .rst( rst ), + .pointer( pointer20 ), + .pointer_s( pointer20_s ), + .ch_csr( ch20_csr ), + .ch_txsz( ch20_txsz ), + .ch_adr0( ch20_adr0 ), + .ch_adr1( ch20_adr1 ), + .ch_am0( ch20_am0 ), + .ch_am1( ch20_am1 ), + .sw_pointer( sw_pointer20 ), + .ch_stop( ch_stop[20] ), + .ch_dis( ch_dis[20] ), + .int( ch_int[20] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[20] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[20] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(21, ch21_conf[0], ch21_conf[1], ch21_conf[2], ch21_conf[3]) u21( + .clk( clk ), + .rst( rst ), + .pointer( pointer21 ), + .pointer_s( pointer21_s ), + .ch_csr( ch21_csr ), + .ch_txsz( ch21_txsz ), + .ch_adr0( ch21_adr0 ), + .ch_adr1( ch21_adr1 ), + .ch_am0( ch21_am0 ), + .ch_am1( ch21_am1 ), + .sw_pointer( sw_pointer21 ), + .ch_stop( ch_stop[21] ), + .ch_dis( ch_dis[21] ), + .int( ch_int[21] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[21] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[21] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(22, ch22_conf[0], ch22_conf[1], ch22_conf[2], ch22_conf[3]) u22( + .clk( clk ), + .rst( rst ), + .pointer( pointer22 ), + .pointer_s( pointer22_s ), + .ch_csr( ch22_csr ), + .ch_txsz( ch22_txsz ), + .ch_adr0( ch22_adr0 ), + .ch_adr1( ch22_adr1 ), + .ch_am0( ch22_am0 ), + .ch_am1( ch22_am1 ), + .sw_pointer( sw_pointer22 ), + .ch_stop( ch_stop[22] ), + .ch_dis( ch_dis[22] ), + .int( ch_int[22] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[22] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[22] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(23, ch23_conf[0], ch23_conf[1], ch23_conf[2], ch23_conf[3]) u23( + .clk( clk ), + .rst( rst ), + .pointer( pointer23 ), + .pointer_s( pointer23_s ), + .ch_csr( ch23_csr ), + .ch_txsz( ch23_txsz ), + .ch_adr0( ch23_adr0 ), + .ch_adr1( ch23_adr1 ), + .ch_am0( ch23_am0 ), + .ch_am1( ch23_am1 ), + .sw_pointer( sw_pointer23 ), + .ch_stop( ch_stop[23] ), + .ch_dis( ch_dis[23] ), + .int( ch_int[23] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[23] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[23] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(24, ch24_conf[0], ch24_conf[1], ch24_conf[2], ch24_conf[3]) u24( + .clk( clk ), + .rst( rst ), + .pointer( pointer24 ), + .pointer_s( pointer24_s ), + .ch_csr( ch24_csr ), + .ch_txsz( ch24_txsz ), + .ch_adr0( ch24_adr0 ), + .ch_adr1( ch24_adr1 ), + .ch_am0( ch24_am0 ), + .ch_am1( ch24_am1 ), + .sw_pointer( sw_pointer24 ), + .ch_stop( ch_stop[24] ), + .ch_dis( ch_dis[24] ), + .int( ch_int[24] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[24] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[24] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(25, ch25_conf[0], ch25_conf[1], ch25_conf[2], ch25_conf[3]) u25( + .clk( clk ), + .rst( rst ), + .pointer( pointer25 ), + .pointer_s( pointer25_s ), + .ch_csr( ch25_csr ), + .ch_txsz( ch25_txsz ), + .ch_adr0( ch25_adr0 ), + .ch_adr1( ch25_adr1 ), + .ch_am0( ch25_am0 ), + .ch_am1( ch25_am1 ), + .sw_pointer( sw_pointer25 ), + .ch_stop( ch_stop[25] ), + .ch_dis( ch_dis[25] ), + .int( ch_int[25] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[25] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[25] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(26, ch26_conf[0], ch26_conf[1], ch26_conf[2], ch26_conf[3]) u26( + .clk( clk ), + .rst( rst ), + .pointer( pointer26 ), + .pointer_s( pointer26_s ), + .ch_csr( ch26_csr ), + .ch_txsz( ch26_txsz ), + .ch_adr0( ch26_adr0 ), + .ch_adr1( ch26_adr1 ), + .ch_am0( ch26_am0 ), + .ch_am1( ch26_am1 ), + .sw_pointer( sw_pointer26 ), + .ch_stop( ch_stop[26] ), + .ch_dis( ch_dis[26] ), + .int( ch_int[26] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[26] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[26] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(27, ch27_conf[0], ch27_conf[1], ch27_conf[2], ch27_conf[3]) u27( + .clk( clk ), + .rst( rst ), + .pointer( pointer27 ), + .pointer_s( pointer27_s ), + .ch_csr( ch27_csr ), + .ch_txsz( ch27_txsz ), + .ch_adr0( ch27_adr0 ), + .ch_adr1( ch27_adr1 ), + .ch_am0( ch27_am0 ), + .ch_am1( ch27_am1 ), + .sw_pointer( sw_pointer27 ), + .ch_stop( ch_stop[27] ), + .ch_dis( ch_dis[27] ), + .int( ch_int[27] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[27] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[27] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(28, ch28_conf[0], ch28_conf[1], ch28_conf[2], ch28_conf[3]) u28( + .clk( clk ), + .rst( rst ), + .pointer( pointer28 ), + .pointer_s( pointer28_s ), + .ch_csr( ch28_csr ), + .ch_txsz( ch28_txsz ), + .ch_adr0( ch28_adr0 ), + .ch_adr1( ch28_adr1 ), + .ch_am0( ch28_am0 ), + .ch_am1( ch28_am1 ), + .sw_pointer( sw_pointer28 ), + .ch_stop( ch_stop[28] ), + .ch_dis( ch_dis[28] ), + .int( ch_int[28] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[28] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[28] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(29, ch29_conf[0], ch29_conf[1], ch29_conf[2], ch29_conf[3]) u29( + .clk( clk ), + .rst( rst ), + .pointer( pointer29 ), + .pointer_s( pointer29_s ), + .ch_csr( ch29_csr ), + .ch_txsz( ch29_txsz ), + .ch_adr0( ch29_adr0 ), + .ch_adr1( ch29_adr1 ), + .ch_am0( ch29_am0 ), + .ch_am1( ch29_am1 ), + .sw_pointer( sw_pointer29 ), + .ch_stop( ch_stop[29] ), + .ch_dis( ch_dis[29] ), + .int( ch_int[29] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[29] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[29] ), + .ptr_set( ptr_set ) + ); + +wb_dma_ch_rf #(30, ch30_conf[0], ch30_conf[1], ch30_conf[2], ch30_conf[3]) u30( + .clk( clk ), + .rst( rst ), + .pointer( pointer30 ), + .pointer_s( pointer30_s ), + .ch_csr( ch30_csr ), + .ch_txsz( ch30_txsz ), + .ch_adr0( ch30_adr0 ), + .ch_adr1( ch30_adr1 ), + .ch_am0( ch30_am0 ), + .ch_am1( ch30_am1 ), + .sw_pointer( sw_pointer30 ), + .ch_stop( ch_stop[30] ), + .ch_dis( ch_dis[30] ), + .int( ch_int[30] ), + .wb_rf_din( wb_rf_din ), + .wb_rf_adr( wb_rf_adr ), + .wb_rf_we( wb_rf_we ), + .wb_rf_re( wb_rf_re ), + .ch_sel( ch_sel ), + .ndnr( ndnr[30] ), + .dma_busy( dma_busy ), + .dma_err( dma_err ), + .dma_done( dma_done ), + .dma_done_all( dma_done_all ), + .de_csr( de_csr ), + .de_txsz( de_txsz ), + .de_adr0( de_adr0 ), + .de_adr1( de_adr1 ), + .de_csr_we( de_csr_we ), + .de_txsz_we( de_txsz_we ), + .de_adr0_we( de_adr0_we ), + .de_adr1_we( de_adr1_we ), + .de_fetch_descr(de_fetch_descr ), + .dma_rest( dma_rest[30] ), + .ptr_set( ptr_set ) + ); + +endmodule Index: wb_dma/trunk/rtl/verilog/wb_dma_de.v =================================================================== --- wb_dma/trunk/rtl/verilog/wb_dma_de.v (nonexistent) +++ wb_dma/trunk/rtl/verilog/wb_dma_de.v (revision 17) @@ -0,0 +1,628 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE DMA DMA Engine Core //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/wb_dma/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: wb_dma_de.v,v 1.3 2002-02-01 01:54:45 rudi Exp $ +// +// $Date: 2002-02-01 01:54:45 $ +// $Revision: 1.3 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.2 2001/08/15 05:40:30 rudi +// +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// - Added Section 3.10, describing DMA restart. +// +// Revision 1.1 2001/07/29 08:57:02 rudi +// +// +// 1) Changed Directory Structure +// 2) Added restart signal (REST) +// +// Revision 1.3 2001/06/13 02:26:48 rudi +// +// +// Small changes after running lint. +// +// Revision 1.2 2001/06/05 10:22:36 rudi +// +// +// - Added Support of up to 31 channels +// - Added support for 2,4 and 8 priority levels +// - Now can have up to 31 channels +// - Added many configuration items +// - Changed reset to async +// +// Revision 1.1.1.1 2001/03/19 13:10:44 rudi +// Initial Release +// +// +// + +`include "wb_dma_defines.v" + +module wb_dma_de(clk, rst, + + // WISHBONE MASTER INTERFACE 0 + mast0_go, mast0_we, mast0_adr, mast0_din, + mast0_dout, mast0_err, mast0_drdy, mast0_wait, + + // WISHBONE MASTER INTERFACE 1 + mast1_go, mast1_we, mast1_adr, mast1_din, + mast1_dout, mast1_err, mast1_drdy, mast1_wait, + + // DMA Engine Init & Setup + de_start, nd, csr, pointer, pointer_s, txsz, + adr0, adr1, am0, am1, + + // DMA Engine Register File Update Outputs + de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we, ptr_set, + de_csr, de_txsz, de_adr0, de_adr1, de_fetch_descr, + + // DMA Engine Control Outputs + next_ch, de_ack, + + // DMA Engine Status + pause_req, paused, + dma_abort, dma_busy, dma_err, dma_done, dma_done_all + ); + +input clk, rst; + +// -------------------------------------- +// WISHBONE MASTER INTERFACE 0 + +output mast0_go; // Perform a Master Cycle +output mast0_we; // Read/Write +output [31:0] mast0_adr; // Address for the transfer +input [31:0] mast0_din; // Internal Input Data +output [31:0] mast0_dout; // Internal Output Data +input mast0_err; // Indicates an error has occurred +input mast0_drdy; // Indicated that either data is available + // during a read, or that the master can accept + // the next data during a write +output mast0_wait; // Tells the master to insert wait cycles + // because data can not be accepted/provided + +// -------------------------------------- +// WISHBONE MASTER INTERFACE 1 + +output mast1_go; // Perform a Master Cycle +output mast1_we; // Read/Write +output [31:0] mast1_adr; // Address for the transfer +input [31:0] mast1_din; // Internal Input Data +output [31:0] mast1_dout; // Internal Output Data +input mast1_err; // Indicates an error has occurred +input mast1_drdy; // Indicated that either data is available + // during a read, or that the master can accept + // the next data during a write +output mast1_wait; // Tells the master to insert wait cycles + // because data can not be accepted/provided + +// -------------------------------------- +// DMA Engine Signals + +// DMA Engine Init & Setup +input de_start; // Start DMA Engine Indicator +input nd; // Next Descriptor Indicator +input [31:0] csr; // Selected Channel CSR +input [31:0] pointer; // Linked List Descriptor pointer +input [31:0] pointer_s; // Previous Pointer +input [31:0] txsz; // Selected Channel Transfer Size +input [31:0] adr0, adr1; // Selected Channel Addresses +input [31:0] am0, am1; // Selected Channel Address Masks + +// DMA Engine Register File Update Outputs +output de_csr_we; // Write enable for csr register +output de_txsz_we; // Write enable for txsz register +output de_adr0_we; // Write enable for adr0 register +output de_adr1_we; // Write enable for adr1 register +output ptr_set; // Set Pointer as Valid +output [31:0] de_csr; // Write Data for CSR when loading External Desc. +output [11:0] de_txsz; // Write back data for txsz register +output [31:0] de_adr0; // Write back data for adr0 register +output [31:0] de_adr1; // Write back data for adr1 register +output de_fetch_descr; // Indicates that we are fetching a descriptor + +// DMA Engine Control Outputs +output next_ch; // Indicates the DMA Engine is done +output de_ack; + +// DMA Abort from RF (software forced abort) +input dma_abort; + +// DMA Engine Status +input pause_req; +output paused; +output dma_busy, dma_err, dma_done, dma_done_all; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +parameter [10:0] // synopsys enum state + IDLE = 11'b000_0000_0001, + READ = 11'b000_0000_0010, + WRITE = 11'b000_0000_0100, + UPDATE = 11'b000_0000_1000, + LD_DESC1 = 11'b000_0001_0000, + LD_DESC2 = 11'b000_0010_0000, + LD_DESC3 = 11'b000_0100_0000, + LD_DESC4 = 11'b000_1000_0000, + LD_DESC5 = 11'b001_0000_0000, + WB = 11'b010_0000_0000, + PAUSE = 11'b100_0000_0000; + +reg [10:0] /* synopsys enum state */ state, next_state; +// synopsys state_vector state + +reg [31:0] mast0_adr, mast1_adr; + +reg [29:0] adr0_cnt, adr1_cnt; +wire [29:0] adr0_cnt_next, adr1_cnt_next; +wire [29:0] adr0_cnt_next1, adr1_cnt_next1; +reg adr0_inc, adr1_inc; + +reg [8:0] chunk_cnt; +reg chunk_dec; + +reg [11:0] tsz_cnt; +reg tsz_dec; + +reg de_txsz_we; +reg de_csr_we; +reg de_adr0_we; +reg de_adr1_we; +reg ld_desc_sel; + +wire chunk_cnt_is_0_d; +reg chunk_cnt_is_0_r; +wire tsz_cnt_is_0_d; +reg tsz_cnt_is_0_r; + +reg read, write; +reg read_r, write_r; +wire rd_ack, wr_ack; +reg rd_ack_r; + +reg chunk_0; +wire done; +reg dma_done_d; +reg dma_done_r; +reg dma_abort_r; +reg next_ch; +wire read_hold, write_hold; +reg write_hold_r; + +reg [1:0] ptr_adr_low; +reg m0_go; +reg m0_we; +reg ptr_set; + +// Aliases +wire a0_inc_en = csr[4]; // Source Address (Adr 0) increment enable +wire a1_inc_en = csr[3]; // Dest. Address (Adr 1) increment enable +wire ptr_valid = pointer[0]; +wire use_ed = csr[`WDMA_USE_ED]; + +reg mast0_drdy_r; +reg paused; + +reg de_fetch_descr; // Indicates that we are fetching a descriptor +//////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +always @(posedge clk) + dma_done_r <= #1 dma_done; + +// Address Counter 0 (Source Address) +always @(posedge clk) + if(de_start | ptr_set) adr0_cnt <= #1 adr0[31:2]; + else + if(adr0_inc & a0_inc_en) adr0_cnt <= #1 adr0_cnt_next; + +// 30 Bit Incrementor (registered) +wb_dma_inc30r u0( .clk( clk ), + .in( adr0_cnt ), + .out( adr0_cnt_next1 ) ); + +assign adr0_cnt_next[1:0] = adr0_cnt_next1[1:0]; +assign adr0_cnt_next[2] = am0[4] ? adr0_cnt_next1[2] : adr0_cnt[2]; +assign adr0_cnt_next[3] = am0[5] ? adr0_cnt_next1[3] : adr0_cnt[3]; +assign adr0_cnt_next[4] = am0[6] ? adr0_cnt_next1[4] : adr0_cnt[4]; +assign adr0_cnt_next[5] = am0[7] ? adr0_cnt_next1[5] : adr0_cnt[5]; +assign adr0_cnt_next[6] = am0[8] ? adr0_cnt_next1[6] : adr0_cnt[6]; +assign adr0_cnt_next[7] = am0[9] ? adr0_cnt_next1[7] : adr0_cnt[7]; +assign adr0_cnt_next[8] = am0[10] ? adr0_cnt_next1[8] : adr0_cnt[8]; +assign adr0_cnt_next[9] = am0[11] ? adr0_cnt_next1[9] : adr0_cnt[9]; +assign adr0_cnt_next[10] = am0[12] ? adr0_cnt_next1[10] : adr0_cnt[10]; +assign adr0_cnt_next[11] = am0[13] ? adr0_cnt_next1[11] : adr0_cnt[11]; +assign adr0_cnt_next[12] = am0[14] ? adr0_cnt_next1[12] : adr0_cnt[12]; +assign adr0_cnt_next[13] = am0[15] ? adr0_cnt_next1[13] : adr0_cnt[13]; +assign adr0_cnt_next[14] = am0[16] ? adr0_cnt_next1[14] : adr0_cnt[14]; +assign adr0_cnt_next[15] = am0[17] ? adr0_cnt_next1[15] : adr0_cnt[15]; +assign adr0_cnt_next[16] = am0[18] ? adr0_cnt_next1[16] : adr0_cnt[16]; +assign adr0_cnt_next[17] = am0[19] ? adr0_cnt_next1[17] : adr0_cnt[17]; +assign adr0_cnt_next[18] = am0[20] ? adr0_cnt_next1[18] : adr0_cnt[18]; +assign adr0_cnt_next[19] = am0[21] ? adr0_cnt_next1[19] : adr0_cnt[19]; +assign adr0_cnt_next[20] = am0[22] ? adr0_cnt_next1[20] : adr0_cnt[20]; +assign adr0_cnt_next[21] = am0[23] ? adr0_cnt_next1[21] : adr0_cnt[21]; +assign adr0_cnt_next[22] = am0[24] ? adr0_cnt_next1[22] : adr0_cnt[22]; +assign adr0_cnt_next[23] = am0[25] ? adr0_cnt_next1[23] : adr0_cnt[23]; +assign adr0_cnt_next[24] = am0[26] ? adr0_cnt_next1[24] : adr0_cnt[24]; +assign adr0_cnt_next[25] = am0[27] ? adr0_cnt_next1[25] : adr0_cnt[25]; +assign adr0_cnt_next[26] = am0[28] ? adr0_cnt_next1[26] : adr0_cnt[26]; +assign adr0_cnt_next[27] = am0[29] ? adr0_cnt_next1[27] : adr0_cnt[27]; +assign adr0_cnt_next[28] = am0[30] ? adr0_cnt_next1[28] : adr0_cnt[28]; +assign adr0_cnt_next[29] = am0[31] ? adr0_cnt_next1[29] : adr0_cnt[29]; + + +// Address Counter 1 (Destination Address) +always @(posedge clk) + if(de_start | ptr_set) adr1_cnt <= #1 adr1[31:2]; + else + if(adr1_inc & a1_inc_en) adr1_cnt <= #1 adr1_cnt_next; + +// 30 Bit Incrementor (registered) +wb_dma_inc30r u1( .clk( clk ), + .in( adr1_cnt ), + .out( adr1_cnt_next1 ) ); + +assign adr1_cnt_next[1:0] = adr1_cnt_next1[1:0]; +assign adr1_cnt_next[2] = am1[4] ? adr1_cnt_next1[2] : adr1_cnt[2]; +assign adr1_cnt_next[3] = am1[5] ? adr1_cnt_next1[3] : adr1_cnt[3]; +assign adr1_cnt_next[4] = am1[6] ? adr1_cnt_next1[4] : adr1_cnt[4]; +assign adr1_cnt_next[5] = am1[7] ? adr1_cnt_next1[5] : adr1_cnt[5]; +assign adr1_cnt_next[6] = am1[8] ? adr1_cnt_next1[6] : adr1_cnt[6]; +assign adr1_cnt_next[7] = am1[9] ? adr1_cnt_next1[7] : adr1_cnt[7]; +assign adr1_cnt_next[8] = am1[10] ? adr1_cnt_next1[8] : adr1_cnt[8]; +assign adr1_cnt_next[9] = am1[11] ? adr1_cnt_next1[9] : adr1_cnt[9]; +assign adr1_cnt_next[10] = am1[12] ? adr1_cnt_next1[10] : adr1_cnt[10]; +assign adr1_cnt_next[11] = am1[13] ? adr1_cnt_next1[11] : adr1_cnt[11]; +assign adr1_cnt_next[12] = am1[14] ? adr1_cnt_next1[12] : adr1_cnt[12]; +assign adr1_cnt_next[13] = am1[15] ? adr1_cnt_next1[13] : adr1_cnt[13]; +assign adr1_cnt_next[14] = am1[16] ? adr1_cnt_next1[14] : adr1_cnt[14]; +assign adr1_cnt_next[15] = am1[17] ? adr1_cnt_next1[15] : adr1_cnt[15]; +assign adr1_cnt_next[16] = am1[18] ? adr1_cnt_next1[16] : adr1_cnt[16]; +assign adr1_cnt_next[17] = am1[19] ? adr1_cnt_next1[17] : adr1_cnt[17]; +assign adr1_cnt_next[18] = am1[20] ? adr1_cnt_next1[18] : adr1_cnt[18]; +assign adr1_cnt_next[19] = am1[21] ? adr1_cnt_next1[19] : adr1_cnt[19]; +assign adr1_cnt_next[20] = am1[22] ? adr1_cnt_next1[20] : adr1_cnt[20]; +assign adr1_cnt_next[21] = am1[23] ? adr1_cnt_next1[21] : adr1_cnt[21]; +assign adr1_cnt_next[22] = am1[24] ? adr1_cnt_next1[22] : adr1_cnt[22]; +assign adr1_cnt_next[23] = am1[25] ? adr1_cnt_next1[23] : adr1_cnt[23]; +assign adr1_cnt_next[24] = am1[26] ? adr1_cnt_next1[24] : adr1_cnt[24]; +assign adr1_cnt_next[25] = am1[27] ? adr1_cnt_next1[25] : adr1_cnt[25]; +assign adr1_cnt_next[26] = am1[28] ? adr1_cnt_next1[26] : adr1_cnt[26]; +assign adr1_cnt_next[27] = am1[29] ? adr1_cnt_next1[27] : adr1_cnt[27]; +assign adr1_cnt_next[28] = am1[30] ? adr1_cnt_next1[28] : adr1_cnt[28]; +assign adr1_cnt_next[29] = am1[31] ? adr1_cnt_next1[29] : adr1_cnt[29]; + +// Chunk Counter +always @(posedge clk) + if(de_start) chunk_cnt <= #1 txsz[24:16]; + else + if(chunk_dec & !chunk_cnt_is_0_r) chunk_cnt <= #1 chunk_cnt - 9'h1; + +assign chunk_cnt_is_0_d = (chunk_cnt == 9'h0); + +always @(posedge clk) + chunk_cnt_is_0_r <= #1 chunk_cnt_is_0_d; + +// Total Size Counter +always @(posedge clk) + if(de_start | ptr_set) tsz_cnt <= #1 txsz[11:0]; + else + if(tsz_dec & !tsz_cnt_is_0_r) tsz_cnt <= #1 tsz_cnt - 12'h1; + +assign tsz_cnt_is_0_d = (tsz_cnt == 12'h0) & !txsz[15]; + +always @(posedge clk) + tsz_cnt_is_0_r <= #1 tsz_cnt_is_0_d; + +// Counter Control Logic +always @(posedge clk) + chunk_dec <= #1 read & !read_r; + +always @(posedge clk) + tsz_dec <= #1 read & !read_r; + +//always @(posedge clk) +always @(rd_ack or read_r) + adr0_inc = rd_ack & read_r; + +//always @(posedge clk) +always @(wr_ack or write_r) + adr1_inc = wr_ack & write_r; + +// Done logic +always @(posedge clk) + chunk_0 <= #1 (txsz[24:16] == 9'h0); + +assign done = chunk_0 ? tsz_cnt_is_0_d : (tsz_cnt_is_0_d | chunk_cnt_is_0_d); +assign dma_done = dma_done_d & done; +assign dma_done_all = dma_done_d & (tsz_cnt_is_0_r | (nd & chunk_cnt_is_0_d)); + +always @(posedge clk) + next_ch <= #1 dma_done; + +// Register Update Outputs +assign de_txsz = ld_desc_sel ? mast0_din[11:0] : tsz_cnt; +assign de_adr0 = ld_desc_sel ? mast0_din : {adr0_cnt, 2'b00}; +assign de_adr1 = ld_desc_sel ? mast0_din : {adr1_cnt, 2'b00}; +assign de_csr = mast0_din; + +// Abort logic +always @(posedge clk) + dma_abort_r <= #1 dma_abort | mast0_err | mast1_err; + +assign dma_err = dma_abort_r; + +assign dma_busy = (state != IDLE); + +//////////////////////////////////////////////////////////////////// +// +// WISHBONE Interface Logic +// + +always @(posedge clk) + read_r <= #1 read; + +always @(posedge clk) + write_r <= #1 write; + +always @(posedge clk) + rd_ack_r <= #1 read_r; + +// Data Path +assign mast0_dout = m0_we ? {20'h0, tsz_cnt} : csr[2] ? mast1_din : mast0_din; +assign mast1_dout = csr[2] ? mast1_din : mast0_din; + +// Address Path +always @(posedge clk) + mast0_adr <= #1 m0_go ? + (m0_we ? pointer_s : {pointer[31:4], ptr_adr_low, 2'b00}) : + read ? {adr0_cnt, 2'b00} : {adr1_cnt, 2'b00}; + +always @(posedge clk) + mast1_adr <= #1 read ? {adr0_cnt, 2'b00} : {adr1_cnt, 2'b00}; + +// CTRL +assign write_hold = (read | write) & write_hold_r; + +always @(posedge clk) + write_hold_r <= #1 read | write; + +assign read_hold = done ? read : (read | write); + +assign mast0_go = (!csr[2] & read_hold) | (!csr[1] & write_hold) | m0_go; +assign mast1_go = ( csr[2] & read_hold) | ( csr[1] & write_hold); + +assign mast0_we = m0_go ? m0_we : (!csr[1] & write); +assign mast1_we = csr[1] & write; + +assign rd_ack = (csr[2] ? mast1_drdy : mast0_drdy); +assign wr_ack = (csr[1] ? mast1_drdy : mast0_drdy); + +assign mast0_wait = !((!csr[2] & read) | (!csr[1] & write)) & !m0_go; +assign mast1_wait = !(( csr[2] & read) | ( csr[1] & write)); + +always @(posedge clk) + mast0_drdy_r <= #1 mast0_drdy; + +assign de_ack = dma_done; + +//////////////////////////////////////////////////////////////////// +// +// State Machine +// + +always @(posedge clk or negedge rst) + if(!rst) state <= #1 IDLE; + else state <= #1 next_state; + +always @(state or pause_req or dma_abort_r or de_start or rd_ack or wr_ack or + done or ptr_valid or use_ed or mast0_drdy or mast0_drdy_r or csr or nd) + begin + next_state = state; // Default keep state + read = 1'b0; + write = 1'b0; + dma_done_d = 1'b0; + de_csr_we = 1'b0; + de_txsz_we = 1'b0; + de_adr0_we = 1'b0; + de_adr1_we = 1'b0; + de_fetch_descr = 1'b0; + + m0_go = 1'b0; + m0_we = 1'b0; + ptr_adr_low = 2'h0; + ptr_set = 1'b0; + ld_desc_sel = 1'b0; + paused = 1'b0; + + case(state) // synopsys parallel_case full_case + + IDLE: + begin + if(pause_req) next_state = PAUSE; + else + if(de_start & !csr[`WDMA_ERR]) + begin + if(use_ed & !ptr_valid) next_state = LD_DESC1; + else next_state = READ; + end + end + + PAUSE: + begin + paused = 1'b1; + if(!pause_req) next_state = IDLE; + end + + READ: // Read From Source + begin + if(dma_abort_r) next_state = UPDATE; + else + if(!rd_ack) read = 1'b1; + else + begin + write = 1'b1; + next_state = WRITE; + end + end + + WRITE: // Write To Destination + begin + if(dma_abort_r) next_state = UPDATE; + else + if(!wr_ack) write = 1'b1; + else + begin + if(done) next_state = UPDATE; + else + begin + read = 1'b1; + next_state = READ; + end + end + end + + UPDATE: // Update Registers + begin + dma_done_d = 1'b1; + de_txsz_we = 1'b1; + de_adr0_we = 1'b1; + de_adr1_we = 1'b1; + if(use_ed & csr[`WDMA_WRB] & nd) + begin + m0_we = 1'b1; + m0_go = 1'b1; + next_state = WB; + end + else next_state = IDLE; + end + + WB: + begin + m0_we = 1'b1; + if(mast0_drdy) + begin + next_state = IDLE; + end + else m0_go = 1'b1; + end + + LD_DESC1: // Load Descriptor from memory to registers + begin + ptr_adr_low = 2'h0; + ld_desc_sel = 1'b1; + m0_go = 1'b1; + de_csr_we = 1'b1; + de_txsz_we = 1'b1; + de_fetch_descr = 1'b1; + if(mast0_drdy) + begin + ptr_adr_low = 2'h1; + next_state = LD_DESC2; + end + end + + LD_DESC2: + begin + de_fetch_descr = 1'b1; + if(mast0_drdy_r) de_csr_we = 1'b1; + if(mast0_drdy_r) de_txsz_we = 1'b1; + ptr_adr_low = 2'h1; + ld_desc_sel = 1'b1; + m0_go = 1'b1; + if(mast0_drdy) + begin + ptr_adr_low = 2'h2; + next_state = LD_DESC3; + end + end + + LD_DESC3: + begin + de_fetch_descr = 1'b1; + if(mast0_drdy_r) de_adr0_we = 1'b1; + ptr_adr_low = 2'h2; + ld_desc_sel = 1'b1; + m0_go = 1'b1; + if(mast0_drdy) + begin + ptr_adr_low = 2'h3; + next_state = LD_DESC4; + end + end + + LD_DESC4: + begin + de_fetch_descr = 1'b1; + if(mast0_drdy_r) de_adr1_we = 1'b1; + ptr_adr_low = 2'h3; + ld_desc_sel = 1'b1; + if(mast0_drdy) + begin + next_state = LD_DESC5; + end + else m0_go = 1'b1; + end + + LD_DESC5: + begin + de_fetch_descr = 1'b1; + ptr_set = 1'b1; + next_state = READ; + end + + endcase + + end + +endmodule Index: wb_dma/trunk/rtl/verilog/wb_dma_pri_enc_sub.v =================================================================== --- wb_dma/trunk/rtl/verilog/wb_dma_pri_enc_sub.v (nonexistent) +++ wb_dma/trunk/rtl/verilog/wb_dma_pri_enc_sub.v (revision 17) @@ -0,0 +1,142 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE DMA Priority Encoder Sub-Module //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/wb_dma/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: wb_dma_pri_enc_sub.v,v 1.4 2002-02-01 01:54:45 rudi Exp $ +// +// $Date: 2002-02-01 01:54:45 $ +// $Revision: 1.4 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.3 2001/10/19 04:35:04 rudi +// +// - Made the core parameterized +// +// Revision 1.2 2001/08/15 05:40:30 rudi +// +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// - Added Section 3.10, describing DMA restart. +// +// Revision 1.1 2001/08/07 08:00:43 rudi +// +// +// Split up priority encoder modules to separate files +// +// +// +// +// +// + +`include "wb_dma_defines.v" + +// Priority Encoder +// +// Determines the channel with the highest priority, also takes +// the valid bit in consideration + +module wb_dma_pri_enc_sub(valid, pri_in, pri_out); + +parameter [3:0] ch_conf = 4'b0000; +parameter [1:0] pri_sel = 2'd0; + +input valid; +input [2:0] pri_in; +output [7:0] pri_out; + +wire [7:0] pri_out; +reg [7:0] pri_out_d; +reg [7:0] pri_out_d0; +reg [7:0] pri_out_d1; +reg [7:0] pri_out_d2; + +assign pri_out = ch_conf[0] ? pri_out_d : 8'h0; + +// Select Configured Priority +always @(pri_sel or pri_out_d0 or pri_out_d1 or pri_out_d2) + case(pri_sel) // synopsys parallel_case full_case + 2'd0: pri_out_d = pri_out_d0; + 2'd1: pri_out_d = pri_out_d1; + 2'd2: pri_out_d = pri_out_d2; + endcase + +// 8 Priority Levels +always @(valid or pri_in) + if(!valid) pri_out_d2 = 8'b0000_0001; + else + if(pri_in==3'h0) pri_out_d2 = 8'b0000_0001; + else + if(pri_in==3'h1) pri_out_d2 = 8'b0000_0010; + else + if(pri_in==3'h2) pri_out_d2 = 8'b0000_0100; + else + if(pri_in==3'h3) pri_out_d2 = 8'b0000_1000; + else + if(pri_in==3'h4) pri_out_d2 = 8'b0001_0000; + else + if(pri_in==3'h5) pri_out_d2 = 8'b0010_0000; + else + if(pri_in==3'h6) pri_out_d2 = 8'b0100_0000; + else pri_out_d2 = 8'b1000_0000; + +// 4 Priority Levels +always @(valid or pri_in) + if(!valid) pri_out_d1 = 8'b0000_0001; + else + if(pri_in==3'h0) pri_out_d1 = 8'b0000_0001; + else + if(pri_in==3'h1) pri_out_d1 = 8'b0000_0010; + else + if(pri_in==3'h2) pri_out_d1 = 8'b0000_0100; + else pri_out_d1 = 8'b0000_1000; + +// 2 Priority Levels +always @(valid or pri_in) + if(!valid) pri_out_d0 = 8'b0000_0001; + else + if(pri_in==3'h0) pri_out_d0 = 8'b0000_0001; + else pri_out_d0 = 8'b0000_0010; + +endmodule + Index: wb_dma/trunk/rtl/verilog/wb_dma_ch_pri_enc.v =================================================================== --- wb_dma/trunk/rtl/verilog/wb_dma_ch_pri_enc.v (nonexistent) +++ wb_dma/trunk/rtl/verilog/wb_dma_ch_pri_enc.v (revision 17) @@ -0,0 +1,380 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE DMA Priority Encoder //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/wb_dma/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: wb_dma_ch_pri_enc.v,v 1.5 2002-02-01 01:54:44 rudi Exp $ +// +// $Date: 2002-02-01 01:54:44 $ +// $Revision: 1.5 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.4 2001/10/19 04:35:04 rudi +// +// - Made the core parameterized +// +// Revision 1.3 2001/08/15 05:40:30 rudi +// +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// - Added Section 3.10, describing DMA restart. +// +// Revision 1.2 2001/08/07 08:00:43 rudi +// +// +// Split up priority encoder modules to separate files +// +// Revision 1.1 2001/07/29 08:57:02 rudi +// +// +// 1) Changed Directory Structure +// 2) Added restart signal (REST) +// +// Revision 1.2 2001/06/05 10:22:36 rudi +// +// +// - Added Support of up to 31 channels +// - Added support for 2,4 and 8 priority levels +// - Now can have up to 31 channels +// - Added many configuration items +// - Changed reset to async +// +// Revision 1.1.1.1 2001/03/19 13:10:50 rudi +// Initial Release +// +// +// + +`include "wb_dma_defines.v" + +// Priority Encoder +// +// Determines the channel with the highest priority, also takes +// the valid bit in consideration + +module wb_dma_ch_pri_enc(clk, valid, + pri0, pri1, pri2, pri3, + pri4, pri5, pri6, pri7, + pri8, pri9, pri10, pri11, + pri12, pri13, pri14, pri15, + pri16, pri17, pri18, pri19, + pri20, pri21, pri22, pri23, + pri24, pri25, pri26, pri27, + pri28, pri29, pri30, + pri_out); + +//////////////////////////////////////////////////////////////////// +// +// Module Parameters +// + +// chXX_conf = { CBUF, ED, ARS, EN } +parameter [1:0] pri_sel = 2'd0; +parameter [3:0] ch0_conf = 4'h1; +parameter [3:0] ch1_conf = 4'h0; +parameter [3:0] ch2_conf = 4'h0; +parameter [3:0] ch3_conf = 4'h0; +parameter [3:0] ch4_conf = 4'h0; +parameter [3:0] ch5_conf = 4'h0; +parameter [3:0] ch6_conf = 4'h0; +parameter [3:0] ch7_conf = 4'h0; +parameter [3:0] ch8_conf = 4'h0; +parameter [3:0] ch9_conf = 4'h0; +parameter [3:0] ch10_conf = 4'h0; +parameter [3:0] ch11_conf = 4'h0; +parameter [3:0] ch12_conf = 4'h0; +parameter [3:0] ch13_conf = 4'h0; +parameter [3:0] ch14_conf = 4'h0; +parameter [3:0] ch15_conf = 4'h0; +parameter [3:0] ch16_conf = 4'h0; +parameter [3:0] ch17_conf = 4'h0; +parameter [3:0] ch18_conf = 4'h0; +parameter [3:0] ch19_conf = 4'h0; +parameter [3:0] ch20_conf = 4'h0; +parameter [3:0] ch21_conf = 4'h0; +parameter [3:0] ch22_conf = 4'h0; +parameter [3:0] ch23_conf = 4'h0; +parameter [3:0] ch24_conf = 4'h0; +parameter [3:0] ch25_conf = 4'h0; +parameter [3:0] ch26_conf = 4'h0; +parameter [3:0] ch27_conf = 4'h0; +parameter [3:0] ch28_conf = 4'h0; +parameter [3:0] ch29_conf = 4'h0; +parameter [3:0] ch30_conf = 4'h0; + +//////////////////////////////////////////////////////////////////// +// +// Module IOs +// + +input clk; +input [30:0] valid; // Channel Valid bits +input [2:0] pri0, pri1, pri2, pri3; // Channel Priorities +input [2:0] pri4, pri5, pri6, pri7; +input [2:0] pri8, pri9, pri10, pri11; +input [2:0] pri12, pri13, pri14, pri15; +input [2:0] pri16, pri17, pri18, pri19; +input [2:0] pri20, pri21, pri22, pri23; +input [2:0] pri24, pri25, pri26, pri27; +input [2:0] pri28, pri29, pri30; +output [2:0] pri_out; // Highest unserviced priority + +wire [7:0] pri0_out, pri1_out, pri2_out, pri3_out; +wire [7:0] pri4_out, pri5_out, pri6_out, pri7_out; +wire [7:0] pri8_out, pri9_out, pri10_out, pri11_out; +wire [7:0] pri12_out, pri13_out, pri14_out, pri15_out; +wire [7:0] pri16_out, pri17_out, pri18_out, pri19_out; +wire [7:0] pri20_out, pri21_out, pri22_out, pri23_out; +wire [7:0] pri24_out, pri25_out, pri26_out, pri27_out; +wire [7:0] pri28_out, pri29_out, pri30_out; + +wire [7:0] pri_out_tmp; +reg [2:0] pri_out; +reg [2:0] pri_out2; +reg [2:0] pri_out1; +reg [2:0] pri_out0; + +wb_dma_pri_enc_sub #(ch1_conf,pri_sel) u0( // Use channel config 1 for channel 0 encoder + .valid( valid[0] ), + .pri_in( pri0 ), + .pri_out( pri0_out ) + ); +wb_dma_pri_enc_sub #(ch1_conf,pri_sel) u1( + .valid( valid[1] ), + .pri_in( pri1 ), + .pri_out( pri1_out ) + ); +wb_dma_pri_enc_sub #(ch2_conf,pri_sel) u2( + .valid( valid[2] ), + .pri_in( pri2 ), + .pri_out( pri2_out ) + ); +wb_dma_pri_enc_sub #(ch3_conf,pri_sel) u3( + .valid( valid[3] ), + .pri_in( pri3 ), + .pri_out( pri3_out ) + ); +wb_dma_pri_enc_sub #(ch4_conf,pri_sel) u4( + .valid( valid[4] ), + .pri_in( pri4 ), + .pri_out( pri4_out ) + ); +wb_dma_pri_enc_sub #(ch5_conf,pri_sel) u5( + .valid( valid[5] ), + .pri_in( pri5 ), + .pri_out( pri5_out ) + ); +wb_dma_pri_enc_sub #(ch6_conf,pri_sel) u6( + .valid( valid[6] ), + .pri_in( pri6 ), + .pri_out( pri6_out ) + ); +wb_dma_pri_enc_sub #(ch7_conf,pri_sel) u7( + .valid( valid[7] ), + .pri_in( pri7 ), + .pri_out( pri7_out ) + ); +wb_dma_pri_enc_sub #(ch8_conf,pri_sel) u8( + .valid( valid[8] ), + .pri_in( pri8 ), + .pri_out( pri8_out ) + ); +wb_dma_pri_enc_sub #(ch9_conf,pri_sel) u9( + .valid( valid[9] ), + .pri_in( pri9 ), + .pri_out( pri9_out ) + ); +wb_dma_pri_enc_sub #(ch10_conf,pri_sel) u10( + .valid( valid[10] ), + .pri_in( pri10 ), + .pri_out( pri10_out ) + ); +wb_dma_pri_enc_sub #(ch11_conf,pri_sel) u11( + .valid( valid[11] ), + .pri_in( pri11 ), + .pri_out( pri11_out ) + ); +wb_dma_pri_enc_sub #(ch12_conf,pri_sel) u12( + .valid( valid[12] ), + .pri_in( pri12 ), + .pri_out( pri12_out ) + ); +wb_dma_pri_enc_sub #(ch13_conf,pri_sel) u13( + .valid( valid[13] ), + .pri_in( pri13 ), + .pri_out( pri13_out ) + ); +wb_dma_pri_enc_sub #(ch14_conf,pri_sel) u14( + .valid( valid[14] ), + .pri_in( pri14 ), + .pri_out( pri14_out ) + ); +wb_dma_pri_enc_sub #(ch15_conf,pri_sel) u15( + .valid( valid[15] ), + .pri_in( pri15 ), + .pri_out( pri15_out ) + ); +wb_dma_pri_enc_sub #(ch16_conf,pri_sel) u16( + .valid( valid[16] ), + .pri_in( pri16 ), + .pri_out( pri16_out ) + ); +wb_dma_pri_enc_sub #(ch17_conf,pri_sel) u17( + .valid( valid[17] ), + .pri_in( pri17 ), + .pri_out( pri17_out ) + ); +wb_dma_pri_enc_sub #(ch18_conf,pri_sel) u18( + .valid( valid[18] ), + .pri_in( pri18 ), + .pri_out( pri18_out ) + ); +wb_dma_pri_enc_sub #(ch19_conf,pri_sel) u19( + .valid( valid[19] ), + .pri_in( pri19 ), + .pri_out( pri19_out ) + ); +wb_dma_pri_enc_sub #(ch20_conf,pri_sel) u20( + .valid( valid[20] ), + .pri_in( pri20 ), + .pri_out( pri20_out ) + ); +wb_dma_pri_enc_sub #(ch21_conf,pri_sel) u21( + .valid( valid[21] ), + .pri_in( pri21 ), + .pri_out( pri21_out ) + ); +wb_dma_pri_enc_sub #(ch22_conf,pri_sel) u22( + .valid( valid[22] ), + .pri_in( pri22 ), + .pri_out( pri22_out ) + ); +wb_dma_pri_enc_sub #(ch23_conf,pri_sel) u23( + .valid( valid[23] ), + .pri_in( pri23 ), + .pri_out( pri23_out ) + ); +wb_dma_pri_enc_sub #(ch24_conf,pri_sel) u24( + .valid( valid[24] ), + .pri_in( pri24 ), + .pri_out( pri24_out ) + ); +wb_dma_pri_enc_sub #(ch25_conf,pri_sel) u25( + .valid( valid[25] ), + .pri_in( pri25 ), + .pri_out( pri25_out ) + ); +wb_dma_pri_enc_sub #(ch26_conf,pri_sel) u26( + .valid( valid[26] ), + .pri_in( pri26 ), + .pri_out( pri26_out ) + ); +wb_dma_pri_enc_sub #(ch27_conf,pri_sel) u27( + .valid( valid[27] ), + .pri_in( pri27 ), + .pri_out( pri27_out ) + ); +wb_dma_pri_enc_sub #(ch28_conf,pri_sel) u28( + .valid( valid[28] ), + .pri_in( pri28 ), + .pri_out( pri28_out ) + ); +wb_dma_pri_enc_sub #(ch29_conf,pri_sel) u29( + .valid( valid[29] ), + .pri_in( pri29 ), + .pri_out( pri29_out ) + ); +wb_dma_pri_enc_sub #(ch30_conf,pri_sel) u30( + .valid( valid[30] ), + .pri_in( pri30 ), + .pri_out( pri30_out ) + ); + +assign pri_out_tmp = pri0_out | pri1_out | pri2_out | pri3_out | + pri4_out | pri5_out | pri6_out | pri7_out | + pri8_out | pri9_out | pri10_out | pri11_out | + pri12_out | pri13_out | pri14_out | pri15_out | + pri16_out | pri17_out | pri18_out | pri19_out | + pri20_out | pri21_out | pri22_out | pri23_out | + pri24_out | pri25_out | pri26_out | pri27_out | + pri28_out | pri29_out | pri30_out; + +// 8 Priority Levels +always @(posedge clk) + if(pri_out_tmp[7]) pri_out2 <= #1 3'h7; + else + if(pri_out_tmp[6]) pri_out2 <= #1 3'h6; + else + if(pri_out_tmp[5]) pri_out2 <= #1 3'h5; + else + if(pri_out_tmp[4]) pri_out2 <= #1 3'h4; + else + if(pri_out_tmp[3]) pri_out2 <= #1 3'h3; + else + if(pri_out_tmp[2]) pri_out2 <= #1 3'h2; + else + if(pri_out_tmp[1]) pri_out2 <= #1 3'h1; + else pri_out2 <= #1 3'h0; + +// 4 Priority Levels +always @(posedge clk) + if(pri_out_tmp[3]) pri_out1 <= #1 3'h3; + else + if(pri_out_tmp[2]) pri_out1 <= #1 3'h2; + else + if(pri_out_tmp[1]) pri_out1 <= #1 3'h1; + else pri_out1 <= #1 3'h0; + +// 2 Priority Levels +always @(posedge clk) + if(pri_out_tmp[1]) pri_out0 <= #1 3'h1; + else pri_out0 <= #1 3'h0; + +// Select configured priority +always @(pri_sel or pri_out0 or pri_out1 or pri_out2) + case(pri_sel) // synopsys parallel_case full_case + 2'd0: pri_out = pri_out0; + 2'd1: pri_out = pri_out1; + 2'd2: pri_out = pri_out2; + endcase + +endmodule Index: wb_dma/trunk/rtl/verilog/wb_dma_wb_mast.v =================================================================== --- wb_dma/trunk/rtl/verilog/wb_dma_wb_mast.v (nonexistent) +++ wb_dma/trunk/rtl/verilog/wb_dma_wb_mast.v (revision 17) @@ -0,0 +1,166 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE DMA WISHBONE Master Interface //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/wb_dma/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: wb_dma_wb_mast.v,v 1.2 2002-02-01 01:54:45 rudi Exp $ +// +// $Date: 2002-02-01 01:54:45 $ +// $Revision: 1.2 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.1 2001/07/29 08:57:02 rudi +// +// +// 1) Changed Directory Structure +// 2) Added restart signal (REST) +// +// Revision 1.2 2001/06/05 10:22:37 rudi +// +// +// - Added Support of up to 31 channels +// - Added support for 2,4 and 8 priority levels +// - Now can have up to 31 channels +// - Added many configuration items +// - Changed reset to async +// +// Revision 1.1.1.1 2001/03/19 13:11:05 rudi +// Initial Release +// +// +// + +`include "wb_dma_defines.v" + +module wb_dma_wb_mast(clk, rst, + + wb_data_i, wb_data_o, wb_addr_o, wb_sel_o, wb_we_o, wb_cyc_o, + wb_stb_o, wb_ack_i, wb_err_i, wb_rty_i, + + mast_go, mast_we, mast_adr, mast_din, mast_dout, mast_err, + mast_drdy, mast_wait, + + pt_sel, mast_pt_in, mast_pt_out + ); + +input clk, rst; + +// -------------------------------------- +// WISHBONE INTERFACE + +input [31:0] wb_data_i; +output [31:0] wb_data_o; +output [31:0] wb_addr_o; +output [3:0] wb_sel_o; +output wb_we_o; +output wb_cyc_o; +output wb_stb_o; +input wb_ack_i; +input wb_err_i; +input wb_rty_i; + +// -------------------------------------- +// INTERNAL DMA INTERFACE +input mast_go; // Perform a Master Cycle (as long as this + // line is asserted) +input mast_we; // Read/Write +input [31:0] mast_adr; // Address for the transfer +input [31:0] mast_din; // Internal Input Data +output [31:0] mast_dout; // Internal Output Data +output mast_err; // Indicates an error has occurred + +output mast_drdy; // Indicated that either data is available + // during a read, or that the master can accept + // the next data during a write +input mast_wait; // Tells the master to insert wait cycles + // because data can not be accepted/provided + +// Pass Through Interface +input pt_sel; // Pass Through Mode Selected +input [70:0] mast_pt_in; // Grouped WISHBONE inputs +output [34:0] mast_pt_out; // Grouped WISHBONE outputs + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +reg mast_cyc, mast_stb; +reg mast_we_r; +reg [3:0] mast_be; +reg [31:0] mast_dout; + +//////////////////////////////////////////////////////////////////// +// +// Pass-Through Interface +// + +assign {wb_data_o, wb_addr_o, wb_sel_o, wb_we_o, wb_cyc_o, wb_stb_o} = + pt_sel ? mast_pt_in : + {mast_din, mast_adr, mast_be, mast_we_r, mast_cyc, mast_stb}; + +assign mast_pt_out = {wb_data_i, wb_ack_i, wb_err_i, wb_rty_i}; + +//////////////////////////////////////////////////////////////////// +// +// DMA Engine Interface +// + +always @(posedge clk) + if(wb_ack_i) mast_dout <= #1 wb_data_i; + +always @(posedge clk) + mast_be <= #1 4'hf; + +always @(posedge clk) + mast_we_r <= #1 mast_we; + +always @(posedge clk) + mast_cyc <= #1 mast_go; + +always @(posedge clk) + mast_stb <= #1 mast_go & !mast_wait; + +assign mast_drdy = wb_ack_i; +assign mast_err = wb_err_i; + +endmodule Index: wb_dma/trunk/rtl/verilog/wb_dma_wb_slv.v =================================================================== --- wb_dma/trunk/rtl/verilog/wb_dma_wb_slv.v (nonexistent) +++ wb_dma/trunk/rtl/verilog/wb_dma_wb_slv.v (revision 17) @@ -0,0 +1,176 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE DMA WISHBONE Slave Interface //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/wb_dma/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: wb_dma_wb_slv.v,v 1.4 2002-02-01 01:54:45 rudi Exp $ +// +// $Date: 2002-02-01 01:54:45 $ +// $Revision: 1.4 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.3 2001/10/19 04:35:04 rudi +// +// - Made the core parameterized +// +// Revision 1.2 2001/08/15 05:40:30 rudi +// +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// - Added Section 3.10, describing DMA restart. +// +// Revision 1.1 2001/07/29 08:57:02 rudi +// +// +// 1) Changed Directory Structure +// 2) Added restart signal (REST) +// +// Revision 1.2 2001/06/05 10:22:37 rudi +// +// +// - Added Support of up to 31 channels +// - Added support for 2,4 and 8 priority levels +// - Now can have up to 31 channels +// - Added many configuration items +// - Changed reset to async +// +// Revision 1.1.1.1 2001/03/19 13:10:59 rudi +// Initial Release +// +// +// + +`include "wb_dma_defines.v" + +module wb_dma_wb_slv(clk, rst, + + wb_data_i, wb_data_o, wb_addr_i, wb_sel_i, wb_we_i, wb_cyc_i, + wb_stb_i, wb_ack_o, wb_err_o, wb_rty_o, + + // This is the register File Interface + slv_adr, slv_din, slv_dout, slv_re, slv_we, + + // Pass through Interface + pt_sel, slv_pt_out, slv_pt_in + + ); + +parameter rf_addr = 0; + +input clk, rst; + +// -------------------------------------- +// WISHBONE INTERFACE + +input [31:0] wb_data_i; +output [31:0] wb_data_o; +input [31:0] wb_addr_i; +input [3:0] wb_sel_i; +input wb_we_i; +input wb_cyc_i; +input wb_stb_i; +output wb_ack_o; +output wb_err_o; +output wb_rty_o; + +// This is the register File Interface +output [31:0] slv_adr; // Slave Address +input [31:0] slv_din; // Slave Input Data +output [31:0] slv_dout; // Slave Output Data +output slv_re; // Slave Read Enable +output slv_we; // Slave Write Enable + +// Pass through Interface +output pt_sel; // Pass Through Mode Active +output [70:0] slv_pt_out; // Grouped WISHBONE out signals +input [34:0] slv_pt_in; // Grouped WISHBONE in signals + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +reg slv_re, slv_we; +wire rf_sel; +reg rf_ack; +reg [31:0] slv_adr, slv_dout; + +//////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +assign rf_sel = `WDMA_REG_SEL ; + +//////////////////////////////////////////////////////////////////// +// +// Pass Through Logic +// + +//assign pt_sel = !rf_sel; +assign pt_sel = !rf_sel & wb_cyc_i; + +assign slv_pt_out = {wb_data_i, wb_addr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i}; +assign {wb_data_o, wb_ack_o, wb_err_o, wb_rty_o} = pt_sel ? slv_pt_in : + {slv_din, rf_ack, 1'b0, 1'b0}; + +//////////////////////////////////////////////////////////////////// +// +// Register File Logic +// + +always @(posedge clk) + slv_adr <= #1 wb_addr_i; + +always @(posedge clk) + slv_re <= #1 rf_sel & wb_cyc_i & wb_stb_i & !wb_we_i & !rf_ack & !slv_re; + +always @(posedge clk) + slv_we <= #1 rf_sel & wb_cyc_i & wb_stb_i & wb_we_i & !rf_ack; + +always @(posedge clk) + slv_dout <= #1 wb_data_i; + +always @(posedge clk) + rf_ack <= #1 (slv_re | slv_we) & wb_cyc_i & wb_stb_i & !rf_ack ; + +endmodule Index: wb_dma/trunk/rtl/verilog/wb_dma_ch_sel.v =================================================================== --- wb_dma/trunk/rtl/verilog/wb_dma_ch_sel.v (nonexistent) +++ wb_dma/trunk/rtl/verilog/wb_dma_ch_sel.v (revision 17) @@ -0,0 +1,1388 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE DMA Channel Select //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/wb_dma/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: wb_dma_ch_sel.v,v 1.4 2002-02-01 01:54:45 rudi Exp $ +// +// $Date: 2002-02-01 01:54:45 $ +// $Revision: 1.4 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.3 2001/10/19 04:35:04 rudi +// +// - Made the core parameterized +// +// Revision 1.2 2001/08/15 05:40:30 rudi +// +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// - Added Section 3.10, describing DMA restart. +// +// Revision 1.1 2001/07/29 08:57:02 rudi +// +// +// 1) Changed Directory Structure +// 2) Added restart signal (REST) +// +// Revision 1.4 2001/06/14 08:52:00 rudi +// +// +// Changed arbiter module name. +// +// Revision 1.3 2001/06/13 02:26:48 rudi +// +// +// Small changes after running lint. +// +// Revision 1.2 2001/06/05 10:22:36 rudi +// +// +// - Added Support of up to 31 channels +// - Added support for 2,4 and 8 priority levels +// - Now can have up to 31 channels +// - Added many configuration items +// - Changed reset to async +// +// Revision 1.1.1.1 2001/03/19 13:10:35 rudi +// Initial Release +// +// +// + +`include "wb_dma_defines.v" + +module wb_dma_ch_sel(clk, rst, + + // DMA Request Lines + req_i, ack_o, nd_i, + + // DMA Registers Inputs + pointer0, pointer0_s, ch0_csr, ch0_txsz, ch0_adr0, ch0_adr1, ch0_am0, ch0_am1, + pointer1, pointer1_s, ch1_csr, ch1_txsz, ch1_adr0, ch1_adr1, ch1_am0, ch1_am1, + pointer2, pointer2_s, ch2_csr, ch2_txsz, ch2_adr0, ch2_adr1, ch2_am0, ch2_am1, + pointer3, pointer3_s, ch3_csr, ch3_txsz, ch3_adr0, ch3_adr1, ch3_am0, ch3_am1, + pointer4, pointer4_s, ch4_csr, ch4_txsz, ch4_adr0, ch4_adr1, ch4_am0, ch4_am1, + pointer5, pointer5_s, ch5_csr, ch5_txsz, ch5_adr0, ch5_adr1, ch5_am0, ch5_am1, + pointer6, pointer6_s, ch6_csr, ch6_txsz, ch6_adr0, ch6_adr1, ch6_am0, ch6_am1, + pointer7, pointer7_s, ch7_csr, ch7_txsz, ch7_adr0, ch7_adr1, ch7_am0, ch7_am1, + pointer8, pointer8_s, ch8_csr, ch8_txsz, ch8_adr0, ch8_adr1, ch8_am0, ch8_am1, + pointer9, pointer9_s, ch9_csr, ch9_txsz, ch9_adr0, ch9_adr1, ch9_am0, ch9_am1, + pointer10, pointer10_s, ch10_csr, ch10_txsz, ch10_adr0, ch10_adr1, ch10_am0, ch10_am1, + pointer11, pointer11_s, ch11_csr, ch11_txsz, ch11_adr0, ch11_adr1, ch11_am0, ch11_am1, + pointer12, pointer12_s, ch12_csr, ch12_txsz, ch12_adr0, ch12_adr1, ch12_am0, ch12_am1, + pointer13, pointer13_s, ch13_csr, ch13_txsz, ch13_adr0, ch13_adr1, ch13_am0, ch13_am1, + pointer14, pointer14_s, ch14_csr, ch14_txsz, ch14_adr0, ch14_adr1, ch14_am0, ch14_am1, + pointer15, pointer15_s, ch15_csr, ch15_txsz, ch15_adr0, ch15_adr1, ch15_am0, ch15_am1, + pointer16, pointer16_s, ch16_csr, ch16_txsz, ch16_adr0, ch16_adr1, ch16_am0, ch16_am1, + pointer17, pointer17_s, ch17_csr, ch17_txsz, ch17_adr0, ch17_adr1, ch17_am0, ch17_am1, + pointer18, pointer18_s, ch18_csr, ch18_txsz, ch18_adr0, ch18_adr1, ch18_am0, ch18_am1, + pointer19, pointer19_s, ch19_csr, ch19_txsz, ch19_adr0, ch19_adr1, ch19_am0, ch19_am1, + pointer20, pointer20_s, ch20_csr, ch20_txsz, ch20_adr0, ch20_adr1, ch20_am0, ch20_am1, + pointer21, pointer21_s, ch21_csr, ch21_txsz, ch21_adr0, ch21_adr1, ch21_am0, ch21_am1, + pointer22, pointer22_s, ch22_csr, ch22_txsz, ch22_adr0, ch22_adr1, ch22_am0, ch22_am1, + pointer23, pointer23_s, ch23_csr, ch23_txsz, ch23_adr0, ch23_adr1, ch23_am0, ch23_am1, + pointer24, pointer24_s, ch24_csr, ch24_txsz, ch24_adr0, ch24_adr1, ch24_am0, ch24_am1, + pointer25, pointer25_s, ch25_csr, ch25_txsz, ch25_adr0, ch25_adr1, ch25_am0, ch25_am1, + pointer26, pointer26_s, ch26_csr, ch26_txsz, ch26_adr0, ch26_adr1, ch26_am0, ch26_am1, + pointer27, pointer27_s, ch27_csr, ch27_txsz, ch27_adr0, ch27_adr1, ch27_am0, ch27_am1, + pointer28, pointer28_s, ch28_csr, ch28_txsz, ch28_adr0, ch28_adr1, ch28_am0, ch28_am1, + pointer29, pointer29_s, ch29_csr, ch29_txsz, ch29_adr0, ch29_adr1, ch29_am0, ch29_am1, + pointer30, pointer30_s, ch30_csr, ch30_txsz, ch30_adr0, ch30_adr1, ch30_am0, ch30_am1, + + // DMA Registers Write Back Channel Select + ch_sel, ndnr, + + // DMA Engine Interface + de_start, ndr, csr, pointer, txsz, adr0, adr1, am0, am1, + pointer_s, next_ch, de_ack, dma_busy + ); + +//////////////////////////////////////////////////////////////////// +// +// Module Parameters +// + +// chXX_conf = { CBUF, ED, ARS, EN } +parameter [1:0] pri_sel = 2'h0; +parameter [3:0] ch0_conf = 4'h1; +parameter [3:0] ch1_conf = 4'h0; +parameter [3:0] ch2_conf = 4'h0; +parameter [3:0] ch3_conf = 4'h0; +parameter [3:0] ch4_conf = 4'h0; +parameter [3:0] ch5_conf = 4'h0; +parameter [3:0] ch6_conf = 4'h0; +parameter [3:0] ch7_conf = 4'h0; +parameter [3:0] ch8_conf = 4'h0; +parameter [3:0] ch9_conf = 4'h0; +parameter [3:0] ch10_conf = 4'h0; +parameter [3:0] ch11_conf = 4'h0; +parameter [3:0] ch12_conf = 4'h0; +parameter [3:0] ch13_conf = 4'h0; +parameter [3:0] ch14_conf = 4'h0; +parameter [3:0] ch15_conf = 4'h0; +parameter [3:0] ch16_conf = 4'h0; +parameter [3:0] ch17_conf = 4'h0; +parameter [3:0] ch18_conf = 4'h0; +parameter [3:0] ch19_conf = 4'h0; +parameter [3:0] ch20_conf = 4'h0; +parameter [3:0] ch21_conf = 4'h0; +parameter [3:0] ch22_conf = 4'h0; +parameter [3:0] ch23_conf = 4'h0; +parameter [3:0] ch24_conf = 4'h0; +parameter [3:0] ch25_conf = 4'h0; +parameter [3:0] ch26_conf = 4'h0; +parameter [3:0] ch27_conf = 4'h0; +parameter [3:0] ch28_conf = 4'h0; +parameter [3:0] ch29_conf = 4'h0; +parameter [3:0] ch30_conf = 4'h0; + +//////////////////////////////////////////////////////////////////// +// +// Module IOs +// + +input clk, rst; + +// DMA Request Lines +input [30:0] req_i; +output [30:0] ack_o; +input [30:0] nd_i; + +// Channel Registers Inputs +input [31:0] pointer0, pointer0_s, ch0_csr, ch0_txsz, ch0_adr0, ch0_adr1, ch0_am0, ch0_am1; +input [31:0] pointer1, pointer1_s, ch1_csr, ch1_txsz, ch1_adr0, ch1_adr1, ch1_am0, ch1_am1; +input [31:0] pointer2, pointer2_s, ch2_csr, ch2_txsz, ch2_adr0, ch2_adr1, ch2_am0, ch2_am1; +input [31:0] pointer3, pointer3_s, ch3_csr, ch3_txsz, ch3_adr0, ch3_adr1, ch3_am0, ch3_am1; +input [31:0] pointer4, pointer4_s, ch4_csr, ch4_txsz, ch4_adr0, ch4_adr1, ch4_am0, ch4_am1; +input [31:0] pointer5, pointer5_s, ch5_csr, ch5_txsz, ch5_adr0, ch5_adr1, ch5_am0, ch5_am1; +input [31:0] pointer6, pointer6_s, ch6_csr, ch6_txsz, ch6_adr0, ch6_adr1, ch6_am0, ch6_am1; +input [31:0] pointer7, pointer7_s, ch7_csr, ch7_txsz, ch7_adr0, ch7_adr1, ch7_am0, ch7_am1; +input [31:0] pointer8, pointer8_s, ch8_csr, ch8_txsz, ch8_adr0, ch8_adr1, ch8_am0, ch8_am1; +input [31:0] pointer9, pointer9_s, ch9_csr, ch9_txsz, ch9_adr0, ch9_adr1, ch9_am0, ch9_am1; +input [31:0] pointer10, pointer10_s, ch10_csr, ch10_txsz, ch10_adr0, ch10_adr1, ch10_am0, ch10_am1; +input [31:0] pointer11, pointer11_s, ch11_csr, ch11_txsz, ch11_adr0, ch11_adr1, ch11_am0, ch11_am1; +input [31:0] pointer12, pointer12_s, ch12_csr, ch12_txsz, ch12_adr0, ch12_adr1, ch12_am0, ch12_am1; +input [31:0] pointer13, pointer13_s, ch13_csr, ch13_txsz, ch13_adr0, ch13_adr1, ch13_am0, ch13_am1; +input [31:0] pointer14, pointer14_s, ch14_csr, ch14_txsz, ch14_adr0, ch14_adr1, ch14_am0, ch14_am1; +input [31:0] pointer15, pointer15_s, ch15_csr, ch15_txsz, ch15_adr0, ch15_adr1, ch15_am0, ch15_am1; +input [31:0] pointer16, pointer16_s, ch16_csr, ch16_txsz, ch16_adr0, ch16_adr1, ch16_am0, ch16_am1; +input [31:0] pointer17, pointer17_s, ch17_csr, ch17_txsz, ch17_adr0, ch17_adr1, ch17_am0, ch17_am1; +input [31:0] pointer18, pointer18_s, ch18_csr, ch18_txsz, ch18_adr0, ch18_adr1, ch18_am0, ch18_am1; +input [31:0] pointer19, pointer19_s, ch19_csr, ch19_txsz, ch19_adr0, ch19_adr1, ch19_am0, ch19_am1; +input [31:0] pointer20, pointer20_s, ch20_csr, ch20_txsz, ch20_adr0, ch20_adr1, ch20_am0, ch20_am1; +input [31:0] pointer21, pointer21_s, ch21_csr, ch21_txsz, ch21_adr0, ch21_adr1, ch21_am0, ch21_am1; +input [31:0] pointer22, pointer22_s, ch22_csr, ch22_txsz, ch22_adr0, ch22_adr1, ch22_am0, ch22_am1; +input [31:0] pointer23, pointer23_s, ch23_csr, ch23_txsz, ch23_adr0, ch23_adr1, ch23_am0, ch23_am1; +input [31:0] pointer24, pointer24_s, ch24_csr, ch24_txsz, ch24_adr0, ch24_adr1, ch24_am0, ch24_am1; +input [31:0] pointer25, pointer25_s, ch25_csr, ch25_txsz, ch25_adr0, ch25_adr1, ch25_am0, ch25_am1; +input [31:0] pointer26, pointer26_s, ch26_csr, ch26_txsz, ch26_adr0, ch26_adr1, ch26_am0, ch26_am1; +input [31:0] pointer27, pointer27_s, ch27_csr, ch27_txsz, ch27_adr0, ch27_adr1, ch27_am0, ch27_am1; +input [31:0] pointer28, pointer28_s, ch28_csr, ch28_txsz, ch28_adr0, ch28_adr1, ch28_am0, ch28_am1; +input [31:0] pointer29, pointer29_s, ch29_csr, ch29_txsz, ch29_adr0, ch29_adr1, ch29_am0, ch29_am1; +input [31:0] pointer30, pointer30_s, ch30_csr, ch30_txsz, ch30_adr0, ch30_adr1, ch30_am0, ch30_am1; + +output [4:0] ch_sel; // Write Back Channel Select +output [30:0] ndnr; // Next Descriptor No Request + +output de_start; // Start DMA Engine Indicator +output ndr; // Next Descriptor With Request (for current channel) +output [31:0] csr; // Selected Channel CSR +output [31:0] pointer; // LL Descriptor pointer +output [31:0] pointer_s; // LL Descriptor previous pointer +output [31:0] txsz; // Selected Channel Transfer Size +output [31:0] adr0, adr1; // Selected Channel Addresses +output [31:0] am0, am1; // Selected Channel Address Masks + +input next_ch; // Indicates the DMA Engine is done + // with current transfer +input de_ack; // DMA engine ack output + +input dma_busy; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires and Registers +// + +reg [30:0] ack_o; +wire [30:0] valid; // Indicates which channel is valid +reg valid_sel; +reg [30:0] req_r; // Channel Request inputs +reg [30:0] ndr_r; // Next Descriptor Registered (and Request) +reg [30:0] ndnr; // Next Descriptor Registered (and Not Request) +wire [2:0] pri_out; // Highest unserviced priority +wire [2:0] pri0, pri1, pri2, pri3; // Channel Priorities +wire [2:0] pri4, pri5, pri6, pri7; +wire [2:0] pri8, pri9, pri10, pri11; +wire [2:0] pri12, pri13, pri14, pri15; +wire [2:0] pri16, pri17, pri18, pri19; +wire [2:0] pri20, pri21, pri22, pri23; +wire [2:0] pri24, pri25, pri26, pri27; +wire [2:0] pri28, pri29, pri30; +reg [4:0] ch_sel_d; +reg [4:0] ch_sel_r; + +reg ndr; +reg next_start; +reg de_start_r; +reg [31:0] csr; // Selected Channel CSR +reg [31:0] pointer; +reg [31:0] pointer_s; +reg [31:0] txsz; // Selected Channel Transfer Size +reg [31:0] adr0, adr1; // Selected Channel Addresses +reg [31:0] am0, am1; // Selected Channel Address Masks + + // Arbiter Request Inputs +wire [30:0] req_p0, req_p1, req_p2, req_p3; +wire [30:0] req_p4, req_p5, req_p6, req_p7; +wire [30:0] req_p8, req_p9, req_p10, req_p11; +wire [30:0] req_p12, req_p13, req_p14, req_p15; +wire [30:0] req_p16, req_p17, req_p18, req_p19; +wire [30:0] req_p20, req_p21, req_p22, req_p23; +wire [30:0] req_p24, req_p25, req_p26, req_p27; +wire [30:0] req_p28, req_p29, req_p30; + // Arbiter Grant Outputs +wire [4:0] gnt_p0_d, gnt_p1_d, gnt_p2_d, gnt_p3_d; +wire [4:0] gnt_p4_d, gnt_p5_d, gnt_p6_d, gnt_p7_d; +wire [4:0] gnt_p0, gnt_p1, gnt_p2, gnt_p3; +wire [4:0] gnt_p4, gnt_p5, gnt_p6, gnt_p7; +wire [4:0] gnt_p8, gnt_p9, gnt_p10, gnt_p11; +wire [4:0] gnt_p12, gnt_p13, gnt_p14, gnt_p15; +wire [4:0] gnt_p16, gnt_p17, gnt_p18, gnt_p19; +wire [4:0] gnt_p20, gnt_p21, gnt_p22, gnt_p23; +wire [4:0] gnt_p24, gnt_p25, gnt_p26, gnt_p27; +wire [4:0] gnt_p28, gnt_p29, gnt_p30; + + +//////////////////////////////////////////////////////////////////// +// +// Aliases +// + +assign pri0[0] = ch0_csr[13]; +assign pri0[1] = (pri_sel == 2'd0) ? 1'b0 : ch0_csr[14]; +assign pri0[2] = (pri_sel == 2'd2) ? ch0_csr[15] : 1'b0; +assign pri1[0] = ch1_csr[13]; +assign pri1[1] = (pri_sel == 2'd0) ? 1'b0 : ch1_csr[14]; +assign pri1[2] = (pri_sel == 2'd2) ? ch1_csr[15] : 1'b0; +assign pri2[0] = ch2_csr[13]; +assign pri2[1] = (pri_sel == 2'd0) ? 1'b0 : ch2_csr[14]; +assign pri2[2] = (pri_sel == 2'd2) ? ch2_csr[15] : 1'b0; +assign pri3[0] = ch3_csr[13]; +assign pri3[1] = (pri_sel == 2'd0) ? 1'b0 : ch3_csr[14]; +assign pri3[2] = (pri_sel == 2'd2) ? ch3_csr[15] : 1'b0; +assign pri4[0] = ch4_csr[13]; +assign pri4[1] = (pri_sel == 2'd0) ? 1'b0 : ch4_csr[14]; +assign pri4[2] = (pri_sel == 2'd2) ? ch4_csr[15] : 1'b0; +assign pri5[0] = ch5_csr[13]; +assign pri5[1] = (pri_sel == 2'd0) ? 1'b0 : ch5_csr[14]; +assign pri5[2] = (pri_sel == 2'd2) ? ch5_csr[15] : 1'b0; +assign pri6[0] = ch6_csr[13]; +assign pri6[1] = (pri_sel == 2'd0) ? 1'b0 : ch6_csr[14]; +assign pri6[2] = (pri_sel == 2'd2) ? ch6_csr[15] : 1'b0; +assign pri7[0] = ch7_csr[13]; +assign pri7[1] = (pri_sel == 2'd0) ? 1'b0 : ch7_csr[14]; +assign pri7[2] = (pri_sel == 2'd2) ? ch7_csr[15] : 1'b0; +assign pri8[0] = ch8_csr[13]; +assign pri8[1] = (pri_sel == 2'd0) ? 1'b0 : ch8_csr[14]; +assign pri8[2] = (pri_sel == 2'd2) ? ch8_csr[15] : 1'b0; +assign pri9[0] = ch9_csr[13]; +assign pri9[1] = (pri_sel == 2'd0) ? 1'b0 : ch9_csr[14]; +assign pri9[2] = (pri_sel == 2'd2) ? ch9_csr[15] : 1'b0; +assign pri10[0] = ch10_csr[13]; +assign pri10[1] = (pri_sel == 2'd0) ? 1'b0 : ch10_csr[14]; +assign pri10[2] = (pri_sel == 2'd2) ? ch10_csr[15] : 1'b0; +assign pri11[0] = ch11_csr[13]; +assign pri11[1] = (pri_sel == 2'd0) ? 1'b0 : ch11_csr[14]; +assign pri11[2] = (pri_sel == 2'd2) ? ch11_csr[15] : 1'b0; +assign pri12[0] = ch12_csr[13]; +assign pri12[1] = (pri_sel == 2'd0) ? 1'b0 : ch12_csr[14]; +assign pri12[2] = (pri_sel == 2'd2) ? ch12_csr[15] : 1'b0; +assign pri13[0] = ch13_csr[13]; +assign pri13[1] = (pri_sel == 2'd0) ? 1'b0 : ch13_csr[14]; +assign pri13[2] = (pri_sel == 2'd2) ? ch13_csr[15] : 1'b0; +assign pri14[0] = ch14_csr[13]; +assign pri14[1] = (pri_sel == 2'd0) ? 1'b0 : ch14_csr[14]; +assign pri14[2] = (pri_sel == 2'd2) ? ch14_csr[15] : 1'b0; +assign pri15[0] = ch15_csr[13]; +assign pri15[1] = (pri_sel == 2'd0) ? 1'b0 : ch15_csr[14]; +assign pri15[2] = (pri_sel == 2'd2) ? ch15_csr[15] : 1'b0; +assign pri16[0] = ch16_csr[13]; +assign pri16[1] = (pri_sel == 2'd0) ? 1'b0 : ch16_csr[14]; +assign pri16[2] = (pri_sel == 2'd2) ? ch16_csr[15] : 1'b0; +assign pri17[0] = ch17_csr[13]; +assign pri17[1] = (pri_sel == 2'd0) ? 1'b0 : ch17_csr[14]; +assign pri17[2] = (pri_sel == 2'd2) ? ch17_csr[15] : 1'b0; +assign pri18[0] = ch18_csr[13]; +assign pri18[1] = (pri_sel == 2'd0) ? 1'b0 : ch18_csr[14]; +assign pri18[2] = (pri_sel == 2'd2) ? ch18_csr[15] : 1'b0; +assign pri19[0] = ch19_csr[13]; +assign pri19[1] = (pri_sel == 2'd0) ? 1'b0 : ch19_csr[14]; +assign pri19[2] = (pri_sel == 2'd2) ? ch19_csr[15] : 1'b0; +assign pri20[0] = ch20_csr[13]; +assign pri20[1] = (pri_sel == 2'd0) ? 1'b0 : ch20_csr[14]; +assign pri20[2] = (pri_sel == 2'd2) ? ch20_csr[15] : 1'b0; +assign pri21[0] = ch21_csr[13]; +assign pri21[1] = (pri_sel == 2'd0) ? 1'b0 : ch21_csr[14]; +assign pri21[2] = (pri_sel == 2'd2) ? ch21_csr[15] : 1'b0; +assign pri22[0] = ch22_csr[13]; +assign pri22[1] = (pri_sel == 2'd0) ? 1'b0 : ch22_csr[14]; +assign pri22[2] = (pri_sel == 2'd2) ? ch22_csr[15] : 1'b0; +assign pri23[0] = ch23_csr[13]; +assign pri23[1] = (pri_sel == 2'd0) ? 1'b0 : ch23_csr[14]; +assign pri23[2] = (pri_sel == 2'd2) ? ch23_csr[15] : 1'b0; +assign pri24[0] = ch24_csr[13]; +assign pri24[1] = (pri_sel == 2'd0) ? 1'b0 : ch24_csr[14]; +assign pri24[2] = (pri_sel == 2'd2) ? ch24_csr[15] : 1'b0; +assign pri25[0] = ch25_csr[13]; +assign pri25[1] = (pri_sel == 2'd0) ? 1'b0 : ch25_csr[14]; +assign pri25[2] = (pri_sel == 2'd2) ? ch25_csr[15] : 1'b0; +assign pri26[0] = ch26_csr[13]; +assign pri26[1] = (pri_sel == 2'd0) ? 1'b0 : ch26_csr[14]; +assign pri26[2] = (pri_sel == 2'd2) ? ch26_csr[15] : 1'b0; +assign pri27[0] = ch27_csr[13]; +assign pri27[1] = (pri_sel == 2'd0) ? 1'b0 : ch27_csr[14]; +assign pri27[2] = (pri_sel == 2'd2) ? ch27_csr[15] : 1'b0; +assign pri28[0] = ch28_csr[13]; +assign pri28[1] = (pri_sel == 2'd0) ? 1'b0 : ch28_csr[14]; +assign pri28[2] = (pri_sel == 2'd2) ? ch28_csr[15] : 1'b0; +assign pri29[0] = ch29_csr[13]; +assign pri29[1] = (pri_sel == 2'd0) ? 1'b0 : ch29_csr[14]; +assign pri29[2] = (pri_sel == 2'd2) ? ch29_csr[15] : 1'b0; +assign pri30[0] = ch30_csr[13]; +assign pri30[1] = (pri_sel == 2'd0) ? 1'b0 : ch30_csr[14]; +assign pri30[2] = (pri_sel == 2'd2) ? ch30_csr[15] : 1'b0; + +//////////////////////////////////////////////////////////////////// +// +// Misc logic +// + +// Chanel Valid flag +// The valid flag is asserted when the channel is enabled, +// and is either in "normal mode" (software control) or +// "hw handshake mode" (reqN control) +// validN = ch_enabled & (sw_mode | (hw_mode & reqN) ) + +always @(posedge clk) + req_r <= #1 req_i & ~ack_o; + +assign valid[0] = ch0_conf[0] & ch0_csr[`WDMA_CH_EN] & (ch0_csr[`WDMA_MODE] ? (req_r[0] & !ack_o[0]) : 1'b1); +assign valid[1] = ch1_conf[0] & ch1_csr[`WDMA_CH_EN] & (ch1_csr[`WDMA_MODE] ? (req_r[1] & !ack_o[1]) : 1'b1); +assign valid[2] = ch2_conf[0] & ch2_csr[`WDMA_CH_EN] & (ch2_csr[`WDMA_MODE] ? (req_r[2] & !ack_o[2]) : 1'b1); +assign valid[3] = ch3_conf[0] & ch3_csr[`WDMA_CH_EN] & (ch3_csr[`WDMA_MODE] ? (req_r[3] & !ack_o[3]) : 1'b1); +assign valid[4] = ch4_conf[0] & ch4_csr[`WDMA_CH_EN] & (ch4_csr[`WDMA_MODE] ? (req_r[4] & !ack_o[4]) : 1'b1); +assign valid[5] = ch5_conf[0] & ch5_csr[`WDMA_CH_EN] & (ch5_csr[`WDMA_MODE] ? (req_r[5] & !ack_o[5]) : 1'b1); +assign valid[6] = ch6_conf[0] & ch6_csr[`WDMA_CH_EN] & (ch6_csr[`WDMA_MODE] ? (req_r[6] & !ack_o[6]) : 1'b1); +assign valid[7] = ch7_conf[0] & ch7_csr[`WDMA_CH_EN] & (ch7_csr[`WDMA_MODE] ? (req_r[7] & !ack_o[7]) : 1'b1); +assign valid[8] = ch8_conf[0] & ch8_csr[`WDMA_CH_EN] & (ch8_csr[`WDMA_MODE] ? (req_r[8] & !ack_o[8]) : 1'b1); +assign valid[9] = ch9_conf[0] & ch9_csr[`WDMA_CH_EN] & (ch9_csr[`WDMA_MODE] ? (req_r[9] & !ack_o[9]) : 1'b1); +assign valid[10] = ch10_conf[0] & ch10_csr[`WDMA_CH_EN] & (ch10_csr[`WDMA_MODE] ? (req_r[10] & !ack_o[10]) : 1'b1); +assign valid[11] = ch11_conf[0] & ch11_csr[`WDMA_CH_EN] & (ch11_csr[`WDMA_MODE] ? (req_r[11] & !ack_o[11]) : 1'b1); +assign valid[12] = ch12_conf[0] & ch12_csr[`WDMA_CH_EN] & (ch12_csr[`WDMA_MODE] ? (req_r[12] & !ack_o[12]) : 1'b1); +assign valid[13] = ch13_conf[0] & ch13_csr[`WDMA_CH_EN] & (ch13_csr[`WDMA_MODE] ? (req_r[13] & !ack_o[13]) : 1'b1); +assign valid[14] = ch14_conf[0] & ch14_csr[`WDMA_CH_EN] & (ch14_csr[`WDMA_MODE] ? (req_r[14] & !ack_o[14]) : 1'b1); +assign valid[15] = ch15_conf[0] & ch15_csr[`WDMA_CH_EN] & (ch15_csr[`WDMA_MODE] ? (req_r[15] & !ack_o[15]) : 1'b1); +assign valid[16] = ch16_conf[0] & ch16_csr[`WDMA_CH_EN] & (ch16_csr[`WDMA_MODE] ? (req_r[16] & !ack_o[16]) : 1'b1); +assign valid[17] = ch17_conf[0] & ch17_csr[`WDMA_CH_EN] & (ch17_csr[`WDMA_MODE] ? (req_r[17] & !ack_o[17]) : 1'b1); +assign valid[18] = ch18_conf[0] & ch18_csr[`WDMA_CH_EN] & (ch18_csr[`WDMA_MODE] ? (req_r[18] & !ack_o[18]) : 1'b1); +assign valid[19] = ch19_conf[0] & ch19_csr[`WDMA_CH_EN] & (ch19_csr[`WDMA_MODE] ? (req_r[19] & !ack_o[19]) : 1'b1); +assign valid[20] = ch20_conf[0] & ch20_csr[`WDMA_CH_EN] & (ch20_csr[`WDMA_MODE] ? (req_r[20] & !ack_o[20]) : 1'b1); +assign valid[21] = ch21_conf[0] & ch21_csr[`WDMA_CH_EN] & (ch21_csr[`WDMA_MODE] ? (req_r[21] & !ack_o[21]) : 1'b1); +assign valid[22] = ch22_conf[0] & ch22_csr[`WDMA_CH_EN] & (ch22_csr[`WDMA_MODE] ? (req_r[22] & !ack_o[22]) : 1'b1); +assign valid[23] = ch23_conf[0] & ch23_csr[`WDMA_CH_EN] & (ch23_csr[`WDMA_MODE] ? (req_r[23] & !ack_o[23]) : 1'b1); +assign valid[24] = ch24_conf[0] & ch24_csr[`WDMA_CH_EN] & (ch24_csr[`WDMA_MODE] ? (req_r[24] & !ack_o[24]) : 1'b1); +assign valid[25] = ch25_conf[0] & ch25_csr[`WDMA_CH_EN] & (ch25_csr[`WDMA_MODE] ? (req_r[25] & !ack_o[25]) : 1'b1); +assign valid[26] = ch26_conf[0] & ch26_csr[`WDMA_CH_EN] & (ch26_csr[`WDMA_MODE] ? (req_r[26] & !ack_o[26]) : 1'b1); +assign valid[27] = ch27_conf[0] & ch27_csr[`WDMA_CH_EN] & (ch27_csr[`WDMA_MODE] ? (req_r[27] & !ack_o[27]) : 1'b1); +assign valid[28] = ch28_conf[0] & ch28_csr[`WDMA_CH_EN] & (ch28_csr[`WDMA_MODE] ? (req_r[28] & !ack_o[28]) : 1'b1); +assign valid[29] = ch29_conf[0] & ch29_csr[`WDMA_CH_EN] & (ch29_csr[`WDMA_MODE] ? (req_r[29] & !ack_o[29]) : 1'b1); +assign valid[30] = ch30_conf[0] & ch30_csr[`WDMA_CH_EN] & (ch30_csr[`WDMA_MODE] ? (req_r[30] & !ack_o[30]) : 1'b1); + +always @(posedge clk) + ndr_r <= #1 nd_i & req_i; + +always @(posedge clk) + ndnr <= #1 nd_i & ~req_i; + +// Start Signal for DMA engine +assign de_start = (valid_sel & !de_start_r ) | next_start; + +always @(posedge clk) + de_start_r <= #1 valid_sel; + +always @(posedge clk) + next_start <= #1 next_ch & valid_sel; + +// Ack outputs for HW handshake mode +always @(posedge clk) + ack_o[0] <= #1 ch0_conf[0] & (ch_sel == 5'h0) & ch0_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[1] <= #1 ch1_conf[0] & (ch_sel == 5'h1) & ch1_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[2] <= #1 ch2_conf[0] & (ch_sel == 5'h2) & ch2_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[3] <= #1 ch3_conf[0] & (ch_sel == 5'h3) & ch3_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[4] <= #1 ch4_conf[0] & (ch_sel == 5'h4) & ch4_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[5] <= #1 ch5_conf[0] & (ch_sel == 5'h5) & ch5_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[6] <= #1 ch6_conf[0] & (ch_sel == 5'h6) & ch6_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[7] <= #1 ch7_conf[0] & (ch_sel == 5'h7) & ch7_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[8] <= #1 ch8_conf[0] & (ch_sel == 5'h8) & ch8_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[9] <= #1 ch9_conf[0] & (ch_sel == 5'h9) & ch9_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[10] <= #1 ch10_conf[0] & (ch_sel == 5'ha) & ch10_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[11] <= #1 ch11_conf[0] & (ch_sel == 5'hb) & ch11_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[12] <= #1 ch12_conf[0] & (ch_sel == 5'hc) & ch12_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[13] <= #1 ch13_conf[0] & (ch_sel == 5'hd) & ch13_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[14] <= #1 ch14_conf[0] & (ch_sel == 5'he) & ch14_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[15] <= #1 ch15_conf[0] & (ch_sel == 5'hf) & ch15_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[16] <= #1 ch16_conf[0] & (ch_sel == 5'h10) & ch16_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[17] <= #1 ch17_conf[0] & (ch_sel == 5'h11) & ch17_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[18] <= #1 ch18_conf[0] & (ch_sel == 5'h12) & ch18_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[19] <= #1 ch19_conf[0] & (ch_sel == 5'h13) & ch19_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[20] <= #1 ch20_conf[0] & (ch_sel == 5'h14) & ch20_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[21] <= #1 ch21_conf[0] & (ch_sel == 5'h15) & ch21_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[22] <= #1 ch22_conf[0] & (ch_sel == 5'h16) & ch22_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[23] <= #1 ch23_conf[0] & (ch_sel == 5'h17) & ch23_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[24] <= #1 ch24_conf[0] & (ch_sel == 5'h18) & ch24_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[25] <= #1 ch25_conf[0] & (ch_sel == 5'h19) & ch25_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[26] <= #1 ch26_conf[0] & (ch_sel == 5'h1a) & ch26_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[27] <= #1 ch27_conf[0] & (ch_sel == 5'h1b) & ch27_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[28] <= #1 ch28_conf[0] & (ch_sel == 5'h1c) & ch28_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[29] <= #1 ch29_conf[0] & (ch_sel == 5'h1d) & ch29_csr[`WDMA_MODE] & de_ack; + +always @(posedge clk) + ack_o[30] <= #1 ch30_conf[0] & (ch_sel == 5'h1e) & ch30_csr[`WDMA_MODE] & de_ack; + +// Channel Select +always @(posedge clk or negedge rst) + if(!rst) ch_sel_r <= #1 0; + else + if(de_start) ch_sel_r <= #1 ch_sel_d; + +assign ch_sel = !dma_busy ? ch_sel_d : ch_sel_r; + +//////////////////////////////////////////////////////////////////// +// +// Select Registers based on arbiter (and priority) outputs +// + +always @(ch_sel or valid) + case(ch_sel) // synopsys parallel_case full_case + 5'h0: valid_sel = valid[0]; + 5'h1: valid_sel = valid[1]; + 5'h2: valid_sel = valid[2]; + 5'h3: valid_sel = valid[3]; + 5'h4: valid_sel = valid[4]; + 5'h5: valid_sel = valid[5]; + 5'h6: valid_sel = valid[6]; + 5'h7: valid_sel = valid[7]; + 5'h8: valid_sel = valid[8]; + 5'h9: valid_sel = valid[9]; + 5'ha: valid_sel = valid[10]; + 5'hb: valid_sel = valid[11]; + 5'hc: valid_sel = valid[12]; + 5'hd: valid_sel = valid[13]; + 5'he: valid_sel = valid[14]; + 5'hf: valid_sel = valid[15]; + 5'h10: valid_sel = valid[16]; + 5'h11: valid_sel = valid[17]; + 5'h12: valid_sel = valid[18]; + 5'h13: valid_sel = valid[19]; + 5'h14: valid_sel = valid[20]; + 5'h15: valid_sel = valid[21]; + 5'h16: valid_sel = valid[22]; + 5'h17: valid_sel = valid[23]; + 5'h18: valid_sel = valid[24]; + 5'h19: valid_sel = valid[25]; + 5'h1a: valid_sel = valid[26]; + 5'h1b: valid_sel = valid[27]; + 5'h1c: valid_sel = valid[28]; + 5'h1d: valid_sel = valid[29]; + 5'h1e: valid_sel = valid[30]; + endcase + +always @(ch_sel or ndr_r) + case(ch_sel) // synopsys parallel_case full_case + 5'h0: ndr = ndr_r[0]; + 5'h1: ndr = ndr_r[1]; + 5'h2: ndr = ndr_r[2]; + 5'h3: ndr = ndr_r[3]; + 5'h4: ndr = ndr_r[4]; + 5'h5: ndr = ndr_r[5]; + 5'h6: ndr = ndr_r[6]; + 5'h7: ndr = ndr_r[7]; + 5'h8: ndr = ndr_r[8]; + 5'h9: ndr = ndr_r[9]; + 5'ha: ndr = ndr_r[10]; + 5'hb: ndr = ndr_r[11]; + 5'hc: ndr = ndr_r[12]; + 5'hd: ndr = ndr_r[13]; + 5'he: ndr = ndr_r[14]; + 5'hf: ndr = ndr_r[15]; + 5'h10: ndr = ndr_r[16]; + 5'h11: ndr = ndr_r[17]; + 5'h12: ndr = ndr_r[18]; + 5'h13: ndr = ndr_r[19]; + 5'h14: ndr = ndr_r[20]; + 5'h15: ndr = ndr_r[21]; + 5'h16: ndr = ndr_r[22]; + 5'h17: ndr = ndr_r[23]; + 5'h18: ndr = ndr_r[24]; + 5'h19: ndr = ndr_r[25]; + 5'h1a: ndr = ndr_r[26]; + 5'h1b: ndr = ndr_r[27]; + 5'h1c: ndr = ndr_r[28]; + 5'h1d: ndr = ndr_r[29]; + 5'h1e: ndr = ndr_r[30]; + endcase + +always @(ch_sel or pointer0 or pointer1 or pointer2 or pointer3 or pointer4 + or pointer5 or pointer6 or pointer7 or pointer8 or pointer9 + or pointer10 or pointer11 or pointer12 or pointer13 or pointer14 + or pointer15 or pointer16 or pointer17 or pointer18 or pointer19 + or pointer20 or pointer21 or pointer22 or pointer23 or pointer24 + or pointer25 or pointer26 or pointer27 or pointer28 or pointer29 + or pointer30 ) + case(ch_sel) // synopsys parallel_case full_case + 5'h0: pointer = pointer0; + 5'h1: pointer = pointer1; + 5'h2: pointer = pointer2; + 5'h3: pointer = pointer3; + 5'h4: pointer = pointer4; + 5'h5: pointer = pointer5; + 5'h6: pointer = pointer6; + 5'h7: pointer = pointer7; + 5'h8: pointer = pointer8; + 5'h9: pointer = pointer9; + 5'ha: pointer = pointer10; + 5'hb: pointer = pointer11; + 5'hc: pointer = pointer12; + 5'hd: pointer = pointer13; + 5'he: pointer = pointer14; + 5'hf: pointer = pointer15; + 5'h10: pointer = pointer16; + 5'h11: pointer = pointer17; + 5'h12: pointer = pointer18; + 5'h13: pointer = pointer19; + 5'h14: pointer = pointer20; + 5'h15: pointer = pointer21; + 5'h16: pointer = pointer22; + 5'h17: pointer = pointer23; + 5'h18: pointer = pointer24; + 5'h19: pointer = pointer25; + 5'h1a: pointer = pointer26; + 5'h1b: pointer = pointer27; + 5'h1c: pointer = pointer28; + 5'h1d: pointer = pointer29; + 5'h1e: pointer = pointer30; + endcase + +always @(ch_sel or pointer0_s or pointer1_s or pointer2_s or pointer3_s or pointer4_s + or pointer5_s or pointer6_s or pointer7_s or pointer8_s or pointer9_s + or pointer10_s or pointer11_s or pointer12_s or pointer13_s or pointer14_s + or pointer15_s or pointer16_s or pointer17_s or pointer18_s or pointer19_s + or pointer20_s or pointer21_s or pointer22_s or pointer23_s or pointer24_s + or pointer25_s or pointer26_s or pointer27_s or pointer28_s or pointer29_s + or pointer30_s ) + case(ch_sel) // synopsys parallel_case full_case + 5'h0: pointer_s = pointer0_s; + 5'h1: pointer_s = pointer1_s; + 5'h2: pointer_s = pointer2_s; + 5'h3: pointer_s = pointer3_s; + 5'h4: pointer_s = pointer4_s; + 5'h5: pointer_s = pointer5_s; + 5'h6: pointer_s = pointer6_s; + 5'h7: pointer_s = pointer7_s; + 5'h8: pointer_s = pointer8_s; + 5'h9: pointer_s = pointer9_s; + 5'ha: pointer_s = pointer10_s; + 5'hb: pointer_s = pointer11_s; + 5'hc: pointer_s = pointer12_s; + 5'hd: pointer_s = pointer13_s; + 5'he: pointer_s = pointer14_s; + 5'hf: pointer_s = pointer15_s; + 5'h10: pointer_s = pointer16_s; + 5'h11: pointer_s = pointer17_s; + 5'h12: pointer_s = pointer18_s; + 5'h13: pointer_s = pointer19_s; + 5'h14: pointer_s = pointer20_s; + 5'h15: pointer_s = pointer21_s; + 5'h16: pointer_s = pointer22_s; + 5'h17: pointer_s = pointer23_s; + 5'h18: pointer_s = pointer24_s; + 5'h19: pointer_s = pointer25_s; + 5'h1a: pointer_s = pointer26_s; + 5'h1b: pointer_s = pointer27_s; + 5'h1c: pointer_s = pointer28_s; + 5'h1d: pointer_s = pointer29_s; + 5'h1e: pointer_s = pointer30_s; + endcase + +always @(ch_sel or ch0_csr or ch1_csr or ch2_csr or ch3_csr or ch4_csr + or ch5_csr or ch6_csr or ch7_csr or ch8_csr or ch9_csr + or ch10_csr or ch11_csr or ch12_csr or ch13_csr or ch14_csr + or ch15_csr or ch16_csr or ch17_csr or ch18_csr or ch19_csr + or ch20_csr or ch21_csr or ch22_csr or ch23_csr or ch24_csr + or ch25_csr or ch26_csr or ch27_csr or ch28_csr or ch29_csr + or ch30_csr ) + case(ch_sel) // synopsys parallel_case full_case + 5'h0: csr = ch0_csr; + 5'h1: csr = ch1_csr; + 5'h2: csr = ch2_csr; + 5'h3: csr = ch3_csr; + 5'h4: csr = ch4_csr; + 5'h5: csr = ch5_csr; + 5'h6: csr = ch6_csr; + 5'h7: csr = ch7_csr; + 5'h8: csr = ch8_csr; + 5'h9: csr = ch9_csr; + 5'ha: csr = ch10_csr; + 5'hb: csr = ch11_csr; + 5'hc: csr = ch12_csr; + 5'hd: csr = ch13_csr; + 5'he: csr = ch14_csr; + 5'hf: csr = ch15_csr; + 5'h10: csr = ch16_csr; + 5'h11: csr = ch17_csr; + 5'h12: csr = ch18_csr; + 5'h13: csr = ch19_csr; + 5'h14: csr = ch20_csr; + 5'h15: csr = ch21_csr; + 5'h16: csr = ch22_csr; + 5'h17: csr = ch23_csr; + 5'h18: csr = ch24_csr; + 5'h19: csr = ch25_csr; + 5'h1a: csr = ch26_csr; + 5'h1b: csr = ch27_csr; + 5'h1c: csr = ch28_csr; + 5'h1d: csr = ch29_csr; + 5'h1e: csr = ch30_csr; + endcase + +always @(ch_sel or ch0_txsz or ch1_txsz or ch2_txsz or ch3_txsz or ch4_txsz + or ch5_txsz or ch6_txsz or ch7_txsz or ch8_txsz or ch9_txsz + or ch10_txsz or ch11_txsz or ch12_txsz or ch13_txsz or ch14_txsz + or ch15_txsz or ch16_txsz or ch17_txsz or ch18_txsz or ch19_txsz + or ch20_txsz or ch21_txsz or ch22_txsz or ch23_txsz or ch24_txsz + or ch25_txsz or ch26_txsz or ch27_txsz or ch28_txsz or ch29_txsz + or ch30_txsz ) + case(ch_sel) // synopsys parallel_case full_case + 5'h0: txsz = ch0_txsz; + 5'h1: txsz = ch1_txsz; + 5'h2: txsz = ch2_txsz; + 5'h3: txsz = ch3_txsz; + 5'h4: txsz = ch4_txsz; + 5'h5: txsz = ch5_txsz; + 5'h6: txsz = ch6_txsz; + 5'h7: txsz = ch7_txsz; + 5'h8: txsz = ch8_txsz; + 5'h9: txsz = ch9_txsz; + 5'ha: txsz = ch10_txsz; + 5'hb: txsz = ch11_txsz; + 5'hc: txsz = ch12_txsz; + 5'hd: txsz = ch13_txsz; + 5'he: txsz = ch14_txsz; + 5'hf: txsz = ch15_txsz; + 5'h10: txsz = ch16_txsz; + 5'h11: txsz = ch17_txsz; + 5'h12: txsz = ch18_txsz; + 5'h13: txsz = ch19_txsz; + 5'h14: txsz = ch20_txsz; + 5'h15: txsz = ch21_txsz; + 5'h16: txsz = ch22_txsz; + 5'h17: txsz = ch23_txsz; + 5'h18: txsz = ch24_txsz; + 5'h19: txsz = ch25_txsz; + 5'h1a: txsz = ch26_txsz; + 5'h1b: txsz = ch27_txsz; + 5'h1c: txsz = ch28_txsz; + 5'h1d: txsz = ch29_txsz; + 5'h1e: txsz = ch30_txsz; + endcase + +always @(ch_sel or ch0_adr0 or ch1_adr0 or ch2_adr0 or ch3_adr0 or ch4_adr0 + or ch5_adr0 or ch6_adr0 or ch7_adr0 or ch8_adr0 or ch9_adr0 + or ch10_adr0 or ch11_adr0 or ch12_adr0 or ch13_adr0 or ch14_adr0 + or ch15_adr0 or ch16_adr0 or ch17_adr0 or ch18_adr0 or ch19_adr0 + or ch20_adr0 or ch21_adr0 or ch22_adr0 or ch23_adr0 or ch24_adr0 + or ch25_adr0 or ch26_adr0 or ch27_adr0 or ch28_adr0 or ch29_adr0 + or ch30_adr0 ) + case(ch_sel) // synopsys parallel_case full_case + 5'h0: adr0 = ch0_adr0; + 5'h1: adr0 = ch1_adr0; + 5'h2: adr0 = ch2_adr0; + 5'h3: adr0 = ch3_adr0; + 5'h4: adr0 = ch4_adr0; + 5'h5: adr0 = ch5_adr0; + 5'h6: adr0 = ch6_adr0; + 5'h7: adr0 = ch7_adr0; + 5'h8: adr0 = ch8_adr0; + 5'h9: adr0 = ch9_adr0; + 5'ha: adr0 = ch10_adr0; + 5'hb: adr0 = ch11_adr0; + 5'hc: adr0 = ch12_adr0; + 5'hd: adr0 = ch13_adr0; + 5'he: adr0 = ch14_adr0; + 5'hf: adr0 = ch15_adr0; + 5'h10: adr0 = ch16_adr0; + 5'h11: adr0 = ch17_adr0; + 5'h12: adr0 = ch18_adr0; + 5'h13: adr0 = ch19_adr0; + 5'h14: adr0 = ch20_adr0; + 5'h15: adr0 = ch21_adr0; + 5'h16: adr0 = ch22_adr0; + 5'h17: adr0 = ch23_adr0; + 5'h18: adr0 = ch24_adr0; + 5'h19: adr0 = ch25_adr0; + 5'h1a: adr0 = ch26_adr0; + 5'h1b: adr0 = ch27_adr0; + 5'h1c: adr0 = ch28_adr0; + 5'h1d: adr0 = ch29_adr0; + 5'h1e: adr0 = ch30_adr0; + endcase + +always @(ch_sel or ch0_adr1 or ch1_adr1 or ch2_adr1 or ch3_adr1 or ch4_adr1 + or ch5_adr1 or ch6_adr1 or ch7_adr1 or ch8_adr1 or ch9_adr1 + or ch10_adr1 or ch11_adr1 or ch12_adr1 or ch13_adr1 or ch14_adr1 + or ch15_adr1 or ch16_adr1 or ch17_adr1 or ch18_adr1 or ch19_adr1 + or ch20_adr1 or ch21_adr1 or ch22_adr1 or ch23_adr1 or ch24_adr1 + or ch25_adr1 or ch26_adr1 or ch27_adr1 or ch28_adr1 or ch29_adr1 + or ch30_adr1 ) + case(ch_sel) // synopsys parallel_case full_case + 5'h0: adr1 = ch0_adr1; + 5'h1: adr1 = ch1_adr1; + 5'h2: adr1 = ch2_adr1; + 5'h3: adr1 = ch3_adr1; + 5'h4: adr1 = ch4_adr1; + 5'h5: adr1 = ch5_adr1; + 5'h6: adr1 = ch6_adr1; + 5'h7: adr1 = ch7_adr1; + 5'h8: adr1 = ch8_adr1; + 5'h9: adr1 = ch9_adr1; + 5'ha: adr1 = ch10_adr1; + 5'hb: adr1 = ch11_adr1; + 5'hc: adr1 = ch12_adr1; + 5'hd: adr1 = ch13_adr1; + 5'he: adr1 = ch14_adr1; + 5'hf: adr1 = ch15_adr1; + 5'h10: adr1 = ch16_adr1; + 5'h11: adr1 = ch17_adr1; + 5'h12: adr1 = ch18_adr1; + 5'h13: adr1 = ch19_adr1; + 5'h14: adr1 = ch20_adr1; + 5'h15: adr1 = ch21_adr1; + 5'h16: adr1 = ch22_adr1; + 5'h17: adr1 = ch23_adr1; + 5'h18: adr1 = ch24_adr1; + 5'h19: adr1 = ch25_adr1; + 5'h1a: adr1 = ch26_adr1; + 5'h1b: adr1 = ch27_adr1; + 5'h1c: adr1 = ch28_adr1; + 5'h1d: adr1 = ch29_adr1; + 5'h1e: adr1 = ch30_adr1; + endcase + +always @(ch_sel or ch0_am0 or ch1_am0 or ch2_am0 or ch3_am0 or ch4_am0 + or ch5_am0 or ch6_am0 or ch7_am0 or ch8_am0 or ch9_am0 + or ch10_am0 or ch11_am0 or ch12_am0 or ch13_am0 or ch14_am0 + or ch15_am0 or ch16_am0 or ch17_am0 or ch18_am0 or ch19_am0 + or ch20_am0 or ch21_am0 or ch22_am0 or ch23_am0 or ch24_am0 + or ch25_am0 or ch26_am0 or ch27_am0 or ch28_am0 or ch29_am0 + or ch30_am0 ) + case(ch_sel) // synopsys parallel_case full_case + 5'h0: am0 = ch0_am0; + 5'h1: am0 = ch1_am0; + 5'h2: am0 = ch2_am0; + 5'h3: am0 = ch3_am0; + 5'h4: am0 = ch4_am0; + 5'h5: am0 = ch5_am0; + 5'h6: am0 = ch6_am0; + 5'h7: am0 = ch7_am0; + 5'h8: am0 = ch8_am0; + 5'h9: am0 = ch9_am0; + 5'ha: am0 = ch10_am0; + 5'hb: am0 = ch11_am0; + 5'hc: am0 = ch12_am0; + 5'hd: am0 = ch13_am0; + 5'he: am0 = ch14_am0; + 5'hf: am0 = ch15_am0; + 5'h10: am0 = ch16_am0; + 5'h11: am0 = ch17_am0; + 5'h12: am0 = ch18_am0; + 5'h13: am0 = ch19_am0; + 5'h14: am0 = ch20_am0; + 5'h15: am0 = ch21_am0; + 5'h16: am0 = ch22_am0; + 5'h17: am0 = ch23_am0; + 5'h18: am0 = ch24_am0; + 5'h19: am0 = ch25_am0; + 5'h1a: am0 = ch26_am0; + 5'h1b: am0 = ch27_am0; + 5'h1c: am0 = ch28_am0; + 5'h1d: am0 = ch29_am0; + 5'h1e: am0 = ch30_am0; + endcase + +always @(ch_sel or ch0_am1 or ch1_am1 or ch2_am1 or ch3_am1 or ch4_am1 + or ch5_am1 or ch6_am1 or ch7_am1 or ch8_am1 or ch9_am1 + or ch10_am1 or ch11_am1 or ch12_am1 or ch13_am1 or ch14_am1 + or ch15_am1 or ch16_am1 or ch17_am1 or ch18_am1 or ch19_am1 + or ch20_am1 or ch21_am1 or ch22_am1 or ch23_am1 or ch24_am1 + or ch25_am1 or ch26_am1 or ch27_am1 or ch28_am1 or ch29_am1 + or ch30_am1 ) + case(ch_sel) // synopsys parallel_case full_case + 5'h0: am1 = ch0_am1; + 5'h1: am1 = ch1_am1; + 5'h2: am1 = ch2_am1; + 5'h3: am1 = ch3_am1; + 5'h4: am1 = ch4_am1; + 5'h5: am1 = ch5_am1; + 5'h6: am1 = ch6_am1; + 5'h7: am1 = ch7_am1; + 5'h8: am1 = ch8_am1; + 5'h9: am1 = ch9_am1; + 5'ha: am1 = ch10_am1; + 5'hb: am1 = ch11_am1; + 5'hc: am1 = ch12_am1; + 5'hd: am1 = ch13_am1; + 5'he: am1 = ch14_am1; + 5'hf: am1 = ch15_am1; + 5'h10: am1 = ch16_am1; + 5'h11: am1 = ch17_am1; + 5'h12: am1 = ch18_am1; + 5'h13: am1 = ch19_am1; + 5'h14: am1 = ch20_am1; + 5'h15: am1 = ch21_am1; + 5'h16: am1 = ch22_am1; + 5'h17: am1 = ch23_am1; + 5'h18: am1 = ch24_am1; + 5'h19: am1 = ch25_am1; + 5'h1a: am1 = ch26_am1; + 5'h1b: am1 = ch27_am1; + 5'h1c: am1 = ch28_am1; + 5'h1d: am1 = ch29_am1; + 5'h1e: am1 = ch30_am1; + endcase + +//////////////////////////////////////////////////////////////////// +// +// Actual Chanel Arbiter and Priority Encoder +// + +// Select the arbiter for current highest priority +always @(pri_out or gnt_p0 or gnt_p1 or gnt_p2 or gnt_p3 or gnt_p4 + or gnt_p5 or gnt_p6 or gnt_p7 ) + case(pri_out) // synopsys parallel_case full_case + 3'h0: ch_sel_d = gnt_p0; + 3'h1: ch_sel_d = gnt_p1; + 3'h2: ch_sel_d = gnt_p2; + 3'h3: ch_sel_d = gnt_p3; + 3'h4: ch_sel_d = gnt_p4; + 3'h5: ch_sel_d = gnt_p5; + 3'h6: ch_sel_d = gnt_p6; + 3'h7: ch_sel_d = gnt_p7; + endcase + + +// Priority Encoder +wb_dma_ch_pri_enc + #( pri_sel, + ch0_conf, + ch1_conf, + ch2_conf, + ch3_conf, + ch4_conf, + ch5_conf, + ch6_conf, + ch7_conf, + ch8_conf, + ch9_conf, + ch10_conf, + ch11_conf, + ch12_conf, + ch13_conf, + ch14_conf, + ch15_conf, + ch16_conf, + ch17_conf, + ch18_conf, + ch19_conf, + ch20_conf, + ch21_conf, + ch22_conf, + ch23_conf, + ch24_conf, + ch25_conf, + ch26_conf, + ch27_conf, + ch28_conf, + ch29_conf, + ch30_conf) + u0( + .clk( clk ), + .valid( valid ), + .pri0( pri0 ), + .pri1( pri1 ), + .pri2( pri2 ), + .pri3( pri3 ), + .pri4( pri4 ), + .pri5( pri5 ), + .pri6( pri6 ), + .pri7( pri7 ), + .pri8( pri8 ), + .pri9( pri9 ), + .pri10( pri10 ), + .pri11( pri11 ), + .pri12( pri12 ), + .pri13( pri13 ), + .pri14( pri14 ), + .pri15( pri15 ), + .pri16( pri16 ), + .pri17( pri17 ), + .pri18( pri18 ), + .pri19( pri19 ), + .pri20( pri20 ), + .pri21( pri21 ), + .pri22( pri22 ), + .pri23( pri23 ), + .pri24( pri24 ), + .pri25( pri25 ), + .pri26( pri26 ), + .pri27( pri27 ), + .pri28( pri28 ), + .pri29( pri29 ), + .pri30( pri30 ), + .pri_out( pri_out ) + ); + +// Arbiter request lines +// Generate request depending on priority and valid bits + +assign req_p0[0] = valid[0] & (pri0==3'h0); +assign req_p0[1] = valid[1] & (pri1==3'h0); +assign req_p0[2] = valid[2] & (pri2==3'h0); +assign req_p0[3] = valid[3] & (pri3==3'h0); +assign req_p0[4] = valid[4] & (pri4==3'h0); +assign req_p0[5] = valid[5] & (pri5==3'h0); +assign req_p0[6] = valid[6] & (pri6==3'h0); +assign req_p0[7] = valid[7] & (pri7==3'h0); +assign req_p0[8] = valid[8] & (pri8==3'h0); +assign req_p0[9] = valid[9] & (pri9==3'h0); +assign req_p0[10] = valid[10] & (pri10==3'h0); +assign req_p0[11] = valid[11] & (pri11==3'h0); +assign req_p0[12] = valid[12] & (pri12==3'h0); +assign req_p0[13] = valid[13] & (pri13==3'h0); +assign req_p0[14] = valid[14] & (pri14==3'h0); +assign req_p0[15] = valid[15] & (pri15==3'h0); +assign req_p0[16] = valid[16] & (pri16==3'h0); +assign req_p0[17] = valid[17] & (pri17==3'h0); +assign req_p0[18] = valid[18] & (pri18==3'h0); +assign req_p0[19] = valid[19] & (pri19==3'h0); +assign req_p0[20] = valid[20] & (pri20==3'h0); +assign req_p0[21] = valid[21] & (pri21==3'h0); +assign req_p0[22] = valid[22] & (pri22==3'h0); +assign req_p0[23] = valid[23] & (pri23==3'h0); +assign req_p0[24] = valid[24] & (pri24==3'h0); +assign req_p0[25] = valid[25] & (pri25==3'h0); +assign req_p0[26] = valid[26] & (pri26==3'h0); +assign req_p0[27] = valid[27] & (pri27==3'h0); +assign req_p0[28] = valid[28] & (pri28==3'h0); +assign req_p0[29] = valid[29] & (pri29==3'h0); +assign req_p0[30] = valid[30] & (pri30==3'h0); + +assign req_p1[0] = valid[0] & (pri0==3'h1); +assign req_p1[1] = valid[1] & (pri1==3'h1); +assign req_p1[2] = valid[2] & (pri2==3'h1); +assign req_p1[3] = valid[3] & (pri3==3'h1); +assign req_p1[4] = valid[4] & (pri4==3'h1); +assign req_p1[5] = valid[5] & (pri5==3'h1); +assign req_p1[6] = valid[6] & (pri6==3'h1); +assign req_p1[7] = valid[7] & (pri7==3'h1); +assign req_p1[8] = valid[8] & (pri8==3'h1); +assign req_p1[9] = valid[9] & (pri9==3'h1); +assign req_p1[10] = valid[10] & (pri10==3'h1); +assign req_p1[11] = valid[11] & (pri11==3'h1); +assign req_p1[12] = valid[12] & (pri12==3'h1); +assign req_p1[13] = valid[13] & (pri13==3'h1); +assign req_p1[14] = valid[14] & (pri14==3'h1); +assign req_p1[15] = valid[15] & (pri15==3'h1); +assign req_p1[16] = valid[16] & (pri16==3'h1); +assign req_p1[17] = valid[17] & (pri17==3'h1); +assign req_p1[18] = valid[18] & (pri18==3'h1); +assign req_p1[19] = valid[19] & (pri19==3'h1); +assign req_p1[20] = valid[20] & (pri20==3'h1); +assign req_p1[21] = valid[21] & (pri21==3'h1); +assign req_p1[22] = valid[22] & (pri22==3'h1); +assign req_p1[23] = valid[23] & (pri23==3'h1); +assign req_p1[24] = valid[24] & (pri24==3'h1); +assign req_p1[25] = valid[25] & (pri25==3'h1); +assign req_p1[26] = valid[26] & (pri26==3'h1); +assign req_p1[27] = valid[27] & (pri27==3'h1); +assign req_p1[28] = valid[28] & (pri28==3'h1); +assign req_p1[29] = valid[29] & (pri29==3'h1); +assign req_p1[30] = valid[30] & (pri30==3'h1); + +assign req_p2[0] = valid[0] & (pri0==3'h2); +assign req_p2[1] = valid[1] & (pri1==3'h2); +assign req_p2[2] = valid[2] & (pri2==3'h2); +assign req_p2[3] = valid[3] & (pri3==3'h2); +assign req_p2[4] = valid[4] & (pri4==3'h2); +assign req_p2[5] = valid[5] & (pri5==3'h2); +assign req_p2[6] = valid[6] & (pri6==3'h2); +assign req_p2[7] = valid[7] & (pri7==3'h2); +assign req_p2[8] = valid[8] & (pri8==3'h2); +assign req_p2[9] = valid[9] & (pri9==3'h2); +assign req_p2[10] = valid[10] & (pri10==3'h2); +assign req_p2[11] = valid[11] & (pri11==3'h2); +assign req_p2[12] = valid[12] & (pri12==3'h2); +assign req_p2[13] = valid[13] & (pri13==3'h2); +assign req_p2[14] = valid[14] & (pri14==3'h2); +assign req_p2[15] = valid[15] & (pri15==3'h2); +assign req_p2[16] = valid[16] & (pri16==3'h2); +assign req_p2[17] = valid[17] & (pri17==3'h2); +assign req_p2[18] = valid[18] & (pri18==3'h2); +assign req_p2[19] = valid[19] & (pri19==3'h2); +assign req_p2[20] = valid[20] & (pri20==3'h2); +assign req_p2[21] = valid[21] & (pri21==3'h2); +assign req_p2[22] = valid[22] & (pri22==3'h2); +assign req_p2[23] = valid[23] & (pri23==3'h2); +assign req_p2[24] = valid[24] & (pri24==3'h2); +assign req_p2[25] = valid[25] & (pri25==3'h2); +assign req_p2[26] = valid[26] & (pri26==3'h2); +assign req_p2[27] = valid[27] & (pri27==3'h2); +assign req_p2[28] = valid[28] & (pri28==3'h2); +assign req_p2[29] = valid[29] & (pri29==3'h2); +assign req_p2[30] = valid[30] & (pri30==3'h2); + +assign req_p3[0] = valid[0] & (pri0==3'h3); +assign req_p3[1] = valid[1] & (pri1==3'h3); +assign req_p3[2] = valid[2] & (pri2==3'h3); +assign req_p3[3] = valid[3] & (pri3==3'h3); +assign req_p3[4] = valid[4] & (pri4==3'h3); +assign req_p3[5] = valid[5] & (pri5==3'h3); +assign req_p3[6] = valid[6] & (pri6==3'h3); +assign req_p3[7] = valid[7] & (pri7==3'h3); +assign req_p3[8] = valid[8] & (pri8==3'h3); +assign req_p3[9] = valid[9] & (pri9==3'h3); +assign req_p3[10] = valid[10] & (pri10==3'h3); +assign req_p3[11] = valid[11] & (pri11==3'h3); +assign req_p3[12] = valid[12] & (pri12==3'h3); +assign req_p3[13] = valid[13] & (pri13==3'h3); +assign req_p3[14] = valid[14] & (pri14==3'h3); +assign req_p3[15] = valid[15] & (pri15==3'h3); +assign req_p3[16] = valid[16] & (pri16==3'h3); +assign req_p3[17] = valid[17] & (pri17==3'h3); +assign req_p3[18] = valid[18] & (pri18==3'h3); +assign req_p3[19] = valid[19] & (pri19==3'h3); +assign req_p3[20] = valid[20] & (pri20==3'h3); +assign req_p3[21] = valid[21] & (pri21==3'h3); +assign req_p3[22] = valid[22] & (pri22==3'h3); +assign req_p3[23] = valid[23] & (pri23==3'h3); +assign req_p3[24] = valid[24] & (pri24==3'h3); +assign req_p3[25] = valid[25] & (pri25==3'h3); +assign req_p3[26] = valid[26] & (pri26==3'h3); +assign req_p3[27] = valid[27] & (pri27==3'h3); +assign req_p3[28] = valid[28] & (pri28==3'h3); +assign req_p3[29] = valid[29] & (pri29==3'h3); +assign req_p3[30] = valid[30] & (pri30==3'h3); + +assign req_p4[0] = valid[0] & (pri0==3'h4); +assign req_p4[1] = valid[1] & (pri1==3'h4); +assign req_p4[2] = valid[2] & (pri2==3'h4); +assign req_p4[3] = valid[3] & (pri3==3'h4); +assign req_p4[4] = valid[4] & (pri4==3'h4); +assign req_p4[5] = valid[5] & (pri5==3'h4); +assign req_p4[6] = valid[6] & (pri6==3'h4); +assign req_p4[7] = valid[7] & (pri7==3'h4); +assign req_p4[8] = valid[8] & (pri8==3'h4); +assign req_p4[9] = valid[9] & (pri9==3'h4); +assign req_p4[10] = valid[10] & (pri10==3'h4); +assign req_p4[11] = valid[11] & (pri11==3'h4); +assign req_p4[12] = valid[12] & (pri12==3'h4); +assign req_p4[13] = valid[13] & (pri13==3'h4); +assign req_p4[14] = valid[14] & (pri14==3'h4); +assign req_p4[15] = valid[15] & (pri15==3'h4); +assign req_p4[16] = valid[16] & (pri16==3'h4); +assign req_p4[17] = valid[17] & (pri17==3'h4); +assign req_p4[18] = valid[18] & (pri18==3'h4); +assign req_p4[19] = valid[19] & (pri19==3'h4); +assign req_p4[20] = valid[20] & (pri20==3'h4); +assign req_p4[21] = valid[21] & (pri21==3'h4); +assign req_p4[22] = valid[22] & (pri22==3'h4); +assign req_p4[23] = valid[23] & (pri23==3'h4); +assign req_p4[24] = valid[24] & (pri24==3'h4); +assign req_p4[25] = valid[25] & (pri25==3'h4); +assign req_p4[26] = valid[26] & (pri26==3'h4); +assign req_p4[27] = valid[27] & (pri27==3'h4); +assign req_p4[28] = valid[28] & (pri28==3'h4); +assign req_p4[29] = valid[29] & (pri29==3'h4); +assign req_p4[30] = valid[30] & (pri30==3'h4); + +assign req_p5[0] = valid[0] & (pri0==3'h5); +assign req_p5[1] = valid[1] & (pri1==3'h5); +assign req_p5[2] = valid[2] & (pri2==3'h5); +assign req_p5[3] = valid[3] & (pri3==3'h5); +assign req_p5[4] = valid[4] & (pri4==3'h5); +assign req_p5[5] = valid[5] & (pri5==3'h5); +assign req_p5[6] = valid[6] & (pri6==3'h5); +assign req_p5[7] = valid[7] & (pri7==3'h5); +assign req_p5[8] = valid[8] & (pri8==3'h5); +assign req_p5[9] = valid[9] & (pri9==3'h5); +assign req_p5[10] = valid[10] & (pri10==3'h5); +assign req_p5[11] = valid[11] & (pri11==3'h5); +assign req_p5[12] = valid[12] & (pri12==3'h5); +assign req_p5[13] = valid[13] & (pri13==3'h5); +assign req_p5[14] = valid[14] & (pri14==3'h5); +assign req_p5[15] = valid[15] & (pri15==3'h5); +assign req_p5[16] = valid[16] & (pri16==3'h5); +assign req_p5[17] = valid[17] & (pri17==3'h5); +assign req_p5[18] = valid[18] & (pri18==3'h5); +assign req_p5[19] = valid[19] & (pri19==3'h5); +assign req_p5[20] = valid[20] & (pri20==3'h5); +assign req_p5[21] = valid[21] & (pri21==3'h5); +assign req_p5[22] = valid[22] & (pri22==3'h5); +assign req_p5[23] = valid[23] & (pri23==3'h5); +assign req_p5[24] = valid[24] & (pri24==3'h5); +assign req_p5[25] = valid[25] & (pri25==3'h5); +assign req_p5[26] = valid[26] & (pri26==3'h5); +assign req_p5[27] = valid[27] & (pri27==3'h5); +assign req_p5[28] = valid[28] & (pri28==3'h5); +assign req_p5[29] = valid[29] & (pri29==3'h5); +assign req_p5[30] = valid[30] & (pri30==3'h5); + +assign req_p6[0] = valid[0] & (pri0==3'h6); +assign req_p6[1] = valid[1] & (pri1==3'h6); +assign req_p6[2] = valid[2] & (pri2==3'h6); +assign req_p6[3] = valid[3] & (pri3==3'h6); +assign req_p6[4] = valid[4] & (pri4==3'h6); +assign req_p6[5] = valid[5] & (pri5==3'h6); +assign req_p6[6] = valid[6] & (pri6==3'h6); +assign req_p6[7] = valid[7] & (pri7==3'h6); +assign req_p6[8] = valid[8] & (pri8==3'h6); +assign req_p6[9] = valid[9] & (pri9==3'h6); +assign req_p6[10] = valid[10] & (pri10==3'h6); +assign req_p6[11] = valid[11] & (pri11==3'h6); +assign req_p6[12] = valid[12] & (pri12==3'h6); +assign req_p6[13] = valid[13] & (pri13==3'h6); +assign req_p6[14] = valid[14] & (pri14==3'h6); +assign req_p6[15] = valid[15] & (pri15==3'h6); +assign req_p6[16] = valid[16] & (pri16==3'h6); +assign req_p6[17] = valid[17] & (pri17==3'h6); +assign req_p6[18] = valid[18] & (pri18==3'h6); +assign req_p6[19] = valid[19] & (pri19==3'h6); +assign req_p6[20] = valid[20] & (pri20==3'h6); +assign req_p6[21] = valid[21] & (pri21==3'h6); +assign req_p6[22] = valid[22] & (pri22==3'h6); +assign req_p6[23] = valid[23] & (pri23==3'h6); +assign req_p6[24] = valid[24] & (pri24==3'h6); +assign req_p6[25] = valid[25] & (pri25==3'h6); +assign req_p6[26] = valid[26] & (pri26==3'h6); +assign req_p6[27] = valid[27] & (pri27==3'h6); +assign req_p6[28] = valid[28] & (pri28==3'h6); +assign req_p6[29] = valid[29] & (pri29==3'h6); +assign req_p6[30] = valid[30] & (pri30==3'h6); + +assign req_p7[0] = valid[0] & (pri0==3'h7); +assign req_p7[1] = valid[1] & (pri1==3'h7); +assign req_p7[2] = valid[2] & (pri2==3'h7); +assign req_p7[3] = valid[3] & (pri3==3'h7); +assign req_p7[4] = valid[4] & (pri4==3'h7); +assign req_p7[5] = valid[5] & (pri5==3'h7); +assign req_p7[6] = valid[6] & (pri6==3'h7); +assign req_p7[7] = valid[7] & (pri7==3'h7); +assign req_p7[8] = valid[8] & (pri8==3'h7); +assign req_p7[9] = valid[9] & (pri9==3'h7); +assign req_p7[10] = valid[10] & (pri10==3'h7); +assign req_p7[11] = valid[11] & (pri11==3'h7); +assign req_p7[12] = valid[12] & (pri12==3'h7); +assign req_p7[13] = valid[13] & (pri13==3'h7); +assign req_p7[14] = valid[14] & (pri14==3'h7); +assign req_p7[15] = valid[15] & (pri15==3'h7); +assign req_p7[16] = valid[16] & (pri16==3'h7); +assign req_p7[17] = valid[17] & (pri17==3'h7); +assign req_p7[18] = valid[18] & (pri18==3'h7); +assign req_p7[19] = valid[19] & (pri19==3'h7); +assign req_p7[20] = valid[20] & (pri20==3'h7); +assign req_p7[21] = valid[21] & (pri21==3'h7); +assign req_p7[22] = valid[22] & (pri22==3'h7); +assign req_p7[23] = valid[23] & (pri23==3'h7); +assign req_p7[24] = valid[24] & (pri24==3'h7); +assign req_p7[25] = valid[25] & (pri25==3'h7); +assign req_p7[26] = valid[26] & (pri26==3'h7); +assign req_p7[27] = valid[27] & (pri27==3'h7); +assign req_p7[28] = valid[28] & (pri28==3'h7); +assign req_p7[29] = valid[29] & (pri29==3'h7); +assign req_p7[30] = valid[30] & (pri30==3'h7); + +// RR Arbiter for priority 0 +wb_dma_ch_arb u1( + .clk( clk ), + .rst( rst ), + .req( req_p0 ), + .gnt( gnt_p0_d ), + .advance( next_ch ) + ); +// RR Arbiter for priority 1 +wb_dma_ch_arb u2( + .clk( clk ), + .rst( rst ), + .req( req_p1 ), + .gnt( gnt_p1_d ), + .advance( next_ch ) + ); + +// RR Arbiter for priority 2 +wb_dma_ch_arb u3( + .clk( clk ), + .rst( rst ), + .req( req_p2 ), + .gnt( gnt_p2_d ), + .advance( next_ch ) + ); +// RR Arbiter for priority 3 +wb_dma_ch_arb u4( + .clk( clk ), + .rst( rst ), + .req( req_p3 ), + .gnt( gnt_p3_d ), + .advance( next_ch ) + ); +// RR Arbiter for priority 4 +wb_dma_ch_arb u5( + .clk( clk ), + .rst( rst ), + .req( req_p4 ), + .gnt( gnt_p4_d ), + .advance( next_ch ) + ); +// RR Arbiter for priority 5 +wb_dma_ch_arb u6( + .clk( clk ), + .rst( rst ), + .req( req_p5 ), + .gnt( gnt_p5_d ), + .advance( next_ch ) + ); +// RR Arbiter for priority 6 +wb_dma_ch_arb u7( + .clk( clk ), + .rst( rst ), + .req( req_p6 ), + .gnt( gnt_p6_d ), + .advance( next_ch ) + ); +// RR Arbiter for priority 7 +wb_dma_ch_arb u8( + .clk( clk ), + .rst( rst ), + .req( req_p7 ), + .gnt( gnt_p7_d ), + .advance( next_ch ) + ); + +// Select grant based on number of priorities +assign gnt_p0 = gnt_p0_d; +assign gnt_p1 = gnt_p1_d; +assign gnt_p2 = (pri_sel==2'd0) ? 5'h0 : gnt_p2_d; +assign gnt_p3 = (pri_sel==2'd0) ? 5'h0 : gnt_p3_d; +assign gnt_p4 = (pri_sel==2'd2) ? gnt_p4_d : 5'h0; +assign gnt_p5 = (pri_sel==2'd2) ? gnt_p5_d : 5'h0; +assign gnt_p6 = (pri_sel==2'd2) ? gnt_p6_d : 5'h0; +assign gnt_p7 = (pri_sel==2'd2) ? gnt_p7_d : 5'h0; + +endmodule Index: wb_dma/trunk/rtl/verilog/wb_dma_defines.v =================================================================== --- wb_dma/trunk/rtl/verilog/wb_dma_defines.v (nonexistent) +++ wb_dma/trunk/rtl/verilog/wb_dma_defines.v (revision 17) @@ -0,0 +1,116 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE DMA Definitions //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/wb_dma/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: wb_dma_defines.v,v 1.5 2002-02-01 01:54:45 rudi Exp $ +// +// $Date: 2002-02-01 01:54:45 $ +// $Revision: 1.5 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.4 2001/10/19 04:35:04 rudi +// +// - Made the core parameterized +// +// Revision 1.3 2001/09/07 15:34:38 rudi +// +// Changed reset to active high. +// +// Revision 1.2 2001/08/15 05:40:30 rudi +// +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// - Added Section 3.10, describing DMA restart. +// +// Revision 1.1 2001/07/29 08:57:02 rudi +// +// +// 1) Changed Directory Structure +// 2) Added restart signal (REST) +// +// Revision 1.2 2001/06/05 10:22:37 rudi +// +// +// - Added Support of up to 31 channels +// - Added support for 2,4 and 8 priority levels +// - Now can have up to 31 channels +// - Added many configuration items +// - Changed reset to async +// +// Revision 1.1.1.1 2001/03/19 13:11:09 rudi +// Initial Release +// +// +// + +`timescale 1ns / 10ps + +// This define selects how the slave interface determines if +// the internal register file or pass through mode are selected. +// This should be a simple address decoder. "wb_addr_i" is the +// WISHBONE address bus (32 bits wide). +// NOTE: The entire pass-through mode is implemented in combinatorial +// logic only. So the more address lines we look at and compare here +// the higher will be the initial delay when pass-through mode is selected. +// Here we look at the top 8 address bit. If they are all 1, the +// register file is selected. Use this with caution !!! +`define WDMA_REG_SEL (wb_addr_i[31:28] == rf_addr) + + +// DO NOT MODIFY BEYOND THIS POINT +// CSR Bits +`define WDMA_CH_EN 0 +`define WDMA_DST_SEL 1 +`define WDMA_SRC_SEL 2 +`define WDMA_INC_DST 3 +`define WDMA_INC_SRC 4 +`define WDMA_MODE 5 +`define WDMA_ARS 6 +`define WDMA_USE_ED 7 +`define WDMA_WRB 8 +`define WDMA_STOP 9 +`define WDMA_BUSY 10 +`define WDMA_DONE 11 +`define WDMA_ERR 12 +`define WDMA_ED_EOL 20 + Index: wb_dma/trunk/rtl/verilog/wb_dma_ch_arb.v =================================================================== --- wb_dma/trunk/rtl/verilog/wb_dma_ch_arb.v (nonexistent) +++ wb_dma/trunk/rtl/verilog/wb_dma_ch_arb.v (revision 17) @@ -0,0 +1,2153 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE DMA Channel Arbiter //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/wb_dma/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: wb_dma_ch_arb.v,v 1.2 2002-02-01 01:54:44 rudi Exp $ +// +// $Date: 2002-02-01 01:54:44 $ +// $Revision: 1.2 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.1 2001/07/29 08:57:02 rudi +// +// +// 1) Changed Directory Structure +// 2) Added restart signal (REST) +// +// Revision 1.4 2001/06/14 08:51:25 rudi +// +// +// Changed Module name to match file name. +// +// Revision 1.3 2001/06/13 02:26:46 rudi +// +// +// Small changes after running lint. +// +// Revision 1.2 2001/06/05 10:22:34 rudi +// +// +// - Added Support of up to 31 channels +// - Added support for 2,4 and 8 priority levels +// - Now can have up to 31 channels +// - Added many configuration items +// - Changed reset to async +// +// Revision 1.1.1.1 2001/03/19 13:10:47 rudi +// Initial Release +// +// +// + +`include "wb_dma_defines.v" + +// Arbiter +// +// Implements a simple round robin arbiter for DMA channels of +// same priority + +module wb_dma_ch_arb(clk, rst, req, gnt, advance); + +input clk; +input rst; +input [30:0] req; // Req input +output [4:0] gnt; // Grant output +input advance; // Next Target + +/////////////////////////////////////////////////////////////////////// +// +// Definitions +// + +parameter [4:0] + grant0 = 5'h0, + grant1 = 5'h1, + grant2 = 5'h2, + grant3 = 5'h3, + grant4 = 5'h4, + grant5 = 5'h5, + grant6 = 5'h6, + grant7 = 5'h7, + grant8 = 5'h8, + grant9 = 5'h9, + grant10 = 5'ha, + grant11 = 5'hb, + grant12 = 5'hc, + grant13 = 5'hd, + grant14 = 5'he, + grant15 = 5'hf, + grant16 = 5'h10, + grant17 = 5'h11, + grant18 = 5'h12, + grant19 = 5'h13, + grant20 = 5'h14, + grant21 = 5'h15, + grant22 = 5'h16, + grant23 = 5'h17, + grant24 = 5'h18, + grant25 = 5'h19, + grant26 = 5'h1a, + grant27 = 5'h1b, + grant28 = 5'h1c, + grant29 = 5'h1d, + grant30 = 5'h1e; + +/////////////////////////////////////////////////////////////////////// +// +// Local Registers and Wires +// + +reg [4:0] state, next_state; + +/////////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +assign gnt = state; + +always@(posedge clk or negedge rst) + if(!rst) state <= #1 grant0; + else state <= #1 next_state; + +/////////////////////////////////////////////////////////////////////// +// +// Next State Logic +// - implements round robin arbitration algorithm +// - switches grant if current req is dropped or next is asserted +// - parks at last grant +// + +always@(state or req or advance) + begin + next_state = state; // Default Keep State + case(state) // synopsys parallel_case full_case + grant0: + // if this req is dropped or next is asserted, check for other req's + if(!req[0] | advance) + begin + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + end + grant1: + // if this req is dropped or next is asserted, check for other req's + if(!req[1] | advance) + begin + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + end + grant2: + // if this req is dropped or next is asserted, check for other req's + if(!req[2] | advance) + begin + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + end + grant3: + // if this req is dropped or next is asserted, check for other req's + if(!req[3] | advance) + begin + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + end + grant4: + // if this req is dropped or next is asserted, check for other req's + if(!req[4] | advance) + begin + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + end + grant5: + // if this req is dropped or next is asserted, check for other req's + if(!req[5] | advance) + begin + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + end + grant6: + // if this req is dropped or next is asserted, check for other req's + if(!req[6] | advance) + begin + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + end + grant7: + // if this req is dropped or next is asserted, check for other req's + if(!req[7] | advance) + begin + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + end + grant8: + // if this req is dropped or next is asserted, check for other req's + if(!req[8] | advance) + begin + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + end + grant9: + // if this req is dropped or next is asserted, check for other req's + if(!req[9] | advance) + begin + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + end + grant10: + // if this req is dropped or next is asserted, check for other req's + if(!req[10] | advance) + begin + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + end + grant11: + // if this req is dropped or next is asserted, check for other req's + if(!req[11] | advance) + begin + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + end + grant12: + // if this req is dropped or next is asserted, check for other req's + if(!req[12] | advance) + begin + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + end + grant13: + // if this req is dropped or next is asserted, check for other req's + if(!req[13] | advance) + begin + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + end + grant14: + // if this req is dropped or next is asserted, check for other req's + if(!req[14] | advance) + begin + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + end + grant15: + // if this req is dropped or next is asserted, check for other req's + if(!req[15] | advance) + begin + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + end + grant16: + // if this req is dropped or next is asserted, check for other req's + if(!req[16] | advance) + begin + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + end + grant17: + // if this req is dropped or next is asserted, check for other req's + if(!req[17] | advance) + begin + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + end + grant18: + // if this req is dropped or next is asserted, check for other req's + if(!req[18] | advance) + begin + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + end + grant19: + // if this req is dropped or next is asserted, check for other req's + if(!req[19] | advance) + begin + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + end + grant20: + // if this req is dropped or next is asserted, check for other req's + if(!req[20] | advance) + begin + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + end + grant21: + // if this req is dropped or next is asserted, check for other req's + if(!req[21] | advance) + begin + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + end + grant22: + // if this req is dropped or next is asserted, check for other req's + if(!req[22] | advance) + begin + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + end + grant23: + // if this req is dropped or next is asserted, check for other req's + if(!req[23] | advance) + begin + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + end + grant24: + // if this req is dropped or next is asserted, check for other req's + if(!req[24] | advance) + begin + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + end + grant25: + // if this req is dropped or next is asserted, check for other req's + if(!req[25] | advance) + begin + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + end + grant26: + // if this req is dropped or next is asserted, check for other req's + if(!req[26] | advance) + begin + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + end + grant27: + // if this req is dropped or next is asserted, check for other req's + if(!req[27] | advance) + begin + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + end + grant28: + // if this req is dropped or next is asserted, check for other req's + if(!req[28] | advance) + begin + if(req[29]) next_state = grant29; + else + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + end + grant29: + // if this req is dropped or next is asserted, check for other req's + if(!req[29] | advance) + begin + if(req[30]) next_state = grant30; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + end + grant30: + // if this req is dropped or next is asserted, check for other req's + if(!req[30] | advance) + begin + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[8]) next_state = grant8; + else + if(req[9]) next_state = grant9; + else + if(req[10]) next_state = grant10; + else + if(req[11]) next_state = grant11; + else + if(req[12]) next_state = grant12; + else + if(req[13]) next_state = grant13; + else + if(req[14]) next_state = grant14; + else + if(req[15]) next_state = grant15; + else + if(req[16]) next_state = grant16; + else + if(req[17]) next_state = grant17; + else + if(req[18]) next_state = grant18; + else + if(req[19]) next_state = grant19; + else + if(req[20]) next_state = grant20; + else + if(req[21]) next_state = grant21; + else + if(req[22]) next_state = grant22; + else + if(req[23]) next_state = grant23; + else + if(req[24]) next_state = grant24; + else + if(req[25]) next_state = grant25; + else + if(req[26]) next_state = grant26; + else + if(req[27]) next_state = grant27; + else + if(req[28]) next_state = grant28; + else + if(req[29]) next_state = grant29; + end + endcase + end + +endmodule + Index: wb_dma/trunk/rtl/verilog/wb_dma_inc30r.v =================================================================== --- wb_dma/trunk/rtl/verilog/wb_dma_inc30r.v (nonexistent) +++ wb_dma/trunk/rtl/verilog/wb_dma_inc30r.v (revision 17) @@ -0,0 +1,92 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE DMA Primitives //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/wb_dma/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: wb_dma_inc30r.v,v 1.2 2002-02-01 01:54:45 rudi Exp $ +// +// $Date: 2002-02-01 01:54:45 $ +// $Revision: 1.2 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.1 2001/07/29 08:57:02 rudi +// +// +// 1) Changed Directory Structure +// 2) Added restart signal (REST) +// +// Revision 1.2 2001/06/05 10:22:37 rudi +// +// +// - Added Support of up to 31 channels +// - Added support for 2,4 and 8 priority levels +// - Now can have up to 31 channels +// - Added many configuration items +// - Changed reset to async +// +// Revision 1.1.1.1 2001/03/19 13:11:12 rudi +// Initial Release +// +// +// + +`include "wb_dma_defines.v" + +module wb_dma_inc30r(clk, in, out); +input clk; +input [29:0] in; +output [29:0] out; + +// INC30_CENTER indicates the center bit of the 30 bit incrementor +// so it can be easily manually optimized for best performance +parameter INC30_CENTER = 16; + +reg [INC30_CENTER:0] out_r; + +always @(posedge clk) + out_r <= #1 in[(INC30_CENTER - 1):0] + 1; + +assign out[29:INC30_CENTER] = in[29:INC30_CENTER] + out_r[INC30_CENTER]; +assign out[(INC30_CENTER - 1):0] = out_r; + +endmodule + Index: wb_dma/trunk/rtl/verilog/wb_dma_ch_rf.v =================================================================== --- wb_dma/trunk/rtl/verilog/wb_dma_ch_rf.v (nonexistent) +++ wb_dma/trunk/rtl/verilog/wb_dma_ch_rf.v (revision 17) @@ -0,0 +1,583 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE DMA One Channel Register File //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/wb_dma/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: wb_dma_ch_rf.v,v 1.5 2002-02-01 01:54:45 rudi Exp $ +// +// $Date: 2002-02-01 01:54:45 $ +// $Revision: 1.5 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.4 2001/10/30 02:06:17 rudi +// +// - Fixed problem where synthesis tools would instantiate latches instead of flip-flops +// +// Revision 1.3 2001/10/19 04:35:04 rudi +// +// - Made the core parameterized +// +// Revision 1.2 2001/08/15 05:40:30 rudi +// +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// - Added Section 3.10, describing DMA restart. +// +// Revision 1.1 2001/07/29 08:57:02 rudi +// +// +// 1) Changed Directory Structure +// 2) Added restart signal (REST) +// +// Revision 1.3 2001/06/14 08:50:01 rudi +// +// Changed Module Name to match file name. +// +// Revision 1.2 2001/06/13 02:26:48 rudi +// +// +// Small changes after running lint. +// +// Revision 1.1 2001/06/05 10:25:27 rudi +// +// +// Initial checkin of register file for one channel. +// +// +// +// + +`include "wb_dma_defines.v" + +module wb_dma_ch_rf( clk, rst, + pointer, pointer_s, ch_csr, ch_txsz, ch_adr0, ch_adr1, + ch_am0, ch_am1, sw_pointer, ch_stop, ch_dis, int, + + wb_rf_din, wb_rf_adr, wb_rf_we, wb_rf_re, + + // DMA Registers Write Back Channel Select + ch_sel, ndnr, + + // DMA Engine Status + dma_busy, dma_err, dma_done, dma_done_all, + + // DMA Engine Reg File Update ctrl signals + de_csr, de_txsz, de_adr0, de_adr1, + de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we, + de_fetch_descr, dma_rest, + ptr_set + + ); + +parameter [4:0] CH_NO = 5'h0; // This Instances Channel ID +parameter [0:0] CH_EN = 1'b1; // This channel exists +parameter [0:0] HAVE_ARS = 1'b1; // 1=this Instance Supports ARS +parameter [0:0] HAVE_ED = 1'b1; // 1=this Instance Supports External Descriptors +parameter [0:0] HAVE_CBUF= 1'b1; // 1=this Instance Supports Cyclic Buffers + +input clk, rst; + +output [31:0] pointer; +output [31:0] pointer_s; +output [31:0] ch_csr; +output [31:0] ch_txsz; +output [31:0] ch_adr0; +output [31:0] ch_adr1; +output [31:0] ch_am0; +output [31:0] ch_am1; +output [31:0] sw_pointer; +output ch_stop; +output ch_dis; +output int; + +input [31:0] wb_rf_din; +input [7:0] wb_rf_adr; +input wb_rf_we; +input wb_rf_re; + +input [4:0] ch_sel; +input ndnr; + +// DMA Engine Status +input dma_busy, dma_err, dma_done, dma_done_all; + +// DMA Engine Reg File Update ctrl signals +input [31:0] de_csr; +input [11:0] de_txsz; +input [31:0] de_adr0; +input [31:0] de_adr1; +input de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we, ptr_set; +input de_fetch_descr; +input dma_rest; + +//////////////////////////////////////////////////////////////////// +// +// Local Wires and Registers +// + +wire [31:0] pointer; +reg [27:0] pointer_r; +reg [27:0] pointer_sr; +reg ptr_valid; +reg ch_eol; + +wire [31:0] ch_csr, ch_txsz; + +reg [8:0] ch_csr_r; +reg [2:0] ch_csr_r2; +reg [2:0] ch_csr_r3; +reg [2:0] int_src_r; +reg ch_err_r; +reg ch_stop; +reg ch_busy; +reg ch_done; +reg ch_err; +reg rest_en; + +reg [10:0] ch_chk_sz_r; +reg [11:0] ch_tot_sz_r; +reg [22:0] ch_txsz_s; +reg ch_sz_inf; + +wire [31:0] ch_adr0, ch_adr1; +reg [29:0] ch_adr0_r, ch_adr1_r; +wire [31:0] ch_am0, ch_am1; +reg [27:0] ch_am0_r, ch_am1_r; + +reg [29:0] ch_adr0_s, ch_adr1_s; + +reg [29:0] sw_pointer_r; +wire sw_pointer_we; +wire [28:0] cmp_adr; +reg ch_dis; +wire ch_enable; + +wire pointer_we; +wire ch_csr_we, ch_csr_re, ch_txsz_we, ch_adr0_we, ch_adr1_we; +wire ch_am0_we, ch_am1_we; +reg ch_rl; +wire ch_done_we; +wire ch_err_we; +wire chunk_done_we; + +wire ch_csr_dewe, ch_txsz_dewe, ch_adr0_dewe, ch_adr1_dewe; + +wire this_ptr_set; +wire ptr_inv; + +//////////////////////////////////////////////////////////////////// +// +// Aliases +// + +assign ch_adr0 = CH_EN ? {ch_adr0_r, 2'h0} : 32'h0; +assign ch_adr1 = CH_EN ? {ch_adr1_r, 2'h0} : 32'h0; +assign ch_am0 = (CH_EN & HAVE_CBUF) ? {ch_am0_r, 4'h0} : 32'hffff_fff0; +assign ch_am1 = (CH_EN & HAVE_CBUF) ? {ch_am1_r, 4'h0} : 32'hffff_fff0; +assign sw_pointer = (CH_EN & HAVE_CBUF) ? {sw_pointer_r,2'h0} : 32'h0; + +assign pointer = CH_EN ? {pointer_r, 3'h0, ptr_valid} : 32'h0; +assign pointer_s = CH_EN ? {pointer_sr, 4'h0} : 32'h0; +assign ch_csr = CH_EN ? {9'h0, int_src_r, ch_csr_r3, rest_en, ch_csr_r2, + ch_err, ch_done, ch_busy, 1'b0, ch_csr_r[8:1], ch_enable} : 32'h0; +assign ch_txsz = CH_EN ? {5'h0, ch_chk_sz_r, ch_sz_inf, 3'h0, ch_tot_sz_r} : 32'h0; + +assign ch_enable = CH_EN ? (ch_csr_r[`WDMA_CH_EN] & (HAVE_CBUF ? !ch_dis : 1'b1) ) : 1'b0; + +//////////////////////////////////////////////////////////////////// +// +// CH0 control signals +// + +parameter [4:0] CH_ADR = CH_NO + 5'h1; + +assign ch_csr_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h0); +assign ch_csr_re = CH_EN & wb_rf_re & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h0); +assign ch_txsz_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h1); +assign ch_adr0_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h2); +assign ch_am0_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h3); +assign ch_adr1_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h4); +assign ch_am1_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h5); +assign pointer_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h6); +assign sw_pointer_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h7); + +assign ch_done_we = CH_EN & (((ch_sel==CH_NO) & dma_done_all) | ndnr) & + (ch_csr[`WDMA_USE_ED] ? ch_eol : !ch_csr[`WDMA_ARS]); +assign chunk_done_we = CH_EN & (ch_sel==CH_NO) & dma_done; +assign ch_err_we = CH_EN & (ch_sel==CH_NO) & dma_err; +assign ch_csr_dewe = CH_EN & de_csr_we & (ch_sel==CH_NO); +assign ch_txsz_dewe = CH_EN & de_txsz_we & (ch_sel==CH_NO); +assign ch_adr0_dewe = CH_EN & de_adr0_we & (ch_sel==CH_NO); +assign ch_adr1_dewe = CH_EN & de_adr1_we & (ch_sel==CH_NO); + +assign ptr_inv = CH_EN & ((ch_sel==CH_NO) & dma_done_all) | ndnr; +assign this_ptr_set = CH_EN & ptr_set & (ch_sel==CH_NO); + +always @(posedge clk) + ch_rl <= #1 CH_EN & HAVE_ARS & ( + (rest_en & dma_rest) | + ((ch_sel==CH_NO) & dma_done_all & ch_csr[`WDMA_ARS] & !ch_csr[`WDMA_USE_ED]) + ); + +// --------------------------------------------------- +// Pointers + +always @(posedge clk or negedge rst) + if(!rst) ptr_valid <= #1 1'b0; + else + if(CH_EN & HAVE_ED) + begin + if( this_ptr_set | (rest_en & dma_rest) ) + ptr_valid <= #1 1'b1; + else + if(ptr_inv) ptr_valid <= #1 1'b0; + end + else ptr_valid <= #1 1'b0; + +always @(posedge clk or negedge rst) + if(!rst) ch_eol <= #1 1'b0; + else + if(CH_EN & HAVE_ED) + begin + if(ch_csr_dewe) ch_eol <= #1 de_csr[`WDMA_ED_EOL]; + else + if(ch_done_we) ch_eol <= #1 1'b0; + end + else ch_eol <= #1 1'b0; + +always @(posedge clk) + if(CH_EN & HAVE_ED) + begin + if(pointer_we) pointer_r <= #1 wb_rf_din[31:4]; + else + if(this_ptr_set) pointer_r <= #1 de_csr[31:4]; + end + else pointer_r <= #1 1'b0; + +always @(posedge clk) + if(CH_EN & HAVE_ED) + begin + if(this_ptr_set) pointer_sr <= #1 pointer_r; + end + else pointer_sr <= #1 1'b0; + +// --------------------------------------------------- +// CSR + +always @(posedge clk or negedge rst) + if(!rst) ch_csr_r <= #1 1'b0; + else + if(CH_EN) + begin + if(ch_csr_we) ch_csr_r <= #1 wb_rf_din[8:0]; + else + begin + if(ch_done_we) ch_csr_r[`WDMA_CH_EN] <= #1 1'b0; + if(ch_csr_dewe) ch_csr_r[4:1] <= #1 de_csr[19:16]; + end + end + +// done bit +always @(posedge clk or negedge rst) + if(!rst) ch_done <= #1 1'b0; + else + if(CH_EN) + begin + if(ch_csr_we) ch_done <= #1 !wb_rf_din[`WDMA_CH_EN]; + else + if(ch_done_we) ch_done <= #1 1'b1; + end + +// busy bit +always @(posedge clk) + ch_busy <= #1 CH_EN & (ch_sel==CH_NO) & dma_busy; + +// stop bit +always @(posedge clk) + ch_stop <= #1 CH_EN & ch_csr_we & wb_rf_din[`WDMA_STOP]; + +// error bit +always @(posedge clk or negedge rst) + if(!rst) ch_err <= #1 1'b0; + else + if(CH_EN) + begin + if(ch_err_we) ch_err <= #1 1'b1; + else + if(ch_csr_re) ch_err <= #1 1'b0; + end + +// Priority Bits +always @(posedge clk or negedge rst) + if(!rst) ch_csr_r2 <= #1 3'h0; + else + if(CH_EN & ch_csr_we) ch_csr_r2 <= #1 wb_rf_din[15:13]; + +// Restart Enable Bit (REST) +always @(posedge clk or negedge rst) + if(!rst) rest_en <= #1 1'b0; + else + if(CH_EN & ch_csr_we) rest_en <= #1 wb_rf_din[16]; + +// INT Mask +always @(posedge clk or negedge rst) + if(!rst) ch_csr_r3 <= #1 3'h0; + else + if(CH_EN & ch_csr_we) ch_csr_r3 <= #1 wb_rf_din[19:17]; + +// INT Source +always @(posedge clk or negedge rst) + if(!rst) int_src_r[2] <= #1 1'b0; + else + if(CH_EN) + begin + if(chunk_done_we) int_src_r[2] <= #1 1'b1; + else + if(ch_csr_re) int_src_r[2] <= #1 1'b0; + end + +always @(posedge clk or negedge rst) + if(!rst) int_src_r[1] <= #1 1'b0; + else + if(CH_EN) + begin + if(ch_done_we) int_src_r[1] <= #1 1'b1; + else + if(ch_csr_re) int_src_r[1] <= #1 1'b0; + end + +always @(posedge clk or negedge rst) + if(!rst) int_src_r[0] <= #1 1'b0; + else + if(CH_EN) + begin + if(ch_err_we) int_src_r[0] <= #1 1'b1; + else + if(ch_csr_re) int_src_r[0] <= #1 1'b0; + end + +// Interrupt Output +assign int = |(int_src_r & ch_csr_r3) & CH_EN; + +// --------------------------------------------------- +// TXZS +always @(posedge clk) + if(CH_EN) + begin + if(ch_txsz_we) + {ch_chk_sz_r, ch_tot_sz_r} <= #1 {wb_rf_din[26:16], wb_rf_din[11:0]}; + else + if(ch_txsz_dewe) + ch_tot_sz_r <= #1 de_txsz; + else + if(ch_rl) + {ch_chk_sz_r, ch_tot_sz_r} <= #1 ch_txsz_s; + end + +// txsz shadow register +always @(posedge clk) + if(CH_EN & HAVE_ARS) + begin + + if(ch_txsz_we) ch_txsz_s <= #1 {wb_rf_din[26:16], wb_rf_din[11:0]}; + else + if(rest_en & ch_txsz_dewe & de_fetch_descr) + ch_txsz_s[11:0] <= #1 de_txsz[11:0]; + end + +// Infinite Size indicator +always @(posedge clk) + if(CH_EN) + begin + if(ch_txsz_we) ch_sz_inf <= #1 wb_rf_din[15]; + end + +// --------------------------------------------------- +// ADR0 +always @(posedge clk) + if(CH_EN) + begin + if(ch_adr0_we) ch_adr0_r <= #1 wb_rf_din[31:2]; + else + if(ch_adr0_dewe) ch_adr0_r <= #1 de_adr0[31:2]; + else + if(ch_rl) ch_adr0_r <= #1 ch_adr0_s; + end + +// Adr0 shadow register +always @(posedge clk) + if(CH_EN & HAVE_ARS) + begin + if(ch_adr0_we) ch_adr0_s <= #1 wb_rf_din[31:2]; + else + if(rest_en & ch_adr0_dewe & de_fetch_descr) + ch_adr0_s <= #1 de_adr0[31:2]; + end + +// --------------------------------------------------- +// AM0 +always @(posedge clk or negedge rst) + if(!rst) ch_am0_r <= #1 28'hfffffff; + else + if(ch_am0_we) ch_am0_r <= #1 wb_rf_din[31:4]; + +// --------------------------------------------------- +// ADR1 +always @(posedge clk) + if(CH_EN) + begin + if(ch_adr1_we) ch_adr1_r <= #1 wb_rf_din[31:2]; + else + if(ch_adr1_dewe) ch_adr1_r <= #1 de_adr1[31:2]; + else + if(ch_rl) ch_adr1_r <= #1 ch_adr1_s; + end + +// Adr1 shadow register +always @(posedge clk) + if(CH_EN & HAVE_ARS) + begin + if(ch_adr1_we) ch_adr1_s <= #1 wb_rf_din[31:2]; + else + if(rest_en & ch_adr1_dewe & de_fetch_descr) + ch_adr1_s <= #1 de_adr1[31:2]; + end + +// --------------------------------------------------- +// AM1 +always @(posedge clk or negedge rst) + if(!rst) ch_am1_r <= #1 28'hfffffff; + else + if(ch_am1_we & CH_EN & HAVE_CBUF) ch_am1_r <= #1 wb_rf_din[31:4]; + +// --------------------------------------------------- +// Software Pointer +always @(posedge clk or negedge rst) + if(!rst) sw_pointer_r <= #1 28'h0; + else + if(sw_pointer_we & CH_EN & HAVE_CBUF) sw_pointer_r <= #1 wb_rf_din[31:4]; + +// --------------------------------------------------- +// Software Pointer Match logic + +assign cmp_adr = ch_csr[2] ? ch_adr1[30:2] : ch_adr0[30:2]; + +always @(posedge clk) + ch_dis <= #1 CH_EN & HAVE_CBUF & (sw_pointer[30:2] == cmp_adr) & sw_pointer[31]; + +endmodule + + +module wb_dma_ch_rf_dummy(clk, rst, + pointer, pointer_s, ch_csr, ch_txsz, ch_adr0, ch_adr1, + ch_am0, ch_am1, sw_pointer, ch_stop, ch_dis, int, + + wb_rf_din, wb_rf_adr, wb_rf_we, wb_rf_re, + + // DMA Registers Write Back Channel Select + ch_sel, ndnr, + + // DMA Engine Status + dma_busy, dma_err, dma_done, dma_done_all, + + // DMA Engine Reg File Update ctrl signals + de_csr, de_txsz, de_adr0, de_adr1, + de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we, + de_fetch_descr, dma_rest, + ptr_set + + ); + +parameter CH_NO = 0; +parameter HAVE_ARS = 1; +parameter HAVE_ED = 1; +parameter HAVE_CBUF= 1; + +input clk, rst; + +output [31:0] pointer; +output [31:0] pointer_s; +output [31:0] ch_csr; +output [31:0] ch_txsz; +output [31:0] ch_adr0; +output [31:0] ch_adr1; +output [31:0] ch_am0; +output [31:0] ch_am1; +output [31:0] sw_pointer; +output ch_stop; +output ch_dis; +output int; + +input [31:0] wb_rf_din; +input [7:0] wb_rf_adr; +input wb_rf_we; +input wb_rf_re; + +input [4:0] ch_sel; +input ndnr; + +// DMA Engine Status +input dma_busy, dma_err, dma_done, dma_done_all; + +// DMA Engine Reg File Update ctrl signals +input [31:0] de_csr; +input [11:0] de_txsz; +input [31:0] de_adr0; +input [31:0] de_adr1; +input de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we, ptr_set; +input de_fetch_descr; +input dma_rest; + +assign pointer = 32'h0; +assign pointer_s = 32'h0; +assign ch_csr = 32'h0; +assign ch_txsz = 32'h0; +assign ch_adr0 = 32'h0; +assign ch_adr1 = 32'h0; +assign ch_am0 = 32'h0; +assign ch_am1 = 32'h0; +assign sw_pointer = 32'h0; +assign ch_stop = 1'b0; +assign ch_dis = 1'b0; +assign int = 1'b0; + +endmodule Index: wb_dma/trunk/doc/dma_doc.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: wb_dma/trunk/doc/dma_doc.pdf =================================================================== --- wb_dma/trunk/doc/dma_doc.pdf (nonexistent) +++ wb_dma/trunk/doc/dma_doc.pdf (revision 17)

wb_dma/trunk/doc/dma_doc.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: wb_dma/trunk/doc/STATUS.txt =================================================================== --- wb_dma/trunk/doc/STATUS.txt (nonexistent) +++ wb_dma/trunk/doc/STATUS.txt (revision 17) @@ -0,0 +1,60 @@ +This file describes the current status of the checked in HDL code. +Please submit all bugs/comments/suggestions regarding the DMA core +to: cores@opencores.org + +Need Help +--------- +I'm looking for help in verifying the core. If you think you can help, +please send an email to the list or to me directly. +Even though I have written a test bench and a few test, I would prefer +if someone else could verify the core as well. + + +STATUS +====== + +Latest Release (10/19/2001) +--------------------------- +- Made the core parameterizable - no more editing of the + wb_defines.v file, just pass the configuration to the core + when instantiating it ! + +Third Release (7/27/2001) +-------------------------- +- Added dma_rest_i. It allows to restart the current transfer at + the beginning. Beginning is defined as the original values that + where either written to the channel registers, or where fetched + from the last external descriptor fetch. +- Made some minor changes: + - Parametarized HW handshake signals (ack, req, nd, rest) +- There still might be many bugs ! Only little testing has been done ! +- Please do not modify the sources (yet !) ! I'm still working on the core. +- Things that are not implemented yet, or are known not to work yet: + - The DMA currently ignores the RTY_I (retry) input. + + +Second Release (5/6/2001) +------------------------- +- Made many, many changes, almost rewrote the entire thing ! + The main changes are: + + - Added Support of up to 31 channels + - Added support for 2,4 and 8 priority levels + - Now can have up to 31 channels + - Added many configuration items + - Changed reset to async + +- There still might be many bugs ! Only little testing has been done ! +- Please do not modify the sources (yet !) ! I'm still working on the core. +- Things that are not implemented yet, or are known not to work yet: + - The DMA currently ignores the RTY_I (retry) input. + + +Initial Release (19/3/2001) +--------------------------- +- This is the very first release of the core +- There might be still many bugs ! Only little testing has been done ! +- Please do not modify the sources (yet !) ! I'm still working on the core. +- Things that are not implemented yet, or are known not to work yet: + - The DMA currently ignores the RTY_I (retry) input. + Index: wb_dma/trunk/doc/README.txt =================================================================== --- wb_dma/trunk/doc/README.txt (nonexistent) +++ wb_dma/trunk/doc/README.txt (revision 17) @@ -0,0 +1,43 @@ + +The WISHBONE DMA/Bridge Project Page is: +http://www.opencores.org/cores/wb_dma/ + +To find out more about me (Rudolf Usselmann), please visit: +http://www.asics.ws + +Directory Structure +------------------- +[core_root] + | + +-doc Documentation + | + +-bench--+ Test Bench + | +- verilog Verilog Sources + | +-vhdl VHDL Sources + | + +-rtl----+ Core RTL Sources + | +-verilog Verilog Sources + | +-vhdl VHDL Sources + | + +-sim----+ + | +-rtl_sim---+ Functional verification Directory + | | +-bin Makefiles/Run Scripts + | | +-run Working Directory + | | + | +-gate_sim--+ Functional & Timing Gate Level + | | Verification Directory + | +-bin Makefiles/Run Scripts + | +-run Working Directory + | + +-lint--+ Lint Directory Tree + | +-bin Makefiles/Run Scripts + | +-run Working Directory + | +-log Linter log & result files + | + +-syn---+ Synthesis Directory Tree + | +-bin Synthesis Scripts + | +-run Working Directory + | +-log Synthesis log files + | +-out Synthesis Output + + Index: wb_dma/trunk/syn/bin/comp.dc =================================================================== --- wb_dma/trunk/syn/bin/comp.dc (nonexistent) +++ wb_dma/trunk/syn/bin/comp.dc (revision 17) @@ -0,0 +1,121 @@ +################################################################################# +# +# Actual Synthesis Script +# +# This script does the actual synthesis +# +# Author: Rudolf Usselmann +# rudi@asics.ws +# +# Revision: +# 3/7/01 RU Initial Sript +# +# +################################################################################# + +# ============================================== +# Setup Design Parameters +source ../bin/design_spec.dc + +# ============================================== +# Setup Libraries +source ../bin/lib_spec.dc + +# ============================================== +# Setup IO Files + +append log_file ../log/$active_design "_cmp.log" +append pre_comp_db_file ../out/$design_name "_pre.db" +append post_comp_db_file ../out/$design_name ".db" +append post_syn_verilog_file ../out/$design_name "_ps.v" + +set junk_file /dev/null +sh rm -f $log_file + +# ============================================== +# Setup Misc Variables + +set hdlin_enable_vpp true ;# Important - this enables 'ifdefs + +# ============================================== +# Read Design + +echo "+++++++++ Reading Design ..." >> $log_file +read_file $pre_comp_db_file >> $log_file + +# ============================================== +# Operating conditions + +echo "+++++++++ Setting up Operation Conditions ..." >> $log_file +current_design $design_name +set_operating_conditions WORST >> $log_file + +# Turn off automatic wire load selection, as this +# always (WHY ???) defaults to "zero_load" +#set auto_wire_load_selection false + +#set_wire_load_mode enclosed >> $log_file +#set_wire_load_mode top >> $log_file +#set_wire_load_model -name suggested_40K >> $log_file + +# ============================================== +# Setup Clocks and Resets + +echo "+++++++++ Setting up Clocks ..." >> $log_file + +set_drive 0 [find port {clk_i}] + +# !!! WISHBONE Clock !!! +set clock_period 5 +create_clock -period $clock_period clk_i +set_clock_skew -uncertainty 0.2 clk_i +set_clock_transition 0.2 clk_i +set_dont_touch_network clk_i + +# !!! Reset !!! +set_drive 0 [find port {rst*}] +set_dont_touch_network [find port {rst*}] + +# ============================================== +# Setup IOs + +echo "+++++++++ Setting up IOs ..." >> $log_file + +# Need to spell out external IOs + +set_driving_cell -cell NAND2D2 -pin Z [all_inputs] >> $junk_file +set_load 0.2 [all_outputs] + +set_input_delay 2.0 -clock clk_i [all_inputs] +set_output_delay 2.0 -clock clk_i [all_outputs] + +# ============================================== +# Setup Area Constrains +set_max_area 0.0 +set compile_sequential_area_recovery true + +# ============================================== +# Force Ultra +set_ultra_optimization -f + +# ============================================== +# Compile Design + +echo "+++++++++ Starting Compile ..." >> $log_file +compile -map_effort low -area_effort low >> $log_file +#compile -map_effort high -area_effort high -boundary_optimization -auto_ungroup >> $log_file + +# ============================================== +# Write Out the optimized design + +echo "+++++++++ Saving Optimized Design ..." >> $log_file +write_file -hierarchy -format verilog -output $post_syn_verilog_file +write_file -hierarchy -format db -output $post_comp_db_file + +# ============================================== +# Create Some Basic Reports + +echo "+++++++++ Reporting Final Results ..." >> $log_file +report_timing -nworst 10 >> $log_file +report_area >> $log_file + Index: wb_dma/trunk/syn/bin/lib_spec.dc =================================================================== --- wb_dma/trunk/syn/bin/lib_spec.dc (nonexistent) +++ wb_dma/trunk/syn/bin/lib_spec.dc (revision 17) @@ -0,0 +1,36 @@ +################################################################################# +# +# Library Specification +# +# Author: Rudolf Usselmann +# rudi@asics.ws +# +# Revision: +# 3/7/01 RU Initial Sript +# +# +################################################################################# + +# ============================================== +# Setup Libraries + +set search_path [list $search_path . \ + /tools/dc_libraries/virtual_silicon/UMCL18U250D2_2.2/design_compiler/ \ + $hdl_src_dir] + +set snps [getenv "SYNOPSYS"] + +set synthetic_library "" +append synthetic_library $snps "/libraries/syn/dw01.sldb " +append synthetic_library $snps "/libraries/syn/dw02.sldb " +append synthetic_library $snps "/libraries/syn/dw03.sldb " +append synthetic_library $snps "/libraries/syn/dw04.sldb " +append synthetic_library $snps "/libraries/syn/dw05.sldb " +append synthetic_library $snps "/libraries/syn/dw06.sldb " +append synthetic_library $snps "/libraries/syn/dw07.sldb " + +set target_library { umcl18u250t2_wc.db } +set link_library "" +append link_library $target_library " " $synthetic_library +set symbol_library { umcl18u250t2.sdb } + Index: wb_dma/trunk/syn/bin/design_spec.dc =================================================================== --- wb_dma/trunk/syn/bin/design_spec.dc (nonexistent) +++ wb_dma/trunk/syn/bin/design_spec.dc (revision 17) @@ -0,0 +1,26 @@ +################################################################################# +# +# Design Specification +# +# Author: Rudolf Usselmann +# rudi@asics.ws +# +# Revision: +# 3/7/01 RU Initial Sript +# +# +################################################################################# + +# ============================================== +# Setup Design Parameters + +set design_files {wb_dma_inc30r wb_dma_ch_arb wb_dma_pri_enc_sub wb_dma_ch_pri_enc wb_dma_ch_sel wb_dma_ch_rf wb_dma_rf wb_dma_wb_mast wb_dma_wb_slv wb_dma_wb_if wb_dma_de wb_dma_top } + +set design_name wb_dma_top +set active_design wb_dma_top + +# Next Statement defines all clocks and resets in the design +set special_net {rst clk} + +set hdl_src_dir ../../rtl/verilog/ + Index: wb_dma/trunk/syn/bin/read.dc =================================================================== --- wb_dma/trunk/syn/bin/read.dc (nonexistent) +++ wb_dma/trunk/syn/bin/read.dc (revision 17) @@ -0,0 +1,65 @@ +################################################################################# +# +# Pre Synthesis Script +# +# This script only reads in the design and saves it in a DB file +# +# Author: Rudolf Usselmann +# rudi@asics.ws +# +# Revision: +# 3/7/01 RU Initial Sript +# +# +################################################################################# + +# ============================================== +# Setup Design Parameters +source ../bin/design_spec.dc + +# ============================================== +# Setup Libraries +source ../bin/lib_spec.dc + +# ============================================== +# Setup IO Files + +append log_file ../log/$active_design "_pre.log" +append pre_comp_db_file ../out/$design_name "_pre.db" +sh rm -f $log_file + +# ============================================== +# Setup Misc Variables + +set hdlin_enable_vpp true ;# Important - this enables 'ifdefs + +# ============================================== +# Read Design + +echo "+++++++++ Analyzing all design files ..." >> $log_file + +foreach module $design_files { + echo "+++++++++ Reading: $module" >> $log_file + echo +++++++++ Reading: $module + set module_file_name "" + append module_file_name $module ".v" + analyze -f verilog $module_file_name >> $log_file + elaborate $module >> $log_file + } + +current_design $active_design + +echo "+++++++++ Linking Design ..." >> $log_file +link >> $log_file + +echo "+++++++++ Uniquifying Design ..." >> $log_file +uniquify >> $log_file + +echo "+++++++++ Checking Design ..." >> $log_file +check_design >> $log_file + +# ============================================== +# Save Design +echo "+++++++++ Saving Design ..." >> $log_file +write_file -hierarchy -format db -output $pre_comp_db_file + Index: wb_dma/trunk =================================================================== --- wb_dma/trunk (nonexistent) +++ wb_dma/trunk (revision 17)

wb_dma/trunk Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: wb_dma/web_uploads =================================================================== --- wb_dma/web_uploads (nonexistent) +++ wb_dma/web_uploads (revision 17)

wb_dma/web_uploads Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: wb_dma/branches =================================================================== --- wb_dma/branches (nonexistent) +++ wb_dma/branches (revision 17)

wb_dma/branches Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: wb_dma/tags/start/doc/STATUS.txt =================================================================== --- wb_dma/tags/start/doc/STATUS.txt (nonexistent) +++ wb_dma/tags/start/doc/STATUS.txt (revision 17) @@ -0,0 +1,23 @@ +This file describes the current status of the checked in HDL code. +Please submit all bugs/comments/suggestions regarding the DMA core +to: cores@opencores.org + +Need Help +--------- +I'm looking for help in verifying the core. If you think you can help, +please send an email to the list or to me directly. +Even though I have written a test bench and a few test, I would prefer +if someone else could verify the core as well. + + +STATUS +====== + +Initial Release (19/3/2001) +--------------------------- +- This is the very first release of the core +- There might be still many bugs ! Only little testing has been done ! +- Please do not modify the sources (yet !) ! I'm still working on the core. +- Things that are not implemented yet, or are known not to work yet: + - The DMA currently ignores the RTY_I (retry) input. + Index: wb_dma/tags/start/doc/README.txt =================================================================== --- wb_dma/tags/start/doc/README.txt (nonexistent) +++ wb_dma/tags/start/doc/README.txt (revision 17) @@ -0,0 +1,10 @@ + +The WISHBONE DMA/Bridge Project Page is: +http://www.opencores.org/cores/wb_dma/ + +The WISHBONE DMA/Bridge core specification can be downloaded from: +http://www.opencores.org/cores/wb_dma/dma_doc.pdf + +To find out more about me (Rudolf Usselmann), please visit: +http://www.asics.ws + Index: wb_dma/tags =================================================================== --- wb_dma/tags (nonexistent) +++ wb_dma/tags (revision 17)

wb_dma/tags Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ##

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