OpenCores
URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

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  • This comparison shows the changes necessary to convert path 
    /
    from Rev 160 to Rev 161
    ↔ Reverse comparison
  •

Rev 160 → Rev 161

/trunk/sim/rtl_sim/run/run
1,9 → 1,5
#!/bin/csh -f
 
rm cds.lib hdl.var RUN_NC
rm nc*
rm -r INCA_libs
 
set failedi = 0;
set failedx = 0;
set all_testsi = 0;
10,9 → 6,25
set all_testsx = 0;
 
 
set internal_tests=(testall lcall negcnt gcd int2bin cast divmul fib sort sqroot div16u test_xram xram_m timer_test counter_test timer2_test interrupt_test interrupt_test2 serial_test r_bank mx_test wdog1 wdog2 wdog3 pca_test)
set external_tests=(testall lcall negcnt gcd int2bin cast divmul fib sort sqroot div16u test_xram xram_m interrupt_test interrupt_test2 r_bank xrom_test mx_test wdog1 wdog2 wdog3)
set internal_tests=(testall lcall \
negcnt gcd int2bin cast divmul fib sort sqroot div16u \
test_xram xram_m \
timer_test counter_test timer2_test interrupt_test serial_test r_bank \
7seg blinkP10 BLINKY calculator cordic Crc cubicroots normalize pwm Sieve sqroot_1 src timer0 \
)
 
set external_tests=(testall lcall \
negcnt gcd int2bin cast divmul fib sort sqroot div16u \
test_xram xram_m \
interrupt_test r_bank xrom_test \
7seg blinkP10 BLINKY calculator cordic Crc cubicroots normalize pwm Sieve sqroot_1 src timer0 \
)
 
rm cds.lib hdl.var RUN_NC
rm nc*
rm -r INCA_libs
 
 
# Prepare all .args files
iteration:
echo ""
66,7 → 78,7
echo "\t@@@ Tesing programs from internal rom"
echo "\t@@@"
 
cp ../oc8051mx_eai.in ../oc8051mx_ea.in
cp ../oc8051_eai.in ../oc8051_ea.in
set i = 0;
foreach internal_test ($internal_tests)
@ i += 1;
75,8 → 87,8
echo "\t### Running test ${i}: ${internal_test}"
echo "\t###"
 
cp ../../../bench/in/${internal_test}.in ../../../bench/in/oc8051mx_rom.in
cp ../../../bench/vec/${internal_test}.vec ../../../bench/vec/oc8051mx_test.vec
cp ../../../bench/in/${internal_test}.in ../../../bench/in/oc8051_rom.in
cp ../../../bench/vec/${internal_test}.vec ../../../bench/vec/oc8051_test.vec
ncsim -NOCOPYRIGHT -f ncsim.args > ../out/ncsim.out
if ($status != 0) then
cat ../out/ncsim.out
90,7 → 102,8
@ all_testsi += 1;
endif
mv ../out/ncsim.out ../out/${internal_test}.out
mv log_file ../out/wb/${internal_test}
 
 
end
 
echo ""
98,7 → 111,7
echo "\t@@@ tesing programs from external rom"
echo "\t@@@"
 
cp ../oc8051mx_eax.in ../oc8051mx_ea.in
cp ../oc8051_eax.in ../oc8051_ea.in
set i = 0;
foreach external_test ($external_tests)
@ i += 1;
106,10 → 119,10
echo "\t###"
echo "\t### Running test ${i}: ${external_test}"
echo "\t###"
 
cp ../../../bench/in/${external_test}.in ../../../bench/in/oc8051mx_xrom.in
cp ../../../bench/vec/${external_test}.vec ../../../bench/vec/oc8051mx_test.vec
cp ../oc8051mx_eax.in ../oc8051mx_ea.in
cp ../../../bench/in/${external_test}.in ../../../bench/in/oc8051_xrom.in
cp ../../../bench/vec/${external_test}.vec ../../../bench/vec/oc8051_test.vec
cp ../oc8051_eax.in ../oc8051_ea.in
ncsim -NOCOPYRIGHT -f ncsim.args > ../out/ncsim.out
if ($status != 0) then
cat ../out/ncsim.out
123,7 → 136,7
@ all_testsx += 1;
endif
mv ../out/ncsim.out ../out/x_${external_test}.out
mv log_file ../out/wb/x_${external_test}
 
end
 
echo ""
133,7 → 146,4
echo "\t### Failed $failedx of $all_testsx external tests"
echo "\t###"
 
rm cds.lib hdl.var RUN_NC
rm nc*
rm -r INCA_libs
 
/trunk/sim/rtl_sim/run/make
1,7 → 146,4
../../../bench/verilog/oc8051mx_tb.v ../../../rtl/verilog/oc8051mx_top.v ../../../rtl/verilog/oc8051mx_mxreg.v ../../../rtl/verilog/oc8051mx_alu_src_sel.v ../../../rtl/verilog/oc8051mx_alu.v ../../../rtl/verilog/oc8051mx_decoder.v ../../../rtl/verilog/oc8051mx_divide.v ../../../rtl/verilog/oc8051mx_multiply.v ../../../rtl/verilog/oc8051mx_memory_interface.v ../../../rtl/verilog/oc8051mx_ram_top.v ../../../bench/verilog/oc8051mx_xram.v ../../../rtl/verilog/oc8051mx_ram.v ../../../rtl/verilog/oc8051mx_acc.v ../../../rtl/verilog/oc8051mx_comp.v ../../../rtl/verilog/oc8051mx_sp.v ../../../bench/verilog/oc8051mx_uart_test.v ../../../rtl/verilog/oc8051mx_rom.v ../../../bench/verilog/oc8051mx_xrom.v ../../../rtl/verilog/oc8051mx_dptr.v ../../../rtl/verilog/oc8051mx_eptr.v ../../../rtl/verilog/oc8051mx_cy_select.v ../../../rtl/verilog/oc8051mx_psw.v ../../../rtl/verilog/oc8051mx_indi_addr.v ../../../rtl/verilog/oc8051mx_ports.v ../../../rtl/verilog/oc8051mx_b_register.v ../../../rtl/verilog/oc8051mx_uart.v ../../../rtl/verilog/oc8051mx_int.v ../../../rtl/verilog/oc8051mx_tc.v ../../../rtl/verilog/oc8051mx_tc2.v ../../../rtl/verilog/oc8051mx_icache.v ../../../rtl/verilog/oc8051mx_cache_ram.v ../../../rtl/verilog/oc8051mx_wb_iinterface.v ../../../rtl/verilog/oc8051mx_sfr.v ../../../rtl/verilog/oc8051mx_mxr.v ../../../rtl/verilog/oc8051mx_wdog.v ../../../rtl/verilog/oc8051mx_pca.v ../../../bench/verilog/wb_bus_mon.v
../../../bench/verilog/oc8051_tb.v ../../../bench/verilog/oc8051_xram.v ../../../bench/verilog/oc8051_uart_test.v ../../../bench/verilog/oc8051_xrom.v ../../../rtl/verilog/oc8051_top.v ../../../rtl/verilog/oc8051_alu_src_sel.v ../../../rtl/verilog/oc8051_alu.v ../../../rtl/verilog/oc8051_decoder.v ../../../rtl/verilog/oc8051_divide.v ../../../rtl/verilog/oc8051_multiply.v ../../../rtl/verilog/oc8051_memory_interface.v ../../../rtl/verilog/oc8051_ram_top.v ../../../rtl/verilog/oc8051_acc.v ../../../rtl/verilog/oc8051_comp.v ../../../rtl/verilog/oc8051_sp.v ../../../rtl/verilog/oc8051_dptr.v ../../../rtl/verilog/oc8051_cy_select.v ../../../rtl/verilog/oc8051_psw.v ../../../rtl/verilog/oc8051_indi_addr.v ../../../rtl/verilog/oc8051_ports.v ../../../rtl/verilog/oc8051_b_register.v ../../../rtl/verilog/oc8051_uart.v ../../../rtl/verilog/oc8051_int.v ../../../rtl/verilog/oc8051_tc.v ../../../rtl/verilog/oc8051_tc2.v ../../../rtl/verilog/oc8051_icache.v ../../../rtl/verilog/oc8051_wb_iinterface.v ../../../rtl/verilog/oc8051_sfr.v ../../../rtl/verilog/oc8051_rom.v ../../../rtl/verilog/oc8051_cache_ram.v ../../../../common/generic_memories/rtl/verilog/generic_dpram.v

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