URL https://opencores.org/ocsvn/or1k/or1k/trunk

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Rev 160 → Rev 161

/trunk/or1200/rtl/verilog/pic.v

0,0 → 1,237

/trunk/or1200/rtl/verilog/pm.v

0,0 → 1,198

/trunk/or1200/rtl/verilog/frz_logic.v

0,0 → 1,146

/trunk/or1200/rtl/verilog/dc_tag.v

0,0 → 1,119

/trunk/or1200/rtl/verilog/or1200.v

0,0 → 1,415

/trunk/or1200/rtl/verilog/multp2_32x32.v

0,0 → 1,2493

/trunk/or1200/rtl/verilog/dc_ram.v

0,0 → 1,226

/trunk/or1200/rtl/verilog/dtlb.v

0,0 → 1,137

/trunk/or1200/rtl/verilog/tt.v

0,0 → 1,183

/trunk/or1200/rtl/verilog/sprs.v

0,0 → 1,226

/trunk/or1200/rtl/verilog/ic.v

0,0 → 1,191

/trunk/or1200/rtl/verilog/dc_fsm.v

0,0 → 1,258

/trunk/or1200/rtl/verilog/reg2mem.v

0,0 → 1,93

/trunk/or1200/rtl/verilog/mem2reg.v

0,0 → 1,244

/trunk/or1200/rtl/verilog/general.h

0,0 → 1,435

/trunk/or1200/rtl/verilog/traceport.v

0,0 → 1,178

/trunk/or1200/rtl/verilog/lsu.v

0,0 → 1,78

/trunk/or1200/rtl/verilog/alu_defs.h

0,0 → 1,82

/trunk/or1200/rtl/verilog/operandmuxes.v

0,0 → 1,115

/trunk/or1200/rtl/verilog/alu.v

0,0 → 1,240

trunk/or1200/rtl/verilog/alu.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/or1200/rtl/verilog/dc.v =================================================================== --- trunk/or1200/rtl/verilog/dc.v (nonexistent) +++ trunk/or1200/rtl/verilog/dc.v (revision 161) @@ -0,0 +1,213 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// OR1200's Data Cache top level //// +//// //// +//// This file is part of the OpenRISC 1200 project //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// Instantiation of all DC blocks. //// +//// //// +//// To Do: //// +//// - make it smaller and faster //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// + +`include "general.h" + +// Data cache + +module dc(clk, rst, clkdiv_by_2, dcbiu_rdy, dclsu_addr, dclsu_lsuop, dclsu_datain, dcbiu_datain, + dclsu_dataout, dcbiu_dataout, dcbiu_addr, dcbiu_read, dcbiu_write, dclsu_stall, + tp2w, tp3w, tpdw +); + +parameter dw = `OPERAND_WIDTH; + +input clk; +input rst; +input clkdiv_by_2; +input dcbiu_rdy; +input [31:0] dclsu_addr; +input [`LSUOP_WIDTH-1:0] dclsu_lsuop; +input [dw-1:0] dclsu_datain; +input [dw-1:0] dcbiu_datain; + +output [dw-1:0] dclsu_dataout; +output [dw-1:0] dcbiu_dataout; +output [31:0] dcbiu_addr; +output dcbiu_read; +output dcbiu_write; +output dclsu_stall; + +input [`TP2W_WIDTH-1:0] tp2w; +input [`TP3W_WIDTH-1:0] tp3w; +input [31:0] tpdw; + +wire [18:0] tag; +wire [dw-1:0] to_dcram; +wire [dw-1:0] from_dcram; +wire [dw-1:0] to_mem2reg; +wire [31:0] saved_addr; +wire refill; +wire [3:0] dcram_we; +wire dctag_we; +wire [dw-1:0] lsu_datain_memaligned; +wire [31:0] dc_addr; +wire refill_first; +wire refill_prepare; +wire refill_start; +wire refill_rest; + +reg hit; +reg [1:0] valid_div; + +wire queue; +wire cntrbusy; +wire dcbiu_valid; + +assign dcbiu_addr = dc_addr; +assign dctag_we = refill; +assign dcbiu_dataout = from_dcram; + +// assign dc_stall = dcbiu_read | dcbiu_write | refill_start; // can't remember if it works +assign queue = (refill && dclsu_lsuop && !refill_first & !refill_rest) ? 1'b1 : 1'b0; + +// assign dclsu_stall = refill_start | (refill_first & ~dcbiu_valid)| refill_rest | queue; // kind of working +assign dclsu_stall = refill_start | (refill_first & ~dcbiu_valid)| refill_rest | queue | cntrbusy; + +// Select between claddr generated by DC FSM and addr[3:2] generated by LSU +assign dc_addr = (refill == 1'b1) ? saved_addr : dclsu_addr; + +// Select between input data generated by LSU or by BIU +assign to_dcram = (refill == 1'b1) ? dcbiu_datain : lsu_datain_memaligned; + +// Select between data generated by DCRAM or passed by BIU +assign to_mem2reg = (refill_first == 1'b1) ? dcbiu_datain : from_dcram; + +// Tag comparison +always @(tag or saved_addr) begin + if (tag == saved_addr[31:13]) + hit <= #1 1'b1; + else + hit <= #1 1'b0; +end + +// Valid_div counts RISC clock cycles by modulo 4 +always @(posedge clk or posedge rst) + if (rst) + valid_div <= #1 2'b0; + else + valid_div <= #1 valid_div + 'd1; + +// dcbiu_valid is one RISC clock cycle long dcbiu_rdy. +// dcbiu_rdy is two or four RISC clock cycles long because memory +// controller works at 1/2 or 1/4 of RISC clock freq (at 1/2 if +// clkdiv_by_2 is asserted). +assign dcbiu_valid = dcbiu_rdy & (valid_div[1] | clkdiv_by_2) & valid_div[0]; + +// Generate refill_start that signals to frz_logic a cache linefill is about to begin +assign refill_start = (refill_prepare & ~hit) ? 1'b1 : 1'b0; + +dtlb dtlb( + .clk(clk), + .rst(rst), + .we(1'b0), + .tlb_en(1'b1), + .datain(dclsu_datain), + .vaddr(saved_addr), + .paddr(), + .cache_en(), + .tlb_miss(), + .tp3w(tp3w), + .tpdw(tpdw) +); + +dc_fsm dc_fsm( + .clk(clk), + .rst(rst), + .lsu_op(dclsu_lsuop), + .miss(~hit), + .biudata_valid(dcbiu_valid), + .start_addr(dclsu_addr), + .saved_addr(saved_addr), + .refill(refill), + .refill_first(refill_first), + .refill_prepare(refill_prepare), + .dcram_we(dcram_we), + .biu_read(dcbiu_read), + .biu_write(dcbiu_write), + .refill_rest(refill_rest), + .cntrbusy(cntrbusy) +); + +// Regfile-to-memory aligner +reg2mem reg2mem( + .addr(dc_addr[1:0]), + .lsu_op(dclsu_lsuop), + .regdata(dclsu_datain), + .memdata(lsu_datain_memaligned) +); + +dc_ram dc_ram( + .clk(clk), + .addr(dc_addr[12:2]), + .we(dcram_we), + .datain(to_dcram), + .dataout(from_dcram), + .tp2w(tp2w), + .tpdw(tpdw) +); + +dc_tag dc_tag( + .clk(clk), + .addr(dc_addr[12:4]), + .we(dctag_we), + .datain(dc_addr[31:13]), + .dataout(tag), + .tp2w(tp2w), + .tpdw(tpdw) +); + +// Memory-to-regfile aligner +mem2reg mem2reg( + .addr(saved_addr[1:0]), + .lsu_op(dclsu_lsuop), + .memdata(to_mem2reg), + .regdata(dclsu_dataout) +); + +endmodule Index: trunk/or1200/rtl/verilog/ic_tag.v =================================================================== --- trunk/or1200/rtl/verilog/ic_tag.v (nonexistent) +++ trunk/or1200/rtl/verilog/ic_tag.v (revision 161) @@ -0,0 +1,114 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// OR1200's IC TAGs //// +//// //// +//// This file is part of the OpenRISC 1200 project //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// Instatiation of instruction cache tag rams //// +//// //// +//// To Do: //// +//// - make it smaller and faster //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// + +`include "general.h" +`define NO_UTI + +module ic_tag(clk, addr, we, datain, dataout, tp4w, tpdw); + +parameter dw = 19; +parameter aw = 9; + +input [dw-1:0] datain; +output [dw-1:0] dataout; + +input [aw-1:0] addr; +input we; + +input clk; + +input [`TP4W_WIDTH-1:0] tp4w; +input [31:0] tpdw; + +wire high, low; + +assign high = 1; +assign low = 0; + +`ifdef NO_UTI + +art_hssp_512x19 ic_tag0( + .q(dataout), + + .clk(clk), + .cen(low), + .oen(low), + .wen(~we), + .a(addr), + .d(datain) +); + +`else + +art_hssp_512x19 ic_tag0( + .q(dataout), + + .censq(), + .oensq(), + .wensq(), + .asq(), + .tq(), + + .clk(clk), + .cen(low), + .oen(low), + .wen(~we), + .a(addr), + .d(datain), + .tis(tp4w[`TP4W_ICT_TIS]), + .tms(tp4w[`TP4W_ICT_TMS]), + .tcen(tp4w[`TP4W_ICT_TCEN]), //normally high + .toen(tp4w[`TP4W_ICT_TOEN]), + .tqoen(tp4w[`TP4W_ICT_TQOEN]), + .twen(tp4w[`TP4W_ICT_TWEN]), + .ta(tp4w[`TP4W_ICT_TA]), + .td(tpdw[dw-1:0]) +); +`endif + +endmodule Index: trunk/or1200/rtl/verilog/cpu.v =================================================================== --- trunk/or1200/rtl/verilog/cpu.v (nonexistent) +++ trunk/or1200/rtl/verilog/cpu.v (revision 161) @@ -0,0 +1,452 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// OR1200's CPU //// +//// //// +//// This file is part of the OpenRISC 1200 project //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// Instantiation of internal CPU blocks. IFETCH, SPRS, FRZ, //// +//// ALU, EXCEPT, ID, WBMUX, OPERANDMUX, RF etc. //// +//// //// +//// To Do: //// +//// - make it smaller and faster //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// + +`include "general.h" +`include "alu_defs.h" + +module cpu( + // Clk & Rst + clk, rst, + + // Insn interface + ic_insn, ic_pcaddr, ic_stall, + + // Trace port + tp_dir_in, tp_sel, tp_in, tp_out, + + // Data interface + dclsu_stall, dclsu_addr, dclsu_datain, dclsu_dataout, dclsu_lsuop, + + // Interrupt exceptions + int_high, int_low, + + // SPR interface + spr_addr, spr_dataout, spr_dat_pic, spr_dat_tt, spr_dat_pm, spr_cs, spr_we, + + // Trace port + tp2w, tp3w, tp4w, tpdw +); + +parameter dw = `OPERAND_WIDTH; +parameter aw = `REGFILE_ADDR_WIDTH; + +// +// I/O ports +// + +// Clk & Rst +input clk; +input rst; + +// Insn interface +input [31:0] ic_insn; +output [31:0] ic_pcaddr; +input ic_stall; + +// Trace +input tp_dir_in; +input [1:0] tp_sel; +input [31:0] tp_in; +output [31:0] tp_out; + +// Data interface +input dclsu_stall; +output [31:0] dclsu_addr; +input [31:0] dclsu_datain; +output [31:0] dclsu_dataout; +output [`LSUOP_WIDTH-1:0] dclsu_lsuop; + +// SPR interface +input [dw-1:0] spr_dat_pic; +input [dw-1:0] spr_dat_tt; +input [dw-1:0] spr_dat_pm; +output [dw-1:0] spr_addr; +output [dw-1:0] spr_dataout; +output [31:0] spr_cs; +output spr_we; + +// Trace +output [`TP2W_WIDTH-1:0] tp2w; +output [`TP3W_WIDTH-1:0] tp3w; +output [`TP4W_WIDTH-1:0] tp4w; +output [31:0] tpdw; +wire [31:0] tpdw; + +// Interrupt exceptions +input int_high, int_low; + +// +// Internal wires +// +wire [31:0] insn; +wire [31:0] if_pc; +wire [31:2] lr_sav; +wire [aw-1:0] #(1) rf_addrw; +wire [aw-1:0] rf_addra; +wire [aw-1:0] rf_addrb; +wire [dw-1:0] simm; +wire [dw-1:2] branch_addrofs; +wire [`ALUOP_WIDTH-1:0] alu_op; +wire [`SHROTOP_WIDTH-1:0] shrot_op; +wire [`COMPOP_WIDTH-1:0] comp_op; +wire [`BRANCHOP_WIDTH-1:0] branch_op; +wire [`LSUOP_WIDTH-1:0] lsu_op; +wire pipeline_freeze; + +wire [`SEL_WIDTH-1:0] sel_a; +wire [`SEL_WIDTH-1:0] sel_b; +wire [`RFWBOP_WIDTH-1:0] #(1) rfwb_op; + +wire [dw-1:0] #(1) rf_dataw; +wire [dw-1:0] rf_dataa; +wire [dw-1:0] rf_datab; +wire [dw-1:0] muxed_b; +wire [dw-1:0] wb_forw; +wire wbforw_valid; + +wire [dw-1:0] operand_a; +wire [dw-1:0] operand_b; +wire [dw-1:0] alu_dataout; +wire [dw-1:0] lsu_dataout; +wire [dw-1:0] sprs_dataout; +wire [31:0] lsu_addrofs; +wire [`MULTICYCLE_WIDTH-1:0] multicycle; + +wire [`EXCEPT_WIDTH-1:0] except_type; +wire except_flushpipe; +wire branch_taken; + +wire flag; +wire lsu_stall; +wire branch_stall; + +wire epcr_we; +wire eear_we; +wire esr_we; +wire [31:0] epcr; +wire [31:0] eear; +wire [`SR_WIDTH-1:0] esr; +wire [`SR_WIDTH-1:0] sr; +wire except_start; +wire except_started; +wire [31:0] wb_pc; +wire [31:0] wb_insn; +wire [31:0] tp_insn; +wire tp_wr_insn; + +// Trace port +wire [31:0] rfa_tqa; +wire [31:0] rfb_tqa; +wire [`TP1R_WIDTH-1:0] rfa_tmuxed; +wire [`TP1R_WIDTH-1:0] rfb_tmuxed; +wire [`TP1W_WIDTH-1:0] tp1w; + +// +// Instantiation of exception block +// +except except( + .clk(clk), + .rst(rst), + .sig_dtlbmiss(1'b0), + .sig_dmmufault(1'b0), + .sig_inthigh(int_high), + .sig_syscall(1'b0), + .sig_itlbmiss(1'b0), + .sig_immufault(1'b0), + .sig_intlow(int_low), + .branch_taken(branch_taken), + .pipeline_freeze(pipeline_freeze), + .ic_stall(ic_stall), + .if_pc(if_pc), + .lr_sav(lr_sav), + .except_flushpipe(except_flushpipe), + .except_type(except_type), + .except_start(except_start), + .except_started(except_started), + .wb_pc(wb_pc), + + .datain(operand_b), + .epcr_we(epcr_we), + .eear_we(eear_we), + .esr_we(esr_we), + .epcr(epcr), + .eear(eear), + .esr(esr), + + .lsu_addr(dclsu_addr), + .sr(sr) +); + +// +// Instantiation of instruction fetch block +// +ifetch ifetch( + .clk(clk), + .rst(rst), + .ic_insn(ic_insn), + .ic_pcaddr(ic_pcaddr), + .ic_stall(ic_stall), + .tp_insn(tp_insn), + .tp_wr_insn(tp_wr_insn), + .pipeline_freeze(pipeline_freeze), + .if_insn(insn), + .if_pc(if_pc), + .branch_op(branch_op), + .except_type(except_type), + .except_start(except_start), + .branch_addrofs(branch_addrofs), + .lr_restor(operand_b), + .flag(flag), + .taken(branch_taken), + .binsn_addr(lr_sav), + .epcr(epcr) +); + +// +// Instantiation of instruction decode/control logic +// +id id( + .clk(clk), + .rst(rst), + .pipeline_freeze(pipeline_freeze), + .except_flushpipe(except_flushpipe), + .if_insn(insn), + .branch_op(branch_op), + .rf_addra(rf_addra), + .rf_addrb(rf_addrb), + .alu_op(alu_op), + .shrot_op(shrot_op), + .comp_op(comp_op), + .rf_addrw(rf_addrw), + .rfwb_op(rfwb_op), + .wb_insn(wb_insn), + .simm(simm), + .branch_addrofs(branch_addrofs), + .lsu_addrofs(lsu_addrofs), + .sel_a(sel_a), + .sel_b(sel_b), + .lsu_op(lsu_op), + .multicycle(multicycle), + .branch_stall(branch_stall), + .wbforw_valid(wbforw_valid) +); + +// +// Instantiation of write-back muxes +// +wbmux wbmux( + .clk(clk), + .rst(rst), + .pipeline_freeze(pipeline_freeze), + .rfwb_op(rfwb_op), + .muxin_a(alu_dataout), + .muxin_b(lsu_dataout), + .muxin_c(sprs_dataout), + .muxin_d({lr_sav, 2'b0}), + .muxout(rf_dataw), + .muxreg(wb_forw), + .muxreg_valid(wbforw_valid) +); + +// +// Instantiation of register file +// +rf rf( + .clk(clk), + .rst(rst), + .addrw(rf_addrw), + .dataw(rf_dataw), + .pipeline_freeze(pipeline_freeze), + .we(rfwb_op[0]), + .addra(rf_addra), + .dataa(rf_dataa), + .addrb(rf_addrb), + .datab(rf_datab), + .rfa_tqa(rfa_tqa), + .rfb_tqa(rfb_tqa), + .rfa_tmuxed(rfa_tmuxed), + .rfb_tmuxed(rfb_tmuxed), + .tp1w(tp1w), + .tpdw(tpdw) +); + +// +// Instantiation of operand muxes +// +operandmuxes operandmuxes( + .clk(clk), + .rst(rst), + .pipeline_freeze(pipeline_freeze), + .rf_dataa(rf_dataa), + .rf_datab(rf_datab), + .ex_forw(rf_dataw), + .wb_forw(wb_forw), + .simm(simm), + .sel_a(sel_a), + .sel_b(sel_b), + .operand_a(operand_a), + .operand_b(operand_b), + .muxed_b(muxed_b) +); + +// +// Instantiation of CPU's ALU +// +alu alu( + .clk(clk), + .rst(rst), + .a(operand_a), + .b(operand_b), + .alu_op(alu_op), + .shrot_op(shrot_op), + .comp_op(comp_op), + .result(alu_dataout), + .flag(flag) +); + +// +// Instantiation of CPU's SPRS block +// +sprs sprs( + .clk(clk), + .rst(rst), + .a(operand_a), + .b(operand_b), + .alu_op(alu_op), + .flag(flag), + .dtlb_we(), + .to_wbmux(sprs_dataout), + + .spr_addr(spr_addr), + .spr_dat_pic(spr_dat_pic), + .spr_dat_tt(spr_dat_tt), + .spr_dat_pm(spr_dat_pm), + .spr_dataout(spr_dataout), + .spr_cs(spr_cs), + .spr_we(spr_we), + + .epcr_we(epcr_we), + .eear_we(eear_we), + .esr_we(esr_we), + .epcr(epcr), + .eear(eear), + .esr(esr), + .except_start(except_start), + .except_started(except_started), + + .sr(sr), + .branch_op(branch_op) +); + +// +// Instantiation of load/store unit +// +lsu lsu( + .clk(clk), + .rst(rst), + .addrbase(operand_a), + .addrofs(lsu_addrofs), + .lsu_op(lsu_op), + .lsu_datain(operand_b), + .lsu_dataout(lsu_dataout), + .lsu_stall(lsu_stall), + .dc_stall(dclsu_stall), + .dc_addr(dclsu_addr), + .dc_datain(dclsu_datain), + .dc_dataout(dclsu_dataout), + .dc_lsuop(dclsu_lsuop) +); + +// +// Instantiation of freeze logic +// +frz_logic frz_logic( + .clk(clk), + .rst(rst), + .multicycle(multicycle), + .except_flushpipe(except_flushpipe), + .lsu_stall(lsu_stall), + .ic_stall(ic_stall), + .branch_stall(branch_stall), + .pipeline_freeze(pipeline_freeze) +); + +// +// Instantiation of Trace port +// +traceport traceport( + // Trace port connection to outside world + .tp_dir_in(tp_dir_in), + .tp_sel(tp_sel), + .tp_in(tp_in), + .tp_out(tp_out), + + // Trace sources coming from RISC core + .rst(rst), + .rfa_tqa(rfa_tqa), + .rfb_tqa(rfb_tqa), + .rfa_tmuxed(rfa_tmuxed), + .rfb_tmuxed(rfb_tmuxed), + .wb_pc(wb_pc), + .wb_insn(wb_insn), + .wb_forw(wb_forw), + + // To RISC core + .wr_insn(tp_wr_insn), + .insn(tp_insn), + .tp1w(tp1w), + .tp2w(tp2w), + .tp3w(tp3w), + .tp4w(tp4w), + .tpdw(tpdw) +); + +endmodule + +

trunk/or1200/rtl/verilog/cpu.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/or1200/rtl/verilog/except.v =================================================================== --- trunk/or1200/rtl/verilog/except.v (nonexistent) +++ trunk/or1200/rtl/verilog/except.v (revision 161) @@ -0,0 +1,238 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// OR1200's Exception logic //// +//// //// +//// This file is part of the OpenRISC 1200 project //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// Handles all OR1K exceptions inside CPU block. //// +//// //// +//// To Do: //// +//// - make it smaller and faster //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// + + +`include "general.h" + +// Exception recognition and sequencing + +`define EXCEPTFSM_WIDTH 2 +`define EXCEPTFSM_IDLE `EXCEPTFSM_WIDTH'd0 +`define EXCEPTFSM_FLU1 `EXCEPTFSM_WIDTH'd1 +`define EXCEPTFSM_FLU2 `EXCEPTFSM_WIDTH'd2 +`define EXCEPTFSM_FLU3 `EXCEPTFSM_WIDTH'd3 + +module except(clk, rst, sig_dtlbmiss, sig_dmmufault, sig_inthigh, sig_syscall, sig_itlbmiss, sig_immufault, sig_intlow, branch_taken, + pipeline_freeze, ic_stall, if_pc, lr_sav, except_flushpipe, except_type, except_start, except_started, wb_pc, + datain, epcr_we, eear_we, esr_we, + epcr, eear, esr, sr, lsu_addr +); + +input clk; +input rst; +input sig_dtlbmiss; +input sig_dmmufault; +input sig_inthigh; +input sig_syscall; +input sig_itlbmiss; +input sig_immufault; +input sig_intlow; +input branch_taken; + +input pipeline_freeze; +input ic_stall; +input [31:0] if_pc; +output [31:2] lr_sav; + +input [31:0] datain; +input epcr_we; +input eear_we; +input esr_we; +output [31:0] epcr; +output [31:0] eear; +output [`SR_WIDTH-1:0] esr; + +input [`SR_WIDTH-1:0] sr; +input [31:0] lsu_addr; + +// We have started execution of exception handler: +// 1. Asserted for 3 clock cycles +// 2. Don't execute any instruction that is still in pipeline and is not part of exception handler +output except_flushpipe; + +// Signals which exception handler we start fetching in: +// 1. Asserted in next clock cycle after exception is recognized +output [`EXCEPT_WIDTH-1:0] except_type; + +output except_start; +output except_started; + +output [31:0] wb_pc; + +reg [`EXCEPT_WIDTH-1:0] except_type; + +reg [31:0] id_pc; +reg [31:0] ex_pc; +reg [31:0] wb_pc; +reg [31:0] epcr; +reg [31:0] eear; +reg [`SR_WIDTH-1:0] esr; + +reg [2:0] id_exceptflags; +reg [2:0] ex_exceptflags; + +reg [`EXCEPTFSM_WIDTH-1:0] state; +reg extend_flush; +reg ex_dslot; +reg delayed1_ex_dslot; +reg delayed2_ex_dslot; + +wire except_started = ~except_start & extend_flush; + +assign lr_sav = ex_pc[31:2]; +assign except_start = (except_type != `EXCEPT_NONE); + +// PC and Exception flags pipelines +always @(posedge clk or posedge rst) begin + if (rst) begin + ex_dslot <= #1 1'b0; + id_pc <= #1 32'd0; + ex_pc <= #1 32'd0; + wb_pc <= #1 32'd0; + id_exceptflags <= #1 2'b0; + ex_exceptflags <= #1 2'b0; + delayed1_ex_dslot <= #1 1'b0; + delayed2_ex_dslot <= #1 1'b0; + end + else if (!pipeline_freeze) begin + $display("%t: id_pc <= %h", $time, if_pc); + $display("%t: ex_pc <= %h", $time, id_pc); + ex_dslot <= #1 branch_taken; + id_pc <= #1 if_pc; + ex_pc <= #1 id_pc; + wb_pc <= #1 ex_pc; + id_exceptflags <= #1 { sig_itlbmiss, sig_immufault, sig_intlow & sr[`SR_EXR]}; + ex_exceptflags <= #1 id_exceptflags; + delayed1_ex_dslot <= #1 ex_dslot; + delayed2_ex_dslot <= #1 delayed1_ex_dslot; + end +end + +assign except_flushpipe = (sr[`SR_EXR] && (sig_dtlbmiss || sig_dmmufault || sig_inthigh || sig_syscall || ex_exceptflags) + || extend_flush) ? 1'b1 : 1'b0; + +// Exception FSM that sequences execution of exception handler +always @(posedge clk or posedge rst) begin + if (rst) begin + state <= #1 `EXCEPTFSM_IDLE; + except_type <= #1 `EXCEPT_NONE; + extend_flush <= #1 1'b0; + epcr <= #1 32'b0; + eear <= #1 32'b0; + esr <= #1 `SR_WIDTH'b0; + end + else begin + case (state) // synopsys full_case parallel_case + `EXCEPTFSM_IDLE: + if (except_flushpipe) begin + state <= #1 `EXCEPTFSM_FLU1; + extend_flush <= #1 1'b1; + if (ex_dslot) begin + $display(" INFO: Exception during first delay slot instruction."); + epcr <= #1 wb_pc; + end + else if (delayed1_ex_dslot) begin + $display(" INFO: Exception during second (NOP) delay slot instruction."); + epcr <= #1 id_pc; + end + else if (delayed2_ex_dslot) begin + $display(" INFO: Exception during third delay slot (SHOULD NOT HAPPEN)."); + epcr <= #1 id_pc; + end + else begin + $display(" INFO: Exception during normal (no delay slot) instruction."); + epcr <= #1 ex_pc; + end + esr <= #1 sr; + eear <= #1 lsu_addr; + casex ({sig_dtlbmiss, sig_dmmufault, sig_inthigh|ex_exceptflags[0], sig_syscall, ex_exceptflags[2:1], 1'b0}) + 7'b1xxxxxx: + except_type <= #1 `EXCEPT_DTLBMISS; + 7'b01xxxxx: + except_type <= #1 `EXCEPT_DMMUFAULT; + 7'b001xxxx: + except_type <= #1 `EXCEPT_INTHIGH; + 7'b0001xxx: + except_type <= #1 `EXCEPT_SYSCALL; + 7'b00001xx: + except_type <= #1 `EXCEPT_ITLBMISS; + 7'b000001x: + except_type <= #1 `EXCEPT_IMMUFAULT; + 7'b0000001: + except_type <= #1 `EXCEPT_RESET; + default: + except_type <= #1 `EXCEPT_NONE; + endcase + end + else begin + if (epcr_we) + epcr <= #1 datain; + if (eear_we) + eear <= #1 datain; + if (esr_we) + esr <= #1 datain; + end + `EXCEPTFSM_FLU1: + if (!ic_stall && !pipeline_freeze) + begin + $display(" INFO: EPCR0 %h EEAR %h ESR %h", epcr, eear, esr); + state <= #1 `EXCEPTFSM_FLU2; + except_type <= #1 `EXCEPT_NONE; + end + `EXCEPTFSM_FLU2: + state <= #1 `EXCEPTFSM_FLU3; + `EXCEPTFSM_FLU3: begin + $display(" INFO: Exception just finished flushing pipeline."); + state <= #1 `EXCEPTFSM_IDLE; + extend_flush <= #1 1'b0; + end + endcase + end +end + +endmodule Index: trunk/or1200/rtl/verilog/ic_ram.v =================================================================== --- trunk/or1200/rtl/verilog/ic_ram.v (nonexistent) +++ trunk/or1200/rtl/verilog/ic_ram.v (revision 161) @@ -0,0 +1,102 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// OR1200's IC RAMs //// +//// //// +//// This file is part of the OpenRISC 1200 project //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// Instantiation of Instruction cache data rams //// +//// //// +//// To Do: //// +//// - make it smaller and faster //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// + +`include "general.h" + +//`define XCV_IC + +module ic_ram(clk, addr, we, datain, dataout, tp4w, tpdw); + +parameter dw = `OPERAND_WIDTH; +parameter aw = `ICINDX; + +input [dw-1:0] datain; +output [dw-1:0] dataout; + +input [aw-1:0] addr; +input [3:0] we; + +input clk; + +input [`TP4W_WIDTH-1:0] tp4w; +input [31:0] tpdw; + +`ifdef XCV_IC +xcv_2048x16 ic_ram0 ( + .DO(dataout[15:0]), + .ADDR(addr), + .DI(datain[15:0]), + .EN(1'b1), + .CLK(clk), + .WE(we[0]), + .RST(1'b0) +); + +xcv_2048x16 ic_ram1 ( + .DO(dataout[31:16]), + .ADDR(addr), + .DI(datain[31:16]), + .EN(1'b1), + .CLK(clk), + .WE(we[0]), + .RST(1'b0) +); + +`else +art_hdsp_2048x32 ic_ram0( + .q(dataout), + .clk(clk), + .cen(1'b0), + .wen(~we[0]), + .a(addr), + .d(datain) +); +`endif + +endmodule + Index: trunk/or1200/rtl/verilog/itlb.v =================================================================== --- trunk/or1200/rtl/verilog/itlb.v (nonexistent) +++ trunk/or1200/rtl/verilog/itlb.v (revision 161) @@ -0,0 +1,137 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// OR1200's Instruction TLB //// +//// //// +//// This file is part of the OpenRISC 1200 project //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// Instruction TLB //// +//// //// +//// To Do: //// +//// - make it smaller and faster //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// + +`include "general.h" +`define NO_UTI + +// ITLB unit +module itlb(clk, rst, we, tlb_en, datain, vaddr, paddr, cache_en, tlb_miss, tp4w, tpdw); + +input clk; +input rst; +input we; +input tlb_en; + +input [31:0] datain; +input [31:0] vaddr; +output [31:0] paddr; +output cache_en; +output tlb_miss; + +input [`TP4W_WIDTH-1:0] tp4w; +input [31:0] tpdw; + +wire [33:0] to_ram; +wire [33:0] from_ram; + +reg [31:0] saved_vaddr; + +// datain[31:12] = PPN +// datain[0] = cache enable +assign to_ram = { datain[31:12], datain[0], vaddr[31:19] }; + +// If TLB disabled then PADDR = VADDR +assign paddr = (tlb_en == 1'b1) ? { from_ram[33:14], saved_vaddr[11:0] } : saved_vaddr; + +// Per page cache control +assign cache_en = from_ram[13]; + +// Comparison of stored TLB tag with current VADDR's page index +// Lower 7 bits of VADDR's page index are ignored since we index +// TLB entries with them so they always match +assign tlb_miss = (from_ram[12:0] != saved_vaddr[31:19]) ? 1'b1 : 1'b0; + +// Save vaddr +always @(posedge clk or posedge rst) + if (rst) + saved_vaddr <= #1 32'b0; + else + saved_vaddr <= #1 vaddr; + +`ifdef NO_UTI +art_hssp_128x34 itlb0( + .q(from_ram), + + .clk(clk), + .cen(1'b0), + .oen(1'b0), + .wen(~we), + .a(vaddr[18:12]), + .d(to_ram) +); + +`else + +art_hssp_128x34 itlb0( + .q(from_ram), + + .censq(), + .oensq(), + .wensq(), + .asq(), + .tq(), + + .clk(clk), + .cen(1'b0), + .oen(1'b0), + .wen(~we), + .a(vaddr[18:12]), + .d(to_ram), + .tis(tp4w[`TP4W_IMT_TIS]), + .tms(tp4w[`TP4W_IMT_TMS]), + .tcen(tp4w[`TP4W_IMT_TCEN]), + .toen(tp4w[`TP4W_IMT_TOEN]), + .tqoen(tp4w[`TP4W_IMT_TQOEN]), + .twen(tp4w[`TP4W_IMT_TWEN]), + .ta(tp4w[`TP4W_IMT_TA]), + .td() +); + +`endif + +endmodule Index: trunk/or1200/rtl/verilog/ic_fsm.v =================================================================== --- trunk/or1200/rtl/verilog/ic_fsm.v (nonexistent) +++ trunk/or1200/rtl/verilog/ic_fsm.v (revision 161) @@ -0,0 +1,192 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// OR1200's IC FSM //// +//// //// +//// This file is part of the OpenRISC 1200 project //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// Instruction cache state machine //// +//// //// +//// To Do: //// +//// - make it smaller and faster //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// + +`include "general.h" + +`define ICFSM_IDLE 'd0 +`define ICFSM_DOLOAD 'd1 +`define ICFSM_LREFILL3 'd2 + +// Insn cache FSM for cache line of 16 bytes (4x singleword) + +module ic_fsm(clk, rst, fetch_op, miss, biudata_valid, start_addr, saved_addr, refill, refill_first, refill_prepare, icram_we, biu_read, refill_rest, cntrbusy); + +input clk; +input rst; +input miss; +input biudata_valid; +input [31:0] start_addr; +input [`FETCHOP_WIDTH-1:0] fetch_op; +output [31:0] saved_addr; +output refill; +output refill_first; +output refill_prepare; +output [3:0] icram_we; +output biu_read; +output refill_rest; +output cntrbusy; + +wire icache_off = 1'b0; + +reg [31:0] saved_addr; +reg refill; + +reg [3:0] icram_we; +reg [2:0] state; +reg [2:0] cnt; +reg refill_first; +reg refill_prepare; +reg biu_read; +reg refill_rest; +reg cntrbusy; + +always @(refill_first or refill or biudata_valid or fetch_op or start_addr) begin + if (refill_first || !refill) + case(fetch_op) + `FETCHOP_LW : icram_we <= #1 4'b0000 ^ {4{refill_first}}; + default : icram_we <= #1 4'b0000; + endcase + else + icram_we <= #1 {4{refill & biudata_valid}}; +end + +always @(posedge clk or posedge rst) begin + if (rst) begin + refill <= #1 1'b0; + state <= #1 3`ICFSM_DOLOAD; + biu_read <= #1 1'b0; + saved_addr <= #1 32'b0; + refill_first <= #1 1'b0; + refill_prepare <= #1 1'b0; + refill_rest <= #1 1'b0; + cntrbusy <= #1 1'b0; + cnt <= #1 3'b0; + end + else + case (state) // synopsys full_case parallel_case + `ICFSM_IDLE : + case(fetch_op) + `FETCHOP_LW: begin + $display("%t: IC_FSM Load op %h start_addr %h", $time, fetch_op, start_addr); + state <= #1 3`ICFSM_DOLOAD; + refill <= #1 1'b0; + saved_addr <= #1 start_addr; + refill_first <= #1 1'b0; + refill_prepare <= #1 1'b1; + biu_read <= #1 1'b0; + refill_rest <= #1 1'b0; + cntrbusy <= #1 1'b0; + end + default: begin + state <= #1 3`ICFSM_IDLE; + refill <= #1 1'b0; + refill_first <= #1 1'b0; + refill_prepare <= #1 1'b0; + refill_rest <= #1 1'b0; + biu_read <= #1 1'b0; + cntrbusy <= #1 1'b0; + end + endcase + `ICFSM_DOLOAD: + if (icache_off) begin +// $display("%t: IC_FSM ICache off", $time); + state <= #1 3`ICFSM_DOLOAD; + refill <= #1 1'b1; + refill_first <= #1 1'b1; + refill_prepare <= #1 1'b0; + refill_rest <= #1 1'b0; + biu_read <= #1 1'b1; + if (biudata_valid) begin + refill <= #1 1'b0; + refill_first <= #1 1'b0; + biu_read <= #1 1'b0; + saved_addr <= #1 start_addr; + end + end else + if (miss) begin + $display("%t: IC_FSM Load miss", $time); + state <= #1 3`ICFSM_LREFILL3; + refill <= #1 1'b1; + refill_first <= #1 1'b1; + refill_prepare <= #1 1'b0; + refill_rest <= #1 1'b0; + cnt <= #1 3'd3; + biu_read <= #1 1'b1; + end + else begin + $display("%t: IC_FSM Load hit", $time); + state <= #1 3`ICFSM_DOLOAD; + saved_addr <= #1 start_addr; + refill <= #1 1'b0; + refill_first <= #1 1'b0; + refill_prepare <= #1 1'b0; + refill_rest <= #1 1'b0; + cntrbusy <= #1 (fetch_op) ? 1'b1 : 1'b0; + end + `ICFSM_LREFILL3 : begin + if (biudata_valid && cnt) begin + $display("%t: IC_FSM Load refill %d", $time, cnt); + cnt <= #1 cnt - 'd1; + saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1; + refill_first <= #1 1'b0; + end + else if (biudata_valid) begin + $display("%t: IC_FSM Load refill end", $time, cnt); + state <= #1 3`ICFSM_DOLOAD; + saved_addr[3:2] <= #1 saved_addr[3:2] + 'd1; + refill <= #1 1'b1; + refill_first <= #1 1'b0; + biu_read <= #1 1'b0; + cntrbusy <= #1 (fetch_op) ? 1'b1 : 1'b0; + end + refill_rest <= #1 ~refill_first & refill; + end + endcase +end + +endmodule Index: trunk/or1200/rtl/verilog/wbmux.v =================================================================== --- trunk/or1200/rtl/verilog/wbmux.v (nonexistent) +++ trunk/or1200/rtl/verilog/wbmux.v (revision 161) @@ -0,0 +1,101 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// OR1200's Write-back Mux //// +//// //// +//// This file is part of the OpenRISC 1200 project //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// CPU's write-back stage of the pipeline //// +//// //// +//// To Do: //// +//// - make it smaller and faster //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// + +`include "general.h" + +module wbmux(clk, rst, pipeline_freeze, rfwb_op, muxin_a, muxin_b, muxin_c, muxin_d, muxout, muxreg, muxreg_valid); + +parameter width = `OPERAND_WIDTH; + +input clk; +input rst; +input pipeline_freeze; +input [`RFWBOP_WIDTH-1:0] rfwb_op; +input [width-1:0] muxin_a; +input [width-1:0] muxin_b; +input [width-1:0] muxin_c; +input [width-1:0] muxin_d; + +output [width-1:0] muxout; +output [width-1:0] muxreg; +output muxreg_valid; + +reg [width-1:0] muxout; +reg [width-1:0] muxreg; +reg muxreg_valid; + +always @(posedge clk or posedge rst) begin + if (rst) begin + muxreg <= #1 32'd0; + muxreg_valid <= #1 1'b0; + end + else if (!pipeline_freeze) begin + muxreg <= #1 muxout; + muxreg_valid <= #1 rfwb_op[0]; + end +end + +always @(muxin_a or muxin_b or muxin_c or muxin_d or rfwb_op) begin + case(rfwb_op[`RFWBOP_WIDTH-1:1]) // synopsys full_case parallel_case infer_mux + 'b00: muxout <= #1 muxin_a; + 'b01: begin + muxout <= #1 muxin_b; + $display(" WBMUX: muxin_b %h", muxin_b); + end + 'b10: begin + muxout <= #1 muxin_c; + $display(" WBMUX: muxin_c %h", muxin_c); + end + 'b11: begin + muxout <= #1 muxin_d + 4'h8; + $display(" WBMUX: muxin_d %h", muxin_d + 4'h8); + end + endcase +end + +endmodule Index: trunk/or1200/rtl/verilog/or32isa.h =================================================================== --- trunk/or1200/rtl/verilog/or32isa.h (nonexistent) +++ trunk/or1200/rtl/verilog/or32isa.h (revision 161) @@ -0,0 +1,84 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Definitions of ORBIS32I //// +//// //// +//// This file is part of the OpenRISC 1200 project //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// OR1200 implements ORBIS32I //// +//// //// +//// To Do: //// +//// None //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// + +// Instruction opcode groups (basic) +`define OR32_J 6'b000000 +`define OR32_JAL 6'b000001 +`define OR32_BNF 6'b000011 +`define OR32_BF 6'b000100 +`define OR32_NOP 6'b000101 +`define OR32_MOVHI 6'b000110 +`define OR32_MFSPR 6'b000111 +`define OR32_XSYNC 6'b001000 +`define OR32_RFE 6'b001001 + +`define OR32_MTSPR 6'b010000 +`define OR32_JR 6'b010001 +`define OR32_JALR 6'b010010 + +`define OR32_LWZ 6'b100001 +`define OR32_LBZ 6'b100011 +`define OR32_LBS 6'b100100 +`define OR32_LHZ 6'b100101 +`define OR32_LHS 6'b100110 +`define OR32_ADDI 6'b100111 +`define OR32_ADDIC 6'b101000 +`define OR32_ANDI 6'b101001 +`define OR32_ORI 6'b101010 +`define OR32_XORI 6'b101011 +`define OR32_MULI 6'b101100 +`define OR32_MACI 6'b101101 +`define OR32_SH_ROTI 6'b101110 +`define OR32_SFXXI 6'b101111 + +`define OR32_SW 6'b110101 +`define OR32_SB 6'b110110 +`define OR32_SH 6'b110111 +`define OR32_ALU 6'b111000 +`define OR32_SFXX 6'b111001 + Index: trunk/or1200/rtl/verilog/rf.v =================================================================== --- trunk/or1200/rtl/verilog/rf.v (nonexistent) +++ trunk/or1200/rtl/verilog/rf.v (revision 161) @@ -0,0 +1,314 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// OR1200's register file inside CPU //// +//// //// +//// This file is part of the OpenRISC 1200 project //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// Instantiation of register file memories //// +//// //// +//// To Do: //// +//// - make it smaller and faster //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// + +`include "general.h" + +//`define XCV_RF +`define ART_DP + +module rf(clk, rst, addrw, dataw, pipeline_freeze, we, addra, dataa, addrb, datab, + rfa_tqa, rfb_tqa, rfa_tmuxed, rfb_tmuxed, tp1w, tpdw +); + +parameter dw = `OPERAND_WIDTH; +parameter aw = `REGFILE_ADDR_WIDTH; + +input clk, rst, pipeline_freeze, we; + +input [dw-1:0] dataw; +output [dw-1:0] dataa; +output [dw-1:0] datab; + +input [aw-1:0] addrw; +input [aw-1:0] addra; +input [aw-1:0] addrb; + +// Trace port +output [31:0] rfa_tqa; +output [31:0] rfb_tqa; +output [`TP1R_WIDTH-1:0] rfa_tmuxed; +output [`TP1R_WIDTH-1:0] rfb_tmuxed; +input [`TP1W_WIDTH-1:0] tp1w; +input [31:0] tpdw; + +wire [dw-1:0] from_rfa, from_rfb; + +wire [dw-1:0] t_dataw; // for test port +wire [aw-1:0] t_addrw; // for test port +wire [aw-1:0] t_addra; // for test port +wire [aw-1:0] t_addrb; // for test port + +reg [dw:0] dataa_saved, datab_saved; + +assign dataa = (dataa_saved[32]) ? dataa_saved[31:0] : from_rfa; +assign datab = (datab_saved[32]) ? datab_saved[31:0] : from_rfb; + +// Stores operand from RF_A into temp reg when pipeline is frozen +always @(posedge clk or posedge rst) + if (rst) begin + dataa_saved <= #1 33'b0; + end + else if (pipeline_freeze & !dataa_saved[32]) begin + dataa_saved <= #1 {1'b1, from_rfa}; + end + else if (!pipeline_freeze) + dataa_saved[32] <= #1 1'b0; + +// Stores operand from RF_B into temp reg when pipeline is frozen +always @(posedge clk or posedge rst) + if (rst) begin + datab_saved <= #1 33'b0; + end + else if (pipeline_freeze & !datab_saved[32]) begin + datab_saved <= #1 {1'b1, from_rfb}; + end + else if (!pipeline_freeze) + datab_saved[32] <= #1 1'b0; + +`ifdef XCV_RF +// Instantiation of register file memory (A) +xcv_rfram rf( + .clk(clk), + .rst(rst), + .we(we), + .addrw(addrw), + .dataw(dataw), + .addra(addra), + .dataa(from_rfa), + .addrb(addrb), + .datab(from_rfb) +); + +`else + +`ifdef ART_DP +// Instatiation of dual port high density artisan sram memory +art_hsdp_32x32 rf_a( + .qa(from_rfa), + .clka(clk), + .cena(1'b0), + .wena(1'b1), + .aa(addra), + .da(32'b0), + .oena(1'b0), + .qb(), + .clkb(clk), + .cenb(1'b0), + .wenb(1'b0), + .ab(addrw), + .db(dataw), + .oenb(1'b1) +); + +art_hsdp_32x32 rf_b( + .qa(from_rfb), + .clka(clk), + .cena(1'b0), + .wena(1'b1), + .aa(addrb), + .da(32'b0), + .oena(1'b0), + .qb(), + .clkb(clk), + .cenb(1'b0), + .wenb(1'b0), + .ab(addrw), + .db(dataw), + .oenb(1'b1) +); + +assign rfa_tqa = 32'b0; +assign rfb_tqa = 32'b0; +assign rfa_tmuxed = `TP1R_WIDTH'b0; +assign rfb_tmuxed = `TP1R_WIDTH'b0; + +`else + +// Instantiation of register file memory (A) +art_rf2r_32x32 rf_a( + .QA(from_rfa), + + .OENSQA(rfa_tmuxed[`TP1R_RF_OENSQA]), + .ASQA(rfa_tmuxed[`TP1R_RF_ASQA]), + .TQA(rfa_tqa), + .QSQA(rfa_tmuxed[`TP1R_RF_QSQA]), + .DSOB(rfa_tmuxed[`TP1R_RF_DSOB]), + .CENSQB(rfa_tmuxed[`TP1R_RF_CENSQB]), + .ASQB(rfa_tmuxed[`TP1R_RF_ASQB]), + + .CLKA(clk), + .CENA(1'b0), + .OENA(1'b0), + .AA(addra), + .TISA(tp1w[`TP1W_RF_TISA]), + .TMSA(tp1w[`TP1W_RF_TMSA]), + .TCENA(tp1w[`TP1W_RF_TCENA]), + .TOENA(tp1w[`TP1W_RF_TOENA]), + .TQOENA(tp1w[`TP1W_RF_TQOENA]), + .TAA(tp1w[`TP1W_RF_TAA]), + .CLKB(clk), + .CENB(~we), + .AB(addrw), + .DB(dataw), + .TISB(tp1w[`TP1W_RF_TISB]), + .TMSB(tp1w[`TP1W_RF_TMSB]), + .TCENB(tp1w[`TP1W_RF_TCENB]), + .TAB(tp1w[`TP1W_RF_TAB]), + .TDB(tpdw), + .SMSB(tp1w[`TP1W_RF_SMSB]), + .DSIB(tp1w[`TP1W_RF_DSIB]) +); + +// Instantiation of register file memory (B) +art_rf2r_32x32 rf_b( + .QA(from_rfb), + + .OENSQA(rfb_tmuxed[`TP1R_RF_OENSQA]), + .ASQA(rfb_tmuxed[`TP1R_RF_ASQA]), + .TQA(rfb_tqa), + .QSQA(rfb_tmuxed[`TP1R_RF_QSQA]), + .DSOB(rfb_tmuxed[`TP1R_RF_DSOB]), + .CENSQB(rfb_tmuxed[`TP1R_RF_CENSQB]), + .ASQB(rfb_tmuxed[`TP1R_RF_ASQB]), + + .CLKA(clk), + .CENA(1'b0), + .OENA(1'b0), + .AA(addrb), + .TISA(tp1w[`TP1W_RF_TISA]), + .TMSA(tp1w[`TP1W_RF_TMSA]), + .TCENA(tp1w[`TP1W_RF_TCENA]), + .TOENA(tp1w[`TP1W_RF_TOENA]), + .TQOENA(tp1w[`TP1W_RF_TQOENA]), + .TAA(tp1w[`TP1W_RF_TAA]), + .CLKB(clk), + .CENB(~we), + .AB(addrw), + .DB(dataw), + .TISB(tp1w[`TP1W_RF_TISB]), + .TMSB(tp1w[`TP1W_RF_TMSB]), + .TCENB(tp1w[`TP1W_RF_TCENB]), + .TAB(tp1w[`TP1W_RF_TAB]), + .TDB(tpdw), + .SMSB(tp1w[`TP1W_RF_SMSB]), + .DSIB(tp1w[`TP1W_RF_DSIB]) +); +`endif +`endif +/* +art_rf2r_32x32 rf_a( + .qa(from_rfa), + + .oensqa(rfa_tmuxed[`TP1R_RF_OENSQA]), + .asqa(rfa_tmuxed[`TP1R_RF_ASQA]), + .tqa(rfa_tqa), + .qsqa(rfa_tmuxed[`TP1R_RF_QSQA]), + .dsob(rfa_tmuxed[`TP1R_RF_DSOB]), + .censqb(rfa_tmuxed[`TP1R_RF_CENSQB]), + .asqb(rfa_tmuxed[`TP1R_RF_ASQB]), + + .clka(clk), + .cena(1'b0), + .oena(1'b0), + .aa(addra), + .tisa(tp1w[`TP1W_RF_TISA]), + .tmsa(tp1w[`TP1W_RF_TMSA]), + .tcena(tp1w[`TP1W_RF_TCENA]), + .toena(tp1w[`TP1W_RF_TOENA]), + .tqoena(tp1w[`TP1W_RF_TQOENA]), + .taa(tp1w[`TP1W_RF_TAA]), + .clkb(clk), + .cenb(~we), + .ab(addrw), + .db(dataw), + .tisb(tp1w[`TP1W_RF_TISB]), + .tmsb(tp1w[`TP1W_RF_TMSB]), + .tcenb(tp1w[`TP1W_RF_TCENB]), + .tab(tp1w[`TP1W_RF_TAB]), + .tdb(tpdw), + .smsb(tp1w[`TP1W_RF_SMSB]), + .dsib(tp1w[`TP1W_RF_DSIB]) +); + +// Instantiation of register file memory (B) +art_rf2r_32x32 rf_b( + .qa(from_rfb), + + .oensqa(rfb_tmuxed[`TP1R_RF_OENSQA]), + .asqa(rfb_tmuxed[`TP1R_RF_ASQA]), + .tqa(rfb_tqa), + .qsqa(rfb_tmuxed[`TP1R_RF_QSQA]), + .dsob(rfb_tmuxed[`TP1R_RF_DSOB]), + .censqb(rfb_tmuxed[`TP1R_RF_CENSQB]), + .asqb(rfb_tmuxed[`TP1R_RF_ASQB]), + + .clka(clk), + .cena(1'b0), + .oena(1'b0), + .aa(addrb), + .tisa(tp1w[`TP1W_RF_TISA]), + .tmsa(tp1w[`TP1W_RF_TMSA]), + .tcena(tp1w[`TP1W_RF_TCENA]), + .toena(tp1w[`TP1W_RF_TOENA]), + .tqoena(tp1w[`TP1W_RF_TQOENA]), + .taa(tp1w[`TP1W_RF_TAA]), + .clkb(clk), + .cenb(~we), + .ab(addrw), + .db(dataw), + .tisb(tp1w[`TP1W_RF_TISB]), + .tmsb(tp1w[`TP1W_RF_TMSB]), + .tcenb(tp1w[`TP1W_RF_TCENB]), + .tab(tp1w[`TP1W_RF_TAB]), + .tdb(tpdw), + .smsb(tp1w[`TP1W_RF_SMSB]), + .dsib(tp1w[`TP1W_RF_DSIB]) +); +*/ + +endmodule

trunk/or1200/rtl/verilog/rf.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/or1200/rtl/verilog/mac16.v =================================================================== --- trunk/or1200/rtl/verilog/mac16.v (nonexistent) +++ trunk/or1200/rtl/verilog/mac16.v (revision 161) @@ -0,0 +1,79 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// OR1200's MAC16 //// +//// //// +//// This file is part of the OpenRISC 1200 project //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// MAC16 //// +//// //// +//// To Do: //// +//// - make it smaller and faster //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// + +`include "general.h" + +module mac16(clk, rst, a, b, prod, sum); + +parameter width = 16; + +input clk, rst; +input [width-1:0] a, b; +output [2*width+7:0] prod, sum; + +reg [2*width+7:0] sum; + + +// Instantiation of actual multiplier +MULT mult16 ( + .CLK(clk), + .X(a), + .Y(b), + .P(prod) +); + +// Behavioral description of accumulate stage +always @(posedge clk or posedge rst) begin + if (rst) + sum <= #1 32'b0; + else + sum <= #1 prod + sum; +end + + +endmodule Index: trunk/or1200/rtl/verilog/wb_biu.v =================================================================== --- trunk/or1200/rtl/verilog/wb_biu.v (nonexistent) +++ trunk/or1200/rtl/verilog/wb_biu.v (revision 161) @@ -0,0 +1,118 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// OR1200's WISHBONE BIU //// +//// //// +//// This file is part of the OpenRISC 1200 project //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// Implements WISHBONE interface //// +//// //// +//// To Do: //// +//// - add support for wb_err_i //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// + +`include "general.h" + +module wb_biu( + // WISHBONE interface + wb_clk_i, wb_rst_i, wb_ack_i, wb_err_i, wb_rty_i, wb_dat_i, + wb_cyc_o, wb_adr_o, wb_stb_o, wb_we_o, wb_sel_o, wb_dat_o, + + // Internal RISC bus + biu_to_biu, biu_addr, biu_read, biu_write, biu_rdy, biu_from_biu +); + +parameter dw = `OPERAND_WIDTH; +parameter aw = `OPERAND_WIDTH; + +// +// WISHBONE interface +// +input wb_clk_i; // clock input +input wb_rst_i; // reset input +input wb_ack_i; // normal termination +input wb_err_i; // termination w/ error +input wb_rty_i; // termination w/ retry +input [dw-1:0] wb_dat_i; // input data bus +output wb_cyc_o; // cycle valid output +output [aw-1:0] wb_adr_o; // address bus outputs +output wb_stb_o; // strobe output +output wb_we_o; // indicates write transfer +output [3:0] wb_sel_o; // byte select outputs +output [dw-1:0] wb_dat_o; // output data bus + +// +// Internal RISC interface +// +input [dw-1:0] biu_to_biu; // input data bus +input [aw-1:0] biu_addr; // address bus +input biu_read; // read request +input biu_write; // write request +output biu_rdy; // data valid +output [dw-1:0] biu_from_biu; // output data bus + + +// +// WISHBONE I/F <-> Internal RISC I/F conversion +// + +// Address bus +assign wb_adr_o = biu_addr; + +// Input data bus +assign biu_from_biu = wb_dat_i; + +// Output data bus +assign wb_dat_o = biu_to_biu; + +// Acknowledgment of the data to the RISC +assign biu_rdy = wb_ack_i; + +// WB cyc_o +assign wb_cyc_o = wb_stb_o; + +// WB stb_o +assign wb_stb_o = biu_read | biu_write; + +// WB we_o +assign wb_we_o = biu_write; + +// WB sel_o +assign wb_sel_o = 4'b1111; + +endmodule Index: trunk/or1200/rtl/verilog/du.v =================================================================== --- trunk/or1200/rtl/verilog/du.v (nonexistent) +++ trunk/or1200/rtl/verilog/du.v (revision 161) @@ -0,0 +1,182 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// OR1200's Debug Unit //// +//// //// +//// This file is part of the OpenRISC 1200 project //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// DU according to OR1K architectural specification. //// +//// //// +//// To Do: //// +//// Some parts are still not implemented yet. //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// + +`include "general.h" + +module du( + // RISC Internal Interface + clk, rst, spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o, + +); + +// +// RISC Internal Interface +// +input clk; // Clock +input rst; // Reset +input spr_cs; // SPR CS +input spr_write; // SPR Write +input [31:0] spr_addr; // SPR Address +input [31:0] spr_dat_i; // SPR Write Data +output [31:0] spr_dat_o; // SPR Read Data + +`ifdef DU_IMPLEMENTED + +// +// DU Mode Register bits (or no register) +// +`ifdef DU_DUMR +reg [31:0] ttmr; // DUMR bits +`else +wire [31:0] ttmr; // No DUMR register +`endif + +// +// DU Count Register bits (or no register) +// +`ifdef DU_DUCR +reg [31:0] ttcr; // DUCR bits +`else +wire [31:0] ttcr; // No DUCR register +`endif + +// +// Internal wires & regs +// +wire ttmr_sel; // DUMR select +wire ttcr_sel; // DUCR select +wire match; // Asserted when DUMR[TP] + // is equal to DUCR[27:0] +wire restart; // Restart counter when asserted +wire stop; // Stop counter when asserted +reg [31:0] spr_dat_o; // SPR data out + +// +// DU registers address decoder +// +assign ttmr_sel = (spr_cs && (spr_addr[`DUOFS_BITS] == `DU_OFS_DUMR)) ? 1'b1 : 1'b0; +assign ttcr_sel = (spr_cs && (spr_addr[`DUOFS_BITS] == `DU_OFS_DUCR)) ? 1'b1 : 1'b0; + +// +// Write to DUMR or update of DUMR[IP] bit +// +`ifdef DU_DUMR +always @(posedge clk or posedge rst) + if (rst) + ttmr <= 32'b0; + else if (ttmr_sel && spr_write) + ttmr <= #1 spr_dat_i; + else if (ttmr[`DU_DUMR_IE]) + ttmr[`DU_DUMR_IP] <= #1 ttmr[`DU_DUMR_IP] | int; +`else +assign ttmr = {2'b11, 30'b0}; // DUMR[M] = 0x3 +`endif + +// +// Write to or increment of DUCR +// +`ifdef DU_DUCR +always @(posedge clk or posedge rst or posedge restart) + if (rst | restart) + ttcr <= 32'b0; + else if (ttcr_sel && spr_write) + ttcr <= #1 spr_dat_i; + else if (!stop) + ttcr <= #1 ttcr + 1'd1; +`else +assign ttcr = 32'b0; +`endif + +// +// Read DU registers +// +always @(spr_addr or ttmr or ttmr_sel or ttcr or ttcr_sel) + case (spr_addr[`DUOFS_BITS]) // synopsys full_case parallel_case +`ifdef DU_READREGS + `DU_OFS_DUMR: spr_dat_o <= ttmr; +`endif + default: spr_dat_o <= ttcr; + endcase + +// +// A match when DUMR[TP] is equal to DUCR[27:0] +// +assign match = (ttmr[`DU_DUMR_TP] == ttcr[27:0]) ? 1'b1 : 1'b0; + +// +// Restart when match and DUMR[M]==0x1 +// +assign restart = (match && (ttmr[`DU_DUMR_M] == 2'b01)) ? 1'b1 : 1'b0; + +// +// Stop when match and DUMR[M]==0x2 or when DUMR[M]==0x0 +// +assign stop = (match && (ttmr[`DU_DUMR_M] == 2'b10) || (ttmr[`DU_DUMR_M] == 2'b00)) ? 1'b1 : 1'b0; + +// +// Generate an interrupt request +// +assign int = match & ttmr[`DU_DUMR_IE]; + +`else + +// +// When DU is not implemented, drive all outputs as would when DU is disabled +// +assign int = 1'b0; + +// +// Read DU registers +// +`ifdef DU_READREGS +assign spr_dat_o = 32'b0; +`endif + +`endif + +endmodule Index: trunk/or1200/rtl/verilog/monitor.h =================================================================== --- trunk/or1200/rtl/verilog/monitor.h (nonexistent) +++ trunk/or1200/rtl/verilog/monitor.h (revision 161) @@ -0,0 +1,178 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// OR1200's simulatiion monitor //// +//// //// +//// This file is part of the OpenRISC 1200 project //// +//// http://www.opencores.org/cores/or1k/ //// +//// //// +//// Description //// +//// Simulation monitor //// +//// //// +//// To Do: //// +//// - move it to bench //// +//// //// +//// Author(s): //// +//// - Damjan Lampret, lampret@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// + + +// Enable debug_mem task. Only affects simulation. +`define enable_debug_mem + +// Enable display_arch_state task. Only affects simulation. +`define enable_display_arch_state + +task monitortask; +begin +/* + $display("cpu.rfwb_op=%h vip.vipcore.risc.cpu.rf_dataw=%h vip.vipcore.risc.cpu.rf_dataa=%h vip.vipcore.risc.cpu.rf_datab=%h", + vip.vipcore.risc.cpu.rfwb_op, vip.vipcore.risc.cpu.rf_dataw, vip.vipcore.risc.cpu.rf_dataa, vip.vipcore.risc.cpu.rf_datab); + + $display("vip.vipcore.risc.cpu.insn=%h vip.vipcore.risc.cpu.rf_addrw=%h vip.vipcore.risc.cpu.rf_addra=%h vip.vipcore.risc.cpu.rf_addrb=%h vip.vipcore.risc.cpu.simm=%h vip.vipcore.risc.cpu.alu_op=%h vip.vipcore.risc.cpu.branch_op=%h vip.vipcore.risc.cpu.sel_a=%h vip.vipcore.risc.cpu.sel_b=%h", + vip.vipcore.risc.cpu.insn, vip.vipcore.risc.cpu.rf_addrw, vip.vipcore.risc.cpu.rf_addra, vip.vipcore.risc.cpu.rf_addrb, vip.vipcore.risc.cpu.simm, vip.vipcore.risc.cpu.alu_op, vip.vipcore.risc.cpu.branch_op, vip.vipcore.risc.cpu.sel_a, vip.vipcore.risc.cpu.sel_b); + + $display("alu.alu_op=%h alu.comp_op=%h alu.a=%h alu.b=%h alu.result=%h alu.flag_we=%b alu.flag=%b", + vip.vipcore.risc.cpu.alu.alu_op, vip.vipcore.risc.cpu.alu.comp_op, vip.vipcore.risc.cpu.alu.a, vip.vipcore.risc.cpu.alu.b, vip.vipcore.risc.cpu.alu.result, vip.vipcore.risc.cpu.alu.flag_we, vip.vipcore.risc.cpu.alu.flag); + + $display("vip.vipcore.risc.cpu.lsu_op=%h", vip.vipcore.risc.cpu.lsu_op); +*/ + $display(""); +end +endtask + +integer fexe; +reg [23:0] ref; + +task start_simulation; +begin + ref = 0; + fexe = $fopen("executed.log"); + $timeformat (-9, 2, " ns", 12); +// $shm_open("waves_nedela2.shm"); +// $shm_probe(tb_vip, "AS"); +// $dumpfile("tb_vip.vcd"); +// `include "tb_vip.trace" +// $dumpvars(0, tb_vip); +// $monitor("TIME %t: dc.dclsu_addr %h", $time, vip.vipcore.risc.dc.dclsu_addr); +end +endtask + +task finish_simulation; +begin + $fclose(fexe); +// display_arch_state; + display_memory(0, 8191); + $shm_save; + $shm_close; + $dumpflush; + $finish; +end +endtask + +task caught_sys203; +begin + $display("simulation terminated due to l.sys 203"); + finish_simulation; +end +endtask + +/* +task display_arch_stateOLD; +reg [5:0] i; +begin +`ifdef enable_display_arch_state + $display("Last:"); + $display("%h: %h: TIME:%t", risc.cpu.except.wb_pc, risc.cpu.id.wb_insn, $time); + $display("PC:"); + $write("%h: %h: ", risc.cpu.except.ex_pc, risc.cpu.id.ex_insn); + $write(" SR: %h EPCR: %h ESR: %h", risc.cpu.sprs.sr, risc.cpu.except.epcr, risc.cpu.except.esr); + for(i = 0; i < 32; i = i + 1) begin + if (i % 4 == 0) + $display(); + $write("GPR%d: %h ", i, risc.cpu.rf.rf_a.mem[i]); + end + $display("flag: %b", risc.cpu.alu.flag); + $display; +`endif +end +endtask +*/ + +task display_arch_state; +reg [5:0] i; +begin +`ifdef enable_display_arch_state + ref = ref + 1; +// if (ref == 17890) begin +// $dumpfile("dump.vcd"); +// $dumpvars(20,tb_or1200); +// end + $fwrite(fexe, "\nEXECUTED(): %h: %h", risc.cpu.except.wb_pc, risc.cpu.id.wb_insn); + for(i = 0; i < 32; i = i + 1) begin + if (i % 4 == 0) + $fdisplay(fexe); + $fwrite(fexe, "GPR%d: %h ", i, risc.cpu.rf.rf_a.mem[i]); + end + $fdisplay(fexe); +`endif +end +endtask + +task display_memory; +input [31:0] from; +input [31:0] to; +integer i; +begin +// for(i = from; i < to; i = i + 4) +// $display("mem[%h] = %h mem[%h] = %h mem[%h] = %h mem[%h] = %h ", +// i, sram2.ramCore[i], i+4, sram2.ramCore[i+1], i+8, sram2.ramCore[i+2], i+12, sram2.ramCore[i+3]); //zSramX32 +// i<<2, sram2.mem[i], (i<<2)+4, sram2.mem[i+1], (i<<2)+8, sram2.mem[i+2], (i<<2)+12, sram2.mem[i+3]); //sram32kx32 +end +endtask + +task debug_mem; +input [79:0] device; +input write; +input [31:0] addr; +input [31:0] data; +input [3:0] bs; +begin +`ifdef enable_debug_mem + if (write) + $display( "%t: WRITE to %s addr 0x%h with a value of 0x%h using byte enables of 'b%b", $time, device, addr, data, bs); + else + $display( "%t: READ from %s addr 0x%h which contains a value of 0x%h using byte enables of 'b%b", $time, device, addr, data, bs); +`endif +end +endtask

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