URL
https://opencores.org/ocsvn/or1k/or1k/trunk
Subversion Repositories or1k
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 1607 to Rev 1608
- ↔ Reverse comparison
Rev 1607 → Rev 1608
/trunk/or1ksim/pic/pic.c
62,9 → 62,9
if(cpu_state.sprs[SPR_SR] & SPR_SR_IEE) { |
TRACE("Delivering interrupt on cycle %lli\n", runtime.sim.cycles); |
except_handle(EXCEPT_INT, cpu_state.sprs[SPR_EEAR_BASE]); |
} else if(cpu_state.sprs[SPR_PICSR] & (1 << (int)dat)) |
} else if(cpu_state.sprs[SPR_PICSR] & cpu_state.sprs[SPR_PICMR]) |
/* Reschedule only if the interrupt hasn't been cleared */ |
sched_next_insn(pic_clock, dat); |
sched_next_insn(pic_clock, NULL); |
} |
|
/* WARNING: Don't eaven try and call this function *during* a simulated |
81,6 → 81,8
TRACE("Asserting interrupt %d (%s).\n", line, |
(cpu_state.sprs[SPR_PICMR] & (1 << line)) ? "Unmasked" : "Masked"); |
|
SCHED_FIND_REMOVE(pic_clock, NULL); |
|
if ((cpu_state.sprs[SPR_PICMR] & (1 << line)) || line < 2) { |
cpu_state.sprs[SPR_PICSR] |= 1 << line; |
/* Don't do anything if interrupts not currently enabled */ |
87,8 → 89,11
if (cpu_state.sprs[SPR_SR] & SPR_SR_IEE) { |
TRACE("Delivering interrupt on cycle %lli\n", runtime.sim.cycles); |
except_handle(EXCEPT_INT, cpu_state.sprs[SPR_EEAR_BASE]); |
} else |
/* Interrupts not currently enabled, retry next clock cycle */ |
sched_next_insn(pic_clock, (void *)line); |
return; |
} |
} |
|
if(cpu_state.sprs[SPR_PICMR] & cpu_state.sprs[SPR_PICSR]) |
/* Interrupts not currently enabled, retry next clock cycle */ |
sched_next_insn(pic_clock, NULL); |
} |