URL
https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk
Subversion Repositories open8_urisc
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- This comparison shows the changes necessary to convert path
/
- from Rev 163 to Rev 164
- ↔ Reverse comparison
Rev 163 → Rev 164
/open8_urisc/trunk/VHDL/Open8.vhd
69,6 → 69,10
-- : places the result of R0 * Rn into R1:R0, and executes in two |
-- : cycles. (R1:R0 = R0 * Rn) |
-- : |
-- : BRK_Implements_WAI modifies the BRK instruction such that it |
-- : triggers the wait for interrupt state, but without triggering |
-- : a soft interrupt in lieu of its normal behavior, which is to |
-- : insert several dead clock cycles - essentially a long NOP |
-- Revision History |
-- Author Date Change |
------------------ -------- --------------------------------------------------- |
83,6 → 87,8
-- Seth Henry 09/20/11 Added BRK_Implements_WAI option, allowing the |
-- processor to wait for an interrupt instead of the |
-- normal BRK behavior. |
-- Seth Henry 12/20/11 Modified core to allow WAIT_FOR_INT state to idle |
-- the bus entirely (Rd_Enable is low) |
|
library ieee; |
use ieee.std_logic_1164.all; |
203,7 → 209,8
Addr : ADDRESS_TYPE; |
end record; |
|
type DP_MODES is ( DATA_IDLE, DATA_REG, DATA_FLAG, DATA_PC ); |
type DP_MODES is ( DATA_BUS_IDLE, DATA_RD_MEM, |
DATA_WR_REG, DATA_WR_FLAG, DATA_WR_PC ); |
|
type DATA_CTRL_TYPE is record |
Src : DP_MODES; |
354,7 → 361,7
-- |
Address <= Program_Ctr; |
-- |
DP_Ctrl.Src <= DATA_IDLE; |
DP_Ctrl.Src <= DATA_RD_MEM; |
DP_Ctrl.Reg <= ACCUM; |
-- |
INT_Ctrl.Mask_Set <= '0'; |
396,7 → 403,7
CPU_Next_State <= PSH_C1; |
Cache_Ctrl <= CACHE_PREFETCH; |
PC_Ctrl.Oper <= PC_REV1; |
DP_Ctrl.Src <= DATA_REG; |
DP_Ctrl.Src <= DATA_WR_REG; |
DP_Ctrl.Reg <= SubOp; |
|
when OP_POP => |
419,6 → 426,7
|
when OP_INT => |
PC_Ctrl.Oper <= PC_INCR; |
-- Make sure the requested interrupt is actually enabled first |
if( Int_Mask(Reg) = '1' )then |
CPU_Next_State <= WAIT_FOR_INT; |
INT_Ctrl.Soft_Ints(Reg) <= '1'; |
463,7 → 471,7
when SOP_JSR => |
CPU_Next_State <= JSR_C1; |
Cache_Ctrl <= CACHE_OPER1; |
DP_Ctrl.Src <= DATA_PC; |
DP_Ctrl.Src <= DATA_WR_PC; |
DP_Ctrl.Reg <= ACCUM+1; |
|
when others => null; |
531,7 → 539,7
CPU_Next_State <= STO_C1; |
Cache_Ctrl <= CACHE_OPER1; |
PC_Ctrl.Oper <= PC_REV2; |
DP_Ctrl.Src <= DATA_REG; |
DP_Ctrl.Src <= DATA_WR_REG; |
DP_Ctrl.Reg <= ACCUM; |
|
when OP_STX => |
538,7 → 546,7
CPU_Next_State <= STX_C1; |
Cache_Ctrl <= CACHE_PREFETCH; |
PC_Ctrl.Oper <= PC_REV2; |
DP_Ctrl.Src <= DATA_REG; |
DP_Ctrl.Src <= DATA_WR_REG; |
DP_Ctrl.Reg <= ACCUM; |
|
when others => |
648,7 → 656,7
when STA_C1 => |
CPU_Next_State <= STA_C2; |
Cache_Ctrl <= CACHE_OPER2; |
DP_Ctrl.Src <= DATA_REG; |
DP_Ctrl.Src <= DATA_WR_REG; |
DP_Ctrl.Reg <= SubOp; |
|
when STA_C2 => |
764,6 → 772,7
-- Subroutines & Interrupts (RTS, JSR) |
------------------------------------------------------------------------------- |
when WAIT_FOR_INT => -- For soft interrupts only, halt the Program_Ctr |
DP_Ctrl.Src <= DATA_BUS_IDLE; |
CPU_Next_State <= WAIT_FOR_INT; |
|
when ISR_C1 => |
774,7 → 783,7
when ISR_C2 => |
CPU_Next_State <= ISR_C3; |
Address <= ISR_Addr; |
DP_Ctrl.Src <= DATA_FLAG; |
DP_Ctrl.Src <= DATA_WR_FLAG; |
|
when ISR_C3 => |
CPU_Next_State <= JSR_C1; |
781,7 → 790,7
Cache_Ctrl <= CACHE_OPER1; |
Address <= Stack_Ptr; |
SP_Ctrl.Oper <= SP_PUSH; |
DP_Ctrl.Src <= DATA_PC; |
DP_Ctrl.Src <= DATA_WR_PC; |
DP_Ctrl.Reg <= ACCUM+1; |
ALU_Ctrl.Oper <= ALU_STP; |
ALU_Ctrl.Reg <= INT_FLAG; |
792,7 → 801,7
Cache_Ctrl <= CACHE_OPER2; |
Address <= Stack_Ptr; |
SP_Ctrl.Oper <= SP_PUSH; |
DP_Ctrl.Src <= DATA_PC; |
DP_Ctrl.Src <= DATA_WR_PC; |
DP_Ctrl.Reg <= ACCUM; |
|
when JSR_C2 => |
861,7 → 870,7
ALU_Ctrl.Oper <= ALU_IDLE; |
Cache_Ctrl <= CACHE_IDLE; |
SP_Ctrl.Oper <= SP_IDLE; |
DP_Ctrl.Src <= DATA_IDLE; -- JSH 7/20 |
DP_Ctrl.Src <= DATA_RD_MEM; -- JSH 7/20 |
INT_Ctrl.Soft_Ints <= (others => '0'); -- JSH 7/22 |
-- Rewind the PC by 3 to compensate for the pipeline registers |
PC_Ctrl.Oper <= PC_INCR; |
932,10 → 941,10
|
elsif( rising_edge(Clock) )then |
Wr_Enable <= '0'; |
Wr_Data <= x"00"; |
Rd_Enable <= '0'; |
|
if( Halt = '0' )then |
Rd_Enable <= '1'; |
------------------------------------------------------------------------------- |
-- Instruction/Operand caching for pipelined memory access |
------------------------------------------------------------------------------- |
996,22 → 1005,22
-- (Write) Data Path |
------------------------------------------------------------------------------- |
case DP_Ctrl.Src is |
when DATA_IDLE => |
when DATA_BUS_IDLE => |
null; |
|
when DATA_REG => |
when DATA_RD_MEM => |
Rd_Enable <= '1'; |
|
when DATA_WR_REG => |
Wr_Enable <= '1'; |
Rd_Enable <= '0'; |
Wr_Data <= Regfile(conv_integer(DP_Ctrl.Reg)); |
|
when DATA_FLAG => |
when DATA_WR_FLAG => |
Wr_Enable <= '1'; |
Rd_Enable <= '0'; |
Wr_Data <= Flags; |
|
when DATA_PC => |
when DATA_WR_PC => |
Wr_Enable <= '1'; |
Rd_Enable <= '0'; |
Wr_Data <= Program_Ctr(15 downto 8); |
if( DP_Ctrl.Reg = ACCUM )then |
Wr_Data <= Program_Ctr(7 downto 0); |