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https://opencores.org/ocsvn/t400/t400/trunk
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- This comparison shows the changes necessary to convert path
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- from Rev 163 to Rev 164
- ↔ Reverse comparison
Rev 163 → Rev 164
/trunk/README
1,7 → 1,7
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README for the T400 uController project |
======================================= |
Version: $Date: 2006-06-12 00:09:56 $ |
Version: $Date: 2008-04-27 22:15:43 $ |
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Introduction |
93,6 → 93,12
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| \-- rtl_sim : Directory for running simulations. |
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+-- syn |
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| +-- ep1c12 : Synthesis for Altera Cyclone. |
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| \-- xc3s1000 : Synthesis for Xilinx Spartan3. |
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\-- sw : General purpose scripts and files. |
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\-- verif : The verification suite. |
183,7 → 189,7
---------------------------- |
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All testbenches listed above load the internal ROM of the controller from a |
file in hex-format. Its existance is mandatory as it is referenced in the |
file in hex-format. Its existance is mandatory since it is referenced in the |
VHDL code of the ROM model lpm_rom.vhd. In case it is missing, the |
simulation will stop immediately after elaborating the design. |
|
309,7 → 315,7
All of the design files contain pure RTL code. This is true even for the |
technology specific power-on reset module. Two flavors exist, each of them |
implementing the desired behavior in a way that is understood by the design |
tools. The RAM for the data memory is described by generic RTL code as |
tools. The RAM for the data memory is described by generic RTL code as |
well. It should be translated automatically by the tool chain to a technology |
specific RAM macro. |
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