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Rev 164 → Rev 165
/trunk/or1200/bench/wb_sram.v
44,7 → 44,10
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.1 2001/07/20 00:49:34 lampret |
// Benches (under development). |
// |
// |
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`include "general.h" |
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110,20 → 113,57
reg [31:0] wb1_dat_o; // output data bus |
reg wb1_read_ok; // Internal read ACK |
reg [31:0] wb1_tmp; |
reg r1_ack_o; |
reg [31:0] wb2_dat_o; // output data bus |
reg wb2_read_ok; // Internal read ACK |
reg [31:0] wb2_tmp; |
reg r2_ack_o; |
reg r2_read_ok; |
reg [31:0] mem [words-1:0];// memory core |
integer i; |
integer f; |
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//`define NODELAY_WB1 |
//`define NODELAY_WB2 |
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// |
// Transfer termination assignments |
// |
always @(posedge wb1_rst_i or posedge wb1_clk_i) |
if (wb1_rst_i) |
r1_ack_o <= #1 1'b0; |
else if (wb1_stb_i & wb1_we_i) |
r1_ack_o <= #1 1'b1; |
else |
r1_ack_o <= #1 1'b0; |
`ifdef NODELAY_WB1 |
assign wb1_ack_o = wb1_stb_i & wb1_we_i | wb1_read_ok; |
`else |
assign wb1_ack_o = r1_ack_o | wb1_read_ok; |
`endif |
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assign wb1_err_o = 1'b0; |
assign wb1_rty_o = 1'b0; |
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always @(posedge wb2_rst_i or posedge wb2_clk_i) |
if (wb2_rst_i) |
r2_ack_o <= #1 1'b0; |
else if (wb2_stb_i & wb2_we_i) |
r2_ack_o <= #1 1'b1; |
else |
r2_ack_o <= #1 1'b0; |
always @(posedge wb2_rst_i or posedge wb2_clk_i) |
if (wb2_rst_i) |
r2_read_ok <= #1 1'b0; |
else if (wb2_read_ok) |
r2_read_ok <= #1 1'b1; |
else |
r2_read_ok <= #1 1'b0; |
`ifdef NODELAY_WB2 |
assign wb2_ack_o = wb2_stb_i & wb2_we_i | wb2_read_ok; |
`else |
assign wb2_ack_o = r2_ack_o | r2_read_ok; |
`endif |
assign wb2_err_o = 1'b0; |
assign wb2_rty_o = 1'b0; |
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