URL
https://opencores.org/ocsvn/t48/t48/trunk
Subversion Repositories t48
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- This comparison shows the changes necessary to convert path
/
- from Rev 166 to Rev 167
- ↔ Reverse comparison
Rev 166 → Rev 167
/trunk/rtl/vhdl/system/wb_master.vhd
2,7 → 2,7
-- |
-- The Wishbone master module. |
-- |
-- $Id: wb_master.vhd,v 1.2 2005-05-06 18:54:03 arniml Exp $ |
-- $Id: wb_master.vhd,v 1.3 2005-05-08 10:36:07 arniml Exp $ |
-- |
-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org) |
-- |
41,6 → 41,27
-- The latest version of this file can be found at: |
-- http://www.opencores.org/cvsweb.shtml/t48/ |
-- |
-- |
-- Short description: |
-- This design implements a simple Wishbone bus master. It connects to the |
-- BUS interface of the T48 uController core. |
-- |
-- The CPU clock is suppressed with en_clk_o to stall the CPU until the |
-- acknowledge signal from the peripheral is detected. |
-- |
-- The adr_i input selects between configuration and Wishbone address range: |
-- 1 - configuration range |
-- 0 - Wishbone range |
-- |
-- When configuration range is selected, two address register are accessible. |
-- 000h -> adr1 |
-- 001h -> adr2 |
-- These registers can be read and written with movx to their addresses. |
-- |
-- When Wishbone range is selected, all movx generate Wishbone bus cycles |
-- (either read or write) at following address: |
-- Wishbone address = adr2 & adr1 & address of movx |
-- |
------------------------------------------------------------------------------- |
|
library ieee; |
51,24 → 72,24
entity wb_master is |
|
port ( |
xtal_i : in std_logic; |
res_i : in std_logic; |
en_clk_o : out std_logic; |
xtal_i : in std_logic; |
res_i : in std_logic; |
en_clk_o : out std_logic; |
-- T48 Interface ---------------------------------------------------------- |
ale_i : in std_logic; |
rd_n_i : in std_logic; |
wr_n_i : in std_logic; |
sel_range_i : in std_logic_vector( 1 downto 0); |
db_bus_i : in std_logic_vector( 7 downto 0); |
db_bus_o : out std_logic_vector( 7 downto 0); |
ale_i : in std_logic; |
rd_n_i : in std_logic; |
wr_n_i : in std_logic; |
adr_i : in std_logic; |
db_bus_i : in std_logic_vector( 7 downto 0); |
db_bus_o : out std_logic_vector( 7 downto 0); |
-- Wishbone Interface ----------------------------------------------------- |
wb_cyc_o : out std_logic; |
wb_stb_o : out std_logic; |
wb_we_o : out std_logic; |
wb_adr_o : out std_logic_vector(23 downto 0); |
wb_ack_i : in std_logic; |
wb_dat_i : in std_logic_vector( 7 downto 0); |
wb_dat_o : out std_logic_vector( 7 downto 0) |
wb_cyc_o : out std_logic; |
wb_stb_o : out std_logic; |
wb_we_o : out std_logic; |
wb_adr_o : out std_logic_vector(23 downto 0); |
wb_ack_i : in std_logic; |
wb_dat_i : in std_logic_vector( 7 downto 0); |
wb_dat_o : out std_logic_vector( 7 downto 0) |
); |
|
end wb_master; |
88,10 → 109,10
----------------------------------------------------------------------------- |
signal sel_adr1_s, |
sel_adr2_s, |
sel_wb_s : boolean; |
sel_wb_s : boolean; |
|
signal wr_s, |
rd_s : boolean; |
rd_s : boolean; |
|
signal adr_q : std_logic_vector(23 downto 0); |
|
100,12 → 121,12
----------------------------------------------------------------------------- |
-- Select signal generation |
----------------------------------------------------------------------------- |
sel_adr1_s <= sel_range_i = "01"; |
sel_adr2_s <= sel_range_i = "10"; |
sel_wb_s <= sel_range_i = "00"; |
sel_adr1_s <= adr_i = '1' and adr_q(word_t'range) = "00000000"; |
sel_adr2_s <= adr_i = '1' and adr_q(word_t'range) = "00000001"; |
sel_wb_s <= adr_i = '0'; |
|
wr_s <= wr_n_i = '0'; |
rd_s <= rd_n_i = '0'; |
wr_s <= wr_n_i = '0'; |
rd_s <= rd_n_i = '0'; |
|
|
----------------------------------------------------------------------------- |
163,11 → 184,13
state_s <= IDLE; |
|
case state_q is |
-- Idle State: Wait for read or write access ---------------------------- |
when IDLE => |
if sel_wb_s and (wr_s or rd_s) then |
state_s <= CYC; |
end if; |
|
-- WB Cycle State: Start Wishbone cycle and wait for ack ---------------- |
when CYC => |
wb_cyc_o <= '1'; |
wb_stb_o <= '1'; |
179,6 → 202,7
state_s <= CYC; |
end if; |
|
-- Wait inact State: Wait for end of T48 access ------------------------- |
when WAIT_INACT => |
if not wr_s and not rd_s then |
state_s <= IDLE; |
202,7 → 226,7
db_bus_o <= adr_q(word_t'length*2 - 1 downto word_t'length) |
when sel_adr1_s else |
adr_q(word_t'length*3 - 1 downto word_t'length*2) |
when sel_adr1_s else |
when sel_adr2_s else |
wb_dat_i; |
|
|
222,6 → 246,9
-- File History: |
-- |
-- $Log: not supported by cvs2svn $ |
-- Revision 1.2 2005/05/06 18:54:03 arniml |
-- assign default for state_s |
-- |
-- Revision 1.1 2005/05/05 19:49:03 arniml |
-- initial check-in |
-- |