OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /
    from Rev 1670 to Rev 1671
    Reverse comparison

Rev 1670 → Rev 1671

/trunk/or1ksim/cpu/or32/dyn_rec.c
524,7 → 524,7
}
 
/* Adds code to the opq for the instruction pointed to by addr */
static void recompile_insn(struct op_queue *opq, oraddr_t addr, int delay_insn)
static void recompile_insn(struct op_queue *opq, int delay_insn)
{
unsigned int pres_t[NUM_T_REGS]; /* Which temporary to preserve */
int i, j, k;
707,7 → 707,7
 
/* Insert code to check if the first instruction is exeucted in a delay slot*/
gen_op_check_delay_slot(opq, 1, 0);
recompile_insn(opq, rec_addr, 1);
recompile_insn(opq, 1);
ship_gprs_out_t(opq, 1, opq->reg_t_d);
gen_op_do_sched_delay(opq, 1);
gen_op_clear_delay_insn(opq, 1);
740,7 → 740,7
opq->reg_t[j] = 32;
}
 
recompile_insn(opq, rec_addr, 0);
recompile_insn(opq, 0);
 
/* Store the state of the temporaries */
memcpy(opq->next->reg_t, opq->reg_t_d, sizeof(opq->reg_t));
831,7 → 831,7
memcpy(delay_opq.reg_t, delay_opq.reg_t_d, sizeof(delay_opq.reg_t));
 
/* Generate the delay slot instruction */
recompile_insn(&delay_opq, opq->insn_addr + 4, 1);
recompile_insn(&delay_opq, 1);
 
ship_gprs_out_t(&delay_opq, 1, delay_opq.reg_t_d);
memcpy(opq->reg_t_d, delay_opq.reg_t_d, sizeof(delay_opq.reg_t));

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.