URL
https://opencores.org/ocsvn/or1k/or1k/trunk
Subversion Repositories or1k
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 1689 to Rev 1690
- ↔ Reverse comparison
Rev 1689 → Rev 1690
/trunk/or1ksim/cpu/or32/execute.c
51,6 → 51,9
#include "dmmu.h" |
#include "debug.h" |
#include "stats.h" |
#include "gdbcomm.h" |
#include "sched.h" |
#include "vapi.h" |
#include "misc.h" |
|
/* Current cpu state */ |
698,6 → 701,50
except_handle(EXCEPT_ILLEGAL, cpu_state.iqueue.insn_addr); |
} |
|
void exec_main(void) |
{ |
long long time_start; |
while(1) { |
time_start = runtime.sim.cycles; |
if (config.debug.enabled) { |
du_clock(); // reset watchpoints |
while (runtime.cpu.stalled) { |
if(config.debug.gdb_enabled) { |
BlockJTAG(); |
HandleServerSocket(false); |
} else { |
fprintf (stderr, "WARNING: CPU stalled and gdb connection not enabled.\n"); |
/* Dump the user into interactive mode. From there he can decide what |
* to do. */ |
handle_sim_command(); |
sim_done(); |
} |
if(runtime.sim.iprompt) |
handle_sim_command(); |
} |
} |
|
/* Each cycle has counter of mem_cycles; this value is joined with cycles |
at the end of the cycle; no sim originated memory accesses should be |
performed inbetween. */ |
runtime.sim.mem_cycles = 0; |
if (!config.pm.enabled || |
!(cpu_state.sprs[SPR_PMR] & (SPR_PMR_DME | SPR_PMR_SME))) |
if (cpu_clock ()) |
/* A breakpoint has been hit, drop to interactive mode */ |
handle_sim_command(); |
|
if (config.vapi.enabled && runtime.vapi.enabled) vapi_check(); |
if (config.debug.gdb_enabled) HandleServerSocket(false); /* block & check_stdin = false */ |
if(config.debug.enabled) |
if (cpu_state.sprs[SPR_DMR1] & SPR_DMR1_ST) set_stall_state (1); |
|
runtime.sim.cycles += runtime.sim.mem_cycles; |
scheduler.job_queue->time -= runtime.sim.cycles - time_start; |
if (scheduler.job_queue->time <= 0) do_scheduler (); |
} |
} |
|
#if COMPLEX_EXECUTION |
|
/* Include decode_execute function */ |
/trunk/or1ksim/cpu/common/execute.h
77,3 → 77,4
|
extern oraddr_t pcnext; |
int depend_operands(struct iqueue_entry *prev, struct iqueue_entry *next); |
void exec_main(void); |
/trunk/or1ksim/toplevel.c
342,44 → 342,7
|
sim_init (); |
|
while(1) { |
long long time_start = runtime.sim.cycles; |
if (config.debug.enabled) { |
du_clock(); // reset watchpoints |
while (runtime.cpu.stalled) { |
if(config.debug.gdb_enabled) { |
BlockJTAG(); |
HandleServerSocket(false); |
} else { |
fprintf (stderr, "WARNING: CPU stalled and gdb connection not enabled.\n"); |
/* Dump the user into interactive mode. From there he can decide what |
* to do. */ |
handle_sim_command(); |
sim_done(); |
} |
if(runtime.sim.iprompt) |
handle_sim_command(); |
} |
} |
exec_main(); |
|
/* Each cycle has counter of mem_cycles; this value is joined with cycles |
at the end of the cycle; no sim originated memory accesses should be |
performed inbetween. */ |
runtime.sim.mem_cycles = 0; |
if (!config.pm.enabled || |
!(cpu_state.sprs[SPR_PMR] & (SPR_PMR_DME | SPR_PMR_SME))) |
if (cpu_clock ()) |
/* A breakpoint has been hit, drop to interactive mode */ |
handle_sim_command(); |
|
if (config.vapi.enabled && runtime.vapi.enabled) vapi_check(); |
if (config.debug.gdb_enabled) HandleServerSocket(false); /* block & check_stdin = false */ |
if(config.debug.enabled) |
if (cpu_state.sprs[SPR_DMR1] & SPR_DMR1_ST) set_stall_state (1); |
|
runtime.sim.cycles += runtime.sim.mem_cycles; |
scheduler.job_queue->time -= runtime.sim.cycles - time_start; |
if (scheduler.job_queue->time <= 0) do_scheduler (); |
} |
sim_done(); |
} |