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URL https://opencores.org/ocsvn/apbi2c/apbi2c/trunk

Subversion Repositories apbi2c

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  • This comparison shows the changes necessary to convert path 
    /
    from Rev 17 to Rev 18
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Rev 17 → Rev 18

/apbi2c/trunk/rtl/i2c.v
124,11 → 124,11
wire tx_empty;
wire rx_empty;
 
wire w_pwrite;
//wire w_pwrite;
wire w_full;
wire w_full_tx;
//wire w_full_tx;
 
assign w_pwrite = (PWRITE == 1'b0)?1'b1:1'b0;
//assign w_pwrite = (PWRITE == 1'b0)?1'b1:1'b0;
 
145,9 → 145,9
);
 
 
and(w_full_tx,w_pwrite,w_full);
//and(w_full_tx,w_pwrite,w_full);
 
assign TX_F_FULL = w_full_tx;
assign TX_F_FULL = w_full;
 
//CONECTIONS WITH FIFO RX
fifo DUT_FIFO_RX (
/apbi2c/trunk/rtl/module_i2c.v
205,15 → 205,15
TX_IDLE:
begin
//OBEYING SPEC
if(DATA_CONFIG_REG[0] == 1'b0 && fifo_tx_f_full == 1'b0 && DATA_CONFIG_REG[1] == 1'b0)
if(DATA_CONFIG_REG[0] == 1'b0 && (fifo_tx_f_full == 1'b1 || fifo_tx_f_empty == 1'b0) && DATA_CONFIG_REG[1] == 1'b0)
begin
next_state_tx = TX_IDLE;
end
else if(DATA_CONFIG_REG[0] == 1'b1 && fifo_tx_f_full == 1'b1 && DATA_CONFIG_REG[1] == 1'b1)
else if(DATA_CONFIG_REG[0] == 1'b1 && (fifo_tx_f_full == 1'b1 || fifo_tx_f_empty == 1'b0) && DATA_CONFIG_REG[1] == 1'b1)
begin
next_state_tx = TX_IDLE;
end
else if(DATA_CONFIG_REG[0] == 1'b1 && fifo_tx_f_full == 1'b1 && DATA_CONFIG_REG[1] == 1'b0)
else if(DATA_CONFIG_REG[0] == 1'b1 && (fifo_tx_f_full == 1'b1 || fifo_tx_f_empty == 1'b0) && DATA_CONFIG_REG[1] == 1'b0)
begin
next_state_tx = TX_START;
end
766,18 → 766,18
fifo_tx_rd_en <= 1'b0;
if(DATA_CONFIG_REG[0] == 1'b0 && fifo_tx_f_full == 1'b0 && DATA_CONFIG_REG[1] == 1'b0)
if(DATA_CONFIG_REG[0] == 1'b0 && (fifo_tx_f_full == 1'b1 ||fifo_tx_f_empty == 1'b0) && DATA_CONFIG_REG[1] == 1'b0)
begin
count_send_data <= 12'd0;
SDA_OUT<= 1'b1;
BR_CLK_O <= 1'b1;
end
else if(DATA_CONFIG_REG[0] == 1'b1 && fifo_tx_f_full == 1'b1 && DATA_CONFIG_REG[1] == 1'b0)
else if(DATA_CONFIG_REG[0] == 1'b1 && (fifo_tx_f_full == 1'b1 ||fifo_tx_f_empty == 1'b0) && DATA_CONFIG_REG[1] == 1'b0)
begin
count_send_data <= count_send_data + 12'd1;
SDA_OUT<=1'b0;
end
else if(DATA_CONFIG_REG[0] == 1'b1 && fifo_tx_f_full == 1'b1 && DATA_CONFIG_REG[1] == 1'b1)
else if(DATA_CONFIG_REG[0] == 1'b1 && (fifo_tx_f_full == 1'b1 ||fifo_tx_f_empty == 1'b0) && DATA_CONFIG_REG[1] == 1'b1)
begin
count_send_data <= 12'd0;
SDA_OUT<= 1'b1;
1304,6 → 1304,7
else
begin
count_send_data <= 12'd0;
SDA_OUT<=1'b0;
end
end
1558,6 → 1559,7
else
begin
count_send_data <= 12'd0;
SDA_OUT<=1'b0;
end
end
1819,6 → 1821,7
else
begin
count_send_data <= 12'd0;
SDA_OUT<=1'b0;
end
end
2610,7 → 2613,7
end
RX_START:
begin
if(SDA == 1'b0 && SCL == 1'b0)
if(SDA == 1'b0 && SCL == 1'b0 && count_receive_data < DATA_CONFIG_REG[13:2] )
begin
count_receive_data <= count_receive_data +12'd1;
end
/apbi2c/trunk/rtl/fifo.v
26,7 → 26,7
////
////
//// Author(s): - Felipe Fernandes Da Costa, fefe2560@gmail.com
//// Ronal Dario Celaya
//// Ronal Dario Celaya ,rcelaya.dario@gmail.com
////
/////////////////////////////////////////////////////////////////
////
98,7 → 98,6
reg [AWIDTH-1:0] rd_ptr;
reg [AWIDTH:0] counter;
 
reg last_was_write;
 
//Write pointer
always@(posedge clock)
146,8 → 145,8
end
end
 
assign f_full = (counter == DEPTH -1) ; //(!last_was_write | last_position != {AWIDTH{1'b0}} )? 1'b1:1'b0;
assign f_empty = (counter == {AWIDTH{1'b0}}); //(last_was_write)? 1'b1:1'b0;
assign f_full = (counter == DEPTH- 1) ;
assign f_empty = (counter == {AWIDTH{1'b0}});
assign wr_en_ram = wr_en;
assign rd_en_ram = rd_en;
assign data_out = data_ram_out;
/apbi2c/trunk/rtl/dual_port_ram.v
1,3 → 1,79
//////////////////////////////////////////////////////////////////
////
////
//// TOP I2C BLOCK to I2C Core
////
////
////
//// This file is part of the APB to I2C project
////
//// http://www.opencores.org/cores/apbi2c/
////
////
////
//// Description
////
//// Implementation of APB IP core according to
////
//// apbi2c_spec IP core specification document.
////
////
////
//// To Do: Things are right here but always all block can suffer changes
////
////
////
////
////
//// Author(s): - Felipe Fernandes Da Costa, fefe2560@gmail.com
//// Ronal Dario Celaya ,rcelaya.dario@gmail.com
////
/////////////////////////////////////////////////////////////////
////
////
//// Copyright (C) 2009 Authors and OPENCORES.ORG
////
////
////
//// This source file may be used and distributed without
////
//// restriction provided that this copyright statement is not
////
//// removed from the file and that any derivative work contains
//// the original copyright notice and the associated disclaimer.
////
////
//// This source file is free software; you can redistribute it
////
//// and/or modify it under the terms of the GNU Lesser General
////
//// Public License as published by the Free Software Foundation;
//// either version 2.1 of the License, or (at your option) any
////
//// later version.
////
////
////
//// This source is distributed in the hope that it will be
////
//// useful, but WITHOUT ANY WARRANTY; without even the implied
////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
////
//// PURPOSE. See the GNU Lesser General Public License for more
//// details.
////
////
////
//// You should have received a copy of the GNU Lesser General
////
//// Public License along with this source; if not, download it
////
//// from http://www.opencores.org/lgpl.shtml
////
////
///////////////////////////////////////////////////////////////////
 
`timescale 1ns/1ps
module dp_ram
#( parameter integer DWIDTH = 32,
8,7 → 84,7
input clock, reset, wr_en, rd_en,
input [DWIDTH-1:0] data_in,
input [AWIDTH-1:0] wr_addr,
output reg [DWIDTH-1:0] data_out,
output [DWIDTH-1:0] data_out,
input [AWIDTH-1:0] rd_addr
);
 
15,7 → 91,7
reg [DWIDTH-1:0] mem [0:2**AWIDTH-1];
integer i;
 
always @(*)
always @(posedge clock)
begin
if (reset)
begin
23,7 → 99,6
begin
mem[i] <= {DWIDTH{1'b0}};
end
data_out <= {DWIDTH{1'b0}};
end
else
begin
31,10 → 106,10
begin
mem[wr_addr] <= data_in;
end
if (rd_en)
begin
data_out <= mem[rd_addr];
end
end
end
 
assign data_out = (rd_en)?mem[rd_addr]:mem[rd_addr];
 
 
endmodule

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