URL
https://opencores.org/ocsvn/can/can/trunk
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Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 17 to Rev 18
- ↔ Reverse comparison
Rev 17 → Rev 18
/trunk/bench/verilog/can_testbench.v
45,6 → 45,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.12 2003/01/14 17:25:03 mohor |
// Addresses corrected to decimal values (previously hex). |
// |
// Revision 1.11 2003/01/14 12:19:29 mohor |
// rx_fifo is now working. |
// |
195,14 → 198,15
|
if(`CAN_CLOCK_DIVIDER_MODE) // Extended mode |
begin |
// send_frame(0, 1, {26'h00000a6, 3'h5}, 2, 15'h2a11); // mode, rtr, id, length, crc |
// send_frame(0, 1, 29'h12567635, 2, 15'h75b4); // mode, rtr, id, length, crc |
send_frame(0, 1, {26'h00000a6, 3'h5}, 4'h2, 15'h2a11); // mode, rtr, id, length, crc |
// receive_frame(0, 0, {26'h00000a6, 3'h5}, 2, 15'h2a11); // mode, rtr, id, length, crc |
// receive_frame(0, 0, 29'h12567635, 2, 15'h75b4); // mode, rtr, id, length, crc |
receive_frame(0, 0, {26'h00000a6, 3'h5}, 4'h2, 15'h2a11); // mode, rtr, id, length, crc |
end |
else |
begin |
// test_empty_fifo; test currently switched off |
test_full_fifo; |
// test_empty_fifo; // test currently switched off |
test_full_fifo; // test currently switched on |
// send_frame; |
end |
|
|
213,11 → 217,50
|
|
|
task send_frame; // CAN IP core sends frames |
begin |
|
if(`CAN_CLOCK_DIVIDER_MODE) // Extended mode |
begin |
|
// Writing TX frame information + identifier + data |
write_register(8'd16, 8'h12); |
write_register(8'd17, 8'h34); |
write_register(8'd18, 8'h56); |
write_register(8'd19, 8'h78); |
write_register(8'd20, 8'h9a); |
write_register(8'd21, 8'hbc); |
write_register(8'd22, 8'hde); |
write_register(8'd23, 8'hf0); |
write_register(8'd24, 8'h0f); |
write_register(8'd25, 8'hed); |
write_register(8'd26, 8'hcb); |
write_register(8'd27, 8'ha9); |
write_register(8'd28, 8'h87); |
end |
else |
begin |
write_register(8'd10, 8'h12); // Writing ID[10:3] = 0x12 |
write_register(8'd11, 8'h04); // Writing ID[3:0] = 0x0, rtr = 0, length = 4 |
write_register(8'd12, 8'h56); // data byte 1 |
write_register(8'd13, 8'h78); // data byte 2 |
write_register(8'd14, 8'h9a); // data byte 3 |
write_register(8'd15, 8'hbc); // data byte 4 |
write_register(8'd16, 8'hde); // data byte 5 |
write_register(8'd17, 8'hf0); // data byte 6 |
write_register(8'd18, 8'h0f); // data byte 7 |
write_register(8'd19, 8'hed); // data byte 8 |
end |
|
end |
endtask |
|
|
|
task test_empty_fifo; |
begin |
send_frame(0, 1, {26'h0000008, 3'h1}, 4'h3, 15'h6231); // mode, rtr, id, length, crc |
send_frame(0, 1, {26'h0000008, 3'h1}, 4'h7, 15'h6047); // mode, rtr, id, length, crc |
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h3, 15'h7bcb); // mode, rtr, id, length, crc |
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h7, 15'h085c); // mode, rtr, id, length, crc |
|
read_receive_buffer; |
fifo_info; |
237,7 → 280,7
read_receive_buffer; |
fifo_info; |
|
send_frame(0, 1, {26'h0000008, 3'h1}, 4'h8, 15'h30e1); // mode, rtr, id, length, crc |
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h8, 15'h57a0); // mode, rtr, id, length, crc |
|
$display("\n\n"); |
read_receive_buffer; |
266,34 → 309,34
|
read_overrun_info(0, 31); |
|
send_frame(0, 1, {26'h0000008, 3'h1}, 4'h0, 15'h3d18); // mode, rtr, id, length, crc |
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h0, 15'h4edd); // mode, rtr, id, length, crc |
read_receive_buffer; |
fifo_info; |
send_frame(0, 1, {26'h0000008, 3'h1}, 4'h1, 15'h00ca); // mode, rtr, id, length, crc |
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h1, 15'h1ccf); // mode, rtr, id, length, crc |
read_receive_buffer; |
fifo_info; |
send_frame(0, 1, {26'h0000008, 3'h1}, 4'h2, 15'h744a); // mode, rtr, id, length, crc |
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h2, 15'h73f4); // mode, rtr, id, length, crc |
fifo_info; |
read_receive_buffer; |
send_frame(0, 1, {26'h0000008, 3'h1}, 4'h3, 15'h6231); // mode, rtr, id, length, crc |
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h3, 15'h7bcb); // mode, rtr, id, length, crc |
fifo_info; |
send_frame(0, 1, {26'h0000008, 3'h1}, 4'h4, 15'h3051); // mode, rtr, id, length, crc |
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h4, 15'h37da); // mode, rtr, id, length, crc |
fifo_info; |
send_frame(0, 1, {26'h0000008, 3'h1}, 4'h5, 15'h52ef); // mode, rtr, id, length, crc |
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h5, 15'h7e15); // mode, rtr, id, length, crc |
fifo_info; |
send_frame(0, 1, {26'h0000008, 3'h1}, 4'h6, 15'h2c03); // mode, rtr, id, length, crc |
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h6, 15'h39cf); // mode, rtr, id, length, crc |
fifo_info; |
send_frame(0, 1, {26'h0000008, 3'h1}, 4'h7, 15'h6047); // mode, rtr, id, length, crc |
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h7, 15'h085c); // mode, rtr, id, length, crc |
fifo_info; |
send_frame(0, 1, {26'h0000008, 3'h1}, 4'h8, 15'h30e1); // mode, rtr, id, length, crc |
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h8, 15'h57a0); // mode, rtr, id, length, crc |
fifo_info; |
send_frame(0, 1, {26'h0000008, 3'h1}, 4'h8, 15'h30e1); // mode, rtr, id, length, crc |
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h8, 15'h57a0); // mode, rtr, id, length, crc |
fifo_info; |
send_frame(0, 1, {26'h0000008, 3'h1}, 4'h8, 15'h30e1); // mode, rtr, id, length, crc |
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h8, 15'h57a0); // mode, rtr, id, length, crc |
fifo_info; |
send_frame(0, 1, {26'h0000008, 3'h1}, 4'h8, 15'h30e1); // mode, rtr, id, length, crc |
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h8, 15'h57a0); // mode, rtr, id, length, crc |
fifo_info; |
send_frame(0, 1, {26'h0000008, 3'h1}, 4'h8, 15'h30e1); // mode, rtr, id, length, crc |
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h8, 15'h57a0); // mode, rtr, id, length, crc |
fifo_info; |
read_overrun_info(0, 15); |
|
302,7 → 345,7
release_rx_buffer; |
read_receive_buffer; |
fifo_info; |
send_frame(0, 1, {26'h0000008, 3'h1}, 4'h8, 15'h30e1); // mode, rtr, id, length, crc |
receive_frame(0, 0, {26'h0000008, 3'h1}, 4'h8, 15'h57a0); // mode, rtr, id, length, crc |
fifo_info; |
read_overrun_info(0, 15); |
$display("\n\n"); |
518,7 → 561,7
endtask |
|
|
task send_frame; |
task receive_frame; // CAN IP core receives frames |
input mode; |
input remote_trans_req; |
input [28:0] id; |
633,7 → 676,7
end |
*/ |
|
/* |
// |
// CRC monitor (used until proper CRC generation is used in testbench |
always @ (posedge clk) |
begin |
640,7 → 683,7
if (can_testbench.i_can_top.i_can_bsp.crc_error) |
$display("Calculated crc = 0x%0x, crc_in = 0x%0x", can_testbench.i_can_top.i_can_bsp.calculated_crc, can_testbench.i_can_top.i_can_bsp.crc_in); |
end |
*/ |
// |
|
|
|
/trunk/rtl/verilog/can_top.v
45,6 → 45,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.8 2003/01/14 17:25:09 mohor |
// Addresses corrected to decimal values (previously hex). |
// |
// Revision 1.7 2003/01/10 17:51:34 mohor |
// Temporary version (backup). |
// |
342,9 → 345,24
/* Acceptance mask register */ |
.acceptance_mask_1(acceptance_mask_1), |
.acceptance_mask_2(acceptance_mask_2), |
.acceptance_mask_3(acceptance_mask_3) |
.acceptance_mask_3(acceptance_mask_3), |
/* End: This section is for EXTENDED mode */ |
|
/* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */ |
.tx_data_0(tx_data_0), |
.tx_data_1(tx_data_1), |
.tx_data_2(tx_data_2), |
.tx_data_3(tx_data_3), |
.tx_data_4(tx_data_4), |
.tx_data_5(tx_data_5), |
.tx_data_6(tx_data_6), |
.tx_data_7(tx_data_7), |
.tx_data_8(tx_data_8), |
.tx_data_9(tx_data_9), |
.tx_data_10(tx_data_10), |
.tx_data_11(tx_data_11), |
.tx_data_12(tx_data_12) |
/* End: Tx data registers */ |
); |
|
|
/trunk/rtl/verilog/can_fifo.v
45,6 → 45,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.5 2003/01/14 17:25:09 mohor |
// Addresses corrected to decimal values (previously hex). |
// |
// Revision 1.4 2003/01/14 12:19:35 mohor |
// rx_fifo is now working. |
// |
71,7 → 74,6
clk, |
rst, |
|
rd, |
wr, |
|
data_in, |
88,7 → 90,6
|
input clk; |
input rst; |
input rd; |
input wr; |
input [7:0] data_in; |
input [7:0] addr; |
/trunk/rtl/verilog/can_bsp.v
45,6 → 45,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.9 2003/01/14 12:19:35 mohor |
// rx_fifo is now working. |
// |
// Revision 1.8 2003/01/10 17:51:33 mohor |
// Temporary version (backup). |
// |
121,9 → 124,25
/* Acceptance mask register */ |
acceptance_mask_1, |
acceptance_mask_2, |
acceptance_mask_3 |
acceptance_mask_3, |
/* End: This section is for EXTENDED mode */ |
|
/* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */ |
tx_data_0, |
tx_data_1, |
tx_data_2, |
tx_data_3, |
tx_data_4, |
tx_data_5, |
tx_data_6, |
tx_data_7, |
tx_data_8, |
tx_data_9, |
tx_data_10, |
tx_data_11, |
tx_data_12 |
/* End: Tx data registers */ |
|
); |
|
parameter Tp = 1; |
168,9 → 187,23
input [7:0] acceptance_mask_1; |
input [7:0] acceptance_mask_2; |
input [7:0] acceptance_mask_3; |
|
/* End: This section is for EXTENDED mode */ |
|
/* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */ |
input [7:0] tx_data_0; |
input [7:0] tx_data_1; |
input [7:0] tx_data_2; |
input [7:0] tx_data_3; |
input [7:0] tx_data_4; |
input [7:0] tx_data_5; |
input [7:0] tx_data_6; |
input [7:0] tx_data_7; |
input [7:0] tx_data_8; |
input [7:0] tx_data_9; |
input [7:0] tx_data_10; |
input [7:0] tx_data_11; |
input [7:0] tx_data_12; |
/* End: Tx data registers */ |
|
|
reg reset_mode_q; |
731,11 → 764,13
wire storing_header; |
wire [3:0] limited_data_len; |
wire reset_wr_fifo; |
wire remote_request; // When remote request comes, no data field is stored to fifo. |
|
assign header_len[2:0] = extended_mode ? (ide? (3'h5) : (3'h3)) : 3'h2; |
assign storing_header = header_cnt < header_len; |
assign limited_data_len[3:0] = (data_len < 8)? (data_len -1'b1) : 4'h7; // - 1 because counter counts from 0 |
assign reset_wr_fifo = data_cnt == limited_data_len + header_len; |
assign remote_request = (extended_mode & rtr2) | ((~extended_mode) & rtr1); // When remote request is active, data length is 0. |
assign limited_data_len[3:0] = remote_request? 4'hf : ((data_len < 8)? (data_len -1'b1) : 4'h7); // - 1 because counter counts from 0 |
assign reset_wr_fifo = data_cnt == (limited_data_len + header_len); |
|
|
// Write enable signal for 64-byte rx fifo |
823,7 → 858,6
.clk(clk), |
.rst(rst), |
|
.rd(1'b0), // FIX ME |
.wr(wr_fifo), |
|
.data_in(data_for_fifo), |
/trunk/rtl/verilog/can_registers.v
45,6 → 45,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.8 2003/01/14 17:25:09 mohor |
// Addresses corrected to decimal values (previously hex). |
// |
// Revision 1.7 2003/01/14 12:19:35 mohor |
// rx_fifo is now working. |
// |
648,15 → 651,15
8'd6 : data_out <= reset_mode? bus_timing_0 : 8'hff; |
8'd7 : data_out <= reset_mode? bus_timing_1 : 8'hff; |
8'd10 : data_out <= reset_mode? 8'hff : tx_data_0; |
8'd11 : data_out <= reset_mode? 8'hff : tx_data_0; |
8'd12 : data_out <= reset_mode? 8'hff : tx_data_0; |
8'd13 : data_out <= reset_mode? 8'hff : tx_data_0; |
8'd14 : data_out <= reset_mode? 8'hff : tx_data_0; |
8'd15 : data_out <= reset_mode? 8'hff : tx_data_0; |
8'd16 : data_out <= reset_mode? 8'hff : tx_data_0; |
8'd17 : data_out <= reset_mode? 8'hff : tx_data_0; |
8'd18 : data_out <= reset_mode? 8'hff : tx_data_0; |
8'd19 : data_out <= reset_mode? 8'hff : tx_data_0; |
8'd11 : data_out <= reset_mode? 8'hff : tx_data_1; |
8'd12 : data_out <= reset_mode? 8'hff : tx_data_2; |
8'd13 : data_out <= reset_mode? 8'hff : tx_data_3; |
8'd14 : data_out <= reset_mode? 8'hff : tx_data_4; |
8'd15 : data_out <= reset_mode? 8'hff : tx_data_5; |
8'd16 : data_out <= reset_mode? 8'hff : tx_data_6; |
8'd17 : data_out <= reset_mode? 8'hff : tx_data_7; |
8'd18 : data_out <= reset_mode? 8'hff : tx_data_8; |
8'd19 : data_out <= reset_mode? 8'hff : tx_data_9; |
8'd31 : data_out <= {clock_divider[7:5], 1'b0, clock_divider[3:0]}; |
|
default: data_out <= 8'h0; |
/trunk/sim/rtl_sim/run/wave.do
116,8 → 116,8
define variable nofullpathfilenames |
include bookmark with filenames |
include scope history without filenames |
define waveform window listpane 5.97 |
define waveform window namepane 13.98 |
define waveform window listpane 9.97 |
define waveform window namepane 13.72 |
define multivalueindication |
define pattern curpos dot |
define pattern cursor1 dot |
201,7 → 201,6
can_testbench.i_can_top.i_can_bsp.i_can_acf.match_df_std \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.match_sf_ext \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.match_sf_std \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.no_data \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.reset_mode \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.rst \ |
can_testbench.i_can_top.i_can_bsp.i_can_acf.rtr1 \ |
300,7 → 299,6
can_testbench.send_frame.stuff_cnt's \ |
can_testbench.send_frame.total_bits's \ |
can_testbench.send_frame.stuff \ |
can_testbench.send_frame.xxx \ |
|
add group \ |
can_bsp \ |
373,10 → 371,8
can_testbench.i_can_top.i_can_bsp.id[28:0]'h \ |
can_testbench.i_can_top.i_can_bsp.id_ok \ |
can_testbench.i_can_top.i_can_bsp.ide \ |
can_testbench.i_can_top.i_can_bsp.no_data \ |
can_testbench.i_can_top.i_can_bsp.reset_mode \ |
can_testbench.i_can_top.i_can_bsp.reset_mode_q \ |
can_testbench.i_can_top.i_can_bsp.reset_wr_fifo_normal_mode \ |
can_testbench.i_can_top.i_can_bsp.resync \ |
can_testbench.i_can_top.i_can_bsp.rst \ |
can_testbench.i_can_top.i_can_bsp.sample_point \ |
398,16 → 394,25
|
add group \ |
can_fifo \ |
can_testbench.i_can_top.i_can_bsp.i_can_fifo.addr[7:0]'h \ |
can_testbench.i_can_top.i_can_bsp.i_can_fifo.clk \ |
can_testbench.i_can_top.i_can_bsp.i_can_fifo.data_in[7:0]'h \ |
can_testbench.i_can_top.i_can_bsp.i_can_fifo.data_out[7:0]'h \ |
can_testbench.i_can_top.i_can_bsp.i_can_fifo.extended_mode \ |
can_testbench.i_can_top.i_can_bsp.i_can_fifo.fifo_cnt[6:0]'h \ |
can_testbench.i_can_top.i_can_bsp.i_can_fifo.fifo_empty \ |
can_testbench.i_can_top.i_can_bsp.i_can_fifo.fifo_full \ |
can_testbench.i_can_top.i_can_bsp.i_can_fifo.latch_overrun \ |
can_testbench.i_can_top.i_can_bsp.i_can_fifo.len_cnt[3:0]'h \ |
can_testbench.i_can_top.i_can_bsp.i_can_fifo.rd \ |
can_testbench.i_can_top.i_can_bsp.i_can_fifo.rd_info_pointer[4:0]'h \ |
can_testbench.i_can_top.i_can_bsp.i_can_fifo.rd_pointer[5:0]'h \ |
can_testbench.i_can_top.i_can_bsp.i_can_fifo.read_address[5:0]'h \ |
can_testbench.i_can_top.i_can_bsp.i_can_fifo.release_buffer \ |
can_testbench.i_can_top.i_can_bsp.i_can_fifo.reset_mode \ |
can_testbench.i_can_top.i_can_bsp.i_can_fifo.rst \ |
can_testbench.i_can_top.i_can_bsp.i_can_fifo.wr \ |
can_testbench.i_can_top.i_can_bsp.i_can_fifo.wr_info_pointer[4:0]'h \ |
can_testbench.i_can_top.i_can_bsp.i_can_fifo.wr_pointer[5:0]'h \ |
can_testbench.i_can_top.i_can_bsp.i_can_fifo.wr_q \ |
can_testbench.i_can_top.i_can_bsp.i_can_fifo.write_length_info \ |
414,6 → 419,7
|
add group \ |
can_registers \ |
can_testbench.i_can_top.i_can_registers.abort_tx \ |
can_testbench.i_can_top.i_can_registers.acceptance_code_0[7:0]'h \ |
can_testbench.i_can_top.i_can_registers.acceptance_code_1[7:0]'h \ |
can_testbench.i_can_top.i_can_registers.acceptance_code_2[7:0]'h \ |
428,26 → 434,44
can_testbench.i_can_top.i_can_registers.bus_timing_0[7:0]'h \ |
can_testbench.i_can_top.i_can_registers.bus_timing_1[7:0]'h \ |
can_testbench.i_can_top.i_can_registers.cd[2:0]'h \ |
can_testbench.i_can_top.i_can_registers.clear_data_overrun \ |
can_testbench.i_can_top.i_can_registers.clk \ |
can_testbench.i_can_top.i_can_registers.clock_divider[7:0]'h \ |
can_testbench.i_can_top.i_can_registers.clock_off \ |
can_testbench.i_can_top.i_can_registers.command[4:0]'h \ |
can_testbench.i_can_top.i_can_registers.command_dummy[2:0]'h \ |
can_testbench.i_can_top.i_can_registers.cs \ |
can_testbench.i_can_top.i_can_registers.data_in[7:0]'h \ |
can_testbench.i_can_top.i_can_registers.data_out[7:0]'h \ |
can_testbench.i_can_top.i_can_registers.extended_mode \ |
can_testbench.i_can_top.i_can_registers.fix_me[7:0]'h \ |
can_testbench.i_can_top.i_can_registers.listen_only_mode \ |
can_testbench.i_can_top.i_can_registers.mode[7:0]'h \ |
can_testbench.i_can_top.i_can_registers.read \ |
can_testbench.i_can_top.i_can_registers.release_buffer \ |
can_testbench.i_can_top.i_can_registers.reset_mode \ |
can_testbench.i_can_top.i_can_registers.rst \ |
can_testbench.i_can_top.i_can_registers.rw \ |
can_testbench.i_can_top.i_can_registers.rx_int_enable \ |
can_testbench.i_can_top.i_can_registers.self_rx_request \ |
can_testbench.i_can_top.i_can_registers.sleep_mode \ |
can_testbench.i_can_top.i_can_registers.sync_jump_width[1:0]'h \ |
can_testbench.i_can_top.i_can_registers.time_segment1[3:0]'h \ |
can_testbench.i_can_top.i_can_registers.time_segment2[2:0]'h \ |
can_testbench.i_can_top.i_can_registers.triple_sampling \ |
can_testbench.i_can_top.i_can_registers.tx_data_0[7:0]'h \ |
can_testbench.i_can_top.i_can_registers.tx_data_1[7:0]'h \ |
can_testbench.i_can_top.i_can_registers.tx_data_2[7:0]'h \ |
can_testbench.i_can_top.i_can_registers.tx_data_3[7:0]'h \ |
can_testbench.i_can_top.i_can_registers.tx_data_4[7:0]'h \ |
can_testbench.i_can_top.i_can_registers.tx_data_5[7:0]'h \ |
can_testbench.i_can_top.i_can_registers.tx_data_6[7:0]'h \ |
can_testbench.i_can_top.i_can_registers.tx_data_7[7:0]'h \ |
can_testbench.i_can_top.i_can_registers.tx_data_8[7:0]'h \ |
can_testbench.i_can_top.i_can_registers.tx_data_9[7:0]'h \ |
can_testbench.i_can_top.i_can_registers.tx_data_10[7:0]'h \ |
can_testbench.i_can_top.i_can_registers.tx_data_11[7:0]'h \ |
can_testbench.i_can_top.i_can_registers.tx_data_12[7:0]'h \ |
can_testbench.i_can_top.i_can_registers.tx_request \ |
can_testbench.i_can_top.i_can_registers.we_acceptance_code_0 \ |
can_testbench.i_can_top.i_can_registers.we_acceptance_code_1 \ |
can_testbench.i_can_top.i_can_registers.we_acceptance_code_2 \ |
460,9 → 484,23
can_testbench.i_can_top.i_can_registers.we_bus_timing_1 \ |
can_testbench.i_can_top.i_can_registers.we_clock_divider_hi \ |
can_testbench.i_can_top.i_can_registers.we_clock_divider_low \ |
can_testbench.i_can_top.i_can_registers.we_command \ |
can_testbench.i_can_top.i_can_registers.we_mode \ |
can_testbench.i_can_top.i_can_registers.we_tx_data_0 \ |
can_testbench.i_can_top.i_can_registers.we_tx_data_1 \ |
can_testbench.i_can_top.i_can_registers.we_tx_data_2 \ |
can_testbench.i_can_top.i_can_registers.we_tx_data_3 \ |
can_testbench.i_can_top.i_can_registers.we_tx_data_4 \ |
can_testbench.i_can_top.i_can_registers.we_tx_data_5 \ |
can_testbench.i_can_top.i_can_registers.we_tx_data_6 \ |
can_testbench.i_can_top.i_can_registers.we_tx_data_7 \ |
can_testbench.i_can_top.i_can_registers.we_tx_data_8 \ |
can_testbench.i_can_top.i_can_registers.we_tx_data_9 \ |
can_testbench.i_can_top.i_can_registers.we_tx_data_10 \ |
can_testbench.i_can_top.i_can_registers.we_tx_data_11 \ |
can_testbench.i_can_top.i_can_registers.we_tx_data_12 \ |
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deselect all |
open window waveform 1 geometry 10 59 1592 1140 |
zoom at 109181(0)ns 0.00016079 0.00000000 |
zoom at 51528.58(0)ns 0.00473837 0.00000000 |