URL
https://opencores.org/ocsvn/ha1588/ha1588/trunk
Subversion Repositories ha1588
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/
- from Rev 17 to Rev 18
- ↔ Reverse comparison
Rev 17 → Rev 18
/ha1588/trunk/rtl/top/top.v
File deleted
/ha1588/trunk/rtl/top/ha1588.v
0,0 → 1,122
`timescale 1ns/1ns |
|
module ha1588 ( |
input rst,clk, |
input wr_in,rd_in, |
input [ 5:0] addr_in, |
input [31:0] data_in, |
output [31:0] data_out, |
|
input rtc_clk, |
|
input rx_gmii_clk, |
input rx_gmii_ctrl, |
input [7:0] rx_gmii_data, |
input tx_gmii_clk, |
input tx_gmii_ctrl, |
input [7:0] tx_gmii_data |
); |
|
wire rtc_rst; |
wire rtc_time_ld, rtc_period_ld, rtc_adj_ld; |
wire [37:0] rtc_time_reg_ns; |
wire [47:0] rtc_time_reg_sec; |
wire [39:0] rtc_period; |
wire [37:0] rtc_time_acc_modulo; |
wire [31:0] rtc_adj_ld_data; |
wire [39:0] rtc_period_adj; |
wire [37:0] rtc_time_reg_ns_val; |
wire [47:0] rtc_time_reg_sec_val; |
wire [31:0] rtc_time_reg_val = {rtc_time_reg_sec_val[1:0],rtc_time_reg_ns_val[37:8]}; // 4.000000000 sec |
|
wire rx_q_rst, rx_q_clk; |
wire rx_q_rd_en; |
wire [ 7:0] rx_q_stat; |
wire [55:0] rx_q_data; |
wire tx_q_rst, tx_q_clk; |
wire tx_q_rd_en; |
wire [ 7:0] tx_q_stat; |
wire [55:0] tx_q_data; |
|
rgs u_rgs |
( |
.rst(rst), |
.clk(clk), |
.wr_in(wr_in), |
.rd_in(rd_in), |
.addr_in(addr_in), |
.data_in(data_in), |
.data_out(data_out), |
.rtc_clk_in(rtc_clk), |
.rtc_rst_out(rtc_rst), |
.time_ld_out(rtc_time_ld), |
.time_reg_ns_out(rtc_time_reg_ns), |
.time_reg_sec_out(rtc_time_reg_sec), |
.period_ld_out(rtc_period_ld), |
.period_out(rtc_period), |
.time_acc_modulo_out(rtc_time_acc_modulo), |
.adj_ld_out(rtc_adj_ld), |
.adj_ld_data_out(rtc_adj_ld_data), |
.period_adj_out(rtc_period_adj), |
.time_reg_ns_in(rtc_time_reg_ns_val), |
.time_reg_sec_in(rtc_time_reg_sec_val), |
.rx_q_rst_out(rx_q_rst), |
.rx_q_rd_clk_out(rx_q_clk), |
.rx_q_rd_en_out(rx_q_rd_en), |
.rx_q_stat_in(rx_q_stat), |
.rx_q_data_in(rx_q_data), |
.tx_q_rst_out(tx_q_rst), |
.tx_q_rd_clk_out(tx_q_clk), |
.tx_q_rd_en_out(tx_q_rd_en), |
.tx_q_stat_in(tx_q_stat), |
.tx_q_data_in(tx_q_data) |
); |
|
rtc u_rtc |
( |
.rst(rtc_rst), |
.clk(rtc_clk), |
.time_ld(rtc_time_ld), |
.time_reg_ns_in(rtc_time_reg_ns), |
.time_reg_sec_in(rtc_time_reg_sec), |
.period_ld(rtc_period_ld), |
.period_in(rtc_period), |
.time_acc_modulo(rtc_time_acc_modulo), |
.adj_ld(rtc_adj_ld), |
.adj_ld_data(rtc_adj_ld_data), |
.period_adj(rtc_period_adj), |
.time_reg_ns(rtc_time_reg_ns_val), |
.time_reg_sec(rtc_time_reg_sec_val) |
); |
|
tsu u_rx_tsu |
( |
.rst(rst), |
.gmii_clk(rx_gmii_clk), |
.gmii_ctrl(rx_gmii_ctrl), |
.gmii_data(rx_gmii_data), |
.rtc_timer_clk(rtc_clk), |
.rtc_timer_in(rtc_time_reg_val), |
.q_rst(rx_q_rst), |
.q_rd_clk(rx_q_clk), |
.q_rd_en(rx_q_rd_en), |
.q_rd_stat(rx_q_stat), |
.q_rd_data(rx_q_data) |
); |
|
tsu u_tx_tsu |
( |
.rst(rst), |
.gmii_clk(tx_gmii_clk), |
.gmii_ctrl(tx_gmii_ctrl), |
.gmii_data(tx_gmii_data), |
.rtc_timer_clk(rtc_clk), |
.rtc_timer_in(rtc_time_reg_val), |
.q_rst(tx_q_rst), |
.q_rd_clk(tx_q_clk), |
.q_rd_en(tx_q_rd_en), |
.q_rd_stat(tx_q_stat), |
.q_rd_data(tx_q_data) |
); |
|
endmodule |
/ha1588/trunk/rtl/tsu/tsu.v
8,13 → 8,13
input [7:0] gmii_data, |
|
input rtc_timer_clk, |
input [31:0] rtc_timer_in, |
input [31:0] rtc_timer_in, // timeStamp1s_2bit + timeStamp1ns_30bit |
|
input q_rst, |
input q_rd_clk, |
input q_rd_en, |
output [ 7:0] q_rd_stat, |
output [55:0] q_rd_data |
output [55:0] q_rd_data // null_4bit + seqId_16bit + msgId_4bit + timeStamp1s_2bit + timeStamp1ns_30bit |
); |
|
// buffer gmii input |
/ha1588/trunk/rtl/reg/reg.v
21,34 → 21,44
output [39:0] period_adj_out, |
input [37:0] time_reg_ns_in, |
input [47:0] time_reg_sec_in, |
// tsu interface |
output q_rst_out, |
output q_rd_clk_out, |
output q_rd_en_out, |
input [ 7:0] q_stat_in, |
input [55:0] q_data_in |
// rx tsu interface |
output rx_q_rst_out, |
output rx_q_rd_clk_out, |
output rx_q_rd_en_out, |
input [ 7:0] rx_q_stat_in, |
input [55:0] rx_q_data_in, |
// tx tsu interface |
output tx_q_rst_out, |
output tx_q_rd_clk_out, |
output tx_q_rd_en_out, |
input [ 7:0] tx_q_stat_in, |
input [55:0] tx_q_data_in |
); |
|
parameter const_00 = 8'h00; |
parameter const_04 = 8'h04; |
parameter const_08 = 8'h08; |
parameter const_0C = 8'h0C; |
parameter const_0c = 8'h0C; |
parameter const_10 = 8'h10; |
parameter const_14 = 8'h14; |
parameter const_18 = 8'h18; |
parameter const_1C = 8'h1C; |
parameter const_1c = 8'h1C; |
parameter const_20 = 8'h20; |
parameter const_24 = 8'h24; |
parameter const_28 = 8'h28; |
parameter const_2C = 8'h2C; |
parameter const_2c = 8'h2C; |
parameter const_30 = 8'h30; |
parameter const_34 = 8'h34; |
parameter const_38 = 8'h38; |
parameter const_3C = 8'h3C; |
parameter const_3c = 8'h3C; |
parameter const_40 = 8'h40; |
parameter const_44 = 8'h44; |
parameter const_48 = 8'h48; |
parameter const_4C = 8'h4C; |
parameter const_4c = 8'h4C; |
parameter const_50 = 8'h50; |
parameter const_54 = 8'h54; |
parameter const_58 = 8'h58; |
parameter const_5c = 8'h5C; |
|
wire cs_00 = (addr_in[5:0]==const_00[5:0])? 1'b1: 1'b0; |
wire cs_04 = (addr_in[5:0]==const_04[5:0])? 1'b1: 1'b0; |
70,11 → 80,15
wire cs_44 = (addr_in[5:0]==const_44[5:0])? 1'b1: 1'b0; |
wire cs_48 = (addr_in[5:0]==const_48[5:0])? 1'b1: 1'b0; |
wire cs_4c = (addr_in[5:0]==const_4c[5:0])? 1'b1: 1'b0; |
wire cs_50 = (addr_in[5:0]==const_50[5:0])? 1'b1: 1'b0; |
wire cs_54 = (addr_in[5:0]==const_54[5:0])? 1'b1: 1'b0; |
wire cs_58 = (addr_in[5:0]==const_58[5:0])? 1'b1: 1'b0; |
wire cs_5c = (addr_in[5:0]==const_5c[5:0])? 1'b1: 1'b0; |
|
reg [31:0] reg_00; // ctrl 8 bit |
reg [31:0] reg_04; // stat 8 bit |
reg [31:0] reg_08; // queu 24 bit |
reg [31:0] reg_0c; // queu 32 bit |
reg [31:0] reg_00; // ctrl 12 bit |
reg [31:0] reg_04; // qsta 16 bit |
reg [31:0] reg_08; // |
reg [31:0] reg_0c; // |
reg [31:0] reg_10; // tout 16 s |
reg [31:0] reg_14; // tout 32 s |
reg [31:0] reg_18; // tout 30 ns |
91,6 → 105,10
reg [31:0] reg_44; // tmin 32 s |
reg [31:0] reg_48; // tmin 30 ns |
reg [31:0] reg_4c; // tmin 8 nsf |
reg [31:0] reg_50; // rxqu 24 bit |
reg [31:0] reg_54; // rxqu 32 bit |
reg [31:0] reg_58; // txqu 24 bit |
reg [31:0] reg_5c; // txqu 32 bit |
|
// write registers |
always @(posedge clk) begin |
114,48 → 132,62
if (wr_in && cs_44) reg_44 <= data_in; |
if (wr_in && cs_48) reg_48 <= data_in; |
if (wr_in && cs_4c) reg_4c <= data_in; |
if (wr_in && cs_50) reg_50 <= data_in; |
if (wr_in && cs_54) reg_54 <= data_in; |
if (wr_in && cs_58) reg_58 <= data_in; |
if (wr_in && cs_5c) reg_5c <= data_in; |
end |
|
// read registers |
reg [37:0] time_reg_ns_int; |
reg [47:0] time_reg_sec_int; |
reg [55:0] q_data_int; |
reg [ 7:0] q_stat_int; |
reg [55:0] rx_q_data_int; |
reg [ 7:0] rx_q_stat_int; |
reg [55:0] tx_q_data_int; |
reg [ 7:0] tx_q_stat_int; |
|
reg [31:0] data_out_reg; |
always @(posedge clk) begin |
if (cs_00) data_out_reg <= reg_00; |
if (cs_04) data_out_reg <= {24'd0, q_stat_int[ 7: 0]}; |
if (cs_08) data_out_reg <= { 8'd0, q_data_int[55:32]}; |
if (cs_0c) data_out_reg <= q_data_int[31: 0]; |
if (cs_10) data_out_reg <= reg_10; |
if (cs_14) data_out_reg <= reg_14; |
if (cs_18) data_out_reg <= reg_18; |
if (cs_1c) data_out_reg <= reg_1c; |
if (cs_20) data_out_reg <= reg_20; |
if (cs_24) data_out_reg <= reg_24; |
if (cs_28) data_out_reg <= reg_28; |
if (cs_2c) data_out_reg <= reg_2c; |
if (cs_30) data_out_reg <= reg_30; |
if (cs_34) data_out_reg <= reg_34; |
if (cs_38) data_out_reg <= reg_38; |
if (cs_3c) data_out_reg <= reg_3c; |
if (cs_40) data_out_reg <= {16'd0, time_reg_sec_int[47:32]); |
if (cs_44) data_out_reg <= time_reg_sec_int[31: 0]; |
if (cs_48) data_out_reg <= { 2'd0, time_reg_ns_int [37: 8]}; |
if (cs_4c) data_out_reg <= {24'd0, time_reg_ns_int [ 7: 0]}; |
if (rd_in && cs_00) data_out_reg <= reg_00; |
if (rd_in && cs_04) data_out_reg <= {8'd0, rx_q_stat_int[ 7: 0], 8'd0, tx_q_stat_int[ 7: 0]}; |
if (rd_in && cs_08) data_out_reg <= reg_08; |
if (rd_in && cs_0c) data_out_reg <= reg_0c; |
if (rd_in && cs_10) data_out_reg <= reg_10; |
if (rd_in && cs_14) data_out_reg <= reg_14; |
if (rd_in && cs_18) data_out_reg <= reg_18; |
if (rd_in && cs_1c) data_out_reg <= reg_1c; |
if (rd_in && cs_20) data_out_reg <= reg_20; |
if (rd_in && cs_24) data_out_reg <= reg_24; |
if (rd_in && cs_28) data_out_reg <= reg_28; |
if (rd_in && cs_2c) data_out_reg <= reg_2c; |
if (rd_in && cs_30) data_out_reg <= reg_30; |
if (rd_in && cs_34) data_out_reg <= reg_34; |
if (rd_in && cs_38) data_out_reg <= reg_38; |
if (rd_in && cs_3c) data_out_reg <= reg_3c; |
if (rd_in && cs_40) data_out_reg <= {16'd0, time_reg_sec_int[47:32]}; |
if (rd_in && cs_44) data_out_reg <= time_reg_sec_int[31: 0]; |
if (rd_in && cs_48) data_out_reg <= { 2'd0, time_reg_ns_int [37: 8]}; |
if (rd_in && cs_4c) data_out_reg <= {24'd0, time_reg_ns_int [ 7: 0]}; |
if (rd_in && cs_50) data_out_reg <= { 8'd0, rx_q_data_int[55:32]}; |
if (rd_in && cs_54) data_out_reg <= rx_q_data_int[31: 0]; |
if (rd_in && cs_58) data_out_reg <= { 8'd0, tx_q_data_int[55:32]}; |
if (rd_in && cs_5c) data_out_reg <= tx_q_data_int[31: 0]; |
end |
assign data_out = data_out_reg; |
|
// register mapping |
wire rtc_rst = reg_00[7]; |
wire que_rst = reg_00[6]; |
wire time_ld = reg_00[5]; |
wire perd_ld = reg_00[4]; |
wire adjt_ld = reg_00[3]; |
wire time_rd = reg_00[2]; |
wire queu_rd = reg_00[1]; |
//wire = reg_00[0]; |
wire rxq_rst = reg_00[11]; |
wire rxqu_rd = reg_00[10]; |
wire txq_rst = reg_00[ 9]; |
wire txqu_rd = reg_00[ 8]; |
//wire = reg_00[ 7]; |
//wire = reg_00[ 6]; |
//wire = reg_00[ 5]; |
wire rtc_rst = reg_00[ 4]; |
wire time_ld = reg_00[ 3]; |
wire perd_ld = reg_00[ 2]; |
wire adjt_ld = reg_00[ 1]; |
wire time_rd = reg_00[ 0]; |
assign time_reg_sec_out [47:0] = {reg_10[15: 0], reg_14[31: 0]}; |
assign time_reg_ns_out [37:0] = {reg_18[29: 0], reg_1c[ 7: 0]}; |
assign period_out [39:0] = {reg_20[ 7: 0], reg_24[31: 0]}; |
211,28 → 243,52
end |
end |
|
// time stamp queue |
assign q_rd_clk_out = clk; |
// rx time stamp queue |
assign rx_q_rd_clk_out = clk; |
|
reg que_rst_d1, que_rst_d2, que_rst_d3; |
assign q_rst_out = que_rst_d2 && !que_rst_d3; |
reg rxq_rst_d1, rxq_rst_d2, rxq_rst_d3; |
assign rx_q_rst_out = rxq_rst_d2 && !rxq_rst_d3; |
always @(posedge clk) begin |
que_rst_d1 <= que_rst; |
que_rst_d2 <= que_rst_d1; |
que_rst_d3 <= que_rst_d2; |
rxq_rst_d1 <= rxq_rst; |
rxq_rst_d2 <= rxq_rst_d1; |
rxq_rst_d3 <= rxq_rst_d2; |
end |
|
reg queu_rd_d1, queu_rd_d2, queu_rd_d3; |
assign q_rd_en_out = queu_rd_d2 && !queu_rd_d3; |
reg rxqu_rd_d1, rxqu_rd_d2, rxqu_rd_d3; |
assign rx_q_rd_en_out = rxqu_rd_d2 && !rxqu_rd_d3; |
always @(posedge clk) begin |
queu_rd_d1 <= queu_rd; |
queu_rd_d2 <= queu_rd_d1; |
queu_rd_d3 <= queu_rd_d2; |
rxqu_rd_d1 <= rxqu_rd; |
rxqu_rd_d2 <= rxqu_rd_d1; |
rxqu_rd_d3 <= rxqu_rd_d2; |
end |
|
always @(posedge clk) begin |
q_data_int <= q_data_in; |
q_stat_int <= q_stat_in; |
rx_q_data_int <= rx_q_data_in; |
rx_q_stat_int <= rx_q_stat_in; |
end |
|
// tx time stamp queue |
assign tx_q_rd_clk_out = clk; |
|
reg txq_rst_d1, txq_rst_d2, txq_rst_d3; |
assign tx_q_rst_out = txq_rst_d2 && !txq_rst_d3; |
always @(posedge clk) begin |
txq_rst_d1 <= txq_rst; |
txq_rst_d2 <= txq_rst_d1; |
txq_rst_d3 <= txq_rst_d2; |
end |
|
reg txqu_rd_d1, txqu_rd_d2, txqu_rd_d3; |
assign tx_q_rd_en_out = txqu_rd_d2 && !txqu_rd_d3; |
always @(posedge clk) begin |
txqu_rd_d1 <= txqu_rd; |
txqu_rd_d2 <= txqu_rd_d1; |
txqu_rd_d3 <= txqu_rd_d2; |
end |
|
always @(posedge clk) begin |
tx_q_data_int <= tx_q_data_in; |
tx_q_stat_int <= tx_q_stat_in; |
end |
|
endmodule |
/ha1588/trunk/par/altera/ha1588.qpf
0,0 → 1,30
# -------------------------------------------------------------------------- # |
# |
# Copyright (C) 1991-2011 Altera Corporation |
# Your use of Altera Corporation's design tools, logic functions |
# and other software and tools, and its AMPP partner logic |
# functions, and any output files from any of the foregoing |
# (including device programming or simulation files), and any |
# associated documentation or information are expressly subject |
# to the terms and conditions of the Altera Program License |
# Subscription Agreement, Altera MegaCore Function License |
# Agreement, or other applicable license agreement, including, |
# without limitation, that your use is for the sole purpose of |
# programming logic devices manufactured by Altera and sold by |
# Altera or its authorized distributors. Please refer to the |
# applicable agreement for further details. |
# |
# -------------------------------------------------------------------------- # |
# |
# Quartus II |
# Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Full Version |
# Date created = 14:35:47 March 31, 2012 |
# |
# -------------------------------------------------------------------------- # |
|
QUARTUS_VERSION = "10.1" |
DATE = "14:35:47 March 31, 2012" |
|
# Revisions |
|
PROJECT_REVISION = "ha1588" |
/ha1588/trunk/par/altera/ha1588.qsf
0,0 → 1,63
# -------------------------------------------------------------------------- # |
# |
# Copyright (C) 1991-2011 Altera Corporation |
# Your use of Altera Corporation's design tools, logic functions |
# and other software and tools, and its AMPP partner logic |
# functions, and any output files from any of the foregoing |
# (including device programming or simulation files), and any |
# associated documentation or information are expressly subject |
# to the terms and conditions of the Altera Program License |
# Subscription Agreement, Altera MegaCore Function License |
# Agreement, or other applicable license agreement, including, |
# without limitation, that your use is for the sole purpose of |
# programming logic devices manufactured by Altera and sold by |
# Altera or its authorized distributors. Please refer to the |
# applicable agreement for further details. |
# |
# -------------------------------------------------------------------------- # |
# |
# Quartus II |
# Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Full Version |
# Date created = 14:35:47 March 31, 2012 |
# |
# -------------------------------------------------------------------------- # |
# |
# Notes: |
# |
# 1) The default values for assignments are stored in the file: |
# ha1588_assignment_defaults.qdf |
# If this file doesn't exist, see file: |
# assignment_defaults.qdf |
# |
# 2) Altera recommends that you do not modify this file. This |
# file is updated automatically by the Quartus II software |
# and any changes you make may be lost or overwritten. |
# |
# -------------------------------------------------------------------------- # |
|
|
set_global_assignment -name FAMILY "Cyclone III" |
set_global_assignment -name DEVICE AUTO |
set_global_assignment -name TOP_LEVEL_ENTITY ha1588 |
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "10.1 SP1" |
set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:35:47 MARCH 31, 2012" |
set_global_assignment -name LAST_QUARTUS_VERSION "10.1 SP1" |
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top |
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top |
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top |
set_global_assignment -name SMART_RECOMPILE ON |
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output |
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" |
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON |
set_global_assignment -name FITTER_EFFORT "STANDARD FIT" |
set_global_assignment -name SDC_FILE ha1588.sdc |
set_global_assignment -name VERILOG_FILE ../../rtl/top/ha1588.v |
set_global_assignment -name VERILOG_FILE ../../rtl/rtc/rtc.v |
set_global_assignment -name VERILOG_FILE ../../rtl/reg/reg.v |
set_global_assignment -name VERILOG_FILE ../../rtl/tsu/tsu.v |
set_global_assignment -name VERILOG_FILE ../../rtl/tsu/ptp_queue.v |
set_global_assignment -name VERILOG_FILE ../../rtl/tsu/ptp_parser.v |
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON |
set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO |
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON |
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top |
/ha1588/trunk/par/altera/ha1588.sdc
0,0 → 1,171
## Generated SDC file "ha1588.sdc" |
|
## Copyright (C) 1991-2011 Altera Corporation |
## Your use of Altera Corporation's design tools, logic functions |
## and other software and tools, and its AMPP partner logic |
## functions, and any output files from any of the foregoing |
## (including device programming or simulation files), and any |
## associated documentation or information are expressly subject |
## to the terms and conditions of the Altera Program License |
## Subscription Agreement, Altera MegaCore Function License |
## Agreement, or other applicable license agreement, including, |
## without limitation, that your use is for the sole purpose of |
## programming logic devices manufactured by Altera and sold by |
## Altera or its authorized distributors. Please refer to the |
## applicable agreement for further details. |
|
|
## VENDOR "Altera" |
## PROGRAM "Quartus II" |
## VERSION "Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Full Version" |
|
## DATE "Sat Mar 31 15:03:15 2012" |
|
## |
## DEVICE "EP3C5F256C6" |
## |
|
|
#************************************************************** |
# Time Information |
#************************************************************** |
|
set_time_format -unit ns -decimal_places 3 |
|
|
|
#************************************************************** |
# Create Clock |
#************************************************************** |
|
create_clock -name {clk} -period 10.000 -waveform { 0.000 5.000 } [get_ports {clk}] |
create_clock -name {rtc_clk} -period 8.000 -waveform { 0.000 4.000 } [get_ports {rtc_clk}] |
create_clock -name {tx_gmii_clk} -period 8.000 -waveform { 0.000 4.000 } [get_ports {tx_gmii_clk}] |
create_clock -name {rx_gmii_clk} -period 8.000 -waveform { 0.000 4.000 } [get_ports {rx_gmii_clk}] |
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#************************************************************** |
# Create Generated Clock |
#************************************************************** |
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#************************************************************** |
# Set Clock Latency |
#************************************************************** |
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#************************************************************** |
# Set Clock Uncertainty |
#************************************************************** |
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set_clock_uncertainty -rise_from [get_clocks {clk}] -rise_to [get_clocks {clk}] 0.020 |
set_clock_uncertainty -rise_from [get_clocks {clk}] -fall_to [get_clocks {clk}] 0.020 |
set_clock_uncertainty -rise_from [get_clocks {clk}] -rise_to [get_clocks {rtc_clk}] 0.040 |
set_clock_uncertainty -rise_from [get_clocks {clk}] -fall_to [get_clocks {rtc_clk}] 0.040 |
set_clock_uncertainty -rise_from [get_clocks {clk}] -rise_to [get_clocks {rx_gmii_clk}] 0.040 |
set_clock_uncertainty -rise_from [get_clocks {clk}] -fall_to [get_clocks {rx_gmii_clk}] 0.040 |
set_clock_uncertainty -rise_from [get_clocks {clk}] -rise_to [get_clocks {tx_gmii_clk}] 0.040 |
set_clock_uncertainty -rise_from [get_clocks {clk}] -fall_to [get_clocks {tx_gmii_clk}] 0.040 |
set_clock_uncertainty -fall_from [get_clocks {clk}] -rise_to [get_clocks {clk}] 0.020 |
set_clock_uncertainty -fall_from [get_clocks {clk}] -fall_to [get_clocks {clk}] 0.020 |
set_clock_uncertainty -fall_from [get_clocks {clk}] -rise_to [get_clocks {rtc_clk}] 0.040 |
set_clock_uncertainty -fall_from [get_clocks {clk}] -fall_to [get_clocks {rtc_clk}] 0.040 |
set_clock_uncertainty -fall_from [get_clocks {clk}] -rise_to [get_clocks {rx_gmii_clk}] 0.040 |
set_clock_uncertainty -fall_from [get_clocks {clk}] -fall_to [get_clocks {rx_gmii_clk}] 0.040 |
set_clock_uncertainty -fall_from [get_clocks {clk}] -rise_to [get_clocks {tx_gmii_clk}] 0.040 |
set_clock_uncertainty -fall_from [get_clocks {clk}] -fall_to [get_clocks {tx_gmii_clk}] 0.040 |
set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -rise_to [get_clocks {clk}] 0.040 |
set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -fall_to [get_clocks {clk}] 0.040 |
set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -rise_to [get_clocks {rtc_clk}] 0.020 |
set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -fall_to [get_clocks {rtc_clk}] 0.020 |
set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -rise_to [get_clocks {rx_gmii_clk}] 0.040 |
set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -fall_to [get_clocks {rx_gmii_clk}] 0.040 |
set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -rise_to [get_clocks {tx_gmii_clk}] 0.040 |
set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -fall_to [get_clocks {tx_gmii_clk}] 0.040 |
set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -rise_to [get_clocks {clk}] 0.040 |
set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -fall_to [get_clocks {clk}] 0.040 |
set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -rise_to [get_clocks {rtc_clk}] 0.020 |
set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -fall_to [get_clocks {rtc_clk}] 0.020 |
set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -rise_to [get_clocks {rx_gmii_clk}] 0.040 |
set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -fall_to [get_clocks {rx_gmii_clk}] 0.040 |
set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -rise_to [get_clocks {tx_gmii_clk}] 0.040 |
set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -fall_to [get_clocks {tx_gmii_clk}] 0.040 |
set_clock_uncertainty -rise_from [get_clocks {rx_gmii_clk}] -rise_to [get_clocks {clk}] 0.040 |
set_clock_uncertainty -rise_from [get_clocks {rx_gmii_clk}] -fall_to [get_clocks {clk}] 0.040 |
set_clock_uncertainty -rise_from [get_clocks {rx_gmii_clk}] -rise_to [get_clocks {rtc_clk}] 0.040 |
set_clock_uncertainty -rise_from [get_clocks {rx_gmii_clk}] -fall_to [get_clocks {rtc_clk}] 0.040 |
set_clock_uncertainty -rise_from [get_clocks {rx_gmii_clk}] -rise_to [get_clocks {rx_gmii_clk}] 0.020 |
set_clock_uncertainty -rise_from [get_clocks {rx_gmii_clk}] -fall_to [get_clocks {rx_gmii_clk}] 0.020 |
set_clock_uncertainty -fall_from [get_clocks {rx_gmii_clk}] -rise_to [get_clocks {clk}] 0.040 |
set_clock_uncertainty -fall_from [get_clocks {rx_gmii_clk}] -fall_to [get_clocks {clk}] 0.040 |
set_clock_uncertainty -fall_from [get_clocks {rx_gmii_clk}] -rise_to [get_clocks {rtc_clk}] 0.040 |
set_clock_uncertainty -fall_from [get_clocks {rx_gmii_clk}] -fall_to [get_clocks {rtc_clk}] 0.040 |
set_clock_uncertainty -fall_from [get_clocks {rx_gmii_clk}] -rise_to [get_clocks {rx_gmii_clk}] 0.020 |
set_clock_uncertainty -fall_from [get_clocks {rx_gmii_clk}] -fall_to [get_clocks {rx_gmii_clk}] 0.020 |
set_clock_uncertainty -rise_from [get_clocks {tx_gmii_clk}] -rise_to [get_clocks {clk}] 0.040 |
set_clock_uncertainty -rise_from [get_clocks {tx_gmii_clk}] -fall_to [get_clocks {clk}] 0.040 |
set_clock_uncertainty -rise_from [get_clocks {tx_gmii_clk}] -rise_to [get_clocks {rtc_clk}] 0.040 |
set_clock_uncertainty -rise_from [get_clocks {tx_gmii_clk}] -fall_to [get_clocks {rtc_clk}] 0.040 |
set_clock_uncertainty -rise_from [get_clocks {tx_gmii_clk}] -rise_to [get_clocks {tx_gmii_clk}] 0.020 |
set_clock_uncertainty -rise_from [get_clocks {tx_gmii_clk}] -fall_to [get_clocks {tx_gmii_clk}] 0.020 |
set_clock_uncertainty -fall_from [get_clocks {tx_gmii_clk}] -rise_to [get_clocks {clk}] 0.040 |
set_clock_uncertainty -fall_from [get_clocks {tx_gmii_clk}] -fall_to [get_clocks {clk}] 0.040 |
set_clock_uncertainty -fall_from [get_clocks {tx_gmii_clk}] -rise_to [get_clocks {rtc_clk}] 0.040 |
set_clock_uncertainty -fall_from [get_clocks {tx_gmii_clk}] -fall_to [get_clocks {rtc_clk}] 0.040 |
set_clock_uncertainty -fall_from [get_clocks {tx_gmii_clk}] -rise_to [get_clocks {tx_gmii_clk}] 0.020 |
set_clock_uncertainty -fall_from [get_clocks {tx_gmii_clk}] -fall_to [get_clocks {tx_gmii_clk}] 0.020 |
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#************************************************************** |
# Set Input Delay |
#************************************************************** |
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#************************************************************** |
# Set Output Delay |
#************************************************************** |
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#************************************************************** |
# Set Clock Groups |
#************************************************************** |
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set_clock_groups -exclusive -group [get_clocks {clk}] \ |
-group [get_clocks {rtc_clk}] \ |
-group [get_clocks {rx_gmii_clk}] \ |
-group [get_clocks {tx_gmii_clk}] |
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#************************************************************** |
# Set False Path |
#************************************************************** |
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set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_gd9:dffpipe18|dffe19a*}] |
set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_fd9:dffpipe15|dffe16a*}] |
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#************************************************************** |
# Set Multicycle Path |
#************************************************************** |
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#************************************************************** |
# Set Maximum Delay |
#************************************************************** |
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#************************************************************** |
# Set Minimum Delay |
#************************************************************** |
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#************************************************************** |
# Set Input Transition |
#************************************************************** |
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