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https://opencores.org/ocsvn/mem_ctrl/mem_ctrl/trunk
Subversion Repositories mem_ctrl
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- from Rev 17 to Rev 18
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Rev 17 → Rev 18
/trunk/rtl/verilog/mc_cs_rf.v
37,10 → 37,10
|
// CVS Log |
// |
// $Id: mc_cs_rf.v,v 1.4 2001-11-29 02:16:28 rudi Exp $ |
// $Id: mc_cs_rf.v,v 1.5 2001-12-11 02:47:19 rudi Exp $ |
// |
// $Date: 2001-11-29 02:16:28 $ |
// $Revision: 1.4 $ |
// $Date: 2001-12-11 02:47:19 $ |
// $Revision: 1.5 $ |
// $Author: rudi $ |
// $Locker: $ |
// $State: Exp $ |
47,6 → 47,15
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.4 2001/11/29 02:16:28 rudi |
// |
// |
// - More Synthesis cleanup, mostly for speed |
// - Several bug fixes |
// - Changed code to avoid auto-precharge and |
// burst-terminate combinations (apparently illegal ?) |
// Now we will do a manual precharge ... |
// |
// Revision 1.3 2001/09/24 00:38:21 rudi |
// |
// Changed Reset to be active high and async. |
134,6 → 143,21
|
//////////////////////////////////////////////////////////////////// |
// |
// A kludge for cases where there is no clock during reset ... |
// |
|
reg rst_r1, rst_r2; |
|
always @(posedge clk or posedge rst) |
if(rst) rst_r1 <= #1 1'b1; |
else rst_r1 <= #1 1'b0; |
|
always @(posedge clk or posedge rst) |
if(rst) rst_r2 <= #1 1'b1; |
else rst_r2 <= #1 rst_r1; |
|
//////////////////////////////////////////////////////////////////// |
// |
// Write Logic |
// |
|
145,13 → 169,13
assign sel = addr_r[6:3] == reg_select[3:0]; |
|
always @(posedge clk) |
if(rst) csc <= #1 (this_cs[2:0] == `MC_DEF_SEL) ? |
{26'h0, poc[1:0], 1'b0, poc[3:2], (poc[3:2] != 2'b00)} : 32'h0; |
if(rst_r2) csc <= #1 (this_cs[2:0] == `MC_DEF_SEL) ? |
{26'h0, poc[1:0], 1'b0, poc[3:2], (poc[3:2] != 2'b00)} : 32'h0; |
else |
if(rf_we & sel & !addr_r[2]) csc <= #1 din; |
|
always @(posedge clk) |
if(rst) tms <= #1 (this_cs[2:0] == `MC_DEF_SEL) ? |
if(rst_r2) tms <= #1 (this_cs[2:0] == `MC_DEF_SEL) ? |
`MC_DEF_POR_TMS : 32'h0; |
else |
if(rf_we & sel & addr_r[2]) tms <= #1 din; |
160,8 → 184,9
// |
// Load Mode Register Request/Ack Logic |
// |
always @(posedge clk) |
lmr_req_we <= #1 rf_we & sel & addr_r[2]; |
always @(posedge clk or posedge rst) |
if(rst) lmr_req_we <= #1 1'b0; |
else lmr_req_we <= #1 rf_we & sel & addr_r[2]; |
|
always @(posedge clk or posedge rst) |
if(rst) lmr_req <= #1 1'b0; |
175,8 → 200,9
// |
// Initialize SDRAM Request/Ack & tracking logic |
// |
always @(posedge clk) |
init_req_we <= #1 rf_we & sel & !addr_r[2]; |
always @(posedge clk or posedge rst) |
if(rst) init_req_we <= #1 1'b0; |
else init_req_we <= #1 rf_we & sel & !addr_r[2]; |
|
always @(posedge clk or posedge rst) |
if(rst) init_req <= #1 1'b0; |
/trunk/rtl/verilog/mc_defines.v
37,10 → 37,10
|
// CVS Log |
// |
// $Id: mc_defines.v,v 1.4 2001-11-29 02:16:28 rudi Exp $ |
// $Id: mc_defines.v,v 1.5 2001-12-11 02:47:19 rudi Exp $ |
// |
// $Date: 2001-11-29 02:16:28 $ |
// $Revision: 1.4 $ |
// $Date: 2001-12-11 02:47:19 $ |
// $Revision: 1.5 $ |
// $Author: rudi $ |
// $Locker: $ |
// $State: Exp $ |
47,6 → 47,15
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.4 2001/11/29 02:16:28 rudi |
// |
// |
// - More Synthesis cleanup, mostly for speed |
// - Several bug fixes |
// - Changed code to avoid auto-precharge and |
// burst-terminate combinations (apparently illegal ?) |
// Now we will do a manual precharge ... |
// |
// Revision 1.3 2001/09/10 13:44:17 rudi |
// *** empty log message *** |
// |
113,7 → 122,7
// |
|
// This will be defined by the run script for my test bench ... |
//`define RUDIS_TB 1 |
`define RUDIS_TB 1 |
|
// Defines which chip select is used for Power On booting |
|
/trunk/rtl/verilog/mc_refresh.v
38,10 → 38,10
|
// CVS Log |
// |
// $Id: mc_refresh.v,v 1.2 2001-09-24 00:38:21 rudi Exp $ |
// $Id: mc_refresh.v,v 1.3 2001-12-11 02:47:19 rudi Exp $ |
// |
// $Date: 2001-09-24 00:38:21 $ |
// $Revision: 1.2 $ |
// $Date: 2001-12-11 02:47:19 $ |
// $Revision: 1.3 $ |
// $Author: rudi $ |
// $Locker: $ |
// $State: Exp $ |
48,6 → 48,10
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2001/09/24 00:38:21 rudi |
// |
// Changed Reset to be active high and async. |
// |
// Revision 1.1 2001/07/29 07:34:41 rudi |
// |
// |
142,8 → 146,9
// Prescaler |
// |
|
always @(posedge clk) |
rfr_en <= #1 |cs_need_rfr; |
always @(posedge clk or posedge rst) |
if(rst) rfr_en <= #1 1'b0; |
else rfr_en <= #1 |cs_need_rfr; |
|
always @(posedge clk or posedge rst) |
if(rst) ps_cnt <= #1 8'h0; |
154,8 → 159,9
|
assign ps_cnt_clr = (ps_cnt == rfr_ps_val) & (rfr_ps_val != 8'h0); |
|
always @(posedge clk) |
rfr_early <= #1 (ps_cnt == rfr_ps_val); |
always @(posedge clk or posedge rst) |
if(rst) rfr_early <= #1 1'b0; |
else rfr_early <= #1 (ps_cnt == rfr_ps_val); |
|
//////////////////////////////////////////////////////////////////// |
// |
162,8 → 168,9
// Refresh Counter |
// |
|
always @(posedge clk) |
rfr_ce <= #1 ps_cnt_clr; |
always @(posedge clk or posedge rst) |
if(rst) rfr_ce <= #1 1'b0; |
else rfr_ce <= #1 ps_cnt_clr; |
|
always @(posedge clk or posedge rst) |
if(rst) rfr_cnt <= #1 8'h0; |
/trunk/rtl/verilog/mc_dp.v
38,10 → 38,10
|
// CVS Log |
// |
// $Id: mc_dp.v,v 1.4 2001-11-29 02:16:28 rudi Exp $ |
// $Id: mc_dp.v,v 1.5 2001-12-11 02:47:19 rudi Exp $ |
// |
// $Date: 2001-11-29 02:16:28 $ |
// $Revision: 1.4 $ |
// $Date: 2001-12-11 02:47:19 $ |
// $Revision: 1.5 $ |
// $Author: rudi $ |
// $Locker: $ |
// $State: Exp $ |
48,6 → 48,15
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.4 2001/11/29 02:16:28 rudi |
// |
// |
// - More Synthesis cleanup, mostly for speed |
// - Several bug fixes |
// - Changed code to avoid auto-precharge and |
// burst-terminate combinations (apparently illegal ?) |
// Now we will do a manual precharge ... |
// |
// Revision 1.3 2001/09/24 00:38:21 rudi |
// |
// Changed Reset to be active high and async. |
155,12 → 164,14
(mem_type == `MC_MEM_TYPE_SRAM) ) wb_data_o = rd_fifo_out[31:0]; |
else wb_data_o = mc_data_d; |
|
assign rd_fifo_clr = !(rst | !wb_cyc_i | (wb_we_i & wb_stb_i) ); |
//assign rd_fifo_clr = !(rst | !wb_cyc_i | (wb_we_i & wb_stb_i) ); |
assign rd_fifo_clr = !wb_cyc_i | (wb_we_i & wb_stb_i); |
assign re = wb_ack_o & wb_read_go; |
|
mc_rd_fifo u0( |
.clk( clk ), |
.rst( rd_fifo_clr ), |
.rst( rst ), |
.clr( rd_fifo_clr ), |
.din( mc_data_del ), |
.we( dv ), |
.dout( rd_fifo_out ), |
/trunk/rtl/verilog/mc_wb_if.v
38,10 → 38,10
|
// CVS Log |
// |
// $Id: mc_wb_if.v,v 1.4 2001-11-29 02:16:28 rudi Exp $ |
// $Id: mc_wb_if.v,v 1.5 2001-12-11 02:47:19 rudi Exp $ |
// |
// $Date: 2001-11-29 02:16:28 $ |
// $Revision: 1.4 $ |
// $Date: 2001-12-11 02:47:19 $ |
// $Revision: 1.5 $ |
// $Author: rudi $ |
// $Locker: $ |
// $State: Exp $ |
48,6 → 48,15
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.4 2001/11/29 02:16:28 rudi |
// |
// |
// - More Synthesis cleanup, mostly for speed |
// - Several bug fixes |
// - Changed code to avoid auto-precharge and |
// burst-terminate combinations (apparently illegal ?) |
// Now we will do a manual precharge ... |
// |
// Revision 1.3 2001/09/24 00:38:21 rudi |
// |
// Changed Reset to be active high and async. |
152,26 → 161,32
else |
if(!wb_cyc_i) rmw_en <= #1 1'b0; |
|
always @(posedge clk) |
rmw_r <= #1 !wr_hold & wb_we_i & wb_cyc_i & wb_stb_i & rmw_en; |
always @(posedge clk or posedge rst) |
if(rst) rmw_r <= #1 1'b0; |
else rmw_r <= #1 !wr_hold & wb_we_i & wb_cyc_i & wb_stb_i & rmw_en; |
|
assign rmw = rmw_r | (!wr_hold & wb_we_i & wb_cyc_i & wb_stb_i & rmw_en); |
|
always @(posedge clk) |
read_go_r1 <= #1 !rmw & wb_cyc_i & |
((wb_stb_i & mem_sel & !wb_we_i) | read_go_r); |
always @(posedge clk or posedge rst) |
if(rst) read_go_r1 <= #1 1'b0; |
else read_go_r1 <= #1 !rmw & wb_cyc_i & |
((wb_stb_i & mem_sel & !wb_we_i) | read_go_r); |
|
always @(posedge clk) |
read_go_r <= #1 read_go_r1 & wb_cyc_i; |
always @(posedge clk or posedge rst) |
if(rst) read_go_r <= #1 1'b0; |
else read_go_r <= #1 read_go_r1 & wb_cyc_i; |
|
assign wb_read_go = !rmw & read_go_r1 & wb_cyc_i; |
|
always @(posedge clk) |
write_go_r1 <= #1 wb_cyc_i & ((wb_stb_i & mem_sel & wb_we_i) | write_go_r); |
always @(posedge clk or posedge rst) |
if(rst) write_go_r1 <= #1 1'b0; |
else write_go_r1 <= #1 wb_cyc_i & |
((wb_stb_i & mem_sel & wb_we_i) | write_go_r); |
|
always @(posedge clk) |
write_go_r <= #1 write_go_r1 & wb_cyc_i & |
((wb_we_i & wb_stb_i) | !wb_stb_i); |
always @(posedge clk or posedge rst) |
if(rst) write_go_r <= #1 1'b0; |
else write_go_r <= #1 write_go_r1 & wb_cyc_i & |
((wb_we_i & wb_stb_i) | !wb_stb_i); |
|
assign wb_write_go = !rmw & write_go_r1 & wb_cyc_i & |
((wb_we_i & wb_stb_i) | !wb_stb_i); |
186,7 → 201,9
else |
if(wb_ack_o | wb_err) wb_first_r <= #1 1'b0; |
|
always @(posedge clk) |
always @(posedge clk or posedge rst) |
if(rst) wr_hold <= #1 1'b0; |
else |
if(wb_cyc_i & wb_stb_i) wr_hold <= #1 wb_we_i; |
|
//////////////////////////////////////////////////////////////////// |
194,13 → 211,15
// WB Ack |
// |
|
always @(posedge clk) |
wb_ack_o <= #1 `MC_MEM_SEL ? mem_ack : |
`MC_REG_SEL & wb_cyc_i & wb_stb_i & !wb_ack_o; |
always @(posedge clk or posedge rst) |
if(rst) wb_ack_o <= #1 1'b0; |
else wb_ack_o <= #1 `MC_MEM_SEL ? mem_ack : |
`MC_REG_SEL & wb_cyc_i & wb_stb_i & !wb_ack_o; |
|
always @(posedge clk) |
wb_err <= #1 wb_cyc_i & wb_stb_i & `MC_MEM_SEL & |
(par_err | err | wp_err) & !wb_err; |
always @(posedge clk or posedge rst) |
if(rst) wb_err <= #1 1'b0; |
else wb_err <= #1 wb_cyc_i & wb_stb_i & `MC_MEM_SEL & |
(par_err | err | wp_err) & !wb_err; |
|
//////////////////////////////////////////////////////////////////// |
// |
/trunk/rtl/verilog/mc_rf.v
37,10 → 37,10
|
// CVS Log |
// |
// $Id: mc_rf.v,v 1.5 2001-11-29 02:16:28 rudi Exp $ |
// $Id: mc_rf.v,v 1.6 2001-12-11 02:47:19 rudi Exp $ |
// |
// $Date: 2001-11-29 02:16:28 $ |
// $Revision: 1.5 $ |
// $Date: 2001-12-11 02:47:19 $ |
// $Revision: 1.6 $ |
// $Author: rudi $ |
// $Locker: $ |
// $State: Exp $ |
47,6 → 47,15
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.5 2001/11/29 02:16:28 rudi |
// |
// |
// - More Synthesis cleanup, mostly for speed |
// - Several bug fixes |
// - Changed code to avoid auto-precharge and |
// burst-terminate combinations (apparently illegal ?) |
// Now we will do a manual precharge ... |
// |
// Revision 1.4 2001/10/04 03:19:37 rudi |
// |
// Fixed Register reads |
257,8 → 266,9
always @(posedge clk) |
wb_addr_r <= #1 wb_addr_i[6:0]; |
|
always @(posedge clk) |
rf_we <= #1 `MC_REG_SEL & wb_we_i & wb_cyc_i & wb_stb_i & !rf_we; |
always @(posedge clk or posedge rst) |
if(rst) rf_we <= #1 1'b0; |
else rf_we <= #1 `MC_REG_SEL & wb_we_i & wb_cyc_i & wb_stb_i & !rf_we; |
|
always @(posedge clk or posedge rst) |
if(rst) csr_r2 <= #1 8'h0; |
285,8 → 295,27
if(rf_we & (wb_addr_r[6:2] == 5'h2) ) |
csc_mask_r <= #1 wb_data_i[10:0]; |
|
//////////////////////////////////////////////////////////////////// |
// |
// A kludge for cases where there is no clock during reset ... |
// |
|
reg rst_r1, rst_r2, rst_r3; |
|
always @(posedge clk or posedge rst) |
if(rst) rst_r1 <= #1 1'b1; |
else rst_r1 <= #1 1'b0; |
|
always @(posedge clk or posedge rst) |
if(rst) rst_r2 <= #1 1'b1; |
else rst_r2 <= #1 rst_r1; |
|
always @(posedge clk or posedge rst) |
if(rst) rst_r3 <= #1 1'b1; |
else rst_r3 <= #1 rst_r2; |
|
always @(posedge clk) |
if(rst) poc <= #1 mc_data_i; |
if(rst_r3) poc <= #1 mc_data_i; |
|
//////////////////////////////////////////////////////////////////// |
// |
301,10 → 330,14
// Select CSC and TMS Registers |
// |
|
always @(posedge clk) |
always @(posedge clk or posedge rst) |
if(rst) cs <= #1 8'h0; |
else |
if(cs_le) cs <= #1 {cs7, cs6, cs5, cs4, cs3, cs2, cs1, cs0}; |
|
always @(posedge clk) |
always @(posedge clk or posedge rst) |
if(rst) wp_err <= #1 1'b0; |
else |
if(cs_le & wb_cyc_i & wb_stb_i) |
wp_err <= #1 wp_err7 | wp_err6 | wp_err5 | wp_err4 | |
wp_err3 | wp_err2 | wp_err1 | wp_err0; |
311,8 → 344,10
else |
if(!wb_cyc_i) wp_err <= #1 1'b0; |
|
always @(posedge clk) |
if(cs_le) |
always @(posedge clk or posedge rst) |
if(rst) csc <= #1 32'h0; |
else |
if(cs_le & wb_cyc_i & wb_stb_i) |
begin |
if(cs0) csc <= #1 csc0; |
else |
330,8 → 365,10
else csc <= #1 csc7; |
end |
|
always @(posedge clk) |
if(cs_le | rf_we) |
always @(posedge clk or posedge rst) |
if(rst) tms <= #1 32'hffff_ffff; |
else |
if((cs_le | rf_we) & wb_cyc_i & wb_stb_i) |
begin |
if(cs0) tms <= #1 tms0; |
else |
349,8 → 386,10
else tms <= #1 tms7; |
end |
|
always @(posedge clk) |
if(cs_le) |
always @(posedge clk or posedge rst) |
if(rst) sp_csc <= #1 32'h0; |
else |
if(cs_le & wb_cyc_i & wb_stb_i) |
begin |
if(spec_req_cs[0]) sp_csc <= #1 csc0; |
else |
368,8 → 407,10
else sp_csc <= #1 csc7; |
end |
|
always @(posedge clk) |
if(cs_le | rf_we) |
always @(posedge clk or posedge rst) |
if(rst) sp_tms <= #1 32'hffff_ffff; |
else |
if((cs_le | rf_we) & wb_cyc_i & wb_stb_i) |
begin |
if(spec_req_cs[0]) sp_tms <= #1 tms0; |
else |
416,11 → 457,14
assign lmr_ack_fe = lmr_ack_r & !lmr_ack; |
|
// Chip Select Output |
always @(posedge clk) |
always @(posedge clk or posedge rst) |
if(rst) spec_req_cs <= #1 8'h0; |
else |
if(sreq_cs_le) spec_req_cs <= #1 spec_req_cs_d; |
|
always @(posedge clk) |
sreq_cs_le <= #1 (!init_req & !lmr_req) | lmr_ack_fe | init_ack_fe; |
always @(posedge clk or posedge rst) |
if(rst) sreq_cs_le <= #1 1'b0; |
else sreq_cs_le <= #1 (!init_req & !lmr_req) | lmr_ack_fe | init_ack_fe; |
|
// Make sure only one is serviced at a time |
assign spec_req_cs_d[0] = spec_req_cs_t[0]; |
433,13 → 477,15
assign spec_req_cs_d[7] = spec_req_cs_t[7] & !( |spec_req_cs_t[6:0] ); |
|
// Request Tracking |
always @(posedge clk) |
init_req <= #1 init_req0 | init_req1 | init_req2 | init_req3 | |
init_req4 | init_req5 | init_req6 | init_req7; |
always @(posedge clk or posedge rst) |
if(rst) init_req <= #1 1'b0; |
else init_req <= #1 init_req0 | init_req1 | init_req2 | init_req3 | |
init_req4 | init_req5 | init_req6 | init_req7; |
|
always @(posedge clk) |
lmr_req <= #1 lmr_req0 | lmr_req1 | lmr_req2 | lmr_req3 | |
lmr_req4 | lmr_req5 | lmr_req6 | lmr_req7; |
always @(posedge clk or posedge rst) |
if(rst) lmr_req <= #1 1'b0; |
else lmr_req <= #1 lmr_req0 | lmr_req1 | lmr_req2 | lmr_req3 | |
lmr_req4 | lmr_req5 | lmr_req6 | lmr_req7; |
|
assign spec_req_cs_t = !init_req ? // Load Mode Register Requests |
{lmr_req7, lmr_req6, lmr_req5, lmr_req4, |
/trunk/rtl/verilog/mc_timing.v
37,10 → 37,10
|
// CVS Log |
// |
// $Id: mc_timing.v,v 1.5 2001-11-29 02:16:28 rudi Exp $ |
// $Id: mc_timing.v,v 1.6 2001-12-11 02:47:19 rudi Exp $ |
// |
// $Date: 2001-11-29 02:16:28 $ |
// $Revision: 1.5 $ |
// $Date: 2001-12-11 02:47:19 $ |
// $Revision: 1.6 $ |
// $Author: rudi $ |
// $Locker: $ |
// $State: Exp $ |
47,6 → 47,15
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.5 2001/11/29 02:16:28 rudi |
// |
// |
// - More Synthesis cleanup, mostly for speed |
// - Several bug fixes |
// - Changed code to avoid auto-precharge and |
// burst-terminate combinations (apparently illegal ?) |
// Now we will do a manual precharge ... |
// |
// Revision 1.4 2001/09/24 00:38:21 rudi |
// |
// Changed Reset to be active high and async. |
238,11 → 247,15
LMR0 = 66'b000000000000000000000000000000000000000000000001000000000000000000, |
LMR1 = 66'b000000000000000000000000000000000000000000000010000000000000000000, |
LMR2 = 66'b000000000000000000000000000000000000000000000100000000000000000000, |
// 6666666555555555544444444443333333333222222222211111111110000000000 |
// 6543210987654321098765432109876543210987654321098765432109876543210 |
INIT0 = 66'b000000000000000000000000000000000000000000001000000000000000000000, |
INIT = 66'b000000000000000000000000000000000000000000010000000000000000000000, |
INIT_W = 66'b000000000000000000000000000000000000000000100000000000000000000000, |
INIT_REFR1 = 66'b000000000000000000000000000000000000000001000000000000000000000000, |
INIT_REFR1_W = 66'b000000000000000000000000000000000000000010000000000000000000000000, |
// 6666666555555555544444444443333333333222222222211111111110000000000 |
// 6543210987654321098765432109876543210987654321098765432109876543210 |
INIT_LMR = 66'b000000000000000000000000000000000000000100000000000000000000000000, |
SUSP1 = 66'b000000000000000000000000000000000000001000000000000000000000000000, |
SUSP2 = 66'b000000000000000000000000000000000000010000000000000000000000000000, |
432,11 → 445,13
always @(posedge clk) |
cs_le <= #1 cs_le_d; |
|
always @(posedge mc_clk) |
rsts1 <= #1 rst; |
always @(posedge mc_clk or posedge rst) |
if(rst) rsts1 <= #1 1'b1; |
else rsts1 <= #1 1'b0; |
|
always @(posedge clk) |
rsts <= #1 rsts1; |
always @(posedge clk or posedge rst) |
if(rst) rsts <= #1 1'b1; |
else rsts <= #1 rsts1; |
|
// Control Signals Output Enable |
always @(posedge clk or posedge rst) |
456,10 → 471,14
always @(posedge clk) |
pack_le2 <= #1 pack_le2_d; |
|
always @(posedge clk) |
always @(posedge clk or posedge rst) |
if(rst) mc_adv_r1 <= #1 1'b0; |
else |
if(!mc_le) mc_adv_r1 <= #1 mc_adv; |
|
always @(posedge clk) |
always @(posedge clk or posedge rst) |
if(rst) mc_adv_r <= #1 1'b0; |
else |
if(!mc_le) mc_adv_r <= #1 mc_adv_r1; |
|
// Bus Width decoder |
472,40 → 491,51
// Memory to Wishbone Ack |
assign mem_ack = (mem_ack_d | mem_ack_s) & (wb_read_go | wb_write_go); |
|
always @(posedge clk) |
mem_ack_r <= #1 mem_ack; |
always @(posedge clk or posedge rst) |
if(rst) mem_ack_r <= #1 1'b0; |
else mem_ack_r <= #1 mem_ack; |
|
assign err = err_d; |
|
// SDRAM Command, either delayed (for writes) or straight through |
always @(posedge clk) |
cmd_r <= #1 cmd; |
always @(posedge clk or posedge rst) |
if(rst) cmd_r <= #1 `MC_CMD_NOP; |
else cmd_r <= #1 cmd; |
|
always @(posedge clk) |
cmd_del <= #1 cmd_r; |
always @(posedge clk or posedge rst) |
if(rst) cmd_del <= #1 `MC_CMD_NOP; |
else cmd_del <= #1 cmd_r; |
|
assign {cs_en, ras_, cas_, we_} = wr_cycle ? cmd_del : cmd; |
|
// Track Timing of Asserting a command |
always @(posedge clk) |
always @(posedge clk or posedge rst) |
if(rst) cmd_asserted <= #1 1'b0; |
else |
if(!mc_le) cmd_asserted <= #1 cmd[3]; |
|
always @(posedge clk) |
always @(posedge clk or posedge rst) |
if(rst) cmd_asserted2 <= #1 1'b0; |
else |
if(!mc_le) cmd_asserted2 <= #1 cmd_asserted; |
|
// Output Enable |
always @(posedge clk) |
oe_ <= #1 ~oe_d; |
always @(posedge clk or posedge rst) |
if(rst) oe_ <= #1 1'b1; |
else oe_ <= #1 ~oe_d; |
|
// Memory Bus Data lines Output Enable |
always @(posedge clk) |
data_oe_r <= #1 data_oe_d; |
always @(posedge clk or posedge rst) |
if(rst) data_oe_r <= #1 1'b0; |
else data_oe_r <= #1 data_oe_d; |
|
always @(posedge clk) |
data_oe_r2 <= #1 data_oe_r; |
always @(posedge clk or posedge rst) |
if(rst) data_oe_r2 <= #1 1'b0; |
else data_oe_r2 <= #1 data_oe_r; |
|
always @(posedge clk) |
data_oe <= #1 wr_cycle ? data_oe_r2 : data_oe_d; |
always @(posedge clk or posedge rst) |
if(rst) data_oe <= #1 1'b0; |
else data_oe <= #1 wr_cycle ? data_oe_r2 : data_oe_d; |
|
// Clock Enable |
always @(posedge clk) |
532,11 → 562,13
wb_wait_r <= #1 wb_wait_r2; |
|
// Indicates when the row_same and bank_open lookups are done |
always @(posedge clk) |
lookup_ready1 <= #1 cs_le & wb_stb_i; |
always @(posedge clk or posedge rst) |
if(rst) lookup_ready1 <= #1 1'b0; |
else lookup_ready1 <= #1 cs_le & wb_stb_i; |
|
always @(posedge clk) |
lookup_ready2 <= #1 lookup_ready1 & wb_stb_i; |
always @(posedge clk or posedge rst) |
if(rst) lookup_ready2 <= #1 1'b0; |
else lookup_ready2 <= #1 lookup_ready1 & wb_stb_i; |
|
// Keep Track if it is a SDRAM write cycle |
always @(posedge clk or posedge rst) |
557,8 → 589,9
// Thses two signals are used to signal that no wishbone cycle is in |
// progress. Need to register them to avoid a very long combinatorial |
// path .... |
always @(posedge clk) |
no_wb_cycle <= #1 !wb_read_go & !wb_write_go; |
always @(posedge clk or posedge rst) |
if(rst) no_wb_cycle <= #1 1'b0; |
else no_wb_cycle <= #1 !wb_read_go & !wb_write_go; |
|
// Track ack's for read cycles |
always @(posedge clk or posedge rst) |
579,23 → 612,27
cnt <= #1 cnt_next; |
|
// Suspend/resume Logic |
always @(posedge clk) |
susp_req_r <= #1 susp_req; |
always @(posedge clk or posedge rst) |
if(rst) susp_req_r <= #1 1'b0; |
else susp_req_r <= #1 susp_req; |
|
always @(posedge clk) |
resume_req_r <= #1 resume_req; |
always @(posedge clk or posedge rst) |
if(rst) resume_req_r <= #1 1'b0; |
else resume_req_r <= #1 resume_req; |
|
always @(posedge clk) |
suspended <= #1 suspended_d; |
always @(posedge clk or posedge rst) |
if(rst) suspended <= #1 1'b0; |
else suspended <= #1 suspended_d; |
|
always @(posedge clk) |
rfr_ack_r <= #1 rfr_ack; |
always @(posedge clk or posedge rst) |
if(rst) rfr_ack_r <= #1 1'b0; |
else rfr_ack_r <= #1 rfr_ack; |
|
// Suspend Select Logic |
assign susp_sel = susp_sel_r | susp_sel_set; |
|
always @(posedge clk or posedge rst) |
if(rst) susp_sel_r <= #1 0; |
if(rst) susp_sel_r <= #1 1'b0; |
else |
if(susp_sel_set) susp_sel_r <= #1 1'b1; |
else |
634,9 → 671,10
|
assign timer2_is_zero = (timer2 == 9'h0); |
|
always @(posedge clk) |
tmr2_done <= #1 timer2_is_zero & !tmr2_ld_trdv & !tmr2_ld_trdz & |
!tmr2_ld_twpw & !tmr2_ld_twd & !tmr2_ld_twwd & !tmr2_ld_tscsto; |
always @(posedge clk or posedge rst) |
if(rst) tmr2_done <= #1 1'b0; |
else tmr2_done <= #1 timer2_is_zero & !tmr2_ld_trdv & !tmr2_ld_trdz & |
!tmr2_ld_twpw & !tmr2_ld_twd & !tmr2_ld_twwd & !tmr2_ld_tscsto; |
|
assign twrp = {2'h0,tms_x[16:15]} + tms_x[23:20]; |
|
670,8 → 708,9
|
assign timer_is_zero = (timer == 8'h0); |
|
always @(posedge clk) |
tmr_done <= #1 timer_is_zero; |
always @(posedge clk or posedge rst) |
if(rst) tmr_done <= #1 1'b0; |
else tmr_done <= #1 timer_is_zero; |
|
// Init Refresh Cycles Counter |
always @(posedge clk) |
701,11 → 740,15
else |
if(bc_dec) burst_cnt <= #1 burst_cnt - 11'h1; |
|
always @(posedge clk) |
always @(posedge clk or posedge rst) |
if(rst) burst_fp <= #1 1'b0; |
else |
if(burst_cnt_ld) burst_fp <= #1 (tms_x[2:0] == 3'h7); |
|
// Auto Precharge Enable |
always @(posedge clk) |
always @(posedge clk or posedge rst) |
if(rst) ap_en <= #1 1'b0; |
else |
if(burst_cnt_ld) ap_en <= #1 (tms_x[2:0] == 3'h0) & !kro; |
|
assign burst_act = |burst_cnt & ( |tms_x[2:0] ); |
713,8 → 756,9
always @(posedge clk) |
burst_act_rd <= #1 |burst_cnt; |
|
always @(posedge clk) |
dv_r <= #1 dv; |
always @(posedge clk or posedge rst) |
if(rst) dv_r <= #1 1'b0; |
else dv_r <= #1 dv; |
|
always @(posedge clk) // Auto Precharge Holding Register |
cmd_a10_r <= #1 cmd_a10; |
728,7 → 772,6
always @(posedge clk) |
wb_write_go_r <= #1 wb_write_go; |
|
|
always @(posedge clk or posedge rst) |
if(rst) wb_stb_first <= #1 1'b0; |
else |
/trunk/rtl/verilog/mc_rd_fifo.v
38,10 → 38,10
|
// CVS Log |
// |
// $Id: mc_rd_fifo.v,v 1.2 2001-11-29 02:16:28 rudi Exp $ |
// $Id: mc_rd_fifo.v,v 1.3 2001-12-11 02:47:19 rudi Exp $ |
// |
// $Date: 2001-11-29 02:16:28 $ |
// $Revision: 1.2 $ |
// $Date: 2001-12-11 02:47:19 $ |
// $Revision: 1.3 $ |
// $Author: rudi $ |
// $Locker: $ |
// $State: Exp $ |
48,6 → 48,15
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2001/11/29 02:16:28 rudi |
// |
// |
// - More Synthesis cleanup, mostly for speed |
// - Several bug fixes |
// - Changed code to avoid auto-precharge and |
// burst-terminate combinations (apparently illegal ?) |
// Now we will do a manual precharge ... |
// |
// Revision 1.1 2001/07/29 07:34:41 rudi |
// |
// |
63,9 → 72,9
|
`include "mc_defines.v" |
|
module mc_rd_fifo(clk, rst, din, we, dout, re); |
module mc_rd_fifo(clk, rst, clr, din, we, dout, re); |
|
input clk, rst; |
input clk, rst, clr; |
input [35:0] din; |
input we; |
output [35:0] dout; |
75,14 → 84,18
reg [35:0] r0, r1, r2, r3; |
reg [35:0] dout; |
|
always @(posedge clk) |
if(!rst) rd_adr <= #1 4'h1; |
always @(posedge clk or posedge rst) |
if(rst) rd_adr <= #1 4'h1; |
else |
if(clr) rd_adr <= #1 4'h1; |
else |
if(re) rd_adr <= #1 {rd_adr[2:0], rd_adr[3]}; |
|
always @(posedge clk) |
if(!rst) wr_adr <= #1 4'h1; |
always @(posedge clk or posedge rst) |
if(rst) wr_adr <= #1 4'h1; |
else |
if(clr) wr_adr <= #1 4'h1; |
else |
if(we) wr_adr <= #1 {wr_adr[2:0], wr_adr[3]}; |
|
always @(posedge clk) |