URL
https://opencores.org/ocsvn/mlite/mlite/trunk
Subversion Repositories mlite
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- This comparison shows the changes necessary to convert path
/
- from Rev 17 to Rev 18
- ↔ Reverse comparison
Rev 17 → Rev 18
/trunk/vhdl/mult.vhd
34,6 → 34,7
signal reg_a : std_logic_vector(31 downto 0); |
signal reg_b : std_logic_vector(63 downto 0); |
signal answer_reg : std_logic_vector(31 downto 0); |
-- signal sum_out : std_logic_vector(32 downto 0); |
begin |
|
--multiplication/division unit |
47,7 → 48,6
variable b_temp : std_logic_vector(63 downto 0); |
variable answer_temp : std_logic_vector(31 downto 0); |
|
variable sign_extension : std_logic; |
variable aa, bb : std_logic_vector(32 downto 0); |
variable sum : std_logic_vector(32 downto 0); |
variable start : std_logic; |
62,7 → 62,6
b_temp := reg_b; |
answer_temp := answer_reg; |
|
sign_extension := '0'; |
aa := '0' & ZERO; |
bb := '0' & ZERO; |
sum := '0' & ZERO; |
98,6 → 97,7
a_temp := a; |
answer_temp := ZERO; |
if do_div_temp = '1' then |
b_temp(63) := '0'; |
if do_signed_temp = '0' or b(31) = '0' then |
b_temp(62 downto 31) := b; |
else |
105,6 → 105,9
a_temp := bv_negate(a); |
end if; |
b_temp(30 downto 0) := ZERO(30 downto 0); |
if do_signed_temp = '1' and a(31) = b(31) then |
do_signed_temp := '0'; |
end if; |
else --multiply |
b_temp := ZERO & b; |
end if; |
121,8 → 124,7
else |
bb := '0' & reg_b(63 downto 32); |
end if; |
sign_extension := reg_a(31) and do_signed_reg; |
aa := sign_extension & reg_a; |
aa := do_signed_reg & reg_a; |
sum := bv_adder(aa, bb, do_div_reg); |
-- sum := bv_adder_lookahead(aa, bb, do_div_reg); |
|
130,7 → 132,7
count_temp := bv_inc6(count_reg); |
if do_div_reg = '1' then |
answer_temp(31 downto 1) := answer_reg(30 downto 0); |
if reg_b(63 downto 32) = ZERO and sum(32) = '0' then |
if reg_b(63 downto 32) = ZERO and sum(32) = do_signed_reg then |
a_temp := sum(31 downto 0); --aa=aa-bb; |
answer_temp(0) := '1'; |
else |
184,6 → 186,8
c_mult <= ZERO; |
end if; |
|
-- sum_out <= sum; |
|
end process; |
|
end; --architecture logic |