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URL https://opencores.org/ocsvn/opencpu32/opencpu32/trunk

Subversion Repositories opencpu32

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    from Rev 17 to Rev 18
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Rev 17 → Rev 18

/opencpu32/trunk/hdl/opencpu32/testMultiplexer2_1.vhd File deleted
/opencpu32/trunk/hdl/opencpu32/Multiplexer2_1.vhd File deleted
/opencpu32/trunk/hdl/opencpu32/opencpu32.xise
20,25 → 20,15
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="Alu.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="Multiplexer2_1.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="testAlu.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="50"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="50"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="50"/>
</file>
<file xil_pn:name="testMultiplexer2_1.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="77"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="77"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="77"/>
</file>
<file xil_pn:name="TriStateBuffer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
60,15 → 50,25
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="146"/>
</file>
<file xil_pn:name="DataPath.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="135"/>
</file>
<file xil_pn:name="testDataPath.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="137"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="137"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="137"/>
</file>
<file xil_pn:name="Multiplexer4_1.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="141"/>
</file>
<file xil_pn:name="testMultiplexer4_1.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="138"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="138"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="138"/>
</file>
</files>
 
<properties>
293,8 → 293,8
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testDataPath" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testDataPath" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testAlu" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testAlu" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
310,7 → 310,7
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testDataPath" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testAlu" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
360,7 → 360,7
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testDataPath|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testAlu|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="opencpu32" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
/opencpu32/trunk/hdl/opencpu32/testMultiplexer4_1.vhd
0,0 → 1,106
--! @file
--! @brief Testbench for Multiplexer4_1
 
--! Use standard library and import the packages (std_logic_1164,std_logic_unsigned,std_logic_arith)
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
--! Use CPU Definitions package
use work.pkgOpenCPU32.all;
ENTITY testMultiplexer4_1 IS
END testMultiplexer4_1;
--! @brief Multiplexer4_1 Testbench file
--! @details Test multiplexer operations changing the selection signal
--! for more information: http://en.wikipedia.org/wiki/Multiplexer
ARCHITECTURE behavior OF testMultiplexer4_1 IS
--! Component declaration to instantiate the Multiplexer circuit
COMPONENT Multiplexer4_1
generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
Port ( A : in STD_LOGIC_VECTOR (n downto 0); --! First Input
B : in STD_LOGIC_VECTOR (n downto 0); --! Second Input
C : in STD_LOGIC_VECTOR (n downto 0); --! Third Input
D : in STD_LOGIC_VECTOR (n downto 0); --! Forth Input
sel : in STD_LOGIC_VECTOR (1 downto 0); --! Select inputs (1, 2, 3, 4)
S : out STD_LOGIC_VECTOR (n downto 0)); --! Mux Output
END COMPONENT;
 
--Inputs
signal A : std_logic_vector((nBits - 1) downto 0) := (others => '0'); --! Wire to connect Test signal to component
signal B : std_logic_vector((nBits - 1) downto 0) := (others => '0'); --! Wire to connect Test signal to component
signal C : std_logic_vector((nBits - 1) downto 0) := (others => '0'); --! Wire to connect Test signal to component
signal D : std_logic_vector((nBits - 1) downto 0) := (others => '0'); --! Wire to connect Test signal to component
signal sel : STD_LOGIC_VECTOR (1 downto 0) := "00"; --! Wire to connect Test signal to component
 
--Outputs
signal S : std_logic_vector((nBits - 1) downto 0); --! Wire to connect Test signal to component
BEGIN
--!Instantiate the Unit Under Test (Multiplexer4_1) (Doxygen bug if it's not commented!)
uut: Multiplexer4_1 PORT MAP (
A => A,
B => B,
C => C,
D => D,
sel => sel,
S => S
);
--! Process that will change sel signal and verify the Mux outputs
stim_proc: process
begin
-- Sel 0 ---------------------------------------------------------------------------
wait for 1 ps;
REPORT "Select first channel" SEVERITY NOTE;
sel <= "00";
A <= conv_std_logic_vector(0, nBits);
B <= conv_std_logic_vector(1000, nBits);
C <= conv_std_logic_vector(2000, nBits);
D <= conv_std_logic_vector(3000, nBits);
wait for 1 ns; -- Wait to stabilize the response
assert S = (A) report "Could not select first channel" severity FAILURE;
-- Sel 1 ---------------------------------------------------------------------------
wait for 1 ns;
REPORT "Select second channel" SEVERITY NOTE;
sel <= "01";
A <= conv_std_logic_vector(0, nBits);
B <= conv_std_logic_vector(1000, nBits);
C <= conv_std_logic_vector(2000, nBits);
D <= conv_std_logic_vector(3000, nBits);
wait for 1 ns; -- Wait to stabilize the response
assert S = (B) report "Could not select second channel" severity FAILURE;
-- Sel 2 ---------------------------------------------------------------------------
wait for 1 ns;
REPORT "Select second channel" SEVERITY NOTE;
sel <= "10";
A <= conv_std_logic_vector(0, nBits);
B <= conv_std_logic_vector(1000, nBits);
C <= conv_std_logic_vector(2000, nBits);
D <= conv_std_logic_vector(3000, nBits);
wait for 1 ns; -- Wait to stabilize the response
assert S = (C) report "Could not select second channel" severity FAILURE;
-- Sel 3 ---------------------------------------------------------------------------
wait for 1 ns;
REPORT "Select second channel" SEVERITY NOTE;
sel <= "11";
A <= conv_std_logic_vector(0, nBits);
B <= conv_std_logic_vector(1000, nBits);
C <= conv_std_logic_vector(2000, nBits);
D <= conv_std_logic_vector(3000, nBits);
wait for 1 ns; -- Wait to stabilize the response
assert S = (D) report "Could not select second channel" severity FAILURE;
-- Finish simulation
assert false report "NONE. End of simulation." severity failure;
end process;
 
END;
/opencpu32/trunk/hdl/opencpu32/Multiplexer4_1.vhd
0,0 → 1,38
--! @file
--! @brief 4:1 Mux using with-select
 
--! Use standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
--! Use CPU Definitions package
use work.pkgOpenCPU32.all;
 
--! Mux 2->1 circuit can select one of the 2 inputs into one output with some selection signal
 
--! Detailed description of this
--! mux design element.
entity Multiplexer4_1 is
generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
Port ( A : in STD_LOGIC_VECTOR (n downto 0); --! First Input
B : in STD_LOGIC_VECTOR (n downto 0); --! Second Input
C : in STD_LOGIC_VECTOR (n downto 0); --! Third Input
D : in STD_LOGIC_VECTOR (n downto 0); --! Forth Input
sel : in STD_LOGIC_VECTOR (1 downto 0); --! Select inputs (1, 2, 3, 4)
S : out STD_LOGIC_VECTOR (n downto 0)); --! Mux Output
end Multiplexer4_1;
 
--! @brief Architure definition of the MUX
--! @details On this case we're going to use VHDL combinational description
architecture Behavioral of Multiplexer4_1 is
 
begin
with sel select
S <= A when "00",
B when "01",
C when "10",
D when "11",
(others => 'Z') when others;
 
end Behavioral;
 
/opencpu32/trunk/hdl/opencpu32/_xmsgs/pn_parser.xmsgs
8,7 → 8,7
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
 
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/opencpu32/hdl/opencpu32/testDataPath.vhd&quot; into library work</arg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/opencpu32/hdl/opencpu32/testMultiplexer4_1.vhd&quot; into library work</arg>
</msg>
 
</messages>
/opencpu32/trunk/hdl/opencpu32/testAlu.vhd
139,7 → 139,8
wait for 1 ns; -- Wait to stabilize the response
assert S = (not A) report "Invalid NOT output" severity FAILURE;
 
wait;
-- Finish simulation
assert false report "NONE. End of simulation." severity failure;
end process;
 
END;
/opencpu32/trunk/hdl/opencpu32/opencpu32.gise
141,7 → 141,10
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testAlu_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testAlu_isim_beh.wdb"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testMultiplexer2_1_isim_beh.exe"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testMultiplexer4_1_isim_beh.exe"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testRegisterFile_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testRegisterFile_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testRegisterFile_isim_beh.wdb"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testTriStateBuffer_isim_beh.exe"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
154,26 → 157,26
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333221390" xil_pn:in_ck="5896367260640228155" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1333221390">
<transform xil_pn:end_ts="1333269930" xil_pn:in_ck="2444604816064773119" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1333269930">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="Alu.vhd"/>
<outfile xil_pn:name="DataPath.vhd"/>
<outfile xil_pn:name="Multiplexer2_1.vhd"/>
<outfile xil_pn:name="Multiplexer4_1.vhd"/>
<outfile xil_pn:name="RegisterFile.vhd"/>
<outfile xil_pn:name="TriStateBuffer.vhd"/>
<outfile xil_pn:name="pkgOpenCPU32.vhd"/>
<outfile xil_pn:name="testAlu.vhd"/>
<outfile xil_pn:name="testDataPath.vhd"/>
<outfile xil_pn:name="testMultiplexer2_1.vhd"/>
<outfile xil_pn:name="testMultiplexer4_1.vhd"/>
<outfile xil_pn:name="testRegisterFile.vhd"/>
<outfile xil_pn:name="testTriStateBuffer.vhd"/>
</transform>
<transform xil_pn:end_ts="1333221353" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-3798934868497889219" xil_pn:start_ts="1333221353">
<transform xil_pn:end_ts="1333269950" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-892635403352863368" xil_pn:start_ts="1333269950">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333221353" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-6007724738129030273" xil_pn:start_ts="1333221353">
<transform xil_pn:end_ts="1333269950" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-7876831410930882182" xil_pn:start_ts="1333269950">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
181,33 → 184,37
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333221390" xil_pn:in_ck="5896367260640228155" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1333221390">
<transform xil_pn:end_ts="1333269930" xil_pn:in_ck="2444604816064773119" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1333269930">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="Alu.vhd"/>
<outfile xil_pn:name="DataPath.vhd"/>
<outfile xil_pn:name="Multiplexer2_1.vhd"/>
<outfile xil_pn:name="Multiplexer4_1.vhd"/>
<outfile xil_pn:name="RegisterFile.vhd"/>
<outfile xil_pn:name="TriStateBuffer.vhd"/>
<outfile xil_pn:name="pkgOpenCPU32.vhd"/>
<outfile xil_pn:name="testAlu.vhd"/>
<outfile xil_pn:name="testDataPath.vhd"/>
<outfile xil_pn:name="testMultiplexer2_1.vhd"/>
<outfile xil_pn:name="testMultiplexer4_1.vhd"/>
<outfile xil_pn:name="testRegisterFile.vhd"/>
<outfile xil_pn:name="testTriStateBuffer.vhd"/>
</transform>
<transform xil_pn:end_ts="1333221392" xil_pn:in_ck="5896367260640228155" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="4679725895911349372" xil_pn:start_ts="1333221390">
<status xil_pn:value="FailedRun"/>
<transform xil_pn:end_ts="1333269952" xil_pn:in_ck="2444604816064773119" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="3692595343167413970" xil_pn:start_ts="1333269950">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="fuse.log"/>
<outfile xil_pn:name="isim"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="testAlu_beh.prj"/>
<outfile xil_pn:name="testAlu_isim_beh.exe"/>
<outfile xil_pn:name="xilinxsim.ini"/>
</transform>
<transform xil_pn:end_ts="1333153231" xil_pn:in_ck="5430170344901993917" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-5331297572704317690" xil_pn:start_ts="1333153230">
<status xil_pn:value="AbortedRun"/>
<transform xil_pn:end_ts="1333269953" xil_pn:in_ck="2214679574356920708" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-5331297572704317690" xil_pn:start_ts="1333269952">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForProperties"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForced"/>
<status xil_pn:value="InputRemoved"/>
<outfile xil_pn:name="isim.cmd"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="testAlu_isim_beh.wdb"/>
</transform>
<transform xil_pn:end_ts="1332968178" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1332968178">
<status xil_pn:value="SuccessfullyRun"/>
242,21 → 249,11
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
<outfile xil_pn:name=".lso"/>
<outfile xil_pn:name="Alu.lso"/>
<outfile xil_pn:name="Alu.ngc"/>
<outfile xil_pn:name="Alu.ngr"/>
<outfile xil_pn:name="Alu.prj"/>
<outfile xil_pn:name="Alu.stx"/>
<outfile xil_pn:name="Alu.syr"/>
<outfile xil_pn:name="Alu.xst"/>
<outfile xil_pn:name="Alu_vhdl.prj"/>
<outfile xil_pn:name="Alu_xst.xrpt"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
<transform xil_pn:end_ts="1333128286" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3437821219266902819" xil_pn:start_ts="1333128286">
<status xil_pn:value="SuccessfullyRun"/>
/opencpu32/trunk/hdl/opencpu32/testRegisterFile.vhd
111,7 → 111,10
-- Mark read B end
Read_B_En <= 'X';
wait;
-- Finish simulation
assert false report "NONE. End of simulation." severity failure;
end process;
 
END;
/opencpu32/trunk/hdl/opencpu32/testTriStateBuffer.vhd
64,7 → 64,8
wait for 1 ns; -- Wait to stabilize the response
assert S = (conv_std_logic_vector(10, nBits)) report "Output should be high impedance..." severity FAILURE;
 
wait;
-- Finish simulation
assert false report "NONE. End of simulation." severity failure;
end process;
 
END;

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