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URL https://opencores.org/ocsvn/pci/pci/trunk

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/trunk/rtl/verilog/pci_rst_int.v
0,0 → 1,160
//////////////////////////////////////////////////////////////////////
//// ////
//// File name: pci_rst_int.v ////
//// ////
//// This file is part of the "PCI bridge" project ////
//// http://www.opencores.org/cores/pci/ ////
//// ////
//// Author(s): ////
//// - Tadej Markovic, tadej@opencores.org ////
//// ////
//// All additional information is avaliable in the README.txt ////
//// file. ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Tadej Markovic, tadej@opencores.org ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
//
 
`include "pci_constants.v"
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
// Module is used to switch appropriate reset and interrupt signals with few logic
module PCI_RST_INT
(
clk_in,
// reset signals
rst_i,
pci_rstn_in,
conf_soft_res_in,
reset,
pci_rstn_out,
pci_rstn_en_out,
rst_o,
// interrupt signals
pci_intan_in,
conf_int_in,
int_i,
out_bckp_perr_en_in,
out_bckp_serr_en_in,
pci_intan_out,
pci_intan_en_out,
int_o,
conf_isr_int_prop_out
);
 
input clk_in;
// RESET inputs and outputs
input rst_i;
input pci_rstn_in;
input conf_soft_res_in;
output reset;
output pci_rstn_out;
output pci_rstn_en_out;
output rst_o;
 
// INTERRUPT inputs and outputs
input pci_intan_in;
input conf_int_in;
input int_i;
input out_bckp_perr_en_in;
input out_bckp_serr_en_in;
output pci_intan_out;
output pci_intan_en_out;
output int_o;
output conf_isr_int_prop_out;
 
/*--------------------------------------------------------------------------------------------------------
RESET logic
--------------------------------------------------------------------------------------------------------*/
assign pci_rstn_out = 1'b0 ;
// host implementation of the bridge gets its reset from WISHBONE bus - RST_I and propagates it to PCI bus
`ifdef HOST
assign reset = rst_i ;
`ifdef ACTIVE_LOW_OE
assign pci_rstn_en_out = ~(rst_i || conf_soft_res_in) ;
`else
assign pci_rstn_en_out = rst_i || conf_soft_res_in ;
`endif
assign rst_o = 1'b0 ;
`else
// guest implementation of the bridge gets its reset from PCI bus - RST# and propagates it to WISHBONE bus
`ifdef GUEST
assign reset = ~pci_rstn_in ;
assign rst_o = (~pci_rstn_in) || conf_soft_res_in ;
`ifdef ACTIVE_LOW_OE
assign pci_rstn_en_out = 1'b1 ; // disabled
`else
assign pci_rstn_en_out = 1'b0 ; // disabled
`endif
`endif
`endif
 
/*--------------------------------------------------------------------------------------------------------
INTERRUPT logic
--------------------------------------------------------------------------------------------------------*/
assign pci_intan_out = 1'b0 ;
// host implementation of the bridge gets its interrupt from PCI bus - INTA# and propagates it to WISHBONE bus
`ifdef HOST
assign conf_isr_int_prop_out = ~pci_intan_in ;
assign int_o = conf_int_in ;
`ifdef ACTIVE_LOW_OE
assign pci_intan_en_out = 1'b1 ; // disabled
`else
assign pci_intan_en_out = 1'b0 ; // disabled
`endif
`else
// guest implementation of the bridge gets its interrupt from WISHBONE bus - INT_I and propagates it to PCI bus
`ifdef GUEST
wire interrupt_a_en;
OUT_REG inta
(
.reset_in ( reset ),
.clk_in ( clk_in) ,
.dat_en_in ( 1'b1 ),
.en_en_in ( 1'b1 ),
.dat_in ( 1'b0 ) , // active low
.en_in ( conf_int_in ) ,
.en_out ( interrupt_a_en ),
.dat_out ( )
);
assign conf_isr_int_prop_out = int_i ;
assign int_o = 1'b0 ;
assign pci_intan_en_out = interrupt_a_en ;
`endif
`endif
 
 
endmodule
/trunk/rtl/verilog/sync_module.v
0,0 → 1,153
//////////////////////////////////////////////////////////////////////
//// ////
//// File name "sync_module.v" ////
//// ////
//// This file is part of the "PCI bridge" project ////
//// http://www.opencores.org/cores/pci/ ////
//// ////
//// Author(s): ////
//// - Tadej Markovic, tadej@opencores.org ////
//// ////
//// All additional information is avaliable in the README.txt ////
//// file. ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Tadej Markovic, tadej@opencores.org ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
module SYNC_MODULE
(
set_clk_in,
delete_clk_in,
reset_in,
delete_set_out,
block_set_out,
delete_in
);
 
// system inputs from two clock domains
input set_clk_in;
input delete_clk_in;
input reset_in;
// control outputs
output delete_set_out;
output block_set_out;
// control input
input delete_in;
 
// internal signals
reg del_bit;
wire meta_del_bit;
reg sync_del_bit;
reg delayed_del_bit;
wire meta_bckp_bit;
reg sync_bckp_bit;
reg delayed_bckp_bit;
 
 
// DELETE_IN input FF - when set must be active, until it is sinchronously cleared
always@(posedge delete_clk_in or posedge reset_in)
begin
if (reset_in)
del_bit <= 1'b0;
else
begin
if (!delayed_bckp_bit && sync_bckp_bit)
del_bit <= 1'b0;
else if (delete_in)
del_bit <= 1'b1;
end
end
assign block_set_out = del_bit;
 
// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability
synchronizer_flop delete_sync
(
.data_in (del_bit),
.clk_out (set_clk_in),
.sync_data_out (meta_del_bit),
.async_reset (reset_in)
) ;
 
// Final synchronization of del_bit signal to the set clock domain
always@(posedge set_clk_in or posedge reset_in)
begin
if (reset_in)
sync_del_bit <= 1'b0;
else
sync_del_bit <= meta_del_bit;
end
 
// Delayed sync_del_bit signal for one clock period pulse generation
always@(posedge set_clk_in or posedge reset_in)
begin
if (reset_in)
delayed_del_bit <= 1'b0;
else
delayed_del_bit <= sync_del_bit;
end
 
assign delete_set_out = !delayed_del_bit && sync_del_bit;
 
// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability
synchronizer_flop clear_delete_sync
(
.data_in (sync_del_bit),
.clk_out (delete_clk_in),
.sync_data_out (meta_bckp_bit),
.async_reset (reset_in)
) ;
 
// Final synchronization of sync_del_bit signal to the delete clock domain
always@(posedge delete_clk_in or posedge reset_in)
begin
if (reset_in)
sync_bckp_bit <= 1'b0;
else
sync_bckp_bit <= meta_bckp_bit;
end
 
// Delayed sync_bckp_bit signal for one clock period pulse generation
always@(posedge delete_clk_in or posedge reset_in)
begin
if (reset_in)
delayed_bckp_bit <= 1'b0;
else
delayed_bckp_bit <= sync_bckp_bit;
end
 
endmodule
/trunk/rtl/verilog/pci_io_mux_ad_en_crit.v
0,0 → 1,69
//////////////////////////////////////////////////////////////////////
//// ////
//// File name "pci_io_mux_ad_en_crit.v" ////
//// ////
//// This file is part of the "PCI bridge" project ////
//// http://www.opencores.org/cores/pci/ ////
//// ////
//// Author(s): ////
//// - Miha Dolenc (mihad@opencores.org) ////
//// ////
//// All additional information is avaliable in the README ////
//// file. ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
// module provides equation for ad output enables, which uses critical pci bus inputs
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
// module is provided for ad bus output enable Flip-Flops values
module PCI_IO_MUX_AD_EN_CRIT
(
ad_en_in,
pci_frame_in,
pci_trdy_in,
pci_stop_in,
ad_en_out
);
input ad_en_in,
pci_frame_in,
pci_trdy_in,
pci_stop_in ;
output ad_en_out ;
 
assign ad_en_out = ad_en_in && ( ~pci_frame_in || (pci_trdy_in && pci_stop_in) ) ;
endmodule
/trunk/rtl/verilog/pci_tpram.v
0,0 → 1,423
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Two-Port Synchronous RAM ////
//// ////
//// This file is part of pci bridge project ////
//// http://www.opencores.org/cvsweb.shtml/pci/ ////
//// ////
//// Description ////
//// This block is a wrapper with common two-port ////
//// synchronous memory interface for different ////
//// types of ASIC and FPGA RAMs. Beside universal memory ////
//// interface it also provides behavioral model of generic ////
//// two-port synchronous RAM. ////
//// It should be used in all OPENCORES designs that want to be ////
//// portable accross different target technologies and ////
//// independent of target memory. ////
//// ////
//// Supported ASIC RAMs are: ////
//// - Artisan Double-Port Sync RAM ////
//// - Avant! Two-Port Sync RAM (*) ////
//// - Virage 2-port Sync RAM ////
//// ////
//// Supported FPGA RAMs are: ////
//// - Xilinx Virtex RAMB4_S16_S16 ////
//// ////
//// To Do: ////
//// - fix Avant! ////
//// - xilinx rams need external tri-state logic ////
//// - add additional RAMs (Altera, VS etc) ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, lampret@opencores.org ////
//// - Miha Dolenc, mihad@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "pci_constants.v"
 
module PCI_TPRAM
(
// Generic synchronous two-port RAM interface
clk_a,
rst_a,
ce_a,
we_a,
oe_a,
addr_a,
di_a,
do_a,
clk_b,
rst_b,
ce_b,
we_b,
oe_b,
addr_b,
di_b,
do_b
);
 
//
// Default address and data buses width
//
parameter aw = 8;
parameter dw = 40;
 
//
// Generic synchronous two-port RAM interface
//
input clk_a; // Clock
input rst_a; // Reset
input ce_a; // Chip enable input
input we_a; // Write enable input
input oe_a; // Output enable input
input [aw-1:0] addr_a; // address bus inputs
input [dw-1:0] di_a; // input data bus
output [dw-1:0] do_a; // output data bus
input clk_b; // Clock
input rst_b; // Reset
input ce_b; // Chip enable input
input we_b; // Write enable input
input oe_b; // Output enable input
input [aw-1:0] addr_b; // address bus inputs
input [dw-1:0] di_b; // input data bus
output [dw-1:0] do_b; // output data bus
 
//
// Internal wires and registers
//
 
 
`ifdef PCI_ARTISAN_SDP
`define RAM_SELECTED
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Double-Port RAM (ra2sh)
//
art_hsdp_256x40 /*#(dw, 1<<aw, aw) */ artisan_sdp
(
.qa(do_a),
.clka(clk_a),
.cena(~ce_a),
.wena(~we_a),
.aa(addr_a),
.da(di_a),
.oena(~oe_a),
.qb(do_b),
.clkb(clk_b),
.cenb(~ce_b),
.wenb(~we_b),
.ab(addr_b),
.db(di_b),
.oenb(~oe_b)
);
`endif
 
`ifdef AVANT_ATP
`define RAM_SELECTED
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
.web(~we),
.reb(),
.oeb(~oe),
.rcsb(),
.wcsb(),
.ra(addr),
.wa(addr),
.di(di),
.do(do)
);
`endif
 
`ifdef VIRAGE_STP
`define RAM_SELECTED
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 2-port R/W RAM
//
virage_stp virage_stp(
.QA(do_a),
.QB(do_b),
 
.ADRA(addr_a),
.DA(di_a),
.WEA(we_a),
.OEA(oe_a),
.MEA(ce_a),
.CLKA(clk_a),
 
.ADRB(adr_b),
.DB(di_b),
.WEB(we_b),
.OEB(oe_b),
.MEB(ce_b),
.CLKB(clk_b)
);
`endif
 
`ifdef PCI_XILINX_RAMB4
`define RAM_SELECTED
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
 
//
// Block 0
//
 
RAMB4_S16_S16 ramb4_s16_s16_0(
.CLKA(clk_a),
.RSTA(rst_a),
.ADDRA(addr_a),
.DIA(di_a[15:0]),
.ENA(ce_a),
.WEA(we_a),
.DOA(do_a[15:0]),
 
.CLKB(clk_b),
.RSTB(rst_b),
.ADDRB(addr_b),
.DIB(di_b[15:0]),
.ENB(ce_b),
.WEB(we_b),
.DOB(do_b[15:0])
);
 
//
// Block 1
//
 
RAMB4_S16_S16 ramb4_s16_s16_1(
.CLKA(clk_a),
.RSTA(rst_a),
.ADDRA(addr_a),
.DIA(di_a[31:16]),
.ENA(ce_a),
.WEA(we_a),
.DOA(do_a[31:16]),
 
.CLKB(clk_b),
.RSTB(rst_b),
.ADDRB(addr_b),
.DIB(di_b[31:16]),
.ENB(ce_b),
.WEB(we_b),
.DOB(do_b[31:16])
);
 
//
// Block 2
//
// block ram2 wires - non generic width of block rams
wire [15:0] blk2_di_a = {8'h00, di_a[39:32]} ;
wire [15:0] blk2_di_b = {8'h00, di_b[39:32]} ;
 
wire [15:0] blk2_do_a ;
wire [15:0] blk2_do_b ;
 
assign do_a[39:32] = blk2_do_a[7:0] ;
assign do_b[39:32] = blk2_do_b[7:0] ;
 
RAMB4_S16_S16 ramb4_s16_s16_2(
.CLKA(clk_a),
.RSTA(rst_a),
.ADDRA(addr_a),
.DIA(blk2_di_a),
.ENA(ce_a),
.WEA(we_a),
.DOA(blk2_do_a),
 
.CLKB(clk_b),
.RSTB(rst_b),
.ADDRB(addr_b),
.DIB(blk2_di_b),
.ENB(ce_b),
.WEB(we_b),
.DOB(blk2_do_b)
);
 
`endif
 
`ifdef PCI_XILINX_DIST_RAM
`define RAM_SELECTED
reg [(aw-1):0] out_address ;
always@(posedge clk_b or posedge rst_b)
begin
if ( rst_b )
out_address <= #1 0 ;
else if (ce_b)
out_address <= #1 addr_b ;
end
 
PCI_DIST_RAM #(aw) pci_distributed_ram
(
.data_out (do_b),
.we (we_a),
.data_in (di_a),
.read_address (out_address),
.write_address (addr_a),
.wclk (clk_a)
);
`endif
 
`ifdef RAM_SELECTED
`undef RAM_SELECTED
`else
//
// Generic two-port synchronous RAM model
//
 
//
// Generic RAM's registers and wires
//
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
reg [dw-1:0] do_reg_a; // RAM data output register
reg [dw-1:0] do_reg_b; // RAM data output register
 
//
// Data output drivers
//
assign do_a = (oe_a) ? do_reg_a : {dw{1'bz}};
assign do_b = (oe_b) ? do_reg_b : {dw{1'bz}};
 
//
// RAM read and write
//
always @(posedge clk_a)
if (ce_a && !we_a)
do_reg_a <= #1 mem[addr_a];
else if (ce_a && we_a)
mem[addr_a] <= #1 di_a;
 
//
// RAM read and write
//
always @(posedge clk_b)
if (ce_b && !we_b)
do_reg_b <= #1 mem[addr_b];
else if (ce_b && we_b)
mem[addr_b] <= #1 di_b;
`endif
 
// synopsys translate_off
initial
begin
if (dw !== 40)
begin
$display("RAM instantiation error! Expected RAM width %d, actual %h!", 40, dw) ;
$finish ;
end
`ifdef XILINX_RAMB4
if (aw !== 8)
begin
$display("RAM instantiation error! Expected RAM address width %d, actual %h!", 40, aw) ;
$finish ;
end
`endif
// currenlty only artisan ram of depth 256 is supported - they don't provide generic ram models
`ifdef ARTISAN_SDP
if (aw !== 8)
begin
$display("RAM instantiation error! Expected RAM address width %d, actual %h!", 40, aw) ;
$finish ;
end
`endif
end
// synopsys translate_on
 
endmodule
 
`ifdef PCI_XILINX_DIST_RAM
module PCI_DIST_RAM (data_out, we, data_in, read_address, write_address, wclk);
parameter addr_width = 4 ;
output [39:0] data_out;
input we, wclk;
input [39:0] data_in;
input [addr_width - 1:0] write_address, read_address;
 
wire [3:0] waddr = write_address ;
wire [3:0] raddr = read_address ;
 
RAM16X1D ram00 (.DPO(data_out[0]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[0]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram01 (.DPO(data_out[1]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[1]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram02 (.DPO(data_out[2]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[2]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram03 (.DPO(data_out[3]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[3]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram04 (.DPO(data_out[4]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[4]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram05 (.DPO(data_out[5]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[5]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram06 (.DPO(data_out[6]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[6]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram07 (.DPO(data_out[7]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[7]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram08 (.DPO(data_out[8]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[8]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram09 (.DPO(data_out[9]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[9]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram10 (.DPO(data_out[10]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[10]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram11 (.DPO(data_out[11]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[11]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram12 (.DPO(data_out[12]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[12]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram13 (.DPO(data_out[13]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[13]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram14 (.DPO(data_out[14]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[14]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram15 (.DPO(data_out[15]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[15]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram16 (.DPO(data_out[16]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[16]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram17 (.DPO(data_out[17]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[17]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram18 (.DPO(data_out[18]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[18]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram19 (.DPO(data_out[19]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[19]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram20 (.DPO(data_out[20]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[20]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram21 (.DPO(data_out[21]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[21]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram22 (.DPO(data_out[22]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[22]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram23 (.DPO(data_out[23]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[23]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram24 (.DPO(data_out[24]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[24]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram25 (.DPO(data_out[25]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[25]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram26 (.DPO(data_out[26]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[26]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram27 (.DPO(data_out[27]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[27]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram28 (.DPO(data_out[28]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[28]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram29 (.DPO(data_out[29]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[29]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram30 (.DPO(data_out[30]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[30]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram31 (.DPO(data_out[31]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[31]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram32 (.DPO(data_out[32]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[32]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram33 (.DPO(data_out[33]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[33]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram34 (.DPO(data_out[34]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[34]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram35 (.DPO(data_out[35]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[35]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram36 (.DPO(data_out[36]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[36]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram37 (.DPO(data_out[37]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[37]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram38 (.DPO(data_out[38]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[38]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram39 (.DPO(data_out[39]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[39]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
endmodule
`endif
/trunk/rtl/verilog/pci_user_constants.v
0,0 → 1,208
//////////////////////////////////////////////////////////////////////
//// ////
//// File name "pci_user_constants.v" ////
//// ////
//// This file is part of the "PCI bridge" project ////
//// http://www.opencores.org/cores/pci/ ////
//// ////
//// Author(s): ////
//// - Miha Dolenc (mihad@opencores.org) ////
//// - Tadej Markovic (tadej@opencores.org) ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
// Fifo implementation defines:
// If FPGA and XILINX are defined, Xilinx's BlockSelectRAM+ is instantiated for Fifo storage.
// 16 bit width is used, so 8 bits of address ( 256 ) locations are available. If RAM_DONT_SHARE is not defined (commented out),
// then one block RAM is shared between two FIFOs. That means each Fifo can have a maximum address length of 7 - depth of 128 and only 6 block rams are used
// If RAM_DONT_SHARE is defined ( not commented out ), then 12 block RAMs are used and each Fifo can have a maximum address length of 8 ( 256 locations )
// If FPGA is not defined, then ASIC RAMs are used. Currently there is only one version of ARTISAN RAM supported. User should generate synchronous RAM with
// width of 40 and instantiate it in pci_tpram.v. If RAM_DONT_SHARE is defined, then these can be dual port rams ( write port
// in one clock domain, read in other ), otherwise it must be two port RAM ( read and write ports in both clock domains ).
// If RAM_DONT_SHARE is defined, then all RAM address lengths must be specified accordingly, otherwise there are two relevant lengths - PCI_FIFO_RAM_ADDR_LENGTH and
// WB_FIFO_RAM_ADDR_LENGTH.
 
`define WBW_ADDR_LENGTH 6
`define WBR_ADDR_LENGTH 4
`define PCIW_ADDR_LENGTH 6
`define PCIR_ADDR_LENGTH 3
 
`define FPGA
`define XILINX
 
//`define WB_RAM_DONT_SHARE
//`define PCI_RAM_DONT_SHARE
 
`ifdef FPGA
`ifdef XILINX
`define PCI_FIFO_RAM_ADDR_LENGTH 8 // PCI target unit fifo storage definition
`define WB_FIFO_RAM_ADDR_LENGTH 8 // WB slave unit fifo storage definition
`define PCI_XILINX_RAMB4
`define WB_XILINX_RAMB4
//`define PCI_XILINX_DIST_RAM
//`define WB_XILINX_DIST_RAM
`endif
`else
`define PCI_FIFO_RAM_ADDR_LENGTH 8 // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM )
`define WB_FIFO_RAM_ADDR_LENGTH 8 // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM )
`define WB_ARTISAN_SDP
`define PCI_ARTISAN_SDP
`endif
 
// these two defines allow user to select active high or low output enables on PCI bus signals, depending on
// output buffers instantiated. Xilinx FPGAs use active low output enables.
`define ACTIVE_LOW_OE
//`define ACTIVE_HIGH_OE
 
// HOST/GUEST implementation selection - see design document and specification for description of each implementation
// only one can be defined at same time
//`define GUEST
`define HOST
 
// if NO_CNF_IMAGE is commented out, then READ-ONLY access to configuration space is ENABLED:
// - ENABLED Read-Only access from WISHBONE for GUEST bridges
// - ENABLED Read-Only access from PCI for HOST bridges
// with defining NO_CNF_IMAGE, one decoder and one multiplexer are saved
`define NO_CNF_IMAGE
 
// number defined here specifies how many MS bits in PCI address are compared with base address, to decode
// accesses. Maximum number allows for minimum image size ( number = 20, image size = 4KB ), minimum number
// allows for maximum image size ( number = 1, image size = 2GB ). If you intend on using different sizes of PCI images,
// you have to define a number of minimum sized image and enlarge others by specifying different address mask.
// smaller the number here, faster the decoder operation
`define PCI_NUM_OF_DEC_ADDR_LINES 3
 
// no. of PCI Target IMAGES
// - PCI provides 6 base address registers for image implementation.
// PCI_IMAGE1 definition is not required and has no effect, since PCI image 1 is always implemented
// If GUEST is defined, PCI Image 0 is also always implemented and is used for configuration space
// access.
// If HOST is defined and NO_CNF_IMAGE is not, then PCI Image 0 is used for Read Only access to configuration
// space. If HOST is defined and NO_CNF_IMAGE is defined, then user can define PCI_IMAGE0 as normal image, and there
// is no access to Configuration space possible from PCI bus.
// Implementation of all other PCI images is selected by defining PCI_IMAGE2 through PCI_IMAGE5 regardles of HOST
// or GUEST implementation.
`ifdef HOST
`ifdef NO_CNF_IMAGE
`define PCI_IMAGE0
`endif
`endif
 
//`define PCI_IMAGE2
`define PCI_IMAGE3
//`define PCI_IMAGE4
`define PCI_IMAGE5
 
// initial value for PCI image address masks. Address masks can be defined in enabled state,
// to allow device independent software to detect size of image and map base addresses to
// memory space. If initial mask for an image is defined as 0, then device independent software
// won't detect base address implemented and device dependent software will have to configure
// address masks as well as base addresses!
`define PCI_AM0 20'hffff_f
`define PCI_AM1 20'hffff_f
`define PCI_AM2 20'hffff_f
`define PCI_AM3 20'hffff_f
`define PCI_AM4 20'hffff_f
`define PCI_AM5 20'hffff_f
 
// initial value for PCI image maping to MEMORY or IO spaces. If initial define is set to 0,
// then IMAGE with that base address points to MEMORY space, othervise it points ti IO space. D
// Device independent software sets the base addresses acording to MEMORY or IO maping!
`define PCI_BA0_MEM_IO 1'b0 // considered only when PCI_IMAGE0 is used as general PCI-WB image!
`define PCI_BA1_MEM_IO 1'b0
`define PCI_BA2_MEM_IO 1'b0
`define PCI_BA3_MEM_IO 1'b0
`define PCI_BA4_MEM_IO 1'b0
`define PCI_BA5_MEM_IO 1'b0
 
// number defined here specifies how many MS bits in WB address are compared with base address, to decode
// accesses. Maximum number allows for minimum image size ( number = 20, image size = 4KB ), minimum number
// allows for maximum image size ( number = 1, image size = 2GB ). If you intend on using different sizes of WB images,
// you have to define a number of minimum sized image and enlarge others by specifying different address mask.
// smaller the number here, faster the decoder operation
`define WB_NUM_OF_DEC_ADDR_LINES 20
 
// no. of WISHBONE Slave IMAGES
// WB image 0 is always used for access to configuration space. In case configuration space access is not implemented,
// ( both GUEST and NO_CNF_IMAGE defined ), then WB image 0 is not implemented. User doesn't need to define image 0.
// WB Image 1 is always implemented and user doesnt need to specify its definition
// WB images' 2 through 5 implementation by defining each one.
//`define WB_IMAGE2
`define WB_IMAGE3
`define WB_IMAGE4
//`define WB_IMAGE5
 
// If this define is commented out, then address translation will not be implemented.
// addresses will pass through bridge unchanged, regardles of address translation enable bits.
// Address translation also slows down the decoding
//`define ADDR_TRAN_IMPL
 
// decode speed for WISHBONE definition - initial cycle on WISHBONE bus will take 1 WS for FAST, 2 WSs for MEDIUM and 3 WSs for slow.
// slower decode speed can be used, to provide enough time for address to be decoded.
//`define WB_DECODE_FAST
`define WB_DECODE_MEDIUM
//`define WB_DECODE_SLOW
 
// Base address for Configuration space access from WB bus. This value cannot be changed during runtime
`define WB_CONFIGURATION_BASE 20'h0000_0
 
// Turn registered WISHBONE slave outputs on or off
// all outputs from WB Slave state machine are registered, if this is defined - WB bus outputs as well as
// outputs to internals of the core.
`define REGISTER_WBS_OUTPUTS
 
/*-----------------------------------------------------------------------------------------------------------
Core speed definition - used for simulation and 66MHz Capable bit value in status register indicating 66MHz
capable device
-----------------------------------------------------------------------------------------------------------*/
`define PCI33
//`define PCI66
 
/*-----------------------------------------------------------------------------------------------------------
[000h-00Ch] First 4 DWORDs (32-bit) of PCI configuration header - the same regardless of the HEADER type !
Vendor_ID is an ID for a specific vendor defined by PCI_SIG - 2321h does not belong to anyone (e.g.
Xilinx's Vendor_ID is 10EEh and Altera's Vendor_ID is 1172h). Device_ID and Revision_ID should be used
together by application.
-----------------------------------------------------------------------------------------------------------*/
`define HEADER_VENDOR_ID 16'h2321
`define HEADER_DEVICE_ID 16'h0001
`define HEADER_REVISION_ID 8'h01
 
// Turn registered WISHBONE master outputs on or off
// all outputs from WB Master state machine are registered, if this is defined - WB bus outputs as well as
// outputs to internals of the core.
//`define REGISTER_WBM_OUTPUTS
 
// MAX Retry counter value for WISHBONE Master state-machine
// This value is 8-bit because of 8-bit retry counter !!!
`define WB_RTY_CNT_MAX 8'hff
/trunk/rtl/verilog/wb_tpram.v
0,0 → 1,425
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Two-Port Synchronous RAM ////
//// ////
//// This file is part of pci bridge project ////
//// http://www.opencores.org/cvsweb.shtml/pci/ ////
//// ////
//// Description ////
//// This block is a wrapper with common two-port ////
//// synchronous memory interface for different ////
//// types of ASIC and FPGA RAMs. Beside universal memory ////
//// interface it also provides behavioral model of generic ////
//// two-port synchronous RAM. ////
//// It should be used in all OPENCORES designs that want to be ////
//// portable accross different target technologies and ////
//// independent of target memory. ////
//// ////
//// Supported ASIC RAMs are: ////
//// - Artisan Double-Port Sync RAM ////
//// - Avant! Two-Port Sync RAM (*) ////
//// - Virage 2-port Sync RAM ////
//// ////
//// Supported FPGA RAMs are: ////
//// - Xilinx Virtex RAMB4_S16_S16 ////
//// ////
//// To Do: ////
//// - fix Avant! ////
//// - xilinx rams need external tri-state logic ////
//// - add additional RAMs (Altera, VS etc) ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, lampret@opencores.org ////
//// - Miha Dolenc, mihad@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "pci_constants.v"
 
module WB_TPRAM
(
// Generic synchronous two-port RAM interface
clk_a,
rst_a,
ce_a,
we_a,
oe_a,
addr_a,
di_a,
do_a,
clk_b,
rst_b,
ce_b,
we_b,
oe_b,
addr_b,
di_b,
do_b
);
 
//
// Default address and data buses width
//
parameter aw = 8;
parameter dw = 40;
 
//
// Generic synchronous two-port RAM interface
//
input clk_a; // Clock
input rst_a; // Reset
input ce_a; // Chip enable input
input we_a; // Write enable input
input oe_a; // Output enable input
input [aw-1:0] addr_a; // address bus inputs
input [dw-1:0] di_a; // input data bus
output [dw-1:0] do_a; // output data bus
input clk_b; // Clock
input rst_b; // Reset
input ce_b; // Chip enable input
input we_b; // Write enable input
input oe_b; // Output enable input
input [aw-1:0] addr_b; // address bus inputs
input [dw-1:0] di_b; // input data bus
output [dw-1:0] do_b; // output data bus
 
//
// Internal wires and registers
//
 
 
`ifdef WB_ARTISAN_SDP
`define RAM_SELECTED
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Double-Port RAM (ra2sh)
//
art_hsdp_256x40 /*#(dw, 1<<aw, aw) */ artisan_sdp
(
.qa(do_a),
.clka(clk_a),
.cena(~ce_a),
.wena(~we_a),
.aa(addr_a),
.da(di_a),
.oena(~oe_a),
.qb(do_b),
.clkb(clk_b),
.cenb(~ce_b),
.wenb(~we_b),
.ab(addr_b),
.db(di_b),
.oenb(~oe_b)
);
 
`endif
 
`ifdef AVANT_ATP
`define RAM_SELECTED
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
.web(~we),
.reb(),
.oeb(~oe),
.rcsb(),
.wcsb(),
.ra(addr),
.wa(addr),
.di(di),
.do(do)
);
 
`endif
 
`ifdef VIRAGE_STP
`define RAM_SELECTED
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 2-port R/W RAM
//
virage_stp virage_stp(
.QA(do_a),
.QB(do_b),
 
.ADRA(addr_a),
.DA(di_a),
.WEA(we_a),
.OEA(oe_a),
.MEA(ce_a),
.CLKA(clk_a),
 
.ADRB(adr_b),
.DB(di_b),
.WEB(we_b),
.OEB(oe_b),
.MEB(ce_b),
.CLKB(clk_b)
);
 
`endif
 
`ifdef WB_XILINX_RAMB4
`define RAM_SELECTED
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
 
//
// Block 0
//
 
RAMB4_S16_S16 ramb4_s16_s16_0(
.CLKA(clk_a),
.RSTA(rst_a),
.ADDRA(addr_a),
.DIA(di_a[15:0]),
.ENA(ce_a),
.WEA(we_a),
.DOA(do_a[15:0]),
 
.CLKB(clk_b),
.RSTB(rst_b),
.ADDRB(addr_b),
.DIB(di_b[15:0]),
.ENB(ce_b),
.WEB(we_b),
.DOB(do_b[15:0])
);
 
//
// Block 1
//
 
RAMB4_S16_S16 ramb4_s16_s16_1(
.CLKA(clk_a),
.RSTA(rst_a),
.ADDRA(addr_a),
.DIA(di_a[31:16]),
.ENA(ce_a),
.WEA(we_a),
.DOA(do_a[31:16]),
 
.CLKB(clk_b),
.RSTB(rst_b),
.ADDRB(addr_b),
.DIB(di_b[31:16]),
.ENB(ce_b),
.WEB(we_b),
.DOB(do_b[31:16])
);
 
//
// Block 2
//
// block ram2 wires - non generic width of block rams
wire [15:0] blk2_di_a = {8'h00, di_a[39:32]} ;
wire [15:0] blk2_di_b = {8'h00, di_b[39:32]} ;
 
wire [15:0] blk2_do_a ;
wire [15:0] blk2_do_b ;
 
assign do_a[39:32] = blk2_do_a[7:0] ;
assign do_b[39:32] = blk2_do_b[7:0] ;
 
RAMB4_S16_S16 ramb4_s16_s16_2(
.CLKA(clk_a),
.RSTA(rst_a),
.ADDRA(addr_a),
.DIA(blk2_di_a),
.ENA(ce_a),
.WEA(we_a),
.DOA(blk2_do_a),
 
.CLKB(clk_b),
.RSTB(rst_b),
.ADDRB(addr_b),
.DIB(blk2_di_b),
.ENB(ce_b),
.WEB(we_b),
.DOB(blk2_do_b)
);
 
`endif
`ifdef WB_XILINX_DIST_RAM
`define RAM_SELECTED
reg [(aw-1):0] out_address ;
always@(posedge clk_b or posedge rst_b)
begin
if ( rst_b )
out_address <= #1 0 ;
else if (ce_b)
out_address <= #1 addr_b ;
end
 
WB_DIST_RAM #(aw) wb_distributed_ram
(
.data_out (do_b),
.we (we_a),
.data_in (di_a),
.read_address (out_address),
.write_address (addr_a),
.wclk (clk_a)
);
`endif
 
`ifdef RAM_SELECTED
`undef RAM_SELECTED
`else
//
// Generic two-port synchronous RAM model
//
 
//
// Generic RAM's registers and wires
//
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
reg [dw-1:0] do_reg_a; // RAM data output register
reg [dw-1:0] do_reg_b; // RAM data output register
 
//
// Data output drivers
//
assign do_a = (oe_a) ? do_reg_a : {dw{1'bz}};
assign do_b = (oe_b) ? do_reg_b : {dw{1'bz}};
 
//
// RAM read and write
//
always @(posedge clk_a)
if (ce_a && !we_a)
do_reg_a <= #1 mem[addr_a];
else if (ce_a && we_a)
mem[addr_a] <= #1 di_a;
 
//
// RAM read and write
//
always @(posedge clk_b)
if (ce_b && !we_b)
do_reg_b <= #1 mem[addr_b];
else if (ce_b && we_b)
mem[addr_b] <= #1 di_b;
`endif
 
// synopsys translate_off
initial
begin
if (dw !== 40)
begin
$display("RAM instantiation error! Expected RAM width %d, actual %h!", 40, dw) ;
$finish ;
end
`ifdef XILINX_RAMB4
if (aw !== 8)
begin
$display("RAM instantiation error! Expected RAM address width %d, actual %h!", 40, aw) ;
$finish ;
end
`endif
// currenlty only artisan ram of depth 256 is supported - they don't provide generic ram models
`ifdef ARTISAN_SDP
if (aw !== 8)
begin
$display("RAM instantiation error! Expected RAM address width %d, actual %h!", 40, aw) ;
$finish ;
end
`endif
end
// synopsys translate_on
 
endmodule
 
`ifdef WB_XILINX_DIST_RAM
module WB_DIST_RAM (data_out, we, data_in, read_address, write_address, wclk);
parameter addr_width = 4 ;
output [39:0] data_out;
input we, wclk;
input [39:0] data_in;
input [addr_width - 1:0] write_address, read_address;
 
wire [3:0] waddr = write_address ;
wire [3:0] raddr = read_address ;
 
RAM16X1D ram00 (.DPO(data_out[0]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[0]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram01 (.DPO(data_out[1]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[1]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram02 (.DPO(data_out[2]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[2]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram03 (.DPO(data_out[3]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[3]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram04 (.DPO(data_out[4]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[4]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram05 (.DPO(data_out[5]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[5]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram06 (.DPO(data_out[6]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[6]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram07 (.DPO(data_out[7]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[7]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram08 (.DPO(data_out[8]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[8]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram09 (.DPO(data_out[9]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[9]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram10 (.DPO(data_out[10]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[10]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram11 (.DPO(data_out[11]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[11]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram12 (.DPO(data_out[12]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[12]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram13 (.DPO(data_out[13]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[13]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram14 (.DPO(data_out[14]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[14]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram15 (.DPO(data_out[15]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[15]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram16 (.DPO(data_out[16]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[16]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram17 (.DPO(data_out[17]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[17]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram18 (.DPO(data_out[18]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[18]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram19 (.DPO(data_out[19]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[19]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram20 (.DPO(data_out[20]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[20]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram21 (.DPO(data_out[21]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[21]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram22 (.DPO(data_out[22]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[22]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram23 (.DPO(data_out[23]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[23]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram24 (.DPO(data_out[24]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[24]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram25 (.DPO(data_out[25]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[25]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram26 (.DPO(data_out[26]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[26]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram27 (.DPO(data_out[27]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[27]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram28 (.DPO(data_out[28]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[28]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram29 (.DPO(data_out[29]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[29]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram30 (.DPO(data_out[30]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[30]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram31 (.DPO(data_out[31]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[31]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram32 (.DPO(data_out[32]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[32]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram33 (.DPO(data_out[33]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[33]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram34 (.DPO(data_out[34]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[34]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram35 (.DPO(data_out[35]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[35]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram36 (.DPO(data_out[36]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[36]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram37 (.DPO(data_out[37]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[37]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram38 (.DPO(data_out[38]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[38]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
RAM16X1D ram39 (.DPO(data_out[39]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[39]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
endmodule
`endif
/trunk/rtl/verilog/pci_io_mux_ad_load_crit.v
0,0 → 1,71
//////////////////////////////////////////////////////////////////////
//// ////
//// File name "pci_io_mux_ad_load_crit.v" ////
//// ////
//// This file is part of the "PCI bridge" project ////
//// http://www.opencores.org/cores/pci/ ////
//// ////
//// Author(s): ////
//// - Miha Dolenc (mihad@opencores.org) ////
//// ////
//// All additional information is avaliable in the README ////
//// file. ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
// module is provided for last level of logic for loading AD output flip-flops
// and output backup flip - flops
module PCI_IO_MUX_AD_LOAD_CRIT
(
load_in,
load_on_transfer_in,
pci_irdy_in,
pci_trdy_in,
load_out
);
 
input load_in,
load_on_transfer_in,
pci_irdy_in,
pci_trdy_in ;
 
output load_out ;
 
assign load_out = load_in || (load_on_transfer_in && ~pci_irdy_in && ~pci_trdy_in) ;
 
endmodule
/trunk/rtl/verilog/async_reset_flop.v
0,0 → 1,88
//===========================================================================
// $Id: async_reset_flop.v,v 1.1 2002-02-01 14:43:31 mihad Exp $
//
//////////////////////////////////////////////////////////////////////
//// ////
//// async_reset_flop ////
//// ////
//// This file is part of the general opencores effort. ////
//// <http://www.opencores.org/cores/misc/> ////
//// ////
//// Module Description: ////
//// ////
//// Make a rising-edge triggered flop with async reset with a ////
//// distinguished name so that it's output can be easily ////
//// traced, because it is used for asynchronous reset of some ////
//// flip-flops. ////
//// ////
//// This flop should be used instead of a regular flop for ALL ////
//// asynchronous-reset generator flops. ////
//// ////
//// To Do: ////
//// Nothing ////
//// ////
//// Author(s): ////
//// - Tadej Markovic, tadej@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
module async_reset_flop (
data_in, clk_in, async_reset_data_out, reset_in
);
 
input data_in;
input clk_in;
output async_reset_data_out;
input reset_in;
 
reg async_reset_data_out;
 
always @(posedge clk_in or posedge reset_in)
begin
if (reset_in)
begin
async_reset_data_out <= #`FF_DELAY 1'b0;
end
else
begin
async_reset_data_out <= #`FF_DELAY data_in;
end
end
 
endmodule
 
/trunk/rtl/verilog/mas_ad_load_crit.v
0,0 → 1,64
//////////////////////////////////////////////////////////////////////
//// ////
//// File name "mas_ad_load_crit.v" ////
//// ////
//// This file is part of the "PCI bridge" project ////
//// http://www.opencores.org/cores/pci/ ////
//// ////
//// Author(s): ////
//// - Miha Dolenc (mihad@opencores.org) ////
//// ////
//// All additional information is avaliable in the README ////
//// file. ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
// module is included for loading output flip - flops by monitoring timing critical GNT pci input
module MAS_AD_LOAD_CRIT
(
ad_load_out,
ad_load_in,
ad_load_on_grant_in,
pci_gnt_in
);
output ad_load_out ;
input ad_load_in,
ad_load_on_grant_in,
pci_gnt_in ;
 
assign ad_load_out = ad_load_in || ( ad_load_on_grant_in && !pci_gnt_in ) ;
endmodule
/trunk/rtl/verilog/pci_constants.v
0,0 → 1,160
//////////////////////////////////////////////////////////////////////
//// ////
//// File name "pci_constants.v" ////
//// ////
//// This file is part of the "PCI bridge" project ////
//// http://www.opencores.org/cores/pci/ ////
//// ////
//// Author(s): ////
//// - Miha Dolenc (mihad@opencores.org) ////
//// - Tadej Markovic (tadej@opencores.org) ////
//// ////
//// All additional information is avaliable in the README.txt ////
//// file. ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2001/10/05 08:14:28 mihad
// Updated all files with inclusion of timescale file for simulation purposes.
//
// Revision 1.1.1.1 2001/10/02 15:33:46 mihad
// New project directory structure
//
 
// first include user definable parameters
`ifdef REGRESSION // Used only for regression testing purposes!!!
`include "pci_regression_constants.v"
`else
`include "pci_user_constants.v"
`endif
 
////////////////////////////////////////////////////////////////////////
//// ////
//// FIFO parameters define behaviour of FIFO control logic and ////
//// FIFO depths. ////
//// ////
////////////////////////////////////////////////////////////////////////
`define WBW_DEPTH (1 << `WBW_ADDR_LENGTH)
`define WBR_DEPTH (1 << `WBR_ADDR_LENGTH)
`define PCIW_DEPTH (1 << `PCIW_ADDR_LENGTH)
`define PCIR_DEPTH (1 << `PCIR_ADDR_LENGTH)
 
// defines on which bit in control bus means what
`define ADDR_CTRL_BIT 3
`define LAST_CTRL_BIT 0
`define DATA_ERROR_CTRL_BIT 1
`define UNUSED_CTRL_BIT 2
`define BURST_BIT 2
 
// MAX Retry counter value for PCI Master state-machine
// This value is 8-bit because of 8-bit retry counter !!!
//`define PCI_RTY_CNT_MAX 8'h08
 
// Value of address mask for WB configuration image. This has to be defined always, since it is a value, that is not changable in runtime.
// !!!!!!!!!!!!!!!!!!!!!!!If this is not defined, WB configuration access will not be possible!!!!!!!!!!!!!!!!!!!!!1
`define WB_AM0 20'hffff_f
 
// PCI target & WB slave ADDRESS names for configuration space !!!
// This does not include address offsets of PCI Header registers - they starts at offset 0 (see PCI spec.)
// ALL VALUES are without 2 LSBits AND there is required that address bit [8] is set while
// accessing this registers, otherwise the configuration header will be accessed !!!
`define P_IMG_CTRL0_ADDR 6'h00 // Address offset = h 100
`define P_BA0_ADDR 6'h01 // Address offset = h 104
`define P_AM0_ADDR 6'h02 // Address offset = h 108
`define P_TA0_ADDR 6'h03 // Address offset = h 10c
`define P_IMG_CTRL1_ADDR 6'h04 // Address offset = h 110
`define P_BA1_ADDR 6'h05 // Address offset = h 114
`define P_AM1_ADDR 6'h06 // Address offset = h 118
`define P_TA1_ADDR 6'h07 // Address offset = h 11c
`define P_IMG_CTRL2_ADDR 6'h08 // Address offset = h 120
`define P_BA2_ADDR 6'h09 // Address offset = h 124
`define P_AM2_ADDR 6'h0a // Address offset = h 128
`define P_TA2_ADDR 6'h0b // Address offset = h 12c
`define P_IMG_CTRL3_ADDR 6'h0c // Address offset = h 130
`define P_BA3_ADDR 6'h0d // Address offset = h 134
`define P_AM3_ADDR 6'h0e // Address offset = h 138
`define P_TA3_ADDR 6'h0f // Address offset = h 13c
`define P_IMG_CTRL4_ADDR 6'h10 // Address offset = h 140
`define P_BA4_ADDR 6'h11 // Address offset = h 144
`define P_AM4_ADDR 6'h12 // Address offset = h 148
`define P_TA4_ADDR 6'h13 // Address offset = h 14c
`define P_IMG_CTRL5_ADDR 6'h14 // Address offset = h 150
`define P_BA5_ADDR 6'h15 // Address offset = h 154
`define P_AM5_ADDR 6'h16 // Address offset = h 158
`define P_TA5_ADDR 6'h17 // Address offset = h 15c
`define P_ERR_CS_ADDR 6'h18 // Address offset = h 160
`define P_ERR_ADDR_ADDR 6'h19 // Address offset = h 164
`define P_ERR_DATA_ADDR 6'h1a // Address offset = h 168
 
`define WB_CONF_SPC_BAR_ADDR 6'h20 // Address offset = h 180
`define W_IMG_CTRL1_ADDR 6'h21 // Address offset = h 184
`define W_BA1_ADDR 6'h22 // Address offset = h 188
`define W_AM1_ADDR 6'h23 // Address offset = h 18c
`define W_TA1_ADDR 6'h24 // Address offset = h 190
`define W_IMG_CTRL2_ADDR 6'h25 // Address offset = h 194
`define W_BA2_ADDR 6'h26 // Address offset = h 198
`define W_AM2_ADDR 6'h27 // Address offset = h 19c
`define W_TA2_ADDR 6'h28 // Address offset = h 1a0
`define W_IMG_CTRL3_ADDR 6'h29 // Address offset = h 1a4
`define W_BA3_ADDR 6'h2a // Address offset = h 1a8
`define W_AM3_ADDR 6'h2b // Address offset = h 1ac
`define W_TA3_ADDR 6'h2c // Address offset = h 1b0
`define W_IMG_CTRL4_ADDR 6'h2d // Address offset = h 1b4
`define W_BA4_ADDR 6'h2e // Address offset = h 1b8
`define W_AM4_ADDR 6'h2f // Address offset = h 1bc
`define W_TA4_ADDR 6'h30 // Address offset = h 1c0
`define W_IMG_CTRL5_ADDR 6'h31 // Address offset = h 1c4
`define W_BA5_ADDR 6'h32 // Address offset = h 1c8
`define W_AM5_ADDR 6'h33 // Address offset = h 1cc
`define W_TA5_ADDR 6'h34 // Address offset = h 1d0
`define W_ERR_CS_ADDR 6'h35 // Address offset = h 1d4
`define W_ERR_ADDR_ADDR 6'h36 // Address offset = h 1d8
`define W_ERR_DATA_ADDR 6'h37 // Address offset = h 1dc
`define CNF_ADDR_ADDR 6'h38 // Address offset = h 1e0
// Following two registers are not implemented in a configuration space but in a WishBone unit!
`define CNF_DATA_ADDR 6'h39 // Address offset = h 1e4
`define INT_ACK_ADDR 6'h3a // Address offset = h 1e8
// -------------------------------------
`define ICR_ADDR 6'h3b // Address offset = h 1ec
`define ISR_ADDR 6'h3c // Address offset = h 1f0
 
`ifdef PCI33
`define HEADER_66MHz 1'b0
`else
`ifdef PCI66
`define HEADER_66MHz 1'b1
`endif
`endif
 
// all flip-flops in the design have this inter-assignment delay
`define FF_DELAY 1
 
/trunk/syn/scr/cons_vs_umc18.inc
0,0 → 1,42
/* Constraints */
CLK_UNCERTAINTY = 0.1 /* 100 ps */
DFFPQ2_CKQ = 0.2 /* Clk to Q in technology time units */
DFFPQ2_SETUP = 0.1 /* Setup time in technology time units */
 
/* Clocks constraints */
set_clock_skew all_clocks() -uncertainty CLK_UNCERTAINTY
set_dont_touch_network all_clocks()
 
/* Reset constraints */
set_driving_cell -none RST
set_drive 0 RST
set_dont_touch_network RST
 
/* All inputs except reset and clock */
all_inputs_wo_rst_clk = all_inputs() - PCI_CLK - WB_CLK - RST
 
/* Set output delays and load for output signals
*
* All outputs are assumed to go directly into
* external flip-flops for the purpose of this
* synthesis
*/
set_load load_of(umcl18u250t2_typ/DFFPQ2/D) * 4 all_outputs()
 
/* Input delay and driving cell of all inputs
*
* All these signals are assumed to come directly from
* flip-flops for the purpose of this synthesis
*
*/
set_driving_cell -cell DFFPQ2 -pin Q all_inputs_wo_rst_clk
 
/* Set design fanout */
/*
set_max_fanout 10 TOPLEVEL
*/
 
/* Set area constraint */
set_max_area MAX_AREA
 
set_operating_conditions -max WORST -max_library umcl18u250t2_wc
trunk/syn/scr/cons_vs_umc18.inc Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/syn/scr/elaborate_design.inc =================================================================== --- trunk/syn/scr/elaborate_design.inc (nonexistent) +++ trunk/syn/scr/elaborate_design.inc (revision 18) @@ -0,0 +1,10 @@ +/* Set search path for verilog include files */ +search_path = search_path + { RTL_PATH } + { GATE_PATH } + +/* Read verilog files of the PCI IP core */ +if (TOPLEVEL == "TOP") { + elaborate TOPLEVEL +} else { + echo "Non-existing top level." + exit +}
trunk/syn/scr/elaborate_design.inc Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/syn/scr/save_design.inc =================================================================== --- trunk/syn/scr/save_design.inc (nonexistent) +++ trunk/syn/scr/save_design.inc (revision 18) @@ -0,0 +1,5 @@ +/* Save current design using synopsys format */ +write -hierarchy -format db -output GATE_PATH + STAGE + _ + TOPLEVEL + .db + +/* Save current design using verilog format */ +write -hierarchy -format verilog -output GATE_PATH + STAGE + _ + TOPLEVEL + .v
trunk/syn/scr/save_design.inc Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/syn/scr/tech_vs_umc18.inc =================================================================== --- trunk/syn/scr/tech_vs_umc18.inc (nonexistent) +++ trunk/syn/scr/tech_vs_umc18.inc (revision 18) @@ -0,0 +1,16 @@ +/* Set Virtual Silicon UMC 0.18u standard cell library */ + +search_path = {. /projects/libs/Virtual_silicon/UMCL18U250D2_2.1/design_compiler/ /projects/libs/Artisan/artisan_rams/art_hsdp_256x40/} +snps = get_unix_variable("SYNOPSYS") +synthetic_library = { \ + snps + "/libraries/syn/dw01.sldb" \ + snps + "/libraries/syn/dw02.sldb" \ + snps + "/libraries/syn/dw03.sldb" \ + snps + "/libraries/syn/dw04.sldb" \ + snps + "/libraries/syn/dw05.sldb" \ + snps + "/libraries/syn/dw06.sldb" \ + snps + "/libraries/syn/dw07.sldb" } +target_library = { umcl18u250t2_bc.db umcl18u250t2_wc.db art_hsdp_256x40_slow_syn.db art_hsdp_256x40_fast_syn.db} +link_library = target_library + synthetic_library +symbol_library = { umcl18u250t2.sdb } +set_min_library umcl18u250t2_wc.db -min_version umcl18u250t2_bc.db
trunk/syn/scr/tech_vs_umc18.inc Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/syn/scr/analyze_design.inc =================================================================== --- trunk/syn/scr/analyze_design.inc (nonexistent) +++ trunk/syn/scr/analyze_design.inc (revision 18) @@ -0,0 +1,67 @@ +/* Set search path for verilog include files */ +search_path = search_path + { RTL_PATH } + { GATE_PATH } + +/* Read verilog files of the PCI IP core */ +if (TOPLEVEL == "TOP") { + analyze -f verilog pci_bridge32.v + analyze -f verilog mas_load_next_crit.v + analyze -f verilog pci_parity_check.v + analyze -f verilog pci_target_unit.v + analyze -f verilog wb_addr_mux.v + analyze -f verilog cbe_en_crit.v + analyze -f verilog fifo_control.v + analyze -f verilog out_reg.v + analyze -f verilog pci_target32_ad_en_crit.v + analyze -f verilog pci_tpram.v + analyze -f verilog wb_master.v + analyze -f verilog conf_cyc_addr_dec.v + analyze -f verilog frame_crit.v + analyze -f verilog par_cbe_crit.v + analyze -f verilog pci_target32_clk_en.v + analyze -f verilog pciw_fifo_control.v + analyze -f verilog wb_slave.v + analyze -f verilog conf_space.v + analyze -f verilog frame_en_crit.v + analyze -f verilog par_crit.v + analyze -f verilog pci_target32_ctrl_en_crit.v + analyze -f verilog pciw_pcir_fifos.v + analyze -f verilog wb_slave_unit.v + analyze -f verilog frame_load_crit.v + analyze -f verilog pci_bridge32.v + analyze -f verilog pci_target32_devs_crit.v + analyze -f verilog perr_crit.v + analyze -f verilog wbr_fifo_control.v + analyze -f verilog cur_out_reg.v + analyze -f verilog io_mux_en_mult.v + analyze -f verilog pci_decoder.v + analyze -f verilog pci_target32_interface.v + analyze -f verilog perr_en_crit.v + analyze -f verilog wbw_fifo_control.v + analyze -f verilog decoder.v + analyze -f verilog io_mux_load_mux.v + analyze -f verilog pci_in_reg.v + analyze -f verilog pci_target32_load_crit.v + analyze -f verilog serr_crit.v + analyze -f verilog wbw_wbr_fifos.v + analyze -f verilog delayed_sync.v + analyze -f verilog irdy_out_crit.v + analyze -f verilog pci_io_mux.v + analyze -f verilog pci_target32_sm.v + analyze -f verilog serr_en_crit.v + analyze -f verilog delayed_write_reg.v + analyze -f verilog mas_ad_en_crit.v + analyze -f verilog pci_master32_sm.v + analyze -f verilog pci_target32_stop_crit.v + analyze -f verilog synchronizer_flop.v + analyze -f verilog mas_ch_state_crit.v + analyze -f verilog pci_master32_sm_if.v + analyze -f verilog pci_target32_trdy_crit.v + analyze -f verilog top.v + analyze -f verilog pci_rst_int.v + analyze -f verilog sync_module.v + analyze -f verilog wb_tpram.v +} else { + echo "Non-existing top level." + exit +} +
trunk/syn/scr/analyze_design.inc Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/syn/scr/reports.inc =================================================================== --- trunk/syn/scr/reports.inc (nonexistent) +++ trunk/syn/scr/reports.inc (revision 18) @@ -0,0 +1,10 @@ +/* Basic reports */ +report_area > LOG_PATH + STAGE + _ + TOPLEVEL + _area.log +report_timing -nworst 1000 > LOG_PATH + STAGE + _ + TOPLEVEL + _timing.log +report_hierarchy > LOG_PATH + STAGE + _ + TOPLEVEL + _hierarchy.log +report_resources > LOG_PATH + STAGE + _ + TOPLEVEL + _resources.log +report_constraint -all_violators > LOG_PATH + STAGE + _ + TOPLEVEL + _constraint.log +/* +report_power > LOG_PATH + STAGE + _ + TOPLEVEL + _power.log +*/ +
trunk/syn/scr/reports.inc Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/syn/scr/top_pci32.scr =================================================================== --- trunk/syn/scr/top_pci32.scr (nonexistent) +++ trunk/syn/scr/top_pci32.scr (revision 18) @@ -0,0 +1,76 @@ +/* + * User defines for synthesizing RTC IP core + * + */ +TOPLEVEL = TOP +include select_tech.inc +PCI_CLK = CLK +WB_CLK = CLK_I +RST = RST_I +PCI_CLK_PERIOD = 15 /* 66 MHz */ +WB_CLK_PERIOD = 5 /* 200 MHz */ +MAX_AREA = 0 /* Push hard */ +DO_UNGROUP = yes /* yes, no */ +DO_VERIFY = no /* yes, no */ +CHECK = no /* yes, no */ + +/* Set some basic variables related to environment */ +include set_env.inc +STAGE = final + +/* Load libraries */ +include tech_ + TECH + .inc + +/* Load HDL source files */ +/*include read_design.inc > LOG_PATH + read_design_ + TOPLEVEL + .log*/ +include analyze_design.inc > LOG_PATH + analyze_design_ + TOPLEVEL + .log +include elaborate_design.inc > LOG_PATH + elaborate_design_ + TOPLEVEL + .log + +/* Set design top */ +current_design TOPLEVEL + +/* Link all blocks and uniquify them */ +link +uniquify + +if (CHECK == "yes"){ +check_design > LOG_PATH + check_design_ + TOPLEVEL + .log +} + +create_clock WB_CLK -period WB_CLK_PERIOD +create_clock PCI_CLK -period PCI_CLK_PERIOD + +/* Apply PCI constraints */ +include cons_pci_ports.inc +include cons_wb_ports.inc + +/* Apply technology constraints */ +if (TECH == "vs_umc18") { + include cons_vs_umc18.inc +} else if (TECH == "art_umc18") { + include cons_art_umc18.inc +} else { + echo "Error: Unsupported technology" + exit +} + +/* Lets do basic synthesis */ +if (DO_UNGROUP == "yes") { + ungroup -all -flatten +} +compile -boundary_optimization -map_effort low + +/* Dump gate-level from incremental synthesis */ +include save_design.inc + +/* Generate reports for incremental synthesis */ +include reports.inc + +/* Verify design */ +if (DO_VERIFY == "yes") { + compile -no_map -verify > LOG_PATH + verify_ + TOPLEVEL + .log +} + +/* Finish */ +sh date +exit
trunk/syn/scr/top_pci32.scr Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/syn/scr/cons_wb_ports.inc =================================================================== --- trunk/syn/scr/cons_wb_ports.inc (nonexistent) +++ trunk/syn/scr/cons_wb_ports.inc (revision 18) @@ -0,0 +1,24 @@ +set_input_delay -max 2 -clock WB_CLK {SDAT_I} +set_input_delay -max 2 -clock WB_CLK {ADR_I} +set_input_delay -max 2 -clock WB_CLK {SDAT_I} +set_input_delay -max 2 -clock WB_CLK {SEL_I} +set_input_delay -max 2 -clock WB_CLK {CYC_I} +set_input_delay -max 2 -clock WB_CLK {STB_I} +set_input_delay -max 2 -clock WB_CLK {CAB_I} +set_input_delay -max 2 -clock WB_CLK {WE_I} + +set_input_delay -max 2 -clock WB_CLK {MDAT_I} +set_input_delay -max 2 -clock WB_CLK {ACK_I} +set_input_delay -max 2 -clock WB_CLK {ERR_I} +set_input_delay -max 2 -clock WB_CLK {RTY_I} + +set_output_delay -max 2 -clock WB_CLK {SDAT_O} +set_output_delay -max 2 -clock WB_CLK {MDAT_O} +set_output_delay -max 2 -clock WB_CLK {ADR_O} +set_output_delay -max 2 -clock WB_CLK {ACK_O} +set_output_delay -max 2 -clock WB_CLK {ERR_O} +set_output_delay -max 2 -clock WB_CLK {RTY_O} +set_output_delay -max 2 -clock WB_CLK {CYC_O} +set_output_delay -max 2 -clock WB_CLK {CAB_O} +set_output_delay -max 2 -clock WB_CLK {WE_O} +set_output_delay -max 2 -clock WB_CLK {STB_O}
trunk/syn/scr/cons_wb_ports.inc Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/syn/scr/select_tech.inc =================================================================== --- trunk/syn/scr/select_tech.inc (nonexistent) +++ trunk/syn/scr/select_tech.inc (revision 18) @@ -0,0 +1,3 @@ +/* Defaults */ + +TECH = vs_umc18 /* vs_umc18, art_umc18 */
trunk/syn/scr/select_tech.inc Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/syn/scr/set_env.inc =================================================================== --- trunk/syn/scr/set_env.inc (nonexistent) +++ trunk/syn/scr/set_env.inc (revision 18) @@ -0,0 +1,18 @@ +/* Enable Verilog HDL preprocessor */ +hdlin_enable_vpp = true + +/* Set log path */ +LOG_PATH = "../logs/" + +/* Set gate-level netlist path */ +GATE_PATH = "../gate/" + +/* Set RAMS_PATH */ +RAMS_PATH = "../../lib/" + +/* Set RTL source path */ +RTL_PATH = "../../rtl/verilog/" + +/* Optimize adders */ +synlib_model_map_effort = high +hlo_share_effort = medium
trunk/syn/scr/set_env.inc Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/syn/scr/cons_pci_ports.inc =================================================================== --- trunk/syn/scr/cons_pci_ports.inc (nonexistent) +++ trunk/syn/scr/cons_pci_ports.inc (revision 18) @@ -0,0 +1,98 @@ +/* PCI input delay constraints definition*/ +if ( PCI_CLK_PERIOD == 15 ){ + + /* 3ns setup time constraint */ + set_input_delay -max 12 -clock PCI_CLK {AD} + set_input_delay -max 12 -clock PCI_CLK {CBE} + set_input_delay -max 12 -clock PCI_CLK {FRAME} + set_input_delay -max 12 -clock PCI_CLK {IRDY} + set_input_delay -max 12 -clock PCI_CLK {IDSEL} + set_input_delay -max 12 -clock PCI_CLK {DEVSEL} + set_input_delay -max 12 -clock PCI_CLK {TRDY} + set_input_delay -max 12 -clock PCI_CLK {STOP} + set_input_delay -max 12 -clock PCI_CLK {PAR} + set_input_delay -max 12 -clock PCI_CLK {PERR} + + /* 0ns hold time constraints */ + set_input_delay -min 0 -clock PCI_CLK {AD} + set_input_delay -min 0 -clock PCI_CLK {CBE} + set_input_delay -min 0 -clock PCI_CLK {FRAME} + set_input_delay -min 0 -clock PCI_CLK {IRDY} + set_input_delay -min 0 -clock PCI_CLK {IDSEL} + set_input_delay -min 0 -clock PCI_CLK {DEVSEL} + set_input_delay -min 0 -clock PCI_CLK {TRDY} + set_input_delay -min 0 -clock PCI_CLK {STOP} + set_input_delay -min 0 -clock PCI_CLK {PAR} + set_input_delay -min 0 -clock PCI_CLK {PERR} + + /* GNT has 5ns constraint */ + set_input_delay -max 10 -clock PCI_CLK {GNT} + set_input_delay -min 0 -clock PCI_CLK {GNT} + + /* 6ns output delay constraints */ + set_output_delay -max 9 -clock PCI_CLK {AD} + set_output_delay -max 9 -clock PCI_CLK {CBE} + set_output_delay -max 9 -clock PCI_CLK {FRAME} + set_output_delay -max 9 -clock PCI_CLK {IRDY} + set_output_delay -max 9 -clock PCI_CLK {DEVSEL} + set_output_delay -max 9 -clock PCI_CLK {TRDY} + set_output_delay -max 9 -clock PCI_CLK {STOP} + set_output_delay -max 9 -clock PCI_CLK {PAR} + set_output_delay -max 9 -clock PCI_CLK {PERR} + set_output_delay -max 9 -clock PCI_CLK {SERR} + set_output_delay -max 9 -clock PCI_CLK {REQ} + +}else if ( PCI_CLK_PERIOD == 30 ){ + + /* 7ns setup time constraint */ + set_input_delay -max 23 -clock PCI_CLK {AD} + set_input_delay -max 23 -clock PCI_CLK {CBE} + set_input_delay -max 23 -clock PCI_CLK {FRAME} + set_input_delay -max 23 -clock PCI_CLK {IRDY} + set_input_delay -max 23 -clock PCI_CLK {IDSEL} + set_input_delay -max 23 -clock PCI_CLK {DEVSEL} + set_input_delay -max 23 -clock PCI_CLK {TRDY} + set_input_delay -max 23 -clock PCI_CLK {STOP} + set_input_delay -max 23 -clock PCI_CLK {PAR} + set_input_delay -max 23 -clock PCI_CLK {PERR} + + /* 0ns hold time constraints */ + set_input_delay -min 0 -clock PCI_CLK {AD} + set_input_delay -min 0 -clock PCI_CLK {CBE} + set_input_delay -min 0 -clock PCI_CLK {FRAME} + set_input_delay -min 0 -clock PCI_CLK {IRDY} + set_input_delay -min 0 -clock PCI_CLK {IDSEL} + set_input_delay -min 0 -clock PCI_CLK {DEVSEL} + set_input_delay -min 0 -clock PCI_CLK {TRDY} + set_input_delay -min 0 -clock PCI_CLK {STOP} + set_input_delay -min 0 -clock PCI_CLK {PAR} + set_input_delay -min 0 -clock PCI_CLK {PERR} + + /* GNT has 10ns constraint */ + set_input_delay -max 20 -clock PCI_CLK {GNT} + set_input_delay -min 0 -clock PCI_CLK {GNT} + + /* 11ns output delay constraints */ + set_output_delay -max 19 -clock PCI_CLK {AD} + set_output_delay -max 19 -clock PCI_CLK {CBE} + set_output_delay -max 19 -clock PCI_CLK {FRAME} + set_output_delay -max 19 -clock PCI_CLK {IRDY} + set_output_delay -max 19 -clock PCI_CLK {DEVSEL} + set_output_delay -max 19 -clock PCI_CLK {TRDY} + set_output_delay -max 19 -clock PCI_CLK {STOP} + set_output_delay -max 19 -clock PCI_CLK {PAR} + set_output_delay -max 19 -clock PCI_CLK {PERR} + set_output_delay -max 19 -clock PCI_CLK {SERR} + + /* REQ has 12ns output delay constraint */ + set_output_delay -max 12 -clock PCI_CLK {REQ} + +}else{ + echo "Error: Unsupported PCI clock period specified!" + exit +} + +set_false_path -from PCI_CLK -to WB_CLK +set_false_path -from WB_CLK -to PCI_CLK +set_false_path -from {bridge/configuration/*} -to {SDAT_O} +
trunk/syn/scr/cons_pci_ports.inc Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/syn/scr/read_design.inc =================================================================== --- trunk/syn/scr/read_design.inc (nonexistent) +++ trunk/syn/scr/read_design.inc (revision 18) @@ -0,0 +1,66 @@ +/* Set search path for verilog include files */ +search_path = search_path + { RTL_PATH } + { GATE_PATH } + +/* Read verilog files of the PCI IP core */ +if (TOPLEVEL == "TOP") { + read -f verilog pci_bridge32.v + read -f verilog mas_load_next_crit.v + read -f verilog pci_parity_check.v + read -f verilog pci_target_unit.v + read -f verilog wb_addr_mux.v + read -f verilog cbe_en_crit.v + read -f verilog fifo_control.v + read -f verilog out_reg.v + read -f verilog pci_target32_ad_en_crit.v + read -f verilog pci_tpram.v + read -f verilog wb_master.v + read -f verilog conf_cyc_addr_dec.v + read -f verilog frame_crit.v + read -f verilog par_cbe_crit.v + read -f verilog pci_target32_clk_en.v + read -f verilog pciw_fifo_control.v + read -f verilog wb_slave.v + read -f verilog conf_space.v + read -f verilog frame_en_crit.v + read -f verilog par_crit.v + read -f verilog pci_target32_ctrl_en_crit.v + read -f verilog pciw_pcir_fifos.v + read -f verilog wb_slave_unit.v + read -f verilog frame_load_crit.v + read -f verilog pci_bridge32.v + read -f verilog pci_target32_devs_crit.v + read -f verilog perr_crit.v + read -f verilog wbr_fifo_control.v + read -f verilog cur_out_reg.v + read -f verilog io_mux_en_mult.v + read -f verilog pci_decoder.v + read -f verilog pci_target32_interface.v + read -f verilog perr_en_crit.v + read -f verilog wbw_fifo_control.v + read -f verilog decoder.v + read -f verilog io_mux_load_mux.v + read -f verilog pci_in_reg.v + read -f verilog pci_target32_load_crit.v + read -f verilog serr_crit.v + read -f verilog wbw_wbr_fifos.v + read -f verilog delayed_sync.v + read -f verilog irdy_out_crit.v + read -f verilog pci_io_mux.v + read -f verilog pci_target32_sm.v + read -f verilog serr_en_crit.v + read -f verilog delayed_write_reg.v + read -f verilog mas_ad_en_crit.v + read -f verilog pci_master32_sm.v + read -f verilog pci_target32_stop_crit.v + read -f verilog synchronizer_flop.v + read -f verilog mas_ch_state_crit.v + read -f verilog pci_master32_sm_if.v + read -f verilog pci_target32_trdy_crit.v + read -f verilog top.v + read -f verilog pci_rst_int.v + read -f verilog wb_tpram.v +} else { + echo "Non-existing top level." + exit +} +
trunk/syn/scr/read_design.inc Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/syn/scr/cons_art_umc18.inc =================================================================== --- trunk/syn/scr/cons_art_umc18.inc (nonexistent) +++ trunk/syn/scr/cons_art_umc18.inc (revision 18) @@ -0,0 +1,51 @@ +/* Constraints */ +CLK_UNCERTAINTY = 0.1 /* 100 ps */ +DFFHQX2_CKQ = 0.2 /* Clk to Q in technology time units */ +DFFHQX2_SETUP = 0.1 /* Setup time in technology time units */ + +/* Clocks constraints */ +create_clock CLK -period CLK_PERIOD +create_clock ECLK -period CLK_PERIOD +set_clock_skew all_clocks() -uncertainty CLK_UNCERTAINTY +set_dont_touch_network all_clocks() + +/* Reset constraints */ +set_driving_cell -none RST +set_drive 0 RST +set_dont_touch_network RST + +/* All inputs except reset and clock */ +all_inputs_wo_rst_clk = all_inputs() - CLK - RST + +/* Set output delays and load for output signals + * + * All outputs are assumed to go directly into + * external flip-flops for the purpose of this + * synthesis + */ +set_output_delay DFFHQX2_SETUP -clock CLK all_outputs() +set_load load_of(typical/DFFHQX2/D) * 1 all_outputs() + +/* Input delay and driving cell of all inputs + * + * All these signals are assumed to come directly from + * flip-flops for the purpose of this synthesis + * + */ +set_input_delay DFFHQX2_CKQ -clock CLK all_inputs_wo_rst_clk +set_driving_cell -cell DFFHQX2 -pin Q all_inputs_wo_rst_clk + +/* Set design fanout */ +/* +set_max_fanout 10 TOPLEVEL +*/ + +/* Set area constraint */ +set_max_area MAX_AREA + +/* Optimize all near-critical paths to give extra slack for layout */ +c_range = CLK_PERIOD * 0.05 +group_path -critical_range c_range -name CLK -to CLK + +/* Operating conditions */ +set_operating_conditions typical
trunk/syn/scr/cons_art_umc18.inc Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property

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