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Rev 17 → Rev 18

/thor/trunk/rtl/verilog/Thor.v
106,9 → 106,9
parameter DBW = 32; // databus width
parameter ABW = 32; // address bus width
parameter RSTCSEG = 52'h0;
parameter RSTPC = 64'hFFFFFFFFFFFFEFF0;
parameter RSTPC = 64'hFFFFFFFFFFFC0000;
parameter STARTUP_POWER = 16'hFFFF;
parameter IMCD = 6'h3E;
parameter IMCD = 6'h30;
localparam AMSB = ABW-1;
parameter QENTRIES = 8;
parameter ALU1BIG = 0;
1051,7 → 1051,7
8'h0D: fnFunc = isn[23:22];
8'h0E: fnFunc = isn[23:22];
8'h0F: fnFunc = isn[23:22];
`INC: fnFunc = isn[24:22];
`INC: fnFunc = {isn[39:37],isn[24:22]};
`TLB: fnFunc = isn[19:16];
`RTS: fnFunc = isn[19:16]; // used to pass a small immediate
`CACHE: fnFunc = isn[31:26];
1229,7 → 1229,7
fnSource2_v = `TRUE;
else
fnSource2_v = `FALSE;
`CACHE,`LCL,`TLB,`LLA,
`CACHE,`LCL,`TLB,`LLA,`LEA,
`LVB,`LVC,`LVH,`LVW,`LVWAR,
`LB,`LBU,`LC,`LCU,`LH,`LHU,`LW,`LWS,`STI,`INC:
fnSource2_v = 1'b1;
1302,7 → 1302,7
fnNumReadPorts = 3'd1;
else
fnNumReadPorts = 3'd2;
`CACHE,`LCL,`TLB,`LLA,
`CACHE,`LCL,`TLB,`LLA,`LEA,
`LB,`LBU,`LC,`LCU,`LH,`LHU,`LW,`LVB,`LVC,`LVH,`LVW,`LVWAR,`LWS,`INC:
fnNumReadPorts = 3'd1;
`JSR,`JSRS,`JSRZ,`SYS,`INT,`RTS,`RTS2,`BR:
1452,7 → 1452,7
);
`endif
 
Thor_icachemem #(DBW) uicm1
Thor_icachemem #(.DBW(DBW),.ABW(ABW)) uicm1
(
.wclk(clk),
.wce(cstate==ICACHE1),
1602,7 → 1602,7
`ADDI,`ADDUI,`SUBI,`SUBUI,
`MULI,`MULUI,`DIVI,`DIVUI,`MODI,`MODUI,
`_2ADDUI,`_4ADDUI,`_8ADDUI,`_16ADDUI,
`ANDI,`ORI,`EORI,`LLA,
`ANDI,`ORI,`EORI,`LLA,`LEA,
`LVB,`LVC,`LVH,`LVW,`LVWAR,
`LB,`LBU,`LC,`LCU,`LH,`LHU,`LW,`LINK:
fnTargetReg = {1'b0,ir[27:22]};
1951,7 → 1951,7
opcode==`LB || opcode==`LBU || opcode==`LC || opcode==`LCU || opcode==`LH || opcode==`LHU || opcode==`LW ||
opcode==`LBX || opcode==`LBUX || opcode==`LCX || opcode==`LCUX || opcode==`LHX || opcode==`LHUX || opcode==`LWX ||
opcode==`LVB || opcode==`LVH || opcode==`LVC || opcode==`LVW || opcode==`LVWAR || opcode==`SWCR ||
opcode==`STP || opcode==`LLA || opcode==`LLAX ||
opcode==`STP || opcode==`LLA || opcode==`LLAX || opcode==`LEA ||
opcode==`CAS || opcode==`LWS || opcode==`STMV || opcode==`STCMP || opcode==`STFND ||
opcode==`STS || opcode==`PUSH || opcode==`POP || opcode==`LINK || opcode==`UNLINK ||
opcode==`JMPI || opcode==`JMPIX ||
2063,7 → 2063,7
else
fnIsIllegal = `FALSE;
8'h43,8'h44,8'h45: fnIsIllegal = `TRUE;
8'h52,8'h56,8'h57,8'h59,8'h5A,8'h5C,8'h5D,8'h5E:
8'h52,8'h56,8'h57,8'h59,8'h5A,8'h5D,8'h5E:
fnIsIllegal = `TRUE;
8'h60,8'h61,8'h62,8'h63,8'h64,8'h65,8'h66,8'h67,8'h68,8'h69:
fnIsIllegal = `TRUE;
2585,7 → 2585,7
`STI: fnImm = {{58{insn[33]}},insn[33:28]};
`PUSH: fnImm = 64'hFFFFFFFFFFFFFFF8; //-8
//`LINK: fnImm = {insn[39:28],3'b000};
`JMPI,`LLA,
`JMPI,`LLA,`LEA,
`LB,`LBU,`LC,`LCU,`LH,`LHU,`LW,`LVB,`LVC,`LVH,`LVW,`LVWAR,
`SB,`SC,`SH,`SW,`SWCR,`LWS,`SWS,`INC,`LCL,`PEA:
fnImm = {{55{insn[36]}},insn[36:28]};
2619,7 → 2619,7
`ifdef STACKOPS
`LINK: fnImm8 = {insn[32:28],3'b000};
`endif
`JMPI,`LLA,
`JMPI,`LLA,`LEA,
`LB,`LBU,`LC,`LCU,`LH,`LHU,`LW,`LVB,`LVC,`LVH,`LVW,`LVWAR,
`SB,`SC,`SH,`SW,`SWCR,`LWS,`SWS,`INC,`LCL,`PEA:
fnImm8 = insn[35:28];
2655,7 → 2655,7
`LBX,`LBUX,`LCX,`LCUX,`LHX,`LHUX,`LWX,
`SBX,`SCX,`SHX,`SWX:
fnImmMSB = insn[47];
`JMPI,`LLA,
`JMPI,`LLA,`LEA,
`LB,`LBU,`LC,`LCU,`LH,`LHU,`LW,`LVB,`LVC,`LVH,`LVW,
`SB,`SC,`SH,`SW,`SWCR,`STI,`LWS,`SWS,`INC,`LCL,`PEA:
fnImmMSB = insn[36];
4233,19 → 4233,19
// What if there's a databus error during the store ?
// set the IQ entry == DONE as soon as the SW is let loose to the memory system
//
if (dram0 == 2'd2 && fnIsStore(dram0_op) && dram0_op != `STS && dram0_op != `STMV) begin
if (dram0 == 2'd2 && fnIsStore(dram0_op) && dram0_op != `STS && dram0_op != `STMV && dram0_op != `SWCR) begin
if ((alu0_v && dram0_id[2:0] == alu0_id[2:0]) || (alu1_v && dram0_id[2:0] == alu1_id[2:0])) panic <= `PANIC_MEMORYRACE;
iqentry_done[ dram0_id[2:0] ] <= `TRUE;
iqentry_cmt [ dram0_id[2:0]] <= `TRUE;
iqentry_out[ dram0_id[2:0] ] <= `FALSE;
end
if (dram1 == 2'd2 && fnIsStore(dram1_op) && dram1_op != `STS && dram1_op != `STMV) begin
if (dram1 == 2'd2 && fnIsStore(dram1_op) && dram1_op != `STS && dram1_op != `STMV && dram1_op != `SWCR) begin
if ((alu0_v && dram1_id[2:0] == alu0_id[2:0]) || (alu1_v && dram1_id[2:0] == alu1_id[2:0])) panic <= `PANIC_MEMORYRACE;
iqentry_done[ dram1_id[2:0] ] <= `TRUE;
iqentry_cmt [ dram1_id[2:0]] <= `TRUE;
iqentry_out[ dram1_id[2:0] ] <= `FALSE;
end
if (dram2 == 2'd2 && fnIsStore(dram2_op) && dram2_op != `STS && dram2_op != `STMV) begin
if (dram2 == 2'd2 && fnIsStore(dram2_op) && dram2_op != `STS && dram2_op != `STMV && dram2_op != `SWCR) begin
if ((alu0_v && dram2_id[2:0] == alu0_id[2:0]) || (alu1_v && dram2_id[2:0] == alu1_id[2:0])) panic <= `PANIC_MEMORYRACE;
iqentry_done[ dram2_id[2:0] ] <= `TRUE;
iqentry_cmt [ dram2_id[2:0]] <= `TRUE;
5695,7 → 5695,7
$stop;
if (fetchbuf0_pc==32'hF44)
$stop;
if (fetchbuf0_pc==32'hFFFFD09B)
if (fetchbuf0_pc==32'hFFFC2F71)
$stop;
`ifdef SEGMENTATION
`ifdef SEGLIMITS
5878,10 → 5878,8
input test_stomp;
input validate_args;
begin
if (`FALSE)
;
// if (opcode0==`NOP)
// queued1 = `TRUE; // to update fetch buffers
if (opcode0==`NOP)
queued1 = `TRUE; // to update fetch buffers
`ifdef DEBUG_LOGIC
else
if (dbg_ctrl[7] && !StatusDBG) begin
5931,7 → 5929,7
$stop;
if (fetchbuf1_pc==32'hF44)
$stop;
if (fetchbuf1_pc==32'hFFFFD09B)
if (fetchbuf1_pc==32'hFFFC2F71)
$stop;
`ifdef SEGMENTATION
`ifdef SEGLIMITS
6047,12 → 6045,10
input test_stomp;
input validate_args;
begin
if (`FALSE)
;
// if (opcode1==`NOP) begin
// if (queued1==`TRUE) queued2 = `TRUE;
// queued1 = `TRUE;
// end
if (opcode1==`NOP) begin
if (queued1==`TRUE) queued2 = `TRUE;
queued1 = `TRUE;
end
`ifdef DEBUG_LOGIC
else
if (dbg_ctrl[7] && !StatusDBG) begin
/thor/trunk/rtl/verilog/Thor_alu.v
288,7 → 288,7
o <= 64'hDEADDEADDEADDEAD;
*/
 
`ADDI,`ADDUI,`ADDUIS:
`ADDI,`ADDUI,`ADDUIS,`LEA:
o <= alu_argA + alu_argI;
`SUBI,`SUBUI:
o <= alu_argA - alu_argI;
/thor/trunk/rtl/verilog/Thor_icachemem.v
1,6 → 1,6
// ============================================================================
// __
// \\__/ o\ (C) 2013,2015 Robert Finch, Stratford
// \\__/ o\ (C) 2013-2016 Robert Finch, Stratford
// \ __ / All rights reserved.
// \/_// robfinch<remove>@finitron.ca
// ||
25,119 → 25,75
//
module Thor_icachemem(wclk, wce, wr, wa, wd, rclk, pc, insn);
parameter DBW=64;
parameter ABW=32;
input wclk;
input wce;
input wr;
input [DBW-1:0] wa;
input [ABW-1:0] wa;
input [DBW-1:0] wd;
input rclk;
input [DBW-1:0] pc;
input [ABW-1:0] pc;
output reg [127:0] insn;
 
wire [127:0] mem0a;
wire [127:0] mem1a;
reg [14:0] pcp16;
wire [127:0] insn0;
wire [127:0] insn1;
 
generate
begin : gen1
if (DBW==32) begin
syncRam2kx32_1w1r uicm0a0 (
.wclk(wclk),
.wce(wce && wa[3:2]==2'b00),
.wr({4{wr}}),
.wa(wa[14:4]),
.wd(wd),
.rclk(rclk),
.rce(1'b1),
.ra(pc[14:4]),
.o(mem0a[31:0])
);
syncRam2kx32_1w1r uicm0a1 (
.wclk(wclk),
.wce(wce && wa[3:2]==2'b01),
.wr({4{wr}}),
.wa(wa[14:4]),
.wd(wd),
.rclk(rclk),
.rce(1'b1),
.ra(pc[14:4]),
.o(mem0a[63:32])
);
syncRam2kx32_1w1r uicm0a2 (
.wclk(wclk),
.wce(wce && wa[3:2]==2'b10),
.wr({4{wr}}),
.wa(wa[14:4]),
.wd(wd),
.rclk(rclk),
.rce(1'b1),
.ra(pc[14:4]),
.o(mem0a[95:64])
);
syncRam2kx32_1w1r uicm0a3 (
.wclk(wclk),
.wce(wce && wa[3:2]==2'b11),
.wr({4{wr}}),
.wa(wa[14:4]),
.wd(wd),
.rclk(rclk),
.rce(1'b1),
.ra(pc[14:4]),
.o(mem0a[127:96])
);
begin : cache_mem
if (DBW==32) begin
blk_mem_gen_0 uicm1 (
.clka(wclk), // input wire clka
.ena(wce), // input wire ena
.wea(wr), // input wire [0 : 0] wea
.addra(wa[14:2]), // input wire [14 : 0] addra
.dina(wd), // input wire [31 : 0] dina
.clkb(rclk), // input wire clkb
.enb(1'b1),
.addrb(pc[14:4]), // input wire [12 : 0] addrb
.doutb(insn0) // output wire [127 : 0] doutb
);
 
syncRam2kx32_1w1r uicm1a0 (
.wclk(wclk),
.wce(wce && wa[3:2]==2'b00),
.wr({4{wr}}),
.wa(wa[14:4]),
.wd(wd),
.rclk(rclk),
.rce(1'b1),
.ra(pcp16[14:4]),
.o(mem1a[31:0])
);
syncRam2kx32_1w1r uicm1a1 (
.wclk(wclk),
.wce(wce && wa[3:2]==2'b01),
.wr({4{wr}}),
.wa(wa[14:4]),
.wd(wd),
.rclk(rclk),
.rce(1'b1),
.ra(pcp16[14:4]),
.o(mem1a[63:32])
);
syncRam2kx32_1w1r uicm1a2 (
.wclk(wclk),
.wce(wce && wa[3:2]==2'b10),
.wr({4{wr}}),
.wa(wa[14:4]),
.wd(wd),
.rclk(rclk),
.rce(1'b1),
.ra(pcp16[14:4]),
.o(mem1a[95:64])
);
syncRam2kx32_1w1r uicm1a3 (
.wclk(wclk),
.wce(wce && wa[3:2]==2'b11),
.wr({4{wr}}),
.wa(wa[14:4]),
.wd(wd),
.rclk(rclk),
.rce(1'b1),
.ra(pcp16[14:4]),
.o(mem1a[127:96])
);
end
blk_mem_gen_0 uicm2 (
.clka(wclk), // input wire clka
.ena(wce), // input wire ena
.wea(wr), // input wire [0 : 0] wea
.addra(wa[14:2]), // input wire [14 : 0] addra
.dina(wd), // input wire [31 : 0] dina
.clkb(rclk), // input wire clkb
.enb(1'b1),
.addrb(pc[14:4]+11'd1), // input wire [12 : 0] addrb
.doutb(insn1) // output wire [127 : 0] doutb
);
end
else begin
blk_mem_gen_1 uicm1 (
.clka(wclk), // input wire clka
.ena(wce), // input wire ena
.wea(wr), // input wire [0 : 0] wea
.addra(wa[14:3]), // input wire [14 : 0] addra
.dina(wd), // input wire [31 : 0] dina
.clkb(rclk), // input wire clkb
.enb(1'b1),
.addrb(pc[14:4]), // input wire [12 : 0] addrb
.doutb(insn0) // output wire [127 : 0] doutb
);
 
blk_mem_gen_1 uicm2 (
.clka(wclk), // input wire clka
.ena(wce), // input wire ena
.wea(wr), // input wire [0 : 0] wea
.addra(wa[14:3]), // input wire [14 : 0] addra
.dina(wd), // input wire [31 : 0] dina
.clkb(rclk), // input wire clkb
.enb(1'b1),
.addrb(pc[14:4]+11'd1), // input wire [12 : 0] addrb
.doutb(insn1) // output wire [127 : 0] doutb
);
end
 
end
endgenerate
 
always @(pc)
pcp16 <= pc[14:0] + 15'd16;
wire [127:0] insn0 = mem0a;
wire [127:0] insn1 = mem1a;
always @(pc or insn0 or insn1)
case(pc[3:0])
4'd0: insn <= insn0;
/thor/trunk/rtl/verilog/Thor_pic.v
141,7 → 141,7
rste <= 16'h0;
end
else begin
rste <= 16'h0;
rste <= 16'h0;
if (cs & we_i) begin
case (adr_i[5:3])
3'd0,3'd1:
149,9 → 149,10
ie[15:0] <= dat_i[15:0];
end
3'd2,3'd3:
ie[dat_i[3:0]] <= adr_i[2];
ie[dat_i[3:0]] <= adr_i[3];
3'd4: es <= dat_i[15:0];
3'd5: rste[dat_i[3:0]] <= 1'b1;
default: ;
endcase
end
end
/thor/trunk/rtl/verilog/Thor_defines.v
121,6 → 121,7
`define ROLI 6'h14
`define RORI 6'h15
`define MODI 8'h5B
`define LEA 8'h5C
`define MODUI 8'h5F
 
`define LLA 8'h6A // compute linear address

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