Subversion Repositories zpu
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Rev 17 → Rev 18
Phi memory map
+The ZPU architecture does not define a memory map as such, but the GCC + libgloss + ecos hal library uses the +memory map below. ++
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+ Address + |
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+ Type + |
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+ Name + |
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+ Description + |
+
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+ 0x080A0000 + |
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+ Write + |
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+ ZPU + enable + |
+
+ Bit + [31:1] Not used +Bit + [0] Enable ZPU operations +0 ZPU + is held in Idle mode +1 ZPU + running + |
+
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+ 0x080A000C + |
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+ Read/ +Write + |
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+ ZPU + UART to ARM7 TX +NOTE! + ZPU side + |
+
+ Bit + [31:9] Not used +Bit + [8] TX buffer ready (valid on ready) +0 TX + buffer not ready (full) +1 TX + buffer ready +Bit + [7:0] TX byte (valid on write) + |
+
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+ 0x080A0010 + |
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+ Read + |
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+ ZPU + UART to ARM7 RX +NOTE! + ZPU side + |
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+ Bit + [31:9] Not used +Bit + [8] RX buffer data valid +0 TX + buffer not valid +1 TX + buffer valid +Bit + [7:0] RX byte (when valid) + |
+
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+ 0x080A0014 + |
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+ Read/ +Write + |
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+ Counter(1) + |
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+ Bit + [0] Reset counter (valid for write) +0 N/A +1 Reset + counter +Bit + [1] Sample counter (valid for write) +0 N/A +1 Sample + counter +Bit + [31:0] Counter bit 31:0 + |
+
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+ 0x080A0018 + |
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+ Read + |
+
+ Counter(2) + |
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+ Bit + [31:0] Counter bit 63:32 + |
+
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+ 0x080A0020 + |
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+ Read + / Write + |
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+ Global_Interrupt_mask + |
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+ Bit + [31:1] Not used +Bit + [0] Global intr. Mask +0 Interrupts + enabled +1 Interrupts + disabled + |
+
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+ 0x080A0024 + |
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+ Write + |
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+ UART_INTERRUPT_ENABLE + |
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+ Bit + [31:1] Not used +Bit + [0] UART RX interrupt enable +0 Interrupt + disable +1 Interrupt + enable + |
+
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+ 0x080A0028 + |
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+ Read +Write + |
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+ UART_interrupt + |
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+ Bit + [31:1] Not used +Bit + [0] UART RX interrupt pending (Read) +0 No + interrupt pending +1 Interrupt + pending +Bit + [0] Clear UART interrupt (Write) +0 N/A +1 Interrupt + cleared + |
+
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+ 0x080A002C + |
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+ Write + |
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+ Timer_Interrupt_enable + |
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+ Bit + [31:1] Not used +Bit + [0] Timer interrupt enable +0 Interrupt + disable +1 Interrupt + enable + |
+
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+ 0x080A0030 + |
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+ Read + / +Write + |
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+ Timer_interrupt + |
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+ Bit + [31:2] Not used +Bit + [0] Timer interrupt pending (Read) +0 No + interrupt pending +1 Interrupt + pending +Bit + [1] Reset Timer counter (Write) +0 N/A +1 Timer + counter reset +Bit + [0] Clear Timer interrupt (Write) +0 N/A +1 Interrupt + cleared + |
+
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+ 0x080A0034 + |
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+ Write + |
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+ Timer_Period + |
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+ Bit + [31:0] Interrupt period (write) +Number + of clock cycles +between + timer interrupts +NOTE! + The timer will start at Timer_Periode value and count down + to zero, and generate an interrupt + |
+
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+ .0x080A0038 + |
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+ Read + |
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+ Timer_Counter + |
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+ Bit + [31:0] Timer counter (read) +
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