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URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

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Rev 171 → Rev 172

/open8_urisc/trunk/VHDL/o8_etc.vhd
23,11 → 23,11
--
-- VHDL Units : o8_etc
-- Description: Provides a 24-bit, 4uS resolution elapsed timer with
-- : alarm and interrupt for the Open8 CPU.
-- : alarm and interrupt for the Open8 CPU.
--
-- Notes : Requires an externally provided uSec tick input - one clock
-- : per microsecond.
--
--
-- Register Map:
-- Offset Bitfield Description Read/Write
-- 0x0 AAAAAAAA B0 of Setpoint (W) and Buffered Time(R)
111,10 → 111,10
Interrupt <= '0';
elsif( rising_edge( Clock ) )then
epoch_tmr <= epoch_tmr + uSec_Tick;
-- Force the lower bits of the setpoint to "11" so that the offset is
-- reduced to 1uS (reproducing the original behavior). Software should
-- always subtract 4uS (-1) from the desired time to compensate
epoch_setpt(1 downto 0) <= "11";
-- Force the lower bits of the setpoint to "11" so that the offset is
-- reduced to 1uS (reproducing the original behavior). Software should
-- always subtract 4uS (-1) from the desired time to compensate
epoch_setpt(1 downto 0) <= "11";
Reg_Addr_q <= Reg_Addr;
Wr_Data_q <= Wr_Data;
 
149,7 → 149,7
 
-- Set and hold on alarm condition
if( (epoch_tmr > epoch_setpt) and (epoch_alarm = '0') )then
epoch_alarm <= '1';
epoch_alarm <= '1';
end if;
 
epoch_alarm_q <= epoch_alarm;
/open8_urisc/trunk/VHDL/o8_gpout.vhd
102,7 → 102,7
end if;
end if;
 
Rd_Data <= (others => '0');
Rd_Data <= (others => '0');
Rd_En <= Addr_Match and Rd_Enable;
if( Rd_En = '1' )then
Rd_Data <= User_Out;
/open8_urisc/trunk/VHDL/o8_vdsm8.vhd
70,12 → 70,12
signal Wr_Data_q : DATA_TYPE;
signal Rd_En : std_logic;
signal DACin : DATA_TYPE;
 
-- DAC WIDTH = 8 is fixed, with all constants normalized
-- against 256 (the MAX PERIOD)
 
constant DAC_WIDTH : integer := 8;
 
constant DELTA_1_I : integer := 1;
constant DELTA_2_I : integer := 5;
constant DELTA_3_I : integer := 25;
146,17 → 146,17
io_reg: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Wr_En <= '0';
Wr_En <= '0';
Wr_Data_q <= x"00";
Rd_En <= '0';
Rd_Data <= x"00";
DACin <= x"00";
DACin <= x"00";
elsif( rising_edge( Clock ) )then
Wr_En <= Addr_Match and Wr_Enable;
Wr_Data_q <= Wr_Data;
if( Wr_En = '1' )then
DACin <= Wr_Data_q;
end if;
DACin <= Wr_Data_q;
end if;
 
Rd_Data <= (others => '0');
Rd_En <= Addr_Match and Rd_Enable;
185,7 → 185,7
(others => '0');
 
Next_Period <= q(7 downto 0) - 1;
 
vDSM_proc: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
/open8_urisc/trunk/VHDL/Open8.vhd
62,7 → 62,7
-- : had no interrupt mask, this should be set to x"FF". Otherwise
-- : it can be initialized to any value. Note that Enable_NMI
-- : will logically force the LSB high.
-- :
-- :
-- : Reset_Level determines whether the processor registers reset
-- : on a high or low level from higher logic.
-- :
116,7 → 116,7
-- :
-- : Seventh, the original CPU model had 8 non-maskable interrupts
-- : with priority. This model has the same 8 interrupts, but
-- : allows software to mask them (with an additional option to
-- : allows software to mask them (with an additional option to
-- : override the highest priority interrupt, making it the NMI.)
-- :
-- : Lastly, previous unmapped instructions in the OP_STK opcode
657,7 → 657,7
ALU_Ctrl.Oper <= ALU_POP;
ALU_Ctrl.Reg <= SubOp;
ALU_Ctrl.Data <= Operand1;
 
-------------------------------------------------------------------------------
-- Subroutines & Interrupts (RTS, JSR)
-------------------------------------------------------------------------------
963,7 → 963,7
-- with the mask. Record any incoming interrupts to the pending buffer
i_Ints := (Interrupts or INT_Ctrl.Soft_Ints) and
Int_Mask;
 
Pending <= i_Ints or Pending;
 
if( Wait_for_FSM = '0' )then
/open8_urisc/trunk/VHDL/Open8_pkg.vhd
39,7 → 39,7
-- External constants and type declarations
--
-- These subtypes can be used with external peripherals to simplify
-- connection to the core.
-- connection to the core.
-------------------------------------------------------------------------------
 
-- These must never be changed, as the core requires them to be these static
79,7 → 79,7
end component;
 
-------------------------------------------------------------------------------
-- Internal constants and type declarations.
-- Internal constants and type declarations.
--
-- These are only used in the actual model, and aren't generally useful for
-- external application.
/open8_urisc/trunk/VHDL/o8_alu16.vhd
97,7 → 97,7
-- 0x1D AAAAAAAA Tolerance (15:8) (RW)
-- 0x1E E---DCBA Status & Flags (RW)
-- A = Zero Flag
-- B = Carry Flag
-- B = Carry Flag
-- C = Negative Flag
-- D = Overflow / Error Flag
-- E = Busy Flag (1 = busy, 0 = idle)
219,7 → 219,7
 
-- Reserved for future use
constant OP_RSVD : std_logic_vector(4 downto 0) := "10110";
 
-- Byte Swap ( U <> L )
constant OP_BSWP : std_logic_vector(4 downto 0) := "10111";
 
495,7 → 495,7
u_accum <= '0' &
Operand_2(7 downto 0) &
Operand_2(15 downto 8);
 
when OP_SMAG =>
s_accum <= S_Operand_2;
if( S_Operand_2 < 0)then
/open8_urisc/trunk/VHDL/o8_rtc.vhd
5,7 → 5,7
-- : to ensure time consistency during accesses. Also provides
-- : a programmable periodic interrupt timer, as well as a uSec
-- : tick for external use.
--
--
-- Register Map:
-- Offset Bitfield Description Read/Write
-- 0x0 AAAAAAAA Periodic Interval Timer in uS (RW)

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