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URL https://opencores.org/ocsvn/funbase_ip_library/funbase_ip_library/trunk

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Rev 176 → Rev 177

/funbase_ip_library/trunk/Altera/ip.hwp.cpu/nios_ii_sdram/2.0/hdl/nios2_sdram.sopcinfo
0,0 → 1,10045
<?xml version="1.0" encoding="UTF-8"?>
<EnsembleReport name="nios2_sdram" kind="nios2_sdram" version="1.0" fabric="QSYS">
<!-- Format version 12.1 177 (Future versions may contain additional information.) -->
<!-- 2013.06.11.13:52:12 -->
<!-- A collection of modules and connections -->
<parameter name="AUTO_GENERATION_ID">
<type>java.lang.Integer</type>
<value>1370947932</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="AUTO_UNIQUE_ID">
<type>java.lang.String</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="AUTO_DEVICE_FAMILY">
<type>java.lang.String</type>
<value>CYCLONEII</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="AUTO_DEVICE">
<type>java.lang.String</type>
<value>EP2C35F672C6</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="AUTO_CLK_CLOCK_RATE">
<type>java.lang.Long</type>
<value>-1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="AUTO_CLK_CLOCK_DOMAIN">
<type>java.lang.Integer</type>
<value>-1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="AUTO_CLK_RESET_DOMAIN">
<type>java.lang.Integer</type>
<value>-1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>Cyclone II</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<module name="clk_0" kind="clock_source" version="12.1" path="clk_0">
<!-- Describes a single module. Module parameters are
the requested settings for a module instance. -->
<parameter name="clockFrequency">
<type>long</type>
<value>50000000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="clockFrequencyKnown">
<type>boolean</type>
<value>true</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="inputClockFrequency">
<type>long</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="resetSynchronousEdges">
<type>com.altera.sopcmodel.reset.Reset$Edges</type>
<value>NONE</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<interface name="clk_in" kind="clock_sink" version="12.1">
<!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
<assignment>
<name>qsys.ui.export_name</name>
<value>clk</value>
</assignment>
<parameter name="externallyDriven">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="ptfSchematicName">
<type>java.lang.String</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="clockRateKnown">
<type>java.lang.Boolean</type>
<value>true</value>
<derived>true</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="clockRate">
<type>java.lang.Long</type>
<value>50000000</value>
<derived>true</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<type>clock</type>
<isStart>false</isStart>
<port>
<name>in_clk</name>
<direction>Input</direction>
<width>1</width>
<role>clk</role>
</port>
</interface>
<interface name="clk_in_reset" kind="reset_sink" version="12.1">
<!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
<assignment>
<name>qsys.ui.export_name</name>
<value>reset</value>
</assignment>
<parameter name="associatedClock">
<type>java.lang.String</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="synchronousEdges">
<type>com.altera.sopcmodel.reset.Reset$Edges</type>
<value>NONE</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<type>reset</type>
<isStart>false</isStart>
<port>
<name>reset_n</name>
<direction>Input</direction>
<width>1</width>
<role>reset_n</role>
</port>
</interface>
<interface name="clk" kind="clock_source" version="12.1">
<!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
<parameter name="associatedDirectClock">
<type>java.lang.String</type>
<value>clk_in</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="clockRate">
<type>long</type>
<value>50000000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="clockRateKnown">
<type>boolean</type>
<value>true</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="externallyDriven">
<type>boolean</type>
<value>true</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="ptfSchematicName">
<type>java.lang.String</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<type>clock</type>
<isStart>true</isStart>
<port>
<name>clk_out</name>
<direction>Output</direction>
<width>1</width>
<role>clk</role>
</port>
<clockDomainMember>
<isBridge>false</isBridge>
<moduleName>sdram_0</moduleName>
<slaveName>clk</slaveName>
<name>sdram_0.clk</name>
</clockDomainMember>
<clockDomainMember>
<isBridge>false</isBridge>
<moduleName>timer_1</moduleName>
<slaveName>clk</slaveName>
<name>timer_1.clk</name>
</clockDomainMember>
<clockDomainMember>
<isBridge>false</isBridge>
<moduleName>timer_0</moduleName>
<slaveName>clk</slaveName>
<name>timer_0.clk</name>
</clockDomainMember>
<clockDomainMember>
<isBridge>false</isBridge>
<moduleName>sysid_qsys_1</moduleName>
<slaveName>clk</slaveName>
<name>sysid_qsys_1.clk</name>
</clockDomainMember>
<clockDomainMember>
<isBridge>false</isBridge>
<moduleName>jtag_uart_1</moduleName>
<slaveName>clk</slaveName>
<name>jtag_uart_1.clk</name>
</clockDomainMember>
<clockDomainMember>
<isBridge>false</isBridge>
<moduleName>onchip_memory2_1</moduleName>
<slaveName>clk2</slaveName>
<name>onchip_memory2_1.clk2</name>
</clockDomainMember>
<clockDomainMember>
<isBridge>false</isBridge>
<moduleName>onchip_memory2_1</moduleName>
<slaveName>clk1</slaveName>
<name>onchip_memory2_1.clk1</name>
</clockDomainMember>
<clockDomainMember>
<isBridge>false</isBridge>
<moduleName>nios2_qsys_1</moduleName>
<slaveName>clk</slaveName>
<name>nios2_qsys_1.clk</name>
</clockDomainMember>
<clockDomainMember>
<isBridge>false</isBridge>
<moduleName>hibi_pe_dma_0</moduleName>
<slaveName>clock</slaveName>
<name>hibi_pe_dma_0.clock</name>
</clockDomainMember>
</interface>
<interface name="clk_reset" kind="reset_source" version="12.1">
<!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
<parameter name="associatedClock">
<type>java.lang.String</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="associatedDirectReset">
<type>java.lang.String</type>
<value>clk_in_reset</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="associatedResetSinks">
<type>[Ljava.lang.String;</type>
<value>clk_in_reset</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="synchronousEdges">
<type>com.altera.sopcmodel.reset.Reset$Edges</type>
<value>NONE</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<type>reset</type>
<isStart>true</isStart>
<port>
<name>reset_n_out</name>
<direction>Output</direction>
<width>1</width>
<role>reset_n</role>
</port>
</interface>
</module>
<module
name="nios2_qsys_1"
kind="altera_nios2_qsys"
version="12.1"
path="nios2_qsys_1">
<!-- Describes a single module. Module parameters are
the requested settings for a module instance. -->
<assignment>
<name>debug.hostConnection</name>
<value>type jtag id 70:34|110:135</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.BIG_ENDIAN</name>
<value>0</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.BREAK_ADDR</name>
<value>0x00002820</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.CPU_FREQ</name>
<value>50000000u</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.CPU_ID_SIZE</name>
<value>24</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.CPU_ID_VALUE</name>
<value>0x01000000</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.CPU_IMPLEMENTATION</name>
<value>"fast"</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.DATA_ADDR_WIDTH</name>
<value>26</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.DCACHE_LINE_SIZE</name>
<value>32</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.DCACHE_LINE_SIZE_LOG2</name>
<value>5</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.DCACHE_SIZE</name>
<value>2048</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.EXCEPTION_ADDR</name>
<value>0x02000020</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.FLUSHDA_SUPPORTED</name>
<value></value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.HARDWARE_DIVIDE_PRESENT</name>
<value>0</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.HARDWARE_MULTIPLY_PRESENT</name>
<value>1</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.HARDWARE_MULX_PRESENT</name>
<value>0</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.HAS_DEBUG_CORE</name>
<value>1</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.HAS_DEBUG_STUB</name>
<value></value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.HAS_JMPI_INSTRUCTION</name>
<value></value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.ICACHE_LINE_SIZE</name>
<value>32</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.ICACHE_LINE_SIZE_LOG2</name>
<value>5</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.ICACHE_SIZE</name>
<value>4096</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.INITDA_SUPPORTED</name>
<value></value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.INST_ADDR_WIDTH</name>
<value>26</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.NUM_OF_SHADOW_REG_SETS</name>
<value>0</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.RESET_ADDR</name>
<value>0x02000000</value>
</assignment>
<assignment>
<name>embeddedsw.configuration.HDLSimCachesCleared</name>
<value>1</value>
</assignment>
<assignment>
<name>embeddedsw.configuration.breakOffset</name>
<value>32</value>
</assignment>
<assignment>
<name>embeddedsw.configuration.breakSlave</name>
<value>nios2_qsys_1.jtag_debug_module</value>
</assignment>
<assignment>
<name>embeddedsw.configuration.cpuArchitecture</name>
<value>Nios II</value>
</assignment>
<assignment>
<name>embeddedsw.configuration.exceptionOffset</name>
<value>32</value>
</assignment>
<assignment>
<name>embeddedsw.configuration.exceptionSlave</name>
<value>sdram_0.s1</value>
</assignment>
<assignment>
<name>embeddedsw.configuration.resetOffset</name>
<value>0</value>
</assignment>
<assignment>
<name>embeddedsw.configuration.resetSlave</name>
<value>sdram_0.s1</value>
</assignment>
<parameter name="setting_showUnpublishedSettings">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="setting_showInternalSettings">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="setting_preciseSlaveAccessErrorException">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="setting_preciseIllegalMemAccessException">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="setting_preciseDivisionErrorException">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>false</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="setting_performanceCounter">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="setting_illegalMemAccessDetection">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="setting_illegalInstructionsTrap">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="setting_fullWaveformSignals">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="setting_extraExceptionInfo">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="setting_exportPCB">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="setting_debugSimGen">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="setting_clearXBitsLDNonBypass">
<type>boolean</type>
<value>true</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="setting_bit31BypassDCache">
<type>boolean</type>
<value>true</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="setting_bigEndian">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="setting_export_large_RAMs">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="setting_asic_enabled">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="setting_asic_synopsys_translate_on_off">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="setting_oci_export_jtag_signals">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="setting_bhtIndexPcOnly">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="setting_avalonDebugPortPresent">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="setting_alwaysEncrypt">
<type>boolean</type>
<value>true</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="setting_allowFullAddressRange">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="setting_activateTrace">
<type>boolean</type>
<value>true</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="setting_activateTestEndChecker">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="setting_activateMonitors">
<type>boolean</type>
<value>true</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="setting_activateModelChecker">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="setting_HDLSimCachesCleared">
<type>boolean</type>
<value>true</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="setting_HBreakTest">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="muldiv_divider">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="mpu_useLimit">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>false</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="mpu_enabled">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="mmu_enabled">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="mmu_autoAssignTlbPtrSz">
<type>boolean</type>
<value>true</value>
<derived>false</derived>
<enabled>false</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="manuallyAssignCpuID">
<type>boolean</type>
<value>true</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="debug_triggerArming">
<type>boolean</type>
<value>true</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="debug_embeddedPLL">
<type>boolean</type>
<value>true</value>
<derived>false</derived>
<enabled>false</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="debug_debugReqSignals">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="debug_assignJtagInstanceID">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="dcache_omitDataMaster">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="cpuReset">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="is_hardcopy_compatible">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="setting_shadowRegisterSets">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="mpu_numOfInstRegion">
<type>int</type>
<value>8</value>
<derived>false</derived>
<enabled>false</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="mpu_numOfDataRegion">
<type>int</type>
<value>8</value>
<derived>false</derived>
<enabled>false</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="mmu_TLBMissExcOffset">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>false</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="debug_jtagInstanceID">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="resetOffset">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="exceptionOffset">
<type>int</type>
<value>32</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="cpuID">
<type>int</type>
<value>16777216</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="cpuID_stored">
<type>int</type>
<value>16777216</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="breakOffset">
<type>int</type>
<value>32</value>
<derived>false</derived>
<enabled>false</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="userDefinedSettings">
<type>java.lang.String</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="resetSlave">
<type>java.lang.String</type>
<value>sdram_0.s1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="mmu_TLBMissExcSlave">
<type>java.lang.String</type>
<value></value>
<derived>false</derived>
<enabled>false</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="exceptionSlave">
<type>java.lang.String</type>
<value>sdram_0.s1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="breakSlave">
<type>java.lang.String</type>
<value>nios2_qsys_1.jtag_debug_module</value>
<derived>false</derived>
<enabled>false</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="setting_perfCounterWidth">
<type>int</type>
<value>32</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="setting_interruptControllerType">
<type>java.lang.String</type>
<value>Internal</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="setting_branchPredictionType">
<type>java.lang.String</type>
<value>Automatic</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="setting_bhtPtrSz">
<type>int</type>
<value>8</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="muldiv_multiplierType">
<type>java.lang.String</type>
<value>EmbeddedMulFast</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="mpu_minInstRegionSize">
<type>int</type>
<value>12</value>
<derived>false</derived>
<enabled>false</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="mpu_minDataRegionSize">
<type>int</type>
<value>12</value>
<derived>false</derived>
<enabled>false</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="mmu_uitlbNumEntries">
<type>int</type>
<value>4</value>
<derived>false</derived>
<enabled>false</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="mmu_udtlbNumEntries">
<type>int</type>
<value>6</value>
<derived>false</derived>
<enabled>false</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="mmu_tlbPtrSz">
<type>int</type>
<value>7</value>
<derived>false</derived>
<enabled>false</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="mmu_tlbNumWays">
<type>int</type>
<value>16</value>
<derived>false</derived>
<enabled>false</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="mmu_processIDNumBits">
<type>int</type>
<value>8</value>
<derived>false</derived>
<enabled>false</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="impl">
<type>java.lang.String</type>
<value>Fast</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="icache_size">
<type>int</type>
<value>4096</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="icache_ramBlockType">
<type>java.lang.String</type>
<value>Automatic</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="icache_numTCIM">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="icache_burstType">
<type>java.lang.String</type>
<value>None</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="dcache_bursts">
<type>java.lang.String</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="debug_level">
<type>java.lang.String</type>
<value>Level1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="debug_OCIOnchipTrace">
<type>java.lang.String</type>
<value>_128</value>
<derived>false</derived>
<enabled>false</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="dcache_size">
<type>int</type>
<value>2048</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="dcache_ramBlockType">
<type>java.lang.String</type>
<value>Automatic</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="dcache_numTCDM">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="dcache_lineSize">
<type>int</type>
<value>32</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="resetAbsoluteAddr">
<type>int</type>
<value>33554432</value>
<derived>true</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="exceptionAbsoluteAddr">
<type>int</type>
<value>33554464</value>
<derived>true</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="breakAbsoluteAddr">
<type>int</type>
<value>10272</value>
<derived>true</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="mmu_TLBMissExcAbsAddr">
<type>int</type>
<value>0</value>
<derived>true</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="translate_on">
<type>java.lang.String</type>
<value> "synthesis translate_on" </value>
<derived>true</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="translate_off">
<type>java.lang.String</type>
<value> "synthesis translate_off" </value>
<derived>true</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="instAddrWidth">
<type>int</type>
<value>26</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="dataAddrWidth">
<type>int</type>
<value>26</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="tightlyCoupledDataMaster0AddrWidth">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="tightlyCoupledDataMaster1AddrWidth">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="tightlyCoupledDataMaster2AddrWidth">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="tightlyCoupledDataMaster3AddrWidth">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="tightlyCoupledInstructionMaster0AddrWidth">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="tightlyCoupledInstructionMaster1AddrWidth">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="tightlyCoupledInstructionMaster2AddrWidth">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="tightlyCoupledInstructionMaster3AddrWidth">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="instSlaveMapParam">
<type>java.lang.String</type>
<value><![CDATA[<address-map><slave name='nios2_qsys_1.jtag_debug_module' start='0x2800' end='0x3000' /><slave name='sdram_0.s1' start='0x2000000' end='0x2800000' /></address-map>]]></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="dataSlaveMapParam">
<type>java.lang.String</type>
<value><![CDATA[<address-map><slave name='onchip_memory2_1.s1' start='0x0' end='0x2000' /><slave name='nios2_qsys_1.jtag_debug_module' start='0x2800' end='0x3000' /><slave name='hibi_pe_dma_0.avalon_slave_0' start='0x3000' end='0x3200' /><slave name='timer_0.s1' start='0x3200' end='0x3220' /><slave name='timer_1.s1' start='0x3220' end='0x3240' /><slave name='sysid_qsys_1.control_slave' start='0x3240' end='0x3248' /><slave name='jtag_uart_1.avalon_jtag_slave' start='0x3248' end='0x3250' /><slave name='sdram_0.s1' start='0x2000000' end='0x2800000' /></address-map>]]></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="clockFrequency">
<type>long</type>
<value>50000000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamilyName">
<type>java.lang.String</type>
<value>CYCLONEII</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="internalIrqMaskSystemInfo">
<type>long</type>
<value>15</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="customInstSlavesSystemInfo">
<type>java.lang.String</type>
<value><![CDATA[<info/>]]></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFeaturesSystemInfo">
<type>java.lang.String</type>
<value>NOT_LISTED 0 INSTALLED 1 IS_DEFAULT_FAMILY 0 ADDRESS_STALL 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 0 HAS_ADVANCED_IO_TIMING_SUPPORT 0 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 1 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 0 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 1 HAS_JITTER_SUPPORT 0 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 1 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 0 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 0 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 1 HAS_SPLIT_IO_SUPPORT 0 HAS_SPLIT_LC_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 0 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 1 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 IS_CONFIG_ROM 0 IS_HARDCOPY_FAMILY 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 1 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 0 MRAM_MEMORY 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 1 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 0 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 1 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 1 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 0 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 0 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 0 USE_ADVANCED_IO_TIMING_BY_DEFAULT 0 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 0 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 0 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="tightlyCoupledDataMaster0MapParam">
<type>java.lang.String</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="tightlyCoupledDataMaster1MapParam">
<type>java.lang.String</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="tightlyCoupledDataMaster2MapParam">
<type>java.lang.String</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="tightlyCoupledDataMaster3MapParam">
<type>java.lang.String</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="tightlyCoupledInstructionMaster0MapParam">
<type>java.lang.String</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="tightlyCoupledInstructionMaster1MapParam">
<type>java.lang.String</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="tightlyCoupledInstructionMaster2MapParam">
<type>java.lang.String</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="tightlyCoupledInstructionMaster3MapParam">
<type>java.lang.String</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<interface name="clk" kind="clock_sink" version="12.1">
<!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
<parameter name="externallyDriven">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="ptfSchematicName">
<type>java.lang.String</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="clockRateKnown">
<type>java.lang.Boolean</type>
<value>true</value>
<derived>true</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="clockRate">
<type>java.lang.Long</type>
<value>50000000</value>
<derived>true</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<type>clock</type>
<isStart>false</isStart>
<port>
<name>clk</name>
<direction>Input</direction>
<width>1</width>
<role>clk</role>
</port>
</interface>
<interface name="reset_n" kind="reset_sink" version="12.1">
<!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
<parameter name="associatedClock">
<type>java.lang.String</type>
<value>clk</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="synchronousEdges">
<type>com.altera.sopcmodel.reset.Reset$Edges</type>
<value>DEASSERT</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<type>reset</type>
<isStart>false</isStart>
<port>
<name>reset_n</name>
<direction>Input</direction>
<width>1</width>
<role>reset_n</role>
</port>
</interface>
<interface name="data_master" kind="avalon_master" version="12.1">
<!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
<assignment>
<name>debug.providesServices</name>
<value>master</value>
</assignment>
<parameter name="adaptsTo">
<type>com.altera.entityinterfaces.IConnectionPoint</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="addressGroup">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="addressUnits">
<type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
<value>SYMBOLS</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="alwaysBurstMaxBurst">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="associatedClock">
<type>java.lang.String</type>
<value>clk</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="associatedReset">
<type>java.lang.String</type>
<value>reset_n</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="bitsPerSymbol">
<type>int</type>
<value>8</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="burstOnBurstBoundariesOnly">
<type>boolean</type>
<value>true</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="burstcountUnits">
<type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
<value>WORDS</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="constantBurstBehavior">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="dBSBigEndian">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="doStreamReads">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="doStreamWrites">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="holdTime">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="interleaveBursts">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="isAsynchronous">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="isBigEndian">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="isReadable">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="isWriteable">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="linewrapBursts">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="maxAddressWidth">
<type>int</type>
<value>32</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="maximumPendingReadTransactions">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="readLatency">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="readWaitTime">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="registerIncomingSignals">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="registerOutgoingSignals">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="setupTime">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="timingUnits">
<type>com.altera.sopcmodel.avalon.TimingUnits</type>
<value>Cycles</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="writeWaitTime">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<type>avalon</type>
<isStart>true</isStart>
<port>
<name>d_address</name>
<direction>Output</direction>
<width>26</width>
<role>address</role>
</port>
<port>
<name>d_byteenable</name>
<direction>Output</direction>
<width>4</width>
<role>byteenable</role>
</port>
<port>
<name>d_read</name>
<direction>Output</direction>
<width>1</width>
<role>read</role>
</port>
<port>
<name>d_readdata</name>
<direction>Input</direction>
<width>32</width>
<role>readdata</role>
</port>
<port>
<name>d_waitrequest</name>
<direction>Input</direction>
<width>1</width>
<role>waitrequest</role>
</port>
<port>
<name>d_write</name>
<direction>Output</direction>
<width>1</width>
<role>write</role>
</port>
<port>
<name>d_writedata</name>
<direction>Output</direction>
<width>32</width>
<role>writedata</role>
</port>
<port>
<name>d_readdatavalid</name>
<direction>Input</direction>
<width>1</width>
<role>readdatavalid</role>
</port>
<port>
<name>jtag_debug_module_debugaccess_to_roms</name>
<direction>Output</direction>
<width>1</width>
<role>debugaccess</role>
</port>
<memoryBlock>
<isBridge>false</isBridge>
<moduleName>nios2_qsys_1</moduleName>
<slaveName>jtag_debug_module</slaveName>
<name>nios2_qsys_1.jtag_debug_module</name>
<baseAddress>10240</baseAddress>
<span>2048</span>
</memoryBlock>
<memoryBlock>
<isBridge>false</isBridge>
<moduleName>jtag_uart_1</moduleName>
<slaveName>avalon_jtag_slave</slaveName>
<name>jtag_uart_1.avalon_jtag_slave</name>
<baseAddress>12872</baseAddress>
<span>8</span>
</memoryBlock>
<memoryBlock>
<isBridge>false</isBridge>
<moduleName>timer_1</moduleName>
<slaveName>s1</slaveName>
<name>timer_1.s1</name>
<baseAddress>12832</baseAddress>
<span>32</span>
</memoryBlock>
<memoryBlock>
<isBridge>false</isBridge>
<moduleName>timer_0</moduleName>
<slaveName>s1</slaveName>
<name>timer_0.s1</name>
<baseAddress>12800</baseAddress>
<span>32</span>
</memoryBlock>
<memoryBlock>
<isBridge>false</isBridge>
<moduleName>sysid_qsys_1</moduleName>
<slaveName>control_slave</slaveName>
<name>sysid_qsys_1.control_slave</name>
<baseAddress>12864</baseAddress>
<span>8</span>
</memoryBlock>
<memoryBlock>
<isBridge>false</isBridge>
<moduleName>sdram_0</moduleName>
<slaveName>s1</slaveName>
<name>sdram_0.s1</name>
<baseAddress>33554432</baseAddress>
<span>8388608</span>
</memoryBlock>
<memoryBlock>
<isBridge>false</isBridge>
<moduleName>onchip_memory2_1</moduleName>
<slaveName>s1</slaveName>
<name>onchip_memory2_1.s1</name>
<baseAddress>0</baseAddress>
<span>8192</span>
</memoryBlock>
<memoryBlock>
<isBridge>false</isBridge>
<moduleName>hibi_pe_dma_0</moduleName>
<slaveName>avalon_slave_0</slaveName>
<name>hibi_pe_dma_0.avalon_slave_0</name>
<baseAddress>12288</baseAddress>
<span>512</span>
</memoryBlock>
</interface>
<interface name="instruction_master" kind="avalon_master" version="12.1">
<!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
<parameter name="adaptsTo">
<type>com.altera.entityinterfaces.IConnectionPoint</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="addressGroup">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="addressUnits">
<type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
<value>SYMBOLS</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="alwaysBurstMaxBurst">
<type>boolean</type>
<value>true</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="associatedClock">
<type>java.lang.String</type>
<value>clk</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="associatedReset">
<type>java.lang.String</type>
<value>reset_n</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="bitsPerSymbol">
<type>int</type>
<value>8</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="burstOnBurstBoundariesOnly">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="burstcountUnits">
<type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
<value>WORDS</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="constantBurstBehavior">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="dBSBigEndian">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="doStreamReads">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="doStreamWrites">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="holdTime">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="interleaveBursts">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="isAsynchronous">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="isBigEndian">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="isReadable">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="isWriteable">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="linewrapBursts">
<type>boolean</type>
<value>true</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="maxAddressWidth">
<type>int</type>
<value>32</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="maximumPendingReadTransactions">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="readLatency">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="readWaitTime">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="registerIncomingSignals">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="registerOutgoingSignals">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="setupTime">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="timingUnits">
<type>com.altera.sopcmodel.avalon.TimingUnits</type>
<value>Cycles</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="writeWaitTime">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<type>avalon</type>
<isStart>true</isStart>
<port>
<name>i_address</name>
<direction>Output</direction>
<width>26</width>
<role>address</role>
</port>
<port>
<name>i_read</name>
<direction>Output</direction>
<width>1</width>
<role>read</role>
</port>
<port>
<name>i_readdata</name>
<direction>Input</direction>
<width>32</width>
<role>readdata</role>
</port>
<port>
<name>i_waitrequest</name>
<direction>Input</direction>
<width>1</width>
<role>waitrequest</role>
</port>
<port>
<name>i_readdatavalid</name>
<direction>Input</direction>
<width>1</width>
<role>readdatavalid</role>
</port>
<memoryBlock>
<isBridge>false</isBridge>
<moduleName>nios2_qsys_1</moduleName>
<slaveName>jtag_debug_module</slaveName>
<name>nios2_qsys_1.jtag_debug_module</name>
<baseAddress>10240</baseAddress>
<span>2048</span>
</memoryBlock>
<memoryBlock>
<isBridge>false</isBridge>
<moduleName>sdram_0</moduleName>
<slaveName>s1</slaveName>
<name>sdram_0.s1</name>
<baseAddress>33554432</baseAddress>
<span>8388608</span>
</memoryBlock>
</interface>
<interface name="d_irq" kind="interrupt_receiver" version="12.1">
<!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
<parameter name="associatedAddressablePoint">
<type>com.altera.entityinterfaces.IConnectionPoint</type>
<value>nios2_qsys_1.data_master</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="associatedClock">
<type>java.lang.String</type>
<value>clk</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="associatedReset">
<type>java.lang.String</type>
<value>reset_n</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="irqScheme">
<type>com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme</type>
<value>INDIVIDUAL_REQUESTS</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<type>interrupt</type>
<isStart>true</isStart>
<port>
<name>d_irq</name>
<direction>Input</direction>
<width>32</width>
<role>irq</role>
</port>
<interrupt>
<isBridge>false</isBridge>
<moduleName>jtag_uart_1</moduleName>
<slaveName>irq</slaveName>
<name>jtag_uart_1.irq</name>
<interruptNumber>0</interruptNumber>
</interrupt>
<interrupt>
<isBridge>false</isBridge>
<moduleName>timer_1</moduleName>
<slaveName>irq</slaveName>
<name>timer_1.irq</name>
<interruptNumber>1</interruptNumber>
</interrupt>
<interrupt>
<isBridge>false</isBridge>
<moduleName>timer_0</moduleName>
<slaveName>irq</slaveName>
<name>timer_0.irq</name>
<interruptNumber>2</interruptNumber>
</interrupt>
<interrupt>
<isBridge>false</isBridge>
<moduleName>hibi_pe_dma_0</moduleName>
<slaveName>interrupt_sender</slaveName>
<name>hibi_pe_dma_0.interrupt_sender</name>
<interruptNumber>3</interruptNumber>
</interrupt>
</interface>
<interface name="jtag_debug_module_reset" kind="reset_source" version="12.1">
<!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
<parameter name="associatedClock">
<type>java.lang.String</type>
<value>clk</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="associatedDirectReset">
<type>java.lang.String</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="associatedResetSinks">
<type>[Ljava.lang.String;</type>
<value>none</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="synchronousEdges">
<type>com.altera.sopcmodel.reset.Reset$Edges</type>
<value>DEASSERT</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<type>reset</type>
<isStart>true</isStart>
<port>
<name>jtag_debug_module_resetrequest</name>
<direction>Output</direction>
<width>1</width>
<role>reset</role>
</port>
</interface>
<interface name="jtag_debug_module" kind="avalon_slave" version="12.1">
<!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
<assignment>
<name>embeddedsw.configuration.hideDevice</name>
<value>1</value>
</assignment>
<assignment>
<name>embeddedsw.configuration.isFlash</name>
<value>0</value>
</assignment>
<assignment>
<name>embeddedsw.configuration.isMemoryDevice</name>
<value>1</value>
</assignment>
<assignment>
<name>embeddedsw.configuration.isNonVolatileStorage</name>
<value>0</value>
</assignment>
<assignment>
<name>embeddedsw.configuration.isPrintableDevice</name>
<value>0</value>
</assignment>
<assignment>
<name>qsys.ui.connect</name>
<value>instruction_master,data_master</value>
</assignment>
<parameter name="addressAlignment">
<type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
<value>DYNAMIC</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="addressGroup">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="addressSpan">
<type>java.math.BigInteger</type>
<value>2048</value>
<derived>true</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="addressUnits">
<type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
<value>WORDS</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="alwaysBurstMaxBurst">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="associatedClock">
<type>java.lang.String</type>
<value>clk</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="associatedReset">
<type>java.lang.String</type>
<value>reset_n</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="bitsPerSymbol">
<type>int</type>
<value>8</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="bridgesToMaster">
<type>com.altera.entityinterfaces.IConnectionPoint</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="burstOnBurstBoundariesOnly">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="burstcountUnits">
<type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
<value>WORDS</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="constantBurstBehavior">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="explicitAddressSpan">
<type>java.math.BigInteger</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="holdTime">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="interleaveBursts">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="isBigEndian">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="isFlash">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="isMemoryDevice">
<type>boolean</type>
<value>true</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="isNonVolatileStorage">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="linewrapBursts">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="maximumPendingReadTransactions">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>false</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="minimumUninterruptedRunLength">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="printableDevice">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="readLatency">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="readWaitStates">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="readWaitTime">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="registerIncomingSignals">
<type>boolean</type>
<value>true</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="registerOutgoingSignals">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="setupTime">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="timingUnits">
<type>com.altera.sopcmodel.avalon.TimingUnits</type>
<value>Cycles</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="transparentBridge">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="wellBehavedWaitrequest">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="writeLatency">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="writeWaitStates">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="writeWaitTime">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<type>avalon</type>
<isStart>false</isStart>
<port>
<name>jtag_debug_module_address</name>
<direction>Input</direction>
<width>9</width>
<role>address</role>
</port>
<port>
<name>jtag_debug_module_begintransfer</name>
<direction>Input</direction>
<width>1</width>
<role>begintransfer</role>
</port>
<port>
<name>jtag_debug_module_byteenable</name>
<direction>Input</direction>
<width>4</width>
<role>byteenable</role>
</port>
<port>
<name>jtag_debug_module_debugaccess</name>
<direction>Input</direction>
<width>1</width>
<role>debugaccess</role>
</port>
<port>
<name>jtag_debug_module_readdata</name>
<direction>Output</direction>
<width>32</width>
<role>readdata</role>
</port>
<port>
<name>jtag_debug_module_select</name>
<direction>Input</direction>
<width>1</width>
<role>chipselect</role>
</port>
<port>
<name>jtag_debug_module_write</name>
<direction>Input</direction>
<width>1</width>
<role>write</role>
</port>
<port>
<name>jtag_debug_module_writedata</name>
<direction>Input</direction>
<width>32</width>
<role>writedata</role>
</port>
</interface>
<interface
name="custom_instruction_master"
kind="nios_custom_instruction_master"
version="12.1">
<!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
<parameter name="CIName">
<type>java.lang.String</type>
<value></value>
<derived>true</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="addressWidth">
<type>int</type>
<value>8</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="clockCycle">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>false</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="enabled">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="maxAddressWidth">
<type>int</type>
<value>8</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="opcodeExtension">
<type>int</type>
<value>0</value>
<derived>true</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="sharedCombinationalAndMulticycle">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<type>nios_custom_instruction</type>
<isStart>true</isStart>
<port>
<name>no_ci_readra</name>
<direction>Output</direction>
<width>1</width>
<role>readra</role>
</port>
</interface>
</module>
<module
name="onchip_memory2_1"
kind="altera_avalon_onchip_memory2"
version="12.1"
path="onchip_memory2_1">
<!-- Describes a single module. Module parameters are
the requested settings for a module instance. -->
<assignment>
<name>embeddedsw.CMacro.ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE</name>
<value>0</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.INIT_CONTENTS_FILE</name>
<value>"onchip_memory2_1"</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.NON_DEFAULT_INIT_FILE_ENABLED</name>
<value>0</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.GUI_RAM_BLOCK_TYPE</name>
<value>"Automatic"</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.WRITABLE</name>
<value>1</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.DUAL_PORT</name>
<value>1</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.SINGLE_CLOCK_OP</name>
<value>0</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.SIZE_VALUE</name>
<value>8192u</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.SIZE_MULTIPLE</name>
<value>1</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.CONTENTS_INFO</name>
<value>""</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.RAM_BLOCK_TYPE</name>
<value>"Auto"</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.INIT_MEM_CONTENT</name>
<value>1</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR</name>
<value>0</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.INSTANCE_ID</name>
<value>"NONE"</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.READ_DURING_WRITE_MODE</name>
<value>"DONT_CARE"</value>
</assignment>
<assignment>
<name>embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH</name>
<value>32</value>
</assignment>
<assignment>
<name>embeddedsw.memoryInfo.HAS_BYTE_LANE</name>
<value>0</value>
</assignment>
<assignment>
<name>embeddedsw.memoryInfo.GENERATE_HEX</name>
<value>1</value>
</assignment>
<assignment>
<name>embeddedsw.memoryInfo.HEX_INSTALL_DIR</name>
<value>QPF_DIR</value>
</assignment>
<assignment>
<name>embeddedsw.memoryInfo.GENERATE_DAT_SYM</name>
<value>1</value>
</assignment>
<assignment>
<name>embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR</name>
<value>SIM_DIR</value>
</assignment>
<assignment>
<name>embeddedsw.memoryInfo.MEM_INIT_FILENAME</name>
<value>nios2_sdram_onchip_memory2_1</value>
</assignment>
<assignment>
<name>postgeneration.simulation.init_file.param_name</name>
<value>INIT_FILE</value>
</assignment>
<assignment>
<name>postgeneration.simulation.init_file.type</name>
<value>MEM_INIT</value>
</assignment>
<parameter name="allowInSystemMemoryContentEditor">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="autoInitializationFileName">
<type>java.lang.String</type>
<value>nios2_sdram_onchip_memory2_1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="blockType">
<type>com.altera.sopcmodel.components.avalon.AlteraAvalonOnchipMemory.AlteraAvalonOnchipMemory$BlockType</type>
<value>AUTO</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="dataWidth">
<type>int</type>
<value>32</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>CYCLONEII</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="dualPort">
<type>boolean</type>
<value>true</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="initMemContent">
<type>boolean</type>
<value>true</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="initializationFileName">
<type>java.lang.String</type>
<value>onchip_memory2_1</value>
<derived>false</derived>
<enabled>false</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="instanceID">
<type>java.lang.String</type>
<value>NONE</value>
<derived>false</derived>
<enabled>false</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="memorySize">
<type>long</type>
<value>8192</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="readDuringWriteMode">
<type>com.altera.sopcmodel.components.avalon.AlteraAvalonOnchipMemory.AlteraAvalonOnchipMemory$ReadDuringWriteMode</type>
<value>DONT_CARE</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="simAllowMRAMContentsFile">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="simMemInitOnlyFilename">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="singleClockOperation">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="slave1Latency">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="slave2Latency">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="useNonDefaultInitFile">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="useShallowMemBlocks">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>false</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="writable">
<type>boolean</type>
<value>true</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<interface name="clk1" kind="clock_sink" version="12.1">
<!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
<parameter name="externallyDriven">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="ptfSchematicName">
<type>java.lang.String</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<type>clock</type>
<isStart>false</isStart>
<port>
<name>clk</name>
<direction>Input</direction>
<width>1</width>
<role>clk</role>
</port>
</interface>
<interface name="s1" kind="avalon_slave" version="12.1">
<!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
<assignment>
<name>embeddedsw.configuration.isMemoryDevice</name>
<value>1</value>
</assignment>
<assignment>
<name>embeddedsw.configuration.isNonVolatileStorage</name>
<value>0</value>
</assignment>
<parameter name="addressAlignment">
<type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
<value>DYNAMIC</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="addressGroup">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="addressSpan">
<type>java.math.BigInteger</type>
<value>8192</value>
<derived>true</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="addressUnits">
<type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
<value>WORDS</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="alwaysBurstMaxBurst">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="associatedClock">
<type>java.lang.String</type>
<value>clk1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="associatedReset">
<type>java.lang.String</type>
<value>reset1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="bitsPerSymbol">
<type>int</type>
<value>8</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="bridgesToMaster">
<type>com.altera.entityinterfaces.IConnectionPoint</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="burstOnBurstBoundariesOnly">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="burstcountUnits">
<type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
<value>WORDS</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="constantBurstBehavior">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="explicitAddressSpan">
<type>java.math.BigInteger</type>
<value>8192</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="holdTime">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="interleaveBursts">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="isBigEndian">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="isFlash">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="isMemoryDevice">
<type>boolean</type>
<value>true</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="isNonVolatileStorage">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="linewrapBursts">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="maximumPendingReadTransactions">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>false</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="minimumUninterruptedRunLength">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="printableDevice">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="readLatency">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="readWaitStates">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="readWaitTime">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="registerIncomingSignals">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="registerOutgoingSignals">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="setupTime">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="timingUnits">
<type>com.altera.sopcmodel.avalon.TimingUnits</type>
<value>Cycles</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="transparentBridge">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="wellBehavedWaitrequest">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="writeLatency">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="writeWaitStates">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="writeWaitTime">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<type>avalon</type>
<isStart>false</isStart>
<port>
<name>address</name>
<direction>Input</direction>
<width>11</width>
<role>address</role>
</port>
<port>
<name>chipselect</name>
<direction>Input</direction>
<width>1</width>
<role>chipselect</role>
</port>
<port>
<name>clken</name>
<direction>Input</direction>
<width>1</width>
<role>clken</role>
</port>
<port>
<name>readdata</name>
<direction>Output</direction>
<width>32</width>
<role>readdata</role>
</port>
<port>
<name>write</name>
<direction>Input</direction>
<width>1</width>
<role>write</role>
</port>
<port>
<name>writedata</name>
<direction>Input</direction>
<width>32</width>
<role>writedata</role>
</port>
<port>
<name>byteenable</name>
<direction>Input</direction>
<width>4</width>
<role>byteenable</role>
</port>
</interface>
<interface name="reset1" kind="reset_sink" version="12.1">
<!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
<parameter name="associatedClock">
<type>java.lang.String</type>
<value>clk1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="synchronousEdges">
<type>com.altera.sopcmodel.reset.Reset$Edges</type>
<value>DEASSERT</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<type>reset</type>
<isStart>false</isStart>
<port>
<name>reset</name>
<direction>Input</direction>
<width>1</width>
<role>reset</role>
</port>
</interface>
<interface name="s2" kind="avalon_slave" version="12.1">
<!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
<assignment>
<name>embeddedsw.configuration.isMemoryDevice</name>
<value>1</value>
</assignment>
<assignment>
<name>embeddedsw.configuration.isNonVolatileStorage</name>
<value>0</value>
</assignment>
<parameter name="addressAlignment">
<type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
<value>DYNAMIC</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="addressGroup">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="addressSpan">
<type>java.math.BigInteger</type>
<value>8192</value>
<derived>true</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="addressUnits">
<type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
<value>WORDS</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="alwaysBurstMaxBurst">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="associatedClock">
<type>java.lang.String</type>
<value>clk2</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="associatedReset">
<type>java.lang.String</type>
<value>reset2</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="bitsPerSymbol">
<type>int</type>
<value>8</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="bridgesToMaster">
<type>com.altera.entityinterfaces.IConnectionPoint</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="burstOnBurstBoundariesOnly">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="burstcountUnits">
<type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
<value>WORDS</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="constantBurstBehavior">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="explicitAddressSpan">
<type>java.math.BigInteger</type>
<value>8192</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="holdTime">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="interleaveBursts">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="isBigEndian">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="isFlash">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="isMemoryDevice">
<type>boolean</type>
<value>true</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="isNonVolatileStorage">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="linewrapBursts">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="maximumPendingReadTransactions">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>false</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="minimumUninterruptedRunLength">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="printableDevice">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="readLatency">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="readWaitStates">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="readWaitTime">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="registerIncomingSignals">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="registerOutgoingSignals">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="setupTime">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="timingUnits">
<type>com.altera.sopcmodel.avalon.TimingUnits</type>
<value>Cycles</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="transparentBridge">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="wellBehavedWaitrequest">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="writeLatency">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="writeWaitStates">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="writeWaitTime">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<type>avalon</type>
<isStart>false</isStart>
<port>
<name>address2</name>
<direction>Input</direction>
<width>11</width>
<role>address</role>
</port>
<port>
<name>chipselect2</name>
<direction>Input</direction>
<width>1</width>
<role>chipselect</role>
</port>
<port>
<name>clken2</name>
<direction>Input</direction>
<width>1</width>
<role>clken</role>
</port>
<port>
<name>readdata2</name>
<direction>Output</direction>
<width>32</width>
<role>readdata</role>
</port>
<port>
<name>write2</name>
<direction>Input</direction>
<width>1</width>
<role>write</role>
</port>
<port>
<name>writedata2</name>
<direction>Input</direction>
<width>32</width>
<role>writedata</role>
</port>
<port>
<name>byteenable2</name>
<direction>Input</direction>
<width>4</width>
<role>byteenable</role>
</port>
</interface>
<interface name="clk2" kind="clock_sink" version="12.1">
<!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
<parameter name="externallyDriven">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="ptfSchematicName">
<type>java.lang.String</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<type>clock</type>
<isStart>false</isStart>
<port>
<name>clk2</name>
<direction>Input</direction>
<width>1</width>
<role>clk</role>
</port>
</interface>
<interface name="reset2" kind="reset_sink" version="12.1">
<!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
<parameter name="associatedClock">
<type>java.lang.String</type>
<value>clk2</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="synchronousEdges">
<type>com.altera.sopcmodel.reset.Reset$Edges</type>
<value>DEASSERT</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<type>reset</type>
<isStart>false</isStart>
<port>
<name>reset2</name>
<direction>Input</direction>
<width>1</width>
<role>reset</role>
</port>
</interface>
</module>
<module
name="jtag_uart_1"
kind="altera_avalon_jtag_uart"
version="12.1"
path="jtag_uart_1">
<!-- Describes a single module. Module parameters are
the requested settings for a module instance. -->
<assignment>
<name>embeddedsw.CMacro.WRITE_DEPTH</name>
<value>64</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.READ_DEPTH</name>
<value>64</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.WRITE_THRESHOLD</name>
<value>8</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.READ_THRESHOLD</name>
<value>8</value>
</assignment>
<parameter name="allowMultipleConnections">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="avalonSpec">
<type>java.lang.String</type>
<value>2.0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="hubInstanceID">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="legacySignalAllow">
<type>boolean</type>
<value>false</value>
<derived>true</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="readBufferDepth">
<type>int</type>
<value>64</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="readIRQThreshold">
<type>int</type>
<value>8</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="simInputCharacterStream">
<type>java.lang.String</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="simInteractiveOptions">
<type>com.altera.sopcmodel.components.avalon.AlteraAvalonJtagUART.AlteraAvalonJtagUART$JtagSimulationOptions</type>
<value>INTERACTIVE_ASCII_OUTPUT</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="useRegistersForReadBuffer">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="useRegistersForWriteBuffer">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="useRelativePathForSimFile">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="writeBufferDepth">
<type>int</type>
<value>64</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="writeIRQThreshold">
<type>int</type>
<value>8</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<interface name="clk" kind="clock_sink" version="12.1">
<!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
<parameter name="externallyDriven">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="ptfSchematicName">
<type>java.lang.String</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<type>clock</type>
<isStart>false</isStart>
<port>
<name>clk</name>
<direction>Input</direction>
<width>1</width>
<role>clk</role>
</port>
</interface>
<interface name="reset" kind="reset_sink" version="12.1">
<!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
<parameter name="associatedClock">
<type>java.lang.String</type>
<value>clk</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="synchronousEdges">
<type>com.altera.sopcmodel.reset.Reset$Edges</type>
<value>DEASSERT</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<type>reset</type>
<isStart>false</isStart>
<port>
<name>rst_n</name>
<direction>Input</direction>
<width>1</width>
<role>reset_n</role>
</port>
</interface>
<interface name="avalon_jtag_slave" kind="avalon_slave" version="12.1">
<!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
<assignment>
<name>embeddedsw.configuration.isPrintableDevice</name>
<value>1</value>
</assignment>
<parameter name="addressAlignment">
<type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
<value>NATIVE</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="addressGroup">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="addressSpan">
<type>java.math.BigInteger</type>
<value>2</value>
<derived>true</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="addressUnits">
<type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
<value>WORDS</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="alwaysBurstMaxBurst">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="associatedClock">
<type>java.lang.String</type>
<value>clk</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="associatedReset">
<type>java.lang.String</type>
<value>reset</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="bitsPerSymbol">
<type>int</type>
<value>8</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="bridgesToMaster">
<type>com.altera.entityinterfaces.IConnectionPoint</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="burstOnBurstBoundariesOnly">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="burstcountUnits">
<type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
<value>WORDS</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="constantBurstBehavior">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="explicitAddressSpan">
<type>java.math.BigInteger</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="holdTime">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>false</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="interleaveBursts">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="isBigEndian">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="isFlash">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="isMemoryDevice">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="isNonVolatileStorage">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="linewrapBursts">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="maximumPendingReadTransactions">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>false</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="minimumUninterruptedRunLength">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="printableDevice">
<type>boolean</type>
<value>true</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="readLatency">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="readWaitStates">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="readWaitTime">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>false</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="registerIncomingSignals">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="registerOutgoingSignals">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="setupTime">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>false</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="timingUnits">
<type>com.altera.sopcmodel.avalon.TimingUnits</type>
<value>Cycles</value>
<derived>false</derived>
<enabled>false</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="transparentBridge">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="wellBehavedWaitrequest">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="writeLatency">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="writeWaitStates">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="writeWaitTime">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>false</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<type>avalon</type>
<isStart>false</isStart>
<port>
<name>av_chipselect</name>
<direction>Input</direction>
<width>1</width>
<role>chipselect</role>
</port>
<port>
<name>av_address</name>
<direction>Input</direction>
<width>1</width>
<role>address</role>
</port>
<port>
<name>av_read_n</name>
<direction>Input</direction>
<width>1</width>
<role>read_n</role>
</port>
<port>
<name>av_readdata</name>
<direction>Output</direction>
<width>32</width>
<role>readdata</role>
</port>
<port>
<name>av_write_n</name>
<direction>Input</direction>
<width>1</width>
<role>write_n</role>
</port>
<port>
<name>av_writedata</name>
<direction>Input</direction>
<width>32</width>
<role>writedata</role>
</port>
<port>
<name>av_waitrequest</name>
<direction>Output</direction>
<width>1</width>
<role>waitrequest</role>
</port>
</interface>
<interface name="irq" kind="interrupt_sender" version="12.1">
<!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
<parameter name="associatedAddressablePoint">
<type>com.altera.entityinterfaces.IConnectionPoint</type>
<value>jtag_uart_1.avalon_jtag_slave</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="associatedClock">
<type>java.lang.String</type>
<value>clk</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="associatedReset">
<type>java.lang.String</type>
<value>reset</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="irqScheme">
<type>com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme</type>
<value>NONE</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<type>interrupt</type>
<isStart>false</isStart>
<port>
<name>av_irq</name>
<direction>Output</direction>
<width>1</width>
<role>irq</role>
</port>
</interface>
</module>
<module
name="sysid_qsys_1"
kind="altera_avalon_sysid_qsys"
version="12.1"
path="sysid_qsys_1">
<!-- Describes a single module. Module parameters are
the requested settings for a module instance. -->
<assignment>
<name>embeddedsw.CMacro.ID</name>
<value>16777216</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.TIMESTAMP</name>
<value>1370947932</value>
</assignment>
<parameter name="id">
<type>int</type>
<value>16777216</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="timestamp">
<type>int</type>
<value>1370947932</value>
<derived>false</derived>
<enabled>false</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="AUTO_CLK_CLOCK_RATE">
<type>java.lang.Long</type>
<value>50000000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="AUTO_DEVICE_FAMILY">
<type>java.lang.String</type>
<value>CYCLONEII</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>Cyclone II</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<interface name="clk" kind="clock_sink" version="12.1">
<!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
<parameter name="externallyDriven">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="ptfSchematicName">
<type>java.lang.String</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="clockRateKnown">
<type>java.lang.Boolean</type>
<value>true</value>
<derived>true</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="clockRate">
<type>java.lang.Long</type>
<value>50000000</value>
<derived>true</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<type>clock</type>
<isStart>false</isStart>
<port>
<name>clock</name>
<direction>Input</direction>
<width>1</width>
<role>clk</role>
</port>
</interface>
<interface name="reset" kind="reset_sink" version="12.1">
<!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
<parameter name="associatedClock">
<type>java.lang.String</type>
<value>clk</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="synchronousEdges">
<type>com.altera.sopcmodel.reset.Reset$Edges</type>
<value>DEASSERT</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<type>reset</type>
<isStart>false</isStart>
<port>
<name>reset_n</name>
<direction>Input</direction>
<width>1</width>
<role>reset_n</role>
</port>
</interface>
<interface name="control_slave" kind="avalon_slave" version="12.1">
<!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
<assignment>
<name>embeddedsw.configuration.isFlash</name>
<value>0</value>
</assignment>
<assignment>
<name>embeddedsw.configuration.isMemoryDevice</name>
<value>0</value>
</assignment>
<assignment>
<name>embeddedsw.configuration.isNonVolatileStorage</name>
<value>0</value>
</assignment>
<assignment>
<name>embeddedsw.configuration.isPrintableDevice</name>
<value>0</value>
</assignment>
<parameter name="addressAlignment">
<type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
<value>DYNAMIC</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="addressGroup">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="addressSpan">
<type>java.math.BigInteger</type>
<value>8</value>
<derived>true</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="addressUnits">
<type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
<value>WORDS</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="alwaysBurstMaxBurst">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="associatedClock">
<type>java.lang.String</type>
<value>clk</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="associatedReset">
<type>java.lang.String</type>
<value>reset</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="bitsPerSymbol">
<type>int</type>
<value>8</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="bridgesToMaster">
<type>com.altera.entityinterfaces.IConnectionPoint</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="burstOnBurstBoundariesOnly">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="burstcountUnits">
<type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
<value>WORDS</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="constantBurstBehavior">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="explicitAddressSpan">
<type>java.math.BigInteger</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="holdTime">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="interleaveBursts">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="isBigEndian">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="isFlash">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="isMemoryDevice">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="isNonVolatileStorage">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="linewrapBursts">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="maximumPendingReadTransactions">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>false</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="minimumUninterruptedRunLength">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="printableDevice">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="readLatency">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="readWaitStates">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="readWaitTime">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="registerIncomingSignals">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="registerOutgoingSignals">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="setupTime">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="timingUnits">
<type>com.altera.sopcmodel.avalon.TimingUnits</type>
<value>Cycles</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="transparentBridge">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="wellBehavedWaitrequest">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="writeLatency">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="writeWaitStates">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="writeWaitTime">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<type>avalon</type>
<isStart>false</isStart>
<port>
<name>readdata</name>
<direction>Output</direction>
<width>32</width>
<role>readdata</role>
</port>
<port>
<name>address</name>
<direction>Input</direction>
<width>1</width>
<role>address</role>
</port>
</interface>
</module>
<module
name="timer_0"
kind="altera_avalon_timer"
version="12.1"
path="timer_0">
<!-- Describes a single module. Module parameters are
the requested settings for a module instance. -->
<assignment>
<name>embeddedsw.CMacro.ALWAYS_RUN</name>
<value>0</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.FIXED_PERIOD</name>
<value>0</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.SNAPSHOT</name>
<value>1</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.PERIOD</name>
<value>1</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.PERIOD_UNITS</name>
<value>"ms"</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.RESET_OUTPUT</name>
<value>0</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.TIMEOUT_PULSE_OUTPUT</name>
<value>0</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.FREQ</name>
<value>50000000u</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.LOAD_VALUE</name>
<value>49999ULL</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.COUNTER_SIZE</name>
<value>32</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.MULT</name>
<value>0.0010</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.TICKS_PER_SEC</name>
<value>1000u</value>
</assignment>
<parameter name="alwaysRun">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="counterSize">
<type>int</type>
<value>32</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="fixedPeriod">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="period">
<type>java.lang.String</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="periodUnits">
<type>com.altera.sopcmodel.components.avalon.AlteraAvalonTimer.AlteraAvalonTimer$TimerPeriodUnit</type>
<value>MSEC</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="resetOutput">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="snapshot">
<type>boolean</type>
<value>true</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="systemFrequency">
<type>long</type>
<value>50000000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="timeoutPulseOutput">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="timerPreset">
<type>com.altera.sopcmodel.components.avalon.AlteraAvalonTimer.TimerPresets</type>
<value>CUSTOM</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<interface name="clk" kind="clock_sink" version="12.1">
<!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
<parameter name="externallyDriven">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="ptfSchematicName">
<type>java.lang.String</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="clockRateKnown">
<type>java.lang.Boolean</type>
<value>true</value>
<derived>true</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="clockRate">
<type>java.lang.Long</type>
<value>50000000</value>
<derived>true</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<type>clock</type>
<isStart>false</isStart>
<port>
<name>clk</name>
<direction>Input</direction>
<width>1</width>
<role>clk</role>
</port>
</interface>
<interface name="reset" kind="reset_sink" version="12.1">
<!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
<parameter name="associatedClock">
<type>java.lang.String</type>
<value>clk</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="synchronousEdges">
<type>com.altera.sopcmodel.reset.Reset$Edges</type>
<value>DEASSERT</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<type>reset</type>
<isStart>false</isStart>
<port>
<name>reset_n</name>
<direction>Input</direction>
<width>1</width>
<role>reset_n</role>
</port>
</interface>
<interface name="s1" kind="avalon_slave" version="12.1">
<!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
<assignment>
<name>embeddedsw.configuration.isTimerDevice</name>
<value>1</value>
</assignment>
<parameter name="addressAlignment">
<type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
<value>NATIVE</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="addressGroup">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="addressSpan">
<type>java.math.BigInteger</type>
<value>8</value>
<derived>true</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="addressUnits">
<type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
<value>WORDS</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="alwaysBurstMaxBurst">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="associatedClock">
<type>java.lang.String</type>
<value>clk</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="associatedReset">
<type>java.lang.String</type>
<value>reset</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="bitsPerSymbol">
<type>int</type>
<value>8</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="bridgesToMaster">
<type>com.altera.entityinterfaces.IConnectionPoint</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="burstOnBurstBoundariesOnly">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="burstcountUnits">
<type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
<value>WORDS</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="constantBurstBehavior">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="explicitAddressSpan">
<type>java.math.BigInteger</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="holdTime">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="interleaveBursts">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="isBigEndian">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="isFlash">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="isMemoryDevice">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="isNonVolatileStorage">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="linewrapBursts">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="maximumPendingReadTransactions">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>false</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="minimumUninterruptedRunLength">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="printableDevice">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="readLatency">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="readWaitStates">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="readWaitTime">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="registerIncomingSignals">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="registerOutgoingSignals">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="setupTime">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="timingUnits">
<type>com.altera.sopcmodel.avalon.TimingUnits</type>
<value>Cycles</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="transparentBridge">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="wellBehavedWaitrequest">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="writeLatency">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="writeWaitStates">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="writeWaitTime">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<type>avalon</type>
<isStart>false</isStart>
<port>
<name>address</name>
<direction>Input</direction>
<width>3</width>
<role>address</role>
</port>
<port>
<name>writedata</name>
<direction>Input</direction>
<width>16</width>
<role>writedata</role>
</port>
<port>
<name>readdata</name>
<direction>Output</direction>
<width>16</width>
<role>readdata</role>
</port>
<port>
<name>chipselect</name>
<direction>Input</direction>
<width>1</width>
<role>chipselect</role>
</port>
<port>
<name>write_n</name>
<direction>Input</direction>
<width>1</width>
<role>write_n</role>
</port>
</interface>
<interface name="irq" kind="interrupt_sender" version="12.1">
<!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
<parameter name="associatedAddressablePoint">
<type>com.altera.entityinterfaces.IConnectionPoint</type>
<value>timer_0.s1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="associatedClock">
<type>java.lang.String</type>
<value>clk</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="associatedReset">
<type>java.lang.String</type>
<value>reset</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="irqScheme">
<type>com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme</type>
<value>NONE</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<type>interrupt</type>
<isStart>false</isStart>
<port>
<name>irq</name>
<direction>Output</direction>
<width>1</width>
<role>irq</role>
</port>
</interface>
</module>
<module
name="timer_1"
kind="altera_avalon_timer"
version="12.1"
path="timer_1">
<!-- Describes a single module. Module parameters are
the requested settings for a module instance. -->
<assignment>
<name>embeddedsw.CMacro.ALWAYS_RUN</name>
<value>0</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.FIXED_PERIOD</name>
<value>0</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.SNAPSHOT</name>
<value>1</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.PERIOD</name>
<value>1</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.PERIOD_UNITS</name>
<value>"ms"</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.RESET_OUTPUT</name>
<value>0</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.TIMEOUT_PULSE_OUTPUT</name>
<value>0</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.FREQ</name>
<value>50000000u</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.LOAD_VALUE</name>
<value>49999ULL</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.COUNTER_SIZE</name>
<value>32</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.MULT</name>
<value>0.0010</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.TICKS_PER_SEC</name>
<value>1000u</value>
</assignment>
<parameter name="alwaysRun">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="counterSize">
<type>int</type>
<value>32</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="fixedPeriod">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="period">
<type>java.lang.String</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="periodUnits">
<type>com.altera.sopcmodel.components.avalon.AlteraAvalonTimer.AlteraAvalonTimer$TimerPeriodUnit</type>
<value>MSEC</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="resetOutput">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="snapshot">
<type>boolean</type>
<value>true</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="systemFrequency">
<type>long</type>
<value>50000000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="timeoutPulseOutput">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="timerPreset">
<type>com.altera.sopcmodel.components.avalon.AlteraAvalonTimer.TimerPresets</type>
<value>CUSTOM</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<interface name="clk" kind="clock_sink" version="12.1">
<!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
<parameter name="externallyDriven">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="ptfSchematicName">
<type>java.lang.String</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="clockRateKnown">
<type>java.lang.Boolean</type>
<value>true</value>
<derived>true</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="clockRate">
<type>java.lang.Long</type>
<value>50000000</value>
<derived>true</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<type>clock</type>
<isStart>false</isStart>
<port>
<name>clk</name>
<direction>Input</direction>
<width>1</width>
<role>clk</role>
</port>
</interface>
<interface name="reset" kind="reset_sink" version="12.1">
<!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
<parameter name="associatedClock">
<type>java.lang.String</type>
<value>clk</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="synchronousEdges">
<type>com.altera.sopcmodel.reset.Reset$Edges</type>
<value>DEASSERT</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<type>reset</type>
<isStart>false</isStart>
<port>
<name>reset_n</name>
<direction>Input</direction>
<width>1</width>
<role>reset_n</role>
</port>
</interface>
<interface name="s1" kind="avalon_slave" version="12.1">
<!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
<assignment>
<name>embeddedsw.configuration.isTimerDevice</name>
<value>1</value>
</assignment>
<parameter name="addressAlignment">
<type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
<value>NATIVE</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="addressGroup">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="addressSpan">
<type>java.math.BigInteger</type>
<value>8</value>
<derived>true</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="addressUnits">
<type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
<value>WORDS</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="alwaysBurstMaxBurst">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="associatedClock">
<type>java.lang.String</type>
<value>clk</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="associatedReset">
<type>java.lang.String</type>
<value>reset</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="bitsPerSymbol">
<type>int</type>
<value>8</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="bridgesToMaster">
<type>com.altera.entityinterfaces.IConnectionPoint</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="burstOnBurstBoundariesOnly">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="burstcountUnits">
<type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
<value>WORDS</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="constantBurstBehavior">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="explicitAddressSpan">
<type>java.math.BigInteger</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="holdTime">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="interleaveBursts">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="isBigEndian">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="isFlash">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="isMemoryDevice">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="isNonVolatileStorage">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="linewrapBursts">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="maximumPendingReadTransactions">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>false</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="minimumUninterruptedRunLength">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="printableDevice">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="readLatency">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="readWaitStates">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="readWaitTime">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="registerIncomingSignals">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="registerOutgoingSignals">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="setupTime">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="timingUnits">
<type>com.altera.sopcmodel.avalon.TimingUnits</type>
<value>Cycles</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="transparentBridge">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="wellBehavedWaitrequest">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="writeLatency">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="writeWaitStates">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="writeWaitTime">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<type>avalon</type>
<isStart>false</isStart>
<port>
<name>address</name>
<direction>Input</direction>
<width>3</width>
<role>address</role>
</port>
<port>
<name>writedata</name>
<direction>Input</direction>
<width>16</width>
<role>writedata</role>
</port>
<port>
<name>readdata</name>
<direction>Output</direction>
<width>16</width>
<role>readdata</role>
</port>
<port>
<name>chipselect</name>
<direction>Input</direction>
<width>1</width>
<role>chipselect</role>
</port>
<port>
<name>write_n</name>
<direction>Input</direction>
<width>1</width>
<role>write_n</role>
</port>
</interface>
<interface name="irq" kind="interrupt_sender" version="12.1">
<!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
<parameter name="associatedAddressablePoint">
<type>com.altera.entityinterfaces.IConnectionPoint</type>
<value>timer_1.s1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="associatedClock">
<type>java.lang.String</type>
<value>clk</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="associatedReset">
<type>java.lang.String</type>
<value>reset</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="irqScheme">
<type>com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme</type>
<value>NONE</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<type>interrupt</type>
<isStart>false</isStart>
<port>
<name>irq</name>
<direction>Output</direction>
<width>1</width>
<role>irq</role>
</port>
</interface>
</module>
<module
name="sdram_0"
kind="altera_avalon_new_sdram_controller"
version="12.1"
path="sdram_0">
<!-- Describes a single module. Module parameters are
the requested settings for a module instance. -->
<assignment>
<name>embeddedsw.CMacro.REGISTER_DATA_IN</name>
<value>1</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.SIM_MODEL_BASE</name>
<value>0</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.SDRAM_DATA_WIDTH</name>
<value>16</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.SDRAM_ADDR_WIDTH</name>
<value>22</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.SDRAM_ROW_WIDTH</name>
<value>12</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.SDRAM_COL_WIDTH</name>
<value>8</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.SDRAM_NUM_CHIPSELECTS</name>
<value>1</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.SDRAM_NUM_BANKS</name>
<value>4</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.REFRESH_PERIOD</name>
<value>15.625</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.POWERUP_DELAY</name>
<value>100.0</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.CAS_LATENCY</name>
<value>3</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.T_RFC</name>
<value>70.0</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.T_RP</name>
<value>20.0</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.T_MRD</name>
<value>3</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.T_RCD</name>
<value>20.0</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.T_AC</name>
<value>5.5</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.T_WR</name>
<value>14.0</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.INIT_REFRESH_COMMANDS</name>
<value>2</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.INIT_NOP_DELAY</name>
<value>0.0</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.SHARED_DATA</name>
<value>0</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.STARVATION_INDICATOR</name>
<value>0</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.TRISTATE_BRIDGE_SLAVE</name>
<value>""</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.IS_INITIALIZED</name>
<value>1</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.SDRAM_BANK_WIDTH</name>
<value>2</value>
</assignment>
<assignment>
<name>embeddedsw.CMacro.CONTENTS_INFO</name>
<value>""</value>
</assignment>
<assignment>
<name>embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH</name>
<value>16</value>
</assignment>
<assignment>
<name>embeddedsw.memoryInfo.GENERATE_DAT_SYM</name>
<value>1</value>
</assignment>
<assignment>
<name>embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR</name>
<value>SIM_DIR</value>
</assignment>
<parameter name="TAC">
<type>double</type>
<value>5.5</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="TMRD">
<type>long</type>
<value>3</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="TRCD">
<type>double</type>
<value>20.0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="TRFC">
<type>double</type>
<value>70.0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="TRP">
<type>double</type>
<value>20.0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="TWR">
<type>double</type>
<value>14.0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="casLatency">
<type>int</type>
<value>3</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="clockRate">
<type>long</type>
<value>50000000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="columnWidth">
<type>int</type>
<value>8</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="dataWidth">
<type>int</type>
<value>16</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateSimulationModel">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="initNOPDelay">
<type>double</type>
<value>0.0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="initRefreshCommands">
<type>int</type>
<value>2</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="masteredTristateBridgeSlave">
<type>com.altera.entityinterfaces.IConnectionPoint</type>
<value></value>
<derived>false</derived>
<enabled>false</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="model">
<type>com.altera.sopcmodel.components.avalon.AlteraAvalonSDRAMController.ModelMangler$PresetModels</type>
<value>custom</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="numberOfBanks">
<type>int</type>
<value>4</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="numberOfChipSelects">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="pinsSharedViaTriState">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="powerUpDelay">
<type>double</type>
<value>100.0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="refreshPeriod">
<type>double</type>
<value>15.625</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="registerDataIn">
<type>boolean</type>
<value>true</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="rowWidth">
<type>int</type>
<value>12</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="size">
<type>long</type>
<value>8388608</value>
<derived>true</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<interface name="clk" kind="clock_sink" version="12.1">
<!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
<parameter name="externallyDriven">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="ptfSchematicName">
<type>java.lang.String</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="clockRateKnown">
<type>java.lang.Boolean</type>
<value>true</value>
<derived>true</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="clockRate">
<type>java.lang.Long</type>
<value>50000000</value>
<derived>true</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<type>clock</type>
<isStart>false</isStart>
<port>
<name>clk</name>
<direction>Input</direction>
<width>1</width>
<role>clk</role>
</port>
</interface>
<interface name="reset" kind="reset_sink" version="12.1">
<!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
<parameter name="associatedClock">
<type>java.lang.String</type>
<value>clk</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="synchronousEdges">
<type>com.altera.sopcmodel.reset.Reset$Edges</type>
<value>DEASSERT</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<type>reset</type>
<isStart>false</isStart>
<port>
<name>reset_n</name>
<direction>Input</direction>
<width>1</width>
<role>reset_n</role>
</port>
</interface>
<interface name="s1" kind="avalon_slave" version="12.1">
<!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
<assignment>
<name>embeddedsw.configuration.isMemoryDevice</name>
<value>1</value>
</assignment>
<parameter name="addressAlignment">
<type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
<value>DYNAMIC</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="addressGroup">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="addressSpan">
<type>java.math.BigInteger</type>
<value>8388608</value>
<derived>true</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="addressUnits">
<type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
<value>WORDS</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="alwaysBurstMaxBurst">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="associatedClock">
<type>java.lang.String</type>
<value>clk</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="associatedReset">
<type>java.lang.String</type>
<value>reset</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="bitsPerSymbol">
<type>int</type>
<value>8</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="bridgesToMaster">
<type>com.altera.entityinterfaces.IConnectionPoint</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="burstOnBurstBoundariesOnly">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="burstcountUnits">
<type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
<value>WORDS</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="constantBurstBehavior">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="explicitAddressSpan">
<type>java.math.BigInteger</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="holdTime">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>false</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="interleaveBursts">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="isBigEndian">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="isFlash">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="isMemoryDevice">
<type>boolean</type>
<value>true</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="isNonVolatileStorage">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="linewrapBursts">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="maximumPendingReadTransactions">
<type>int</type>
<value>7</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="minimumUninterruptedRunLength">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="printableDevice">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="readLatency">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>false</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="readWaitStates">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="readWaitTime">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>false</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="registerIncomingSignals">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="registerOutgoingSignals">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="setupTime">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>false</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="timingUnits">
<type>com.altera.sopcmodel.avalon.TimingUnits</type>
<value>Cycles</value>
<derived>false</derived>
<enabled>false</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="transparentBridge">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="wellBehavedWaitrequest">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="writeLatency">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="writeWaitStates">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="writeWaitTime">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>false</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<type>avalon</type>
<isStart>false</isStart>
<port>
<name>az_addr</name>
<direction>Input</direction>
<width>22</width>
<role>address</role>
</port>
<port>
<name>az_be_n</name>
<direction>Input</direction>
<width>2</width>
<role>byteenable_n</role>
</port>
<port>
<name>az_cs</name>
<direction>Input</direction>
<width>1</width>
<role>chipselect</role>
</port>
<port>
<name>az_data</name>
<direction>Input</direction>
<width>16</width>
<role>writedata</role>
</port>
<port>
<name>az_rd_n</name>
<direction>Input</direction>
<width>1</width>
<role>read_n</role>
</port>
<port>
<name>az_wr_n</name>
<direction>Input</direction>
<width>1</width>
<role>write_n</role>
</port>
<port>
<name>za_data</name>
<direction>Output</direction>
<width>16</width>
<role>readdata</role>
</port>
<port>
<name>za_valid</name>
<direction>Output</direction>
<width>1</width>
<role>readdatavalid</role>
</port>
<port>
<name>za_waitrequest</name>
<direction>Output</direction>
<width>1</width>
<role>waitrequest</role>
</port>
</interface>
<interface name="wire" kind="conduit_end" version="12.1">
<!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
<parameter name="associatedClock">
<type>java.lang.String</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="associatedReset">
<type>java.lang.String</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<type>conduit</type>
<isStart>false</isStart>
<port>
<name>zs_addr</name>
<direction>Output</direction>
<width>12</width>
<role>export</role>
</port>
<port>
<name>zs_ba</name>
<direction>Output</direction>
<width>2</width>
<role>export</role>
</port>
<port>
<name>zs_cas_n</name>
<direction>Output</direction>
<width>1</width>
<role>export</role>
</port>
<port>
<name>zs_cke</name>
<direction>Output</direction>
<width>1</width>
<role>export</role>
</port>
<port>
<name>zs_cs_n</name>
<direction>Output</direction>
<width>1</width>
<role>export</role>
</port>
<port>
<name>zs_dq</name>
<direction>Bidir</direction>
<width>16</width>
<role>export</role>
</port>
<port>
<name>zs_dqm</name>
<direction>Output</direction>
<width>2</width>
<role>export</role>
</port>
<port>
<name>zs_ras_n</name>
<direction>Output</direction>
<width>1</width>
<role>export</role>
</port>
<port>
<name>zs_we_n</name>
<direction>Output</direction>
<width>1</width>
<role>export</role>
</port>
</interface>
</module>
<module
name="hibi_pe_dma_0"
kind="hibi_pe_dma"
version="1.0"
path="hibi_pe_dma_0">
<!-- Describes a single module. Module parameters are
the requested settings for a module instance. -->
<parameter name="data_width_g">
<type>int</type>
<value>32</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="addr_width_g">
<type>int</type>
<value>32</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="words_width_g">
<type>int</type>
<value>16</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="n_stream_chans_g">
<type>int</type>
<value>2</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="n_packet_chans_g">
<type>int</type>
<value>2</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="n_chans_bits_g">
<type>int</type>
<value>3</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="hibi_addr_cmp_lo_g">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="hibi_addr_cmp_hi_g">
<type>int</type>
<value>31</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="AUTO_CLOCK_CLOCK_RATE">
<type>java.lang.Long</type>
<value>50000000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<interface name="avalon_slave_0" kind="avalon_slave" version="12.1">
<!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
<assignment>
<name>embeddedsw.configuration.isFlash</name>
<value>0</value>
</assignment>
<assignment>
<name>embeddedsw.configuration.isMemoryDevice</name>
<value>0</value>
</assignment>
<assignment>
<name>embeddedsw.configuration.isNonVolatileStorage</name>
<value>0</value>
</assignment>
<assignment>
<name>embeddedsw.configuration.isPrintableDevice</name>
<value>0</value>
</assignment>
<parameter name="addressAlignment">
<type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
<value>DYNAMIC</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="addressGroup">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="addressSpan">
<type>java.math.BigInteger</type>
<value>512</value>
<derived>true</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="addressUnits">
<type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
<value>WORDS</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="alwaysBurstMaxBurst">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="associatedClock">
<type>java.lang.String</type>
<value>clock</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="associatedReset">
<type>java.lang.String</type>
<value>clock_sink_reset</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="bitsPerSymbol">
<type>int</type>
<value>8</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="bridgesToMaster">
<type>com.altera.entityinterfaces.IConnectionPoint</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="burstOnBurstBoundariesOnly">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="burstcountUnits">
<type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
<value>WORDS</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="constantBurstBehavior">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="explicitAddressSpan">
<type>java.math.BigInteger</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="holdTime">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>false</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="interleaveBursts">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="isBigEndian">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="isFlash">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="isMemoryDevice">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="isNonVolatileStorage">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="linewrapBursts">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="maximumPendingReadTransactions">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>false</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="minimumUninterruptedRunLength">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="printableDevice">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="readLatency">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="readWaitStates">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="readWaitTime">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>false</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="registerIncomingSignals">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="registerOutgoingSignals">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="setupTime">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>false</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="timingUnits">
<type>com.altera.sopcmodel.avalon.TimingUnits</type>
<value>Cycles</value>
<derived>false</derived>
<enabled>false</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="transparentBridge">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="wellBehavedWaitrequest">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="writeLatency">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="writeWaitStates">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="writeWaitTime">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>false</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<type>avalon</type>
<isStart>false</isStart>
<port>
<name>avalon_cfg_addr_in</name>
<direction>Input</direction>
<width>7</width>
<role>address</role>
</port>
<port>
<name>avalon_cfg_we_in</name>
<direction>Input</direction>
<width>1</width>
<role>write</role>
</port>
<port>
<name>avalon_cfg_re_in</name>
<direction>Input</direction>
<width>1</width>
<role>read</role>
</port>
<port>
<name>avalon_cfg_cs_in</name>
<direction>Input</direction>
<width>1</width>
<role>chipselect</role>
</port>
<port>
<name>avalon_cfg_waitrequest_out</name>
<direction>Output</direction>
<width>1</width>
<role>waitrequest</role>
</port>
<port>
<name>avalon_cfg_writedata_in</name>
<direction>Input</direction>
<width>32</width>
<role>writedata</role>
</port>
<port>
<name>avalon_cfg_readdata_out</name>
<direction>Output</direction>
<width>32</width>
<role>readdata</role>
</port>
</interface>
<interface name="conduit_end" kind="conduit_end" version="12.1">
<!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
<parameter name="associatedClock">
<type>java.lang.String</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="associatedReset">
<type>java.lang.String</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<type>conduit</type>
<isStart>false</isStart>
<port>
<name>hibi_data_in</name>
<direction>Input</direction>
<width>32</width>
<role>export</role>
</port>
<port>
<name>hibi_av_in</name>
<direction>Input</direction>
<width>1</width>
<role>export</role>
</port>
<port>
<name>hibi_empty_in</name>
<direction>Input</direction>
<width>1</width>
<role>export</role>
</port>
<port>
<name>hibi_comm_in</name>
<direction>Input</direction>
<width>5</width>
<role>export</role>
</port>
<port>
<name>hibi_re_out</name>
<direction>Output</direction>
<width>1</width>
<role>export</role>
</port>
<port>
<name>hibi_data_out</name>
<direction>Output</direction>
<width>32</width>
<role>export</role>
</port>
<port>
<name>hibi_av_out</name>
<direction>Output</direction>
<width>1</width>
<role>export</role>
</port>
<port>
<name>hibi_full_in</name>
<direction>Input</direction>
<width>1</width>
<role>export</role>
</port>
<port>
<name>hibi_comm_out</name>
<direction>Output</direction>
<width>5</width>
<role>export</role>
</port>
<port>
<name>hibi_we_out</name>
<direction>Output</direction>
<width>1</width>
<role>export</role>
</port>
</interface>
<interface name="clock_sink_reset" kind="reset_sink" version="12.1">
<!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
<parameter name="associatedClock">
<type>java.lang.String</type>
<value>clock</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="synchronousEdges">
<type>com.altera.sopcmodel.reset.Reset$Edges</type>
<value>DEASSERT</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<type>reset</type>
<isStart>false</isStart>
<port>
<name>rst_n</name>
<direction>Input</direction>
<width>1</width>
<role>reset_n</role>
</port>
</interface>
<interface name="interrupt_sender" kind="interrupt_sender" version="12.1">
<!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
<parameter name="associatedAddressablePoint">
<type>com.altera.entityinterfaces.IConnectionPoint</type>
<value>hibi_pe_dma_0.avalon_slave_0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="associatedClock">
<type>java.lang.String</type>
<value>clock</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="associatedReset">
<type>java.lang.String</type>
<value>clock_sink_reset</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="irqScheme">
<type>com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme</type>
<value>NONE</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<type>interrupt</type>
<isStart>false</isStart>
<port>
<name>rx_irq_out</name>
<direction>Output</direction>
<width>1</width>
<role>irq</role>
</port>
</interface>
<interface name="avalon_master" kind="avalon_master" version="12.1">
<!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
<parameter name="adaptsTo">
<type>com.altera.entityinterfaces.IConnectionPoint</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="addressGroup">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="addressUnits">
<type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
<value>SYMBOLS</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="alwaysBurstMaxBurst">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="associatedClock">
<type>java.lang.String</type>
<value>clock</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="associatedReset">
<type>java.lang.String</type>
<value>clock_sink_reset</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="bitsPerSymbol">
<type>int</type>
<value>8</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="burstOnBurstBoundariesOnly">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="burstcountUnits">
<type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
<value>WORDS</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="constantBurstBehavior">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="dBSBigEndian">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="doStreamReads">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="doStreamWrites">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="holdTime">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="interleaveBursts">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="isAsynchronous">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="isBigEndian">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="isReadable">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="isWriteable">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="linewrapBursts">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="maxAddressWidth">
<type>int</type>
<value>32</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="maximumPendingReadTransactions">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="readLatency">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="readWaitTime">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="registerIncomingSignals">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="registerOutgoingSignals">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="setupTime">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="timingUnits">
<type>com.altera.sopcmodel.avalon.TimingUnits</type>
<value>Cycles</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="writeWaitTime">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<type>avalon</type>
<isStart>true</isStart>
<port>
<name>avalon_addr_out_rx</name>
<direction>Output</direction>
<width>32</width>
<role>address</role>
</port>
<port>
<name>avalon_we_out_rx</name>
<direction>Output</direction>
<width>1</width>
<role>write</role>
</port>
<port>
<name>avalon_be_out_rx</name>
<direction>Output</direction>
<width>4</width>
<role>byteenable</role>
</port>
<port>
<name>avalon_writedata_out_rx</name>
<direction>Output</direction>
<width>32</width>
<role>writedata</role>
</port>
<port>
<name>avalon_waitrequest_in_rx</name>
<direction>Input</direction>
<width>1</width>
<role>waitrequest</role>
</port>
<memoryBlock>
<isBridge>false</isBridge>
<moduleName>onchip_memory2_1</moduleName>
<slaveName>s2</slaveName>
<name>onchip_memory2_1.s2</name>
<baseAddress>0</baseAddress>
<span>8192</span>
</memoryBlock>
</interface>
<interface name="avalon_master_1" kind="avalon_master" version="12.1">
<!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
<parameter name="adaptsTo">
<type>com.altera.entityinterfaces.IConnectionPoint</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="addressGroup">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="addressUnits">
<type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
<value>SYMBOLS</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="alwaysBurstMaxBurst">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="associatedClock">
<type>java.lang.String</type>
<value>clock</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="associatedReset">
<type>java.lang.String</type>
<value>clock_sink_reset</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="bitsPerSymbol">
<type>int</type>
<value>8</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="burstOnBurstBoundariesOnly">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="burstcountUnits">
<type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
<value>WORDS</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="constantBurstBehavior">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="dBSBigEndian">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="doStreamReads">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="doStreamWrites">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="holdTime">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="interleaveBursts">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="isAsynchronous">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="isBigEndian">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="isReadable">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="isWriteable">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="linewrapBursts">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="maxAddressWidth">
<type>int</type>
<value>32</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="maximumPendingReadTransactions">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="readLatency">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="readWaitTime">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="registerIncomingSignals">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="registerOutgoingSignals">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="setupTime">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="timingUnits">
<type>com.altera.sopcmodel.avalon.TimingUnits</type>
<value>Cycles</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="writeWaitTime">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<type>avalon</type>
<isStart>true</isStart>
<port>
<name>avalon_readdatavalid_in_tx</name>
<direction>Input</direction>
<width>1</width>
<role>readdatavalid</role>
</port>
<port>
<name>avalon_waitrequest_in_tx</name>
<direction>Input</direction>
<width>1</width>
<role>waitrequest</role>
</port>
<port>
<name>avalon_readdata_in_tx</name>
<direction>Input</direction>
<width>32</width>
<role>readdata</role>
</port>
<port>
<name>avalon_re_out_tx</name>
<direction>Output</direction>
<width>1</width>
<role>read</role>
</port>
<port>
<name>avalon_addr_out_tx</name>
<direction>Output</direction>
<width>32</width>
<role>address</role>
</port>
<memoryBlock>
<isBridge>false</isBridge>
<moduleName>onchip_memory2_1</moduleName>
<slaveName>s2</slaveName>
<name>onchip_memory2_1.s2</name>
<baseAddress>0</baseAddress>
<span>8192</span>
</memoryBlock>
</interface>
<interface name="clock" kind="clock_sink" version="12.1">
<!-- The connection points exposed by a module instance for the
particular module parameters. Connection points and their
parameters are a RESULT of the module parameters. -->
<parameter name="externallyDriven">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="ptfSchematicName">
<type>java.lang.String</type>
<value></value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="clockRateKnown">
<type>java.lang.Boolean</type>
<value>true</value>
<derived>true</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="clockRate">
<type>java.lang.Long</type>
<value>50000000</value>
<derived>true</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<type>clock</type>
<isStart>false</isStart>
<port>
<name>clk</name>
<direction>Input</direction>
<width>1</width>
<role>clk</role>
</port>
</interface>
</module>
<connection
name="nios2_qsys_1.instruction_master/nios2_qsys_1.jtag_debug_module"
kind="avalon"
version="12.1"
start="nios2_qsys_1.instruction_master"
end="nios2_qsys_1.jtag_debug_module">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
<value>0x2800</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<startModule>nios2_qsys_1</startModule>
<startConnectionPoint>instruction_master</startConnectionPoint>
<endModule>nios2_qsys_1</endModule>
<endConnectionPoint>jtag_debug_module</endConnectionPoint>
</connection>
<connection
name="nios2_qsys_1.data_master/nios2_qsys_1.jtag_debug_module"
kind="avalon"
version="12.1"
start="nios2_qsys_1.data_master"
end="nios2_qsys_1.jtag_debug_module">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
<value>0x2800</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<startModule>nios2_qsys_1</startModule>
<startConnectionPoint>data_master</startConnectionPoint>
<endModule>nios2_qsys_1</endModule>
<endConnectionPoint>jtag_debug_module</endConnectionPoint>
</connection>
<connection
name="clk_0.clk/sdram_0.clk"
kind="clock"
version="12.1"
start="clk_0.clk"
end="sdram_0.clk">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<startModule>clk_0</startModule>
<startConnectionPoint>clk</startConnectionPoint>
<endModule>sdram_0</endModule>
<endConnectionPoint>clk</endConnectionPoint>
</connection>
<connection
name="clk_0.clk_reset/sdram_0.reset"
kind="reset"
version="12.1"
start="clk_0.clk_reset"
end="sdram_0.reset">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<startModule>clk_0</startModule>
<startConnectionPoint>clk_reset</startConnectionPoint>
<endModule>sdram_0</endModule>
<endConnectionPoint>reset</endConnectionPoint>
</connection>
<connection
name="clk_0.clk/timer_1.clk"
kind="clock"
version="12.1"
start="clk_0.clk"
end="timer_1.clk">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<startModule>clk_0</startModule>
<startConnectionPoint>clk</startConnectionPoint>
<endModule>timer_1</endModule>
<endConnectionPoint>clk</endConnectionPoint>
</connection>
<connection
name="clk_0.clk_reset/timer_1.reset"
kind="reset"
version="12.1"
start="clk_0.clk_reset"
end="timer_1.reset">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<startModule>clk_0</startModule>
<startConnectionPoint>clk_reset</startConnectionPoint>
<endModule>timer_1</endModule>
<endConnectionPoint>reset</endConnectionPoint>
</connection>
<connection
name="clk_0.clk/timer_0.clk"
kind="clock"
version="12.1"
start="clk_0.clk"
end="timer_0.clk">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<startModule>clk_0</startModule>
<startConnectionPoint>clk</startConnectionPoint>
<endModule>timer_0</endModule>
<endConnectionPoint>clk</endConnectionPoint>
</connection>
<connection
name="clk_0.clk_reset/timer_0.reset"
kind="reset"
version="12.1"
start="clk_0.clk_reset"
end="timer_0.reset">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<startModule>clk_0</startModule>
<startConnectionPoint>clk_reset</startConnectionPoint>
<endModule>timer_0</endModule>
<endConnectionPoint>reset</endConnectionPoint>
</connection>
<connection
name="clk_0.clk/sysid_qsys_1.clk"
kind="clock"
version="12.1"
start="clk_0.clk"
end="sysid_qsys_1.clk">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<startModule>clk_0</startModule>
<startConnectionPoint>clk</startConnectionPoint>
<endModule>sysid_qsys_1</endModule>
<endConnectionPoint>clk</endConnectionPoint>
</connection>
<connection
name="clk_0.clk_reset/sysid_qsys_1.reset"
kind="reset"
version="12.1"
start="clk_0.clk_reset"
end="sysid_qsys_1.reset">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<startModule>clk_0</startModule>
<startConnectionPoint>clk_reset</startConnectionPoint>
<endModule>sysid_qsys_1</endModule>
<endConnectionPoint>reset</endConnectionPoint>
</connection>
<connection
name="clk_0.clk/jtag_uart_1.clk"
kind="clock"
version="12.1"
start="clk_0.clk"
end="jtag_uart_1.clk">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<startModule>clk_0</startModule>
<startConnectionPoint>clk</startConnectionPoint>
<endModule>jtag_uart_1</endModule>
<endConnectionPoint>clk</endConnectionPoint>
</connection>
<connection
name="clk_0.clk_reset/jtag_uart_1.reset"
kind="reset"
version="12.1"
start="clk_0.clk_reset"
end="jtag_uart_1.reset">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<startModule>clk_0</startModule>
<startConnectionPoint>clk_reset</startConnectionPoint>
<endModule>jtag_uart_1</endModule>
<endConnectionPoint>reset</endConnectionPoint>
</connection>
<connection
name="clk_0.clk/onchip_memory2_1.clk2"
kind="clock"
version="12.1"
start="clk_0.clk"
end="onchip_memory2_1.clk2">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<startModule>clk_0</startModule>
<startConnectionPoint>clk</startConnectionPoint>
<endModule>onchip_memory2_1</endModule>
<endConnectionPoint>clk2</endConnectionPoint>
</connection>
<connection
name="clk_0.clk_reset/onchip_memory2_1.reset2"
kind="reset"
version="12.1"
start="clk_0.clk_reset"
end="onchip_memory2_1.reset2">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<startModule>clk_0</startModule>
<startConnectionPoint>clk_reset</startConnectionPoint>
<endModule>onchip_memory2_1</endModule>
<endConnectionPoint>reset2</endConnectionPoint>
</connection>
<connection
name="clk_0.clk/onchip_memory2_1.clk1"
kind="clock"
version="12.1"
start="clk_0.clk"
end="onchip_memory2_1.clk1">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<startModule>clk_0</startModule>
<startConnectionPoint>clk</startConnectionPoint>
<endModule>onchip_memory2_1</endModule>
<endConnectionPoint>clk1</endConnectionPoint>
</connection>
<connection
name="clk_0.clk_reset/onchip_memory2_1.reset1"
kind="reset"
version="12.1"
start="clk_0.clk_reset"
end="onchip_memory2_1.reset1">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<startModule>clk_0</startModule>
<startConnectionPoint>clk_reset</startConnectionPoint>
<endModule>onchip_memory2_1</endModule>
<endConnectionPoint>reset1</endConnectionPoint>
</connection>
<connection
name="clk_0.clk/nios2_qsys_1.clk"
kind="clock"
version="12.1"
start="clk_0.clk"
end="nios2_qsys_1.clk">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<startModule>clk_0</startModule>
<startConnectionPoint>clk</startConnectionPoint>
<endModule>nios2_qsys_1</endModule>
<endConnectionPoint>clk</endConnectionPoint>
</connection>
<connection
name="clk_0.clk_reset/nios2_qsys_1.reset_n"
kind="reset"
version="12.1"
start="clk_0.clk_reset"
end="nios2_qsys_1.reset_n">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<startModule>clk_0</startModule>
<startConnectionPoint>clk_reset</startConnectionPoint>
<endModule>nios2_qsys_1</endModule>
<endConnectionPoint>reset_n</endConnectionPoint>
</connection>
<connection
name="nios2_qsys_1.d_irq/jtag_uart_1.irq"
kind="interrupt"
version="12.1"
start="nios2_qsys_1.d_irq"
end="jtag_uart_1.irq">
<parameter name="irqNumber">
<type>int</type>
<value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<startModule>nios2_qsys_1</startModule>
<startConnectionPoint>d_irq</startConnectionPoint>
<endModule>jtag_uart_1</endModule>
<endConnectionPoint>irq</endConnectionPoint>
</connection>
<connection
name="nios2_qsys_1.d_irq/timer_1.irq"
kind="interrupt"
version="12.1"
start="nios2_qsys_1.d_irq"
end="timer_1.irq">
<parameter name="irqNumber">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<startModule>nios2_qsys_1</startModule>
<startConnectionPoint>d_irq</startConnectionPoint>
<endModule>timer_1</endModule>
<endConnectionPoint>irq</endConnectionPoint>
</connection>
<connection
name="nios2_qsys_1.d_irq/timer_0.irq"
kind="interrupt"
version="12.1"
start="nios2_qsys_1.d_irq"
end="timer_0.irq">
<parameter name="irqNumber">
<type>int</type>
<value>2</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<startModule>nios2_qsys_1</startModule>
<startConnectionPoint>d_irq</startConnectionPoint>
<endModule>timer_0</endModule>
<endConnectionPoint>irq</endConnectionPoint>
</connection>
<connection
name="nios2_qsys_1.data_master/jtag_uart_1.avalon_jtag_slave"
kind="avalon"
version="12.1"
start="nios2_qsys_1.data_master"
end="jtag_uart_1.avalon_jtag_slave">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
<value>0x3248</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<startModule>nios2_qsys_1</startModule>
<startConnectionPoint>data_master</startConnectionPoint>
<endModule>jtag_uart_1</endModule>
<endConnectionPoint>avalon_jtag_slave</endConnectionPoint>
</connection>
<connection
name="nios2_qsys_1.data_master/timer_1.s1"
kind="avalon"
version="12.1"
start="nios2_qsys_1.data_master"
end="timer_1.s1">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
<value>0x3220</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<startModule>nios2_qsys_1</startModule>
<startConnectionPoint>data_master</startConnectionPoint>
<endModule>timer_1</endModule>
<endConnectionPoint>s1</endConnectionPoint>
</connection>
<connection
name="nios2_qsys_1.data_master/timer_0.s1"
kind="avalon"
version="12.1"
start="nios2_qsys_1.data_master"
end="timer_0.s1">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
<value>0x3200</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<startModule>nios2_qsys_1</startModule>
<startConnectionPoint>data_master</startConnectionPoint>
<endModule>timer_0</endModule>
<endConnectionPoint>s1</endConnectionPoint>
</connection>
<connection
name="nios2_qsys_1.data_master/sysid_qsys_1.control_slave"
kind="avalon"
version="12.1"
start="nios2_qsys_1.data_master"
end="sysid_qsys_1.control_slave">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
<value>0x3240</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<startModule>nios2_qsys_1</startModule>
<startConnectionPoint>data_master</startConnectionPoint>
<endModule>sysid_qsys_1</endModule>
<endConnectionPoint>control_slave</endConnectionPoint>
</connection>
<connection
name="nios2_qsys_1.data_master/sdram_0.s1"
kind="avalon"
version="12.1"
start="nios2_qsys_1.data_master"
end="sdram_0.s1">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
<value>0x02000000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<startModule>nios2_qsys_1</startModule>
<startConnectionPoint>data_master</startConnectionPoint>
<endModule>sdram_0</endModule>
<endConnectionPoint>s1</endConnectionPoint>
</connection>
<connection
name="nios2_qsys_1.instruction_master/sdram_0.s1"
kind="avalon"
version="12.1"
start="nios2_qsys_1.instruction_master"
end="sdram_0.s1">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
<value>0x02000000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<startModule>nios2_qsys_1</startModule>
<startConnectionPoint>instruction_master</startConnectionPoint>
<endModule>sdram_0</endModule>
<endConnectionPoint>s1</endConnectionPoint>
</connection>
<connection
name="nios2_qsys_1.data_master/onchip_memory2_1.s1"
kind="avalon"
version="12.1"
start="nios2_qsys_1.data_master"
end="onchip_memory2_1.s1">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
<value>0x0000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<startModule>nios2_qsys_1</startModule>
<startConnectionPoint>data_master</startConnectionPoint>
<endModule>onchip_memory2_1</endModule>
<endConnectionPoint>s1</endConnectionPoint>
</connection>
<connection
name="clk_0.clk/hibi_pe_dma_0.clock"
kind="clock"
version="12.1"
start="clk_0.clk"
end="hibi_pe_dma_0.clock">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<startModule>clk_0</startModule>
<startConnectionPoint>clk</startConnectionPoint>
<endModule>hibi_pe_dma_0</endModule>
<endConnectionPoint>clock</endConnectionPoint>
</connection>
<connection
name="clk_0.clk_reset/hibi_pe_dma_0.clock_sink_reset"
kind="reset"
version="12.1"
start="clk_0.clk_reset"
end="hibi_pe_dma_0.clock_sink_reset">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<startModule>clk_0</startModule>
<startConnectionPoint>clk_reset</startConnectionPoint>
<endModule>hibi_pe_dma_0</endModule>
<endConnectionPoint>clock_sink_reset</endConnectionPoint>
</connection>
<connection
name="nios2_qsys_1.data_master/hibi_pe_dma_0.avalon_slave_0"
kind="avalon"
version="12.1"
start="nios2_qsys_1.data_master"
end="hibi_pe_dma_0.avalon_slave_0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
<value>0x3000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<startModule>nios2_qsys_1</startModule>
<startConnectionPoint>data_master</startConnectionPoint>
<endModule>hibi_pe_dma_0</endModule>
<endConnectionPoint>avalon_slave_0</endConnectionPoint>
</connection>
<connection
name="nios2_qsys_1.d_irq/hibi_pe_dma_0.interrupt_sender"
kind="interrupt"
version="12.1"
start="nios2_qsys_1.d_irq"
end="hibi_pe_dma_0.interrupt_sender">
<parameter name="irqNumber">
<type>int</type>
<value>3</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<startModule>nios2_qsys_1</startModule>
<startConnectionPoint>d_irq</startConnectionPoint>
<endModule>hibi_pe_dma_0</endModule>
<endConnectionPoint>interrupt_sender</endConnectionPoint>
</connection>
<connection
name="hibi_pe_dma_0.avalon_master/onchip_memory2_1.s2"
kind="avalon"
version="12.1"
start="hibi_pe_dma_0.avalon_master"
end="onchip_memory2_1.s2">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
<value>0x0000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<startModule>hibi_pe_dma_0</startModule>
<startConnectionPoint>avalon_master</startConnectionPoint>
<endModule>onchip_memory2_1</endModule>
<endConnectionPoint>s2</endConnectionPoint>
</connection>
<connection
name="hibi_pe_dma_0.avalon_master_1/onchip_memory2_1.s2"
kind="avalon"
version="12.1"
start="hibi_pe_dma_0.avalon_master_1"
end="onchip_memory2_1.s2">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
<value>0x0000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
<startModule>hibi_pe_dma_0</startModule>
<startConnectionPoint>avalon_master_1</startConnectionPoint>
<endModule>onchip_memory2_1</endModule>
<endConnectionPoint>s2</endConnectionPoint>
</connection>
<plugin>
<instanceCount>3</instanceCount>
<name>clock_sink</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
<displayName>Clock Input</displayName>
<version>12.1</version>
</plugin>
<plugin>
<instanceCount>1</instanceCount>
<name>interrupt_sender</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
<displayName>Interrupt Sender</displayName>
<version>12.1</version>
</plugin>
<plugin>
<instanceCount>3</instanceCount>
<name>avalon_slave</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
<displayName>Avalon Memory Mapped Slave</displayName>
<version>12.1</version>
</plugin>
<plugin>
<instanceCount>1</instanceCount>
<name>altera_avalon_sysid_qsys</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IModule</subtype>
<displayName>System ID Peripheral</displayName>
<version>12.1</version>
</plugin>
<plugin>
<instanceCount>1</instanceCount>
<name>altera_avalon_new_sdram_controller</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IModule</subtype>
<displayName>SDRAM Controller</displayName>
<version>12.1</version>
</plugin>
<plugin>
<instanceCount>1</instanceCount>
<name>clock_source</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
<displayName>Clock Output</displayName>
<version>12.1</version>
</plugin>
<plugin>
<instanceCount>1</instanceCount>
<name>altera_nios2_qsys</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IModule</subtype>
<displayName>Nios II Processor</displayName>
<version>12.1</version>
</plugin>
<plugin>
<instanceCount>1</instanceCount>
<name>reset_source</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
<displayName>Reset Output</displayName>
<version>12.1</version>
</plugin>
<plugin>
<instanceCount>1</instanceCount>
<name>nios_custom_instruction_master</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
<displayName>Custom Instruction Master</displayName>
<version>12.1</version>
</plugin>
<plugin>
<instanceCount>3</instanceCount>
<name>interrupt_sender</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
<displayName>Interrupt Sender</displayName>
<version>12.1</version>
</plugin>
<plugin>
<instanceCount>1</instanceCount>
<name>conduit_end</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
<displayName>Conduit</displayName>
<version>12.1</version>
</plugin>
<plugin>
<instanceCount>3</instanceCount>
<name>reset_sink</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
<displayName>Reset Input</displayName>
<version>12.1</version>
</plugin>
<plugin>
<instanceCount>12</instanceCount>
<name>avalon</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IConnection</subtype>
<displayName>Avalon Memory Mapped Connection</displayName>
<version>12.1</version>
</plugin>
<plugin>
<instanceCount>1</instanceCount>
<name>clock_source</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IModule</subtype>
<displayName>Clock Source</displayName>
<version>12.1</version>
</plugin>
<plugin>
<instanceCount>1</instanceCount>
<name>hibi_pe_dma</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IModule</subtype>
<displayName>hibi_pe_dma</displayName>
<version>1.0</version>
</plugin>
<plugin>
<instanceCount>1</instanceCount>
<name>conduit_end</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
<displayName>Conduit</displayName>
<version>12.1</version>
</plugin>
<plugin>
<instanceCount>4</instanceCount>
<name>interrupt</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IConnection</subtype>
<displayName>Interrupt Connection</displayName>
<version>12.1</version>
</plugin>
<plugin>
<instanceCount>9</instanceCount>
<name>reset</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IConnection</subtype>
<displayName>Reset Connection</displayName>
<version>12.1</version>
</plugin>
<plugin>
<instanceCount>1</instanceCount>
<name>reset_source</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
<displayName>Reset Output</displayName>
<version>12.1</version>
</plugin>
<plugin>
<instanceCount>9</instanceCount>
<name>clock</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IConnection</subtype>
<displayName>Clock Connection</displayName>
<version>12.1</version>
</plugin>
<plugin>
<instanceCount>7</instanceCount>
<name>clock_sink</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
<displayName>Clock Input</displayName>
<version>12.1</version>
</plugin>
<plugin>
<instanceCount>4</instanceCount>
<name>avalon_master</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
<displayName>Avalon Memory Mapped Master</displayName>
<version>12.1</version>
</plugin>
<plugin>
<instanceCount>7</instanceCount>
<name>reset_sink</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
<displayName>Reset Input</displayName>
<version>12.1</version>
</plugin>
<plugin>
<instanceCount>2</instanceCount>
<name>altera_avalon_timer</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IModule</subtype>
<displayName>Interval Timer</displayName>
<version>12.1</version>
</plugin>
<plugin>
<instanceCount>1</instanceCount>
<name>interrupt_receiver</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
<displayName>Interrupt Receiver</displayName>
<version>12.1</version>
</plugin>
<plugin>
<instanceCount>1</instanceCount>
<name>altera_avalon_onchip_memory2</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IModule</subtype>
<displayName>On-Chip Memory (RAM or ROM)</displayName>
<version>12.1</version>
</plugin>
<plugin>
<instanceCount>1</instanceCount>
<name>altera_avalon_jtag_uart</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IModule</subtype>
<displayName>JTAG UART</displayName>
<version>12.1</version>
</plugin>
<plugin>
<instanceCount>6</instanceCount>
<name>avalon_slave</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
<displayName>Avalon Memory Mapped Slave</displayName>
<version>12.1</version>
</plugin>
<reportVersion>12.1 177</reportVersion>
<uniqueIdentifier></uniqueIdentifier>
</EnsembleReport>
/funbase_ip_library/trunk/Altera/ip.hwp.cpu/nios_ii_sdram/2.0/hdl/nios2_sdram/synthesis/nios2_sdram.v
0,0 → 1,3907
// nios2_sdram.v
 
// Generated using ACDS version 12.1 177 at 2013.06.11.13:52:14
 
`timescale 1 ps / 1 ps
module nios2_sdram (
input wire [31:0] hibi_pe_dma_data_in, // hibi_pe_dma.data_in
input wire hibi_pe_dma_av_in, // .av_in
input wire hibi_pe_dma_empty_in, // .empty_in
input wire [4:0] hibi_pe_dma_comm_in, // .comm_in
output wire hibi_pe_dma_re_out, // .re_out
output wire [31:0] hibi_pe_dma_data_out, // .data_out
output wire hibi_pe_dma_av_out, // .av_out
input wire hibi_pe_dma_full_in, // .full_in
output wire [4:0] hibi_pe_dma_comm_out, // .comm_out
output wire hibi_pe_dma_we_out, // .we_out
output wire [11:0] sdram_0_addr, // sdram_0.addr
output wire [1:0] sdram_0_ba, // .ba
output wire sdram_0_cas_n, // .cas_n
output wire sdram_0_cke, // .cke
output wire sdram_0_cs_n, // .cs_n
inout wire [15:0] sdram_0_dq, // .dq
output wire [1:0] sdram_0_dqm, // .dqm
output wire sdram_0_ras_n, // .ras_n
output wire sdram_0_we_n, // .we_n
input wire reset_reset_n, // reset.reset_n
input wire clk_clk // clk.clk
);
 
wire nios2_qsys_1_instruction_master_waitrequest; // nios2_qsys_1_instruction_master_translator:av_waitrequest -> nios2_qsys_1:i_waitrequest
wire [25:0] nios2_qsys_1_instruction_master_address; // nios2_qsys_1:i_address -> nios2_qsys_1_instruction_master_translator:av_address
wire nios2_qsys_1_instruction_master_read; // nios2_qsys_1:i_read -> nios2_qsys_1_instruction_master_translator:av_read
wire [31:0] nios2_qsys_1_instruction_master_readdata; // nios2_qsys_1_instruction_master_translator:av_readdata -> nios2_qsys_1:i_readdata
wire nios2_qsys_1_instruction_master_readdatavalid; // nios2_qsys_1_instruction_master_translator:av_readdatavalid -> nios2_qsys_1:i_readdatavalid
wire nios2_qsys_1_data_master_waitrequest; // nios2_qsys_1_data_master_translator:av_waitrequest -> nios2_qsys_1:d_waitrequest
wire [31:0] nios2_qsys_1_data_master_writedata; // nios2_qsys_1:d_writedata -> nios2_qsys_1_data_master_translator:av_writedata
wire [25:0] nios2_qsys_1_data_master_address; // nios2_qsys_1:d_address -> nios2_qsys_1_data_master_translator:av_address
wire nios2_qsys_1_data_master_write; // nios2_qsys_1:d_write -> nios2_qsys_1_data_master_translator:av_write
wire nios2_qsys_1_data_master_read; // nios2_qsys_1:d_read -> nios2_qsys_1_data_master_translator:av_read
wire [31:0] nios2_qsys_1_data_master_readdata; // nios2_qsys_1_data_master_translator:av_readdata -> nios2_qsys_1:d_readdata
wire nios2_qsys_1_data_master_debugaccess; // nios2_qsys_1:jtag_debug_module_debugaccess_to_roms -> nios2_qsys_1_data_master_translator:av_debugaccess
wire nios2_qsys_1_data_master_readdatavalid; // nios2_qsys_1_data_master_translator:av_readdatavalid -> nios2_qsys_1:d_readdatavalid
wire [3:0] nios2_qsys_1_data_master_byteenable; // nios2_qsys_1:d_byteenable -> nios2_qsys_1_data_master_translator:av_byteenable
wire [31:0] nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_writedata; // nios2_qsys_1_jtag_debug_module_translator:av_writedata -> nios2_qsys_1:jtag_debug_module_writedata
wire [8:0] nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_address; // nios2_qsys_1_jtag_debug_module_translator:av_address -> nios2_qsys_1:jtag_debug_module_address
wire nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_chipselect; // nios2_qsys_1_jtag_debug_module_translator:av_chipselect -> nios2_qsys_1:jtag_debug_module_select
wire nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_write; // nios2_qsys_1_jtag_debug_module_translator:av_write -> nios2_qsys_1:jtag_debug_module_write
wire [31:0] nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_readdata; // nios2_qsys_1:jtag_debug_module_readdata -> nios2_qsys_1_jtag_debug_module_translator:av_readdata
wire nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_begintransfer; // nios2_qsys_1_jtag_debug_module_translator:av_begintransfer -> nios2_qsys_1:jtag_debug_module_begintransfer
wire nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess; // nios2_qsys_1_jtag_debug_module_translator:av_debugaccess -> nios2_qsys_1:jtag_debug_module_debugaccess
wire [3:0] nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_byteenable; // nios2_qsys_1_jtag_debug_module_translator:av_byteenable -> nios2_qsys_1:jtag_debug_module_byteenable
wire sdram_0_s1_translator_avalon_anti_slave_0_waitrequest; // sdram_0:za_waitrequest -> sdram_0_s1_translator:av_waitrequest
wire [15:0] sdram_0_s1_translator_avalon_anti_slave_0_writedata; // sdram_0_s1_translator:av_writedata -> sdram_0:az_data
wire [21:0] sdram_0_s1_translator_avalon_anti_slave_0_address; // sdram_0_s1_translator:av_address -> sdram_0:az_addr
wire sdram_0_s1_translator_avalon_anti_slave_0_chipselect; // sdram_0_s1_translator:av_chipselect -> sdram_0:az_cs
wire sdram_0_s1_translator_avalon_anti_slave_0_write; // sdram_0_s1_translator:av_write -> sdram_0:az_wr_n
wire sdram_0_s1_translator_avalon_anti_slave_0_read; // sdram_0_s1_translator:av_read -> sdram_0:az_rd_n
wire [15:0] sdram_0_s1_translator_avalon_anti_slave_0_readdata; // sdram_0:za_data -> sdram_0_s1_translator:av_readdata
wire sdram_0_s1_translator_avalon_anti_slave_0_readdatavalid; // sdram_0:za_valid -> sdram_0_s1_translator:av_readdatavalid
wire [1:0] sdram_0_s1_translator_avalon_anti_slave_0_byteenable; // sdram_0_s1_translator:av_byteenable -> sdram_0:az_be_n
wire jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest; // jtag_uart_1:av_waitrequest -> jtag_uart_1_avalon_jtag_slave_translator:av_waitrequest
wire [31:0] jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata; // jtag_uart_1_avalon_jtag_slave_translator:av_writedata -> jtag_uart_1:av_writedata
wire [0:0] jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_address; // jtag_uart_1_avalon_jtag_slave_translator:av_address -> jtag_uart_1:av_address
wire jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect; // jtag_uart_1_avalon_jtag_slave_translator:av_chipselect -> jtag_uart_1:av_chipselect
wire jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_write; // jtag_uart_1_avalon_jtag_slave_translator:av_write -> jtag_uart_1:av_write_n
wire jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_read; // jtag_uart_1_avalon_jtag_slave_translator:av_read -> jtag_uart_1:av_read_n
wire [31:0] jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata; // jtag_uart_1:av_readdata -> jtag_uart_1_avalon_jtag_slave_translator:av_readdata
wire [15:0] timer_1_s1_translator_avalon_anti_slave_0_writedata; // timer_1_s1_translator:av_writedata -> timer_1:writedata
wire [2:0] timer_1_s1_translator_avalon_anti_slave_0_address; // timer_1_s1_translator:av_address -> timer_1:address
wire timer_1_s1_translator_avalon_anti_slave_0_chipselect; // timer_1_s1_translator:av_chipselect -> timer_1:chipselect
wire timer_1_s1_translator_avalon_anti_slave_0_write; // timer_1_s1_translator:av_write -> timer_1:write_n
wire [15:0] timer_1_s1_translator_avalon_anti_slave_0_readdata; // timer_1:readdata -> timer_1_s1_translator:av_readdata
wire [15:0] timer_0_s1_translator_avalon_anti_slave_0_writedata; // timer_0_s1_translator:av_writedata -> timer_0:writedata
wire [2:0] timer_0_s1_translator_avalon_anti_slave_0_address; // timer_0_s1_translator:av_address -> timer_0:address
wire timer_0_s1_translator_avalon_anti_slave_0_chipselect; // timer_0_s1_translator:av_chipselect -> timer_0:chipselect
wire timer_0_s1_translator_avalon_anti_slave_0_write; // timer_0_s1_translator:av_write -> timer_0:write_n
wire [15:0] timer_0_s1_translator_avalon_anti_slave_0_readdata; // timer_0:readdata -> timer_0_s1_translator:av_readdata
wire [0:0] sysid_qsys_1_control_slave_translator_avalon_anti_slave_0_address; // sysid_qsys_1_control_slave_translator:av_address -> sysid_qsys_1:address
wire [31:0] sysid_qsys_1_control_slave_translator_avalon_anti_slave_0_readdata; // sysid_qsys_1:readdata -> sysid_qsys_1_control_slave_translator:av_readdata
wire [31:0] onchip_memory2_1_s1_translator_avalon_anti_slave_0_writedata; // onchip_memory2_1_s1_translator:av_writedata -> onchip_memory2_1:writedata
wire [10:0] onchip_memory2_1_s1_translator_avalon_anti_slave_0_address; // onchip_memory2_1_s1_translator:av_address -> onchip_memory2_1:address
wire onchip_memory2_1_s1_translator_avalon_anti_slave_0_chipselect; // onchip_memory2_1_s1_translator:av_chipselect -> onchip_memory2_1:chipselect
wire onchip_memory2_1_s1_translator_avalon_anti_slave_0_clken; // onchip_memory2_1_s1_translator:av_clken -> onchip_memory2_1:clken
wire onchip_memory2_1_s1_translator_avalon_anti_slave_0_write; // onchip_memory2_1_s1_translator:av_write -> onchip_memory2_1:write
wire [31:0] onchip_memory2_1_s1_translator_avalon_anti_slave_0_readdata; // onchip_memory2_1:readdata -> onchip_memory2_1_s1_translator:av_readdata
wire [3:0] onchip_memory2_1_s1_translator_avalon_anti_slave_0_byteenable; // onchip_memory2_1_s1_translator:av_byteenable -> onchip_memory2_1:byteenable
wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest; // hibi_pe_dma_0:avalon_cfg_waitrequest_out -> hibi_pe_dma_0_avalon_slave_0_translator:av_waitrequest
wire [31:0] hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_writedata; // hibi_pe_dma_0_avalon_slave_0_translator:av_writedata -> hibi_pe_dma_0:avalon_cfg_writedata_in
wire [6:0] hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_address; // hibi_pe_dma_0_avalon_slave_0_translator:av_address -> hibi_pe_dma_0:avalon_cfg_addr_in
wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_chipselect; // hibi_pe_dma_0_avalon_slave_0_translator:av_chipselect -> hibi_pe_dma_0:avalon_cfg_cs_in
wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_write; // hibi_pe_dma_0_avalon_slave_0_translator:av_write -> hibi_pe_dma_0:avalon_cfg_we_in
wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_read; // hibi_pe_dma_0_avalon_slave_0_translator:av_read -> hibi_pe_dma_0:avalon_cfg_re_in
wire [31:0] hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata; // hibi_pe_dma_0:avalon_cfg_readdata_out -> hibi_pe_dma_0_avalon_slave_0_translator:av_readdata
wire hibi_pe_dma_0_avalon_master_waitrequest; // hibi_pe_dma_0_avalon_master_translator:av_waitrequest -> hibi_pe_dma_0:avalon_waitrequest_in_rx
wire [31:0] hibi_pe_dma_0_avalon_master_writedata; // hibi_pe_dma_0:avalon_writedata_out_rx -> hibi_pe_dma_0_avalon_master_translator:av_writedata
wire [31:0] hibi_pe_dma_0_avalon_master_address; // hibi_pe_dma_0:avalon_addr_out_rx -> hibi_pe_dma_0_avalon_master_translator:av_address
wire hibi_pe_dma_0_avalon_master_write; // hibi_pe_dma_0:avalon_we_out_rx -> hibi_pe_dma_0_avalon_master_translator:av_write
wire [3:0] hibi_pe_dma_0_avalon_master_byteenable; // hibi_pe_dma_0:avalon_be_out_rx -> hibi_pe_dma_0_avalon_master_translator:av_byteenable
wire hibi_pe_dma_0_avalon_master_1_waitrequest; // hibi_pe_dma_0_avalon_master_1_translator:av_waitrequest -> hibi_pe_dma_0:avalon_waitrequest_in_tx
wire [31:0] hibi_pe_dma_0_avalon_master_1_address; // hibi_pe_dma_0:avalon_addr_out_tx -> hibi_pe_dma_0_avalon_master_1_translator:av_address
wire hibi_pe_dma_0_avalon_master_1_read; // hibi_pe_dma_0:avalon_re_out_tx -> hibi_pe_dma_0_avalon_master_1_translator:av_read
wire [31:0] hibi_pe_dma_0_avalon_master_1_readdata; // hibi_pe_dma_0_avalon_master_1_translator:av_readdata -> hibi_pe_dma_0:avalon_readdata_in_tx
wire hibi_pe_dma_0_avalon_master_1_readdatavalid; // hibi_pe_dma_0_avalon_master_1_translator:av_readdatavalid -> hibi_pe_dma_0:avalon_readdatavalid_in_tx
wire [31:0] onchip_memory2_1_s2_translator_avalon_anti_slave_0_writedata; // onchip_memory2_1_s2_translator:av_writedata -> onchip_memory2_1:writedata2
wire [10:0] onchip_memory2_1_s2_translator_avalon_anti_slave_0_address; // onchip_memory2_1_s2_translator:av_address -> onchip_memory2_1:address2
wire onchip_memory2_1_s2_translator_avalon_anti_slave_0_chipselect; // onchip_memory2_1_s2_translator:av_chipselect -> onchip_memory2_1:chipselect2
wire onchip_memory2_1_s2_translator_avalon_anti_slave_0_clken; // onchip_memory2_1_s2_translator:av_clken -> onchip_memory2_1:clken2
wire onchip_memory2_1_s2_translator_avalon_anti_slave_0_write; // onchip_memory2_1_s2_translator:av_write -> onchip_memory2_1:write2
wire [31:0] onchip_memory2_1_s2_translator_avalon_anti_slave_0_readdata; // onchip_memory2_1:readdata2 -> onchip_memory2_1_s2_translator:av_readdata
wire [3:0] onchip_memory2_1_s2_translator_avalon_anti_slave_0_byteenable; // onchip_memory2_1_s2_translator:av_byteenable -> onchip_memory2_1:byteenable2
wire nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_waitrequest; // nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:av_waitrequest -> nios2_qsys_1_instruction_master_translator:uav_waitrequest
wire [2:0] nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_burstcount; // nios2_qsys_1_instruction_master_translator:uav_burstcount -> nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:av_burstcount
wire [31:0] nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_writedata; // nios2_qsys_1_instruction_master_translator:uav_writedata -> nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:av_writedata
wire [25:0] nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_address; // nios2_qsys_1_instruction_master_translator:uav_address -> nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:av_address
wire nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_lock; // nios2_qsys_1_instruction_master_translator:uav_lock -> nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:av_lock
wire nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_write; // nios2_qsys_1_instruction_master_translator:uav_write -> nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:av_write
wire nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_read; // nios2_qsys_1_instruction_master_translator:uav_read -> nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:av_read
wire [31:0] nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_readdata; // nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:av_readdata -> nios2_qsys_1_instruction_master_translator:uav_readdata
wire nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_debugaccess; // nios2_qsys_1_instruction_master_translator:uav_debugaccess -> nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:av_debugaccess
wire [3:0] nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_byteenable; // nios2_qsys_1_instruction_master_translator:uav_byteenable -> nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:av_byteenable
wire nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_readdatavalid; // nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> nios2_qsys_1_instruction_master_translator:uav_readdatavalid
wire nios2_qsys_1_data_master_translator_avalon_universal_master_0_waitrequest; // nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:av_waitrequest -> nios2_qsys_1_data_master_translator:uav_waitrequest
wire [2:0] nios2_qsys_1_data_master_translator_avalon_universal_master_0_burstcount; // nios2_qsys_1_data_master_translator:uav_burstcount -> nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:av_burstcount
wire [31:0] nios2_qsys_1_data_master_translator_avalon_universal_master_0_writedata; // nios2_qsys_1_data_master_translator:uav_writedata -> nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:av_writedata
wire [25:0] nios2_qsys_1_data_master_translator_avalon_universal_master_0_address; // nios2_qsys_1_data_master_translator:uav_address -> nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:av_address
wire nios2_qsys_1_data_master_translator_avalon_universal_master_0_lock; // nios2_qsys_1_data_master_translator:uav_lock -> nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:av_lock
wire nios2_qsys_1_data_master_translator_avalon_universal_master_0_write; // nios2_qsys_1_data_master_translator:uav_write -> nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:av_write
wire nios2_qsys_1_data_master_translator_avalon_universal_master_0_read; // nios2_qsys_1_data_master_translator:uav_read -> nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:av_read
wire [31:0] nios2_qsys_1_data_master_translator_avalon_universal_master_0_readdata; // nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:av_readdata -> nios2_qsys_1_data_master_translator:uav_readdata
wire nios2_qsys_1_data_master_translator_avalon_universal_master_0_debugaccess; // nios2_qsys_1_data_master_translator:uav_debugaccess -> nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:av_debugaccess
wire [3:0] nios2_qsys_1_data_master_translator_avalon_universal_master_0_byteenable; // nios2_qsys_1_data_master_translator:uav_byteenable -> nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:av_byteenable
wire nios2_qsys_1_data_master_translator_avalon_universal_master_0_readdatavalid; // nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> nios2_qsys_1_data_master_translator:uav_readdatavalid
wire nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest; // nios2_qsys_1_jtag_debug_module_translator:uav_waitrequest -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount; // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_burstcount -> nios2_qsys_1_jtag_debug_module_translator:uav_burstcount
wire [31:0] nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata; // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_writedata -> nios2_qsys_1_jtag_debug_module_translator:uav_writedata
wire [25:0] nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address; // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_address -> nios2_qsys_1_jtag_debug_module_translator:uav_address
wire nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write; // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_write -> nios2_qsys_1_jtag_debug_module_translator:uav_write
wire nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock; // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_lock -> nios2_qsys_1_jtag_debug_module_translator:uav_lock
wire nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read; // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_read -> nios2_qsys_1_jtag_debug_module_translator:uav_read
wire [31:0] nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata; // nios2_qsys_1_jtag_debug_module_translator:uav_readdata -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdata
wire nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // nios2_qsys_1_jtag_debug_module_translator:uav_readdatavalid -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess; // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_debugaccess -> nios2_qsys_1_jtag_debug_module_translator:uav_debugaccess
wire [3:0] nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable; // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_byteenable -> nios2_qsys_1_jtag_debug_module_translator:uav_byteenable
wire nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid; // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_valid -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [99:0] nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data; // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_data -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready; // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_ready
wire nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [99:0] nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_data
wire nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_ready -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // sdram_0_s1_translator:uav_waitrequest -> sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [1:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> sdram_0_s1_translator:uav_burstcount
wire [15:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> sdram_0_s1_translator:uav_writedata
wire [25:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_address; // sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_address -> sdram_0_s1_translator:uav_address
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_write; // sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_write -> sdram_0_s1_translator:uav_write
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_lock; // sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_lock -> sdram_0_s1_translator:uav_lock
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_read; // sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_read -> sdram_0_s1_translator:uav_read
wire [15:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // sdram_0_s1_translator:uav_readdata -> sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_readdata
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // sdram_0_s1_translator:uav_readdatavalid -> sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sdram_0_s1_translator:uav_debugaccess
wire [1:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> sdram_0_s1_translator:uav_byteenable
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [81:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [81:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [15:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest; // jtag_uart_1_avalon_jtag_slave_translator:uav_waitrequest -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount; // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> jtag_uart_1_avalon_jtag_slave_translator:uav_burstcount
wire [31:0] jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata; // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> jtag_uart_1_avalon_jtag_slave_translator:uav_writedata
wire [25:0] jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address; // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_address -> jtag_uart_1_avalon_jtag_slave_translator:uav_address
wire jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write; // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_write -> jtag_uart_1_avalon_jtag_slave_translator:uav_write
wire jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock; // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_lock -> jtag_uart_1_avalon_jtag_slave_translator:uav_lock
wire jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read; // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_read -> jtag_uart_1_avalon_jtag_slave_translator:uav_read
wire [31:0] jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata; // jtag_uart_1_avalon_jtag_slave_translator:uav_readdata -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_readdata
wire jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // jtag_uart_1_avalon_jtag_slave_translator:uav_readdatavalid -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess; // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> jtag_uart_1_avalon_jtag_slave_translator:uav_debugaccess
wire [3:0] jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable; // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> jtag_uart_1_avalon_jtag_slave_translator:uav_byteenable
wire jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid; // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [99:0] jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data; // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready; // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
wire jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [99:0] jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
wire jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire timer_1_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // timer_1_s1_translator:uav_waitrequest -> timer_1_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] timer_1_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // timer_1_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> timer_1_s1_translator:uav_burstcount
wire [31:0] timer_1_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // timer_1_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> timer_1_s1_translator:uav_writedata
wire [25:0] timer_1_s1_translator_avalon_universal_slave_0_agent_m0_address; // timer_1_s1_translator_avalon_universal_slave_0_agent:m0_address -> timer_1_s1_translator:uav_address
wire timer_1_s1_translator_avalon_universal_slave_0_agent_m0_write; // timer_1_s1_translator_avalon_universal_slave_0_agent:m0_write -> timer_1_s1_translator:uav_write
wire timer_1_s1_translator_avalon_universal_slave_0_agent_m0_lock; // timer_1_s1_translator_avalon_universal_slave_0_agent:m0_lock -> timer_1_s1_translator:uav_lock
wire timer_1_s1_translator_avalon_universal_slave_0_agent_m0_read; // timer_1_s1_translator_avalon_universal_slave_0_agent:m0_read -> timer_1_s1_translator:uav_read
wire [31:0] timer_1_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // timer_1_s1_translator:uav_readdata -> timer_1_s1_translator_avalon_universal_slave_0_agent:m0_readdata
wire timer_1_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // timer_1_s1_translator:uav_readdatavalid -> timer_1_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire timer_1_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // timer_1_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> timer_1_s1_translator:uav_debugaccess
wire [3:0] timer_1_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // timer_1_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> timer_1_s1_translator:uav_byteenable
wire timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // timer_1_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // timer_1_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // timer_1_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [99:0] timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // timer_1_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> timer_1_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
wire timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> timer_1_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> timer_1_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> timer_1_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [99:0] timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> timer_1_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
wire timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // timer_1_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire timer_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // timer_1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> timer_1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] timer_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // timer_1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> timer_1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire timer_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // timer_1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> timer_1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire timer_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // timer_0_s1_translator:uav_waitrequest -> timer_0_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] timer_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // timer_0_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> timer_0_s1_translator:uav_burstcount
wire [31:0] timer_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // timer_0_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> timer_0_s1_translator:uav_writedata
wire [25:0] timer_0_s1_translator_avalon_universal_slave_0_agent_m0_address; // timer_0_s1_translator_avalon_universal_slave_0_agent:m0_address -> timer_0_s1_translator:uav_address
wire timer_0_s1_translator_avalon_universal_slave_0_agent_m0_write; // timer_0_s1_translator_avalon_universal_slave_0_agent:m0_write -> timer_0_s1_translator:uav_write
wire timer_0_s1_translator_avalon_universal_slave_0_agent_m0_lock; // timer_0_s1_translator_avalon_universal_slave_0_agent:m0_lock -> timer_0_s1_translator:uav_lock
wire timer_0_s1_translator_avalon_universal_slave_0_agent_m0_read; // timer_0_s1_translator_avalon_universal_slave_0_agent:m0_read -> timer_0_s1_translator:uav_read
wire [31:0] timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // timer_0_s1_translator:uav_readdata -> timer_0_s1_translator_avalon_universal_slave_0_agent:m0_readdata
wire timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // timer_0_s1_translator:uav_readdatavalid -> timer_0_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire timer_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // timer_0_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> timer_0_s1_translator:uav_debugaccess
wire [3:0] timer_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // timer_0_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> timer_0_s1_translator:uav_byteenable
wire timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [99:0] timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
wire timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [99:0] timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
wire timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest; // sysid_qsys_1_control_slave_translator:uav_waitrequest -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount; // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> sysid_qsys_1_control_slave_translator:uav_burstcount
wire [31:0] sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata; // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> sysid_qsys_1_control_slave_translator:uav_writedata
wire [25:0] sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_address; // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:m0_address -> sysid_qsys_1_control_slave_translator:uav_address
wire sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_write; // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:m0_write -> sysid_qsys_1_control_slave_translator:uav_write
wire sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_lock; // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:m0_lock -> sysid_qsys_1_control_slave_translator:uav_lock
wire sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_read; // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:m0_read -> sysid_qsys_1_control_slave_translator:uav_read
wire [31:0] sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata; // sysid_qsys_1_control_slave_translator:uav_readdata -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:m0_readdata
wire sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // sysid_qsys_1_control_slave_translator:uav_readdatavalid -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess; // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sysid_qsys_1_control_slave_translator:uav_debugaccess
wire [3:0] sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable; // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> sysid_qsys_1_control_slave_translator:uav_byteenable
wire sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid; // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [99:0] sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data; // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready; // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
wire sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [99:0] sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
wire sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // onchip_memory2_1_s1_translator:uav_waitrequest -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> onchip_memory2_1_s1_translator:uav_burstcount
wire [31:0] onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> onchip_memory2_1_s1_translator:uav_writedata
wire [25:0] onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_address; // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:m0_address -> onchip_memory2_1_s1_translator:uav_address
wire onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_write; // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:m0_write -> onchip_memory2_1_s1_translator:uav_write
wire onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_lock; // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:m0_lock -> onchip_memory2_1_s1_translator:uav_lock
wire onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_read; // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:m0_read -> onchip_memory2_1_s1_translator:uav_read
wire [31:0] onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // onchip_memory2_1_s1_translator:uav_readdata -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:m0_readdata
wire onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // onchip_memory2_1_s1_translator:uav_readdatavalid -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> onchip_memory2_1_s1_translator:uav_debugaccess
wire [3:0] onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> onchip_memory2_1_s1_translator:uav_byteenable
wire onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [99:0] onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
wire onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [99:0] onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
wire onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hibi_pe_dma_0_avalon_slave_0_translator:uav_waitrequest -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_burstcount -> hibi_pe_dma_0_avalon_slave_0_translator:uav_burstcount
wire [31:0] hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_writedata -> hibi_pe_dma_0_avalon_slave_0_translator:uav_writedata
wire [25:0] hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_address -> hibi_pe_dma_0_avalon_slave_0_translator:uav_address
wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_write -> hibi_pe_dma_0_avalon_slave_0_translator:uav_write
wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_lock -> hibi_pe_dma_0_avalon_slave_0_translator:uav_lock
wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_read -> hibi_pe_dma_0_avalon_slave_0_translator:uav_read
wire [31:0] hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata; // hibi_pe_dma_0_avalon_slave_0_translator:uav_readdata -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdata
wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hibi_pe_dma_0_avalon_slave_0_translator:uav_readdatavalid -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hibi_pe_dma_0_avalon_slave_0_translator:uav_debugaccess
wire [3:0] hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_byteenable -> hibi_pe_dma_0_avalon_slave_0_translator:uav_byteenable
wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_valid -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [99:0] hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_data -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_ready
wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [99:0] hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_data
wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_waitrequest; // hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:av_waitrequest -> hibi_pe_dma_0_avalon_master_translator:uav_waitrequest
wire [2:0] hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_burstcount; // hibi_pe_dma_0_avalon_master_translator:uav_burstcount -> hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:av_burstcount
wire [31:0] hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_writedata; // hibi_pe_dma_0_avalon_master_translator:uav_writedata -> hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:av_writedata
wire [31:0] hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_address; // hibi_pe_dma_0_avalon_master_translator:uav_address -> hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:av_address
wire hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_lock; // hibi_pe_dma_0_avalon_master_translator:uav_lock -> hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:av_lock
wire hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_write; // hibi_pe_dma_0_avalon_master_translator:uav_write -> hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:av_write
wire hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_read; // hibi_pe_dma_0_avalon_master_translator:uav_read -> hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:av_read
wire [31:0] hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_readdata; // hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:av_readdata -> hibi_pe_dma_0_avalon_master_translator:uav_readdata
wire hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_debugaccess; // hibi_pe_dma_0_avalon_master_translator:uav_debugaccess -> hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:av_debugaccess
wire [3:0] hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_byteenable; // hibi_pe_dma_0_avalon_master_translator:uav_byteenable -> hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:av_byteenable
wire hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_readdatavalid; // hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> hibi_pe_dma_0_avalon_master_translator:uav_readdatavalid
wire hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_waitrequest; // hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:av_waitrequest -> hibi_pe_dma_0_avalon_master_1_translator:uav_waitrequest
wire [2:0] hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_burstcount; // hibi_pe_dma_0_avalon_master_1_translator:uav_burstcount -> hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:av_burstcount
wire [31:0] hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_writedata; // hibi_pe_dma_0_avalon_master_1_translator:uav_writedata -> hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:av_writedata
wire [31:0] hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_address; // hibi_pe_dma_0_avalon_master_1_translator:uav_address -> hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:av_address
wire hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_lock; // hibi_pe_dma_0_avalon_master_1_translator:uav_lock -> hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:av_lock
wire hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_write; // hibi_pe_dma_0_avalon_master_1_translator:uav_write -> hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:av_write
wire hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_read; // hibi_pe_dma_0_avalon_master_1_translator:uav_read -> hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:av_read
wire [31:0] hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_readdata; // hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:av_readdata -> hibi_pe_dma_0_avalon_master_1_translator:uav_readdata
wire hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_debugaccess; // hibi_pe_dma_0_avalon_master_1_translator:uav_debugaccess -> hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:av_debugaccess
wire [3:0] hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_byteenable; // hibi_pe_dma_0_avalon_master_1_translator:uav_byteenable -> hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:av_byteenable
wire hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_readdatavalid; // hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:av_readdatavalid -> hibi_pe_dma_0_avalon_master_1_translator:uav_readdatavalid
wire onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_waitrequest; // onchip_memory2_1_s2_translator:uav_waitrequest -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_burstcount; // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:m0_burstcount -> onchip_memory2_1_s2_translator:uav_burstcount
wire [31:0] onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_writedata; // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:m0_writedata -> onchip_memory2_1_s2_translator:uav_writedata
wire [31:0] onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_address; // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:m0_address -> onchip_memory2_1_s2_translator:uav_address
wire onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_write; // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:m0_write -> onchip_memory2_1_s2_translator:uav_write
wire onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_lock; // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:m0_lock -> onchip_memory2_1_s2_translator:uav_lock
wire onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_read; // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:m0_read -> onchip_memory2_1_s2_translator:uav_read
wire [31:0] onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_readdata; // onchip_memory2_1_s2_translator:uav_readdata -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:m0_readdata
wire onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // onchip_memory2_1_s2_translator:uav_readdatavalid -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_debugaccess; // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:m0_debugaccess -> onchip_memory2_1_s2_translator:uav_debugaccess
wire [3:0] onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_byteenable; // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:m0_byteenable -> onchip_memory2_1_s2_translator:uav_byteenable
wire onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rf_source_valid; // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rf_source_valid -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [101:0] onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rf_source_data; // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rf_source_data -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rf_source_ready; // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rf_source_ready
wire onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [101:0] onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rf_sink_data
wire onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rf_sink_ready -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router:sink_endofpacket
wire nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent_cp_valid; // nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router:sink_valid
wire nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router:sink_startofpacket
wire [98:0] nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent_cp_data; // nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router:sink_data
wire nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router:sink_ready -> nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:cp_ready
wire nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_001:sink_endofpacket
wire nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent_cp_valid; // nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_001:sink_valid
wire nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_001:sink_startofpacket
wire [98:0] nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent_cp_data; // nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router_001:sink_data
wire nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router_001:sink_ready -> nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:cp_ready
wire nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket; // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router:sink_endofpacket
wire nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid; // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_valid -> id_router:sink_valid
wire nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket; // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router:sink_startofpacket
wire [98:0] nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data; // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_data -> id_router:sink_data
wire nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready; // id_router:sink_ready -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_ready
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_001:sink_endofpacket
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_valid; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_001:sink_valid
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_001:sink_startofpacket
wire [80:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_data; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_001:sink_data
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_001:sink_ready -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_ready
wire jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket; // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_002:sink_endofpacket
wire jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid; // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_002:sink_valid
wire jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket; // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_002:sink_startofpacket
wire [98:0] jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data; // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_002:sink_data
wire jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_002:sink_ready -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_ready
wire timer_1_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // timer_1_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_003:sink_endofpacket
wire timer_1_s1_translator_avalon_universal_slave_0_agent_rp_valid; // timer_1_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_003:sink_valid
wire timer_1_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // timer_1_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_003:sink_startofpacket
wire [98:0] timer_1_s1_translator_avalon_universal_slave_0_agent_rp_data; // timer_1_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_003:sink_data
wire timer_1_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_003:sink_ready -> timer_1_s1_translator_avalon_universal_slave_0_agent:rp_ready
wire timer_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // timer_0_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_004:sink_endofpacket
wire timer_0_s1_translator_avalon_universal_slave_0_agent_rp_valid; // timer_0_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_004:sink_valid
wire timer_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // timer_0_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_004:sink_startofpacket
wire [98:0] timer_0_s1_translator_avalon_universal_slave_0_agent_rp_data; // timer_0_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_004:sink_data
wire timer_0_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_004:sink_ready -> timer_0_s1_translator_avalon_universal_slave_0_agent:rp_ready
wire sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket; // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_005:sink_endofpacket
wire sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rp_valid; // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_005:sink_valid
wire sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket; // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_005:sink_startofpacket
wire [98:0] sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rp_data; // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_005:sink_data
wire sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_005:sink_ready -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:rp_ready
wire onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_006:sink_endofpacket
wire onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rp_valid; // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_006:sink_valid
wire onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_006:sink_startofpacket
wire [98:0] onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rp_data; // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_006:sink_data
wire onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_006:sink_ready -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:rp_ready
wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_007:sink_endofpacket
wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_007:sink_valid
wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_007:sink_startofpacket
wire [98:0] hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_data -> id_router_007:sink_data
wire hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_007:sink_ready -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_ready
wire hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_002:sink_endofpacket
wire hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_valid; // hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_002:sink_valid
wire hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_002:sink_startofpacket
wire [100:0] hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_data; // hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router_002:sink_data
wire hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router_002:sink_ready -> hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:cp_ready
wire hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_endofpacket; // hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_003:sink_endofpacket
wire hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_valid; // hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_003:sink_valid
wire hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_startofpacket; // hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_003:sink_startofpacket
wire [100:0] hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_data; // hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:cp_data -> addr_router_003:sink_data
wire hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_ready; // addr_router_003:sink_ready -> hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:cp_ready
wire onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rp_endofpacket; // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_008:sink_endofpacket
wire onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rp_valid; // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_008:sink_valid
wire onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rp_startofpacket; // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_008:sink_startofpacket
wire [100:0] onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rp_data; // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rp_data -> id_router_008:sink_data
wire onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_008:sink_ready -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:rp_ready
wire addr_router_src_endofpacket; // addr_router:src_endofpacket -> limiter:cmd_sink_endofpacket
wire addr_router_src_valid; // addr_router:src_valid -> limiter:cmd_sink_valid
wire addr_router_src_startofpacket; // addr_router:src_startofpacket -> limiter:cmd_sink_startofpacket
wire [98:0] addr_router_src_data; // addr_router:src_data -> limiter:cmd_sink_data
wire [7:0] addr_router_src_channel; // addr_router:src_channel -> limiter:cmd_sink_channel
wire addr_router_src_ready; // limiter:cmd_sink_ready -> addr_router:src_ready
wire limiter_rsp_src_endofpacket; // limiter:rsp_src_endofpacket -> nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:rp_endofpacket
wire limiter_rsp_src_valid; // limiter:rsp_src_valid -> nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:rp_valid
wire limiter_rsp_src_startofpacket; // limiter:rsp_src_startofpacket -> nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:rp_startofpacket
wire [98:0] limiter_rsp_src_data; // limiter:rsp_src_data -> nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:rp_data
wire [7:0] limiter_rsp_src_channel; // limiter:rsp_src_channel -> nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:rp_channel
wire limiter_rsp_src_ready; // nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:rp_ready -> limiter:rsp_src_ready
wire addr_router_001_src_endofpacket; // addr_router_001:src_endofpacket -> limiter_001:cmd_sink_endofpacket
wire addr_router_001_src_valid; // addr_router_001:src_valid -> limiter_001:cmd_sink_valid
wire addr_router_001_src_startofpacket; // addr_router_001:src_startofpacket -> limiter_001:cmd_sink_startofpacket
wire [98:0] addr_router_001_src_data; // addr_router_001:src_data -> limiter_001:cmd_sink_data
wire [7:0] addr_router_001_src_channel; // addr_router_001:src_channel -> limiter_001:cmd_sink_channel
wire addr_router_001_src_ready; // limiter_001:cmd_sink_ready -> addr_router_001:src_ready
wire limiter_001_rsp_src_endofpacket; // limiter_001:rsp_src_endofpacket -> nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:rp_endofpacket
wire limiter_001_rsp_src_valid; // limiter_001:rsp_src_valid -> nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:rp_valid
wire limiter_001_rsp_src_startofpacket; // limiter_001:rsp_src_startofpacket -> nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:rp_startofpacket
wire [98:0] limiter_001_rsp_src_data; // limiter_001:rsp_src_data -> nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:rp_data
wire [7:0] limiter_001_rsp_src_channel; // limiter_001:rsp_src_channel -> nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:rp_channel
wire limiter_001_rsp_src_ready; // nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:rp_ready -> limiter_001:rsp_src_ready
wire burst_adapter_source0_endofpacket; // burst_adapter:source0_endofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire burst_adapter_source0_valid; // burst_adapter:source0_valid -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_valid
wire burst_adapter_source0_startofpacket; // burst_adapter:source0_startofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [80:0] burst_adapter_source0_data; // burst_adapter:source0_data -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_data
wire burst_adapter_source0_ready; // sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_ready -> burst_adapter:source0_ready
wire [7:0] burst_adapter_source0_channel; // burst_adapter:source0_channel -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_channel
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [addr_router:reset, addr_router_001:reset, addr_router_002:reset, addr_router_003:reset, burst_adapter:reset, cmd_xbar_demux:reset, cmd_xbar_demux_001:reset, cmd_xbar_demux_002:reset, cmd_xbar_demux_003:reset, cmd_xbar_mux:reset, cmd_xbar_mux_001:reset, cmd_xbar_mux_008:reset, hibi_pe_dma_0:rst_n, hibi_pe_dma_0_avalon_master_1_translator:reset, hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:reset, hibi_pe_dma_0_avalon_master_translator:reset, hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:reset, hibi_pe_dma_0_avalon_slave_0_translator:reset, hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:reset, hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, id_router:reset, id_router_001:reset, id_router_002:reset, id_router_003:reset, id_router_004:reset, id_router_005:reset, id_router_006:reset, id_router_007:reset, id_router_008:reset, irq_mapper:reset, jtag_uart_1:rst_n, jtag_uart_1_avalon_jtag_slave_translator:reset, jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:reset, jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, limiter:reset, limiter_001:reset, nios2_qsys_1:reset_n, nios2_qsys_1_data_master_translator:reset, nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent:reset, nios2_qsys_1_instruction_master_translator:reset, nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent:reset, nios2_qsys_1_jtag_debug_module_translator:reset, nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:reset, nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, onchip_memory2_1:reset, onchip_memory2_1:reset2, onchip_memory2_1_s1_translator:reset, onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:reset, onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, onchip_memory2_1_s2_translator:reset, onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:reset, onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, rsp_xbar_demux:reset, rsp_xbar_demux_001:reset, rsp_xbar_demux_002:reset, rsp_xbar_demux_003:reset, rsp_xbar_demux_004:reset, rsp_xbar_demux_005:reset, rsp_xbar_demux_006:reset, rsp_xbar_demux_007:reset, rsp_xbar_demux_008:reset, rsp_xbar_mux:reset, rsp_xbar_mux_001:reset, sdram_0:reset_n, sdram_0_s1_translator:reset, sdram_0_s1_translator_avalon_universal_slave_0_agent:reset, sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, sysid_qsys_1:reset_n, sysid_qsys_1_control_slave_translator:reset, sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:reset, sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, timer_0:reset_n, timer_0_s1_translator:reset, timer_0_s1_translator_avalon_universal_slave_0_agent:reset, timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, timer_1:reset_n, timer_1_s1_translator:reset, timer_1_s1_translator_avalon_universal_slave_0_agent:reset, timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, width_adapter:reset, width_adapter_001:reset]
wire cmd_xbar_demux_src0_endofpacket; // cmd_xbar_demux:src0_endofpacket -> cmd_xbar_mux:sink0_endofpacket
wire cmd_xbar_demux_src0_valid; // cmd_xbar_demux:src0_valid -> cmd_xbar_mux:sink0_valid
wire cmd_xbar_demux_src0_startofpacket; // cmd_xbar_demux:src0_startofpacket -> cmd_xbar_mux:sink0_startofpacket
wire [98:0] cmd_xbar_demux_src0_data; // cmd_xbar_demux:src0_data -> cmd_xbar_mux:sink0_data
wire [7:0] cmd_xbar_demux_src0_channel; // cmd_xbar_demux:src0_channel -> cmd_xbar_mux:sink0_channel
wire cmd_xbar_demux_src0_ready; // cmd_xbar_mux:sink0_ready -> cmd_xbar_demux:src0_ready
wire cmd_xbar_demux_src1_endofpacket; // cmd_xbar_demux:src1_endofpacket -> cmd_xbar_mux_001:sink0_endofpacket
wire cmd_xbar_demux_src1_valid; // cmd_xbar_demux:src1_valid -> cmd_xbar_mux_001:sink0_valid
wire cmd_xbar_demux_src1_startofpacket; // cmd_xbar_demux:src1_startofpacket -> cmd_xbar_mux_001:sink0_startofpacket
wire [98:0] cmd_xbar_demux_src1_data; // cmd_xbar_demux:src1_data -> cmd_xbar_mux_001:sink0_data
wire [7:0] cmd_xbar_demux_src1_channel; // cmd_xbar_demux:src1_channel -> cmd_xbar_mux_001:sink0_channel
wire cmd_xbar_demux_src1_ready; // cmd_xbar_mux_001:sink0_ready -> cmd_xbar_demux:src1_ready
wire cmd_xbar_demux_001_src0_endofpacket; // cmd_xbar_demux_001:src0_endofpacket -> cmd_xbar_mux:sink1_endofpacket
wire cmd_xbar_demux_001_src0_valid; // cmd_xbar_demux_001:src0_valid -> cmd_xbar_mux:sink1_valid
wire cmd_xbar_demux_001_src0_startofpacket; // cmd_xbar_demux_001:src0_startofpacket -> cmd_xbar_mux:sink1_startofpacket
wire [98:0] cmd_xbar_demux_001_src0_data; // cmd_xbar_demux_001:src0_data -> cmd_xbar_mux:sink1_data
wire [7:0] cmd_xbar_demux_001_src0_channel; // cmd_xbar_demux_001:src0_channel -> cmd_xbar_mux:sink1_channel
wire cmd_xbar_demux_001_src0_ready; // cmd_xbar_mux:sink1_ready -> cmd_xbar_demux_001:src0_ready
wire cmd_xbar_demux_001_src1_endofpacket; // cmd_xbar_demux_001:src1_endofpacket -> cmd_xbar_mux_001:sink1_endofpacket
wire cmd_xbar_demux_001_src1_valid; // cmd_xbar_demux_001:src1_valid -> cmd_xbar_mux_001:sink1_valid
wire cmd_xbar_demux_001_src1_startofpacket; // cmd_xbar_demux_001:src1_startofpacket -> cmd_xbar_mux_001:sink1_startofpacket
wire [98:0] cmd_xbar_demux_001_src1_data; // cmd_xbar_demux_001:src1_data -> cmd_xbar_mux_001:sink1_data
wire [7:0] cmd_xbar_demux_001_src1_channel; // cmd_xbar_demux_001:src1_channel -> cmd_xbar_mux_001:sink1_channel
wire cmd_xbar_demux_001_src1_ready; // cmd_xbar_mux_001:sink1_ready -> cmd_xbar_demux_001:src1_ready
wire cmd_xbar_demux_001_src2_endofpacket; // cmd_xbar_demux_001:src2_endofpacket -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_001_src2_valid; // cmd_xbar_demux_001:src2_valid -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_001_src2_startofpacket; // cmd_xbar_demux_001:src2_startofpacket -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [98:0] cmd_xbar_demux_001_src2_data; // cmd_xbar_demux_001:src2_data -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_data
wire [7:0] cmd_xbar_demux_001_src2_channel; // cmd_xbar_demux_001:src2_channel -> jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_001_src3_endofpacket; // cmd_xbar_demux_001:src3_endofpacket -> timer_1_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_001_src3_valid; // cmd_xbar_demux_001:src3_valid -> timer_1_s1_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_001_src3_startofpacket; // cmd_xbar_demux_001:src3_startofpacket -> timer_1_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [98:0] cmd_xbar_demux_001_src3_data; // cmd_xbar_demux_001:src3_data -> timer_1_s1_translator_avalon_universal_slave_0_agent:cp_data
wire [7:0] cmd_xbar_demux_001_src3_channel; // cmd_xbar_demux_001:src3_channel -> timer_1_s1_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_001_src4_endofpacket; // cmd_xbar_demux_001:src4_endofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_001_src4_valid; // cmd_xbar_demux_001:src4_valid -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_001_src4_startofpacket; // cmd_xbar_demux_001:src4_startofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [98:0] cmd_xbar_demux_001_src4_data; // cmd_xbar_demux_001:src4_data -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_data
wire [7:0] cmd_xbar_demux_001_src4_channel; // cmd_xbar_demux_001:src4_channel -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_001_src5_endofpacket; // cmd_xbar_demux_001:src5_endofpacket -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_001_src5_valid; // cmd_xbar_demux_001:src5_valid -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_001_src5_startofpacket; // cmd_xbar_demux_001:src5_startofpacket -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [98:0] cmd_xbar_demux_001_src5_data; // cmd_xbar_demux_001:src5_data -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:cp_data
wire [7:0] cmd_xbar_demux_001_src5_channel; // cmd_xbar_demux_001:src5_channel -> sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_001_src6_endofpacket; // cmd_xbar_demux_001:src6_endofpacket -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_001_src6_valid; // cmd_xbar_demux_001:src6_valid -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_001_src6_startofpacket; // cmd_xbar_demux_001:src6_startofpacket -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [98:0] cmd_xbar_demux_001_src6_data; // cmd_xbar_demux_001:src6_data -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:cp_data
wire [7:0] cmd_xbar_demux_001_src6_channel; // cmd_xbar_demux_001:src6_channel -> onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_001_src7_endofpacket; // cmd_xbar_demux_001:src7_endofpacket -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_001_src7_valid; // cmd_xbar_demux_001:src7_valid -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_001_src7_startofpacket; // cmd_xbar_demux_001:src7_startofpacket -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [98:0] cmd_xbar_demux_001_src7_data; // cmd_xbar_demux_001:src7_data -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_data
wire [7:0] cmd_xbar_demux_001_src7_channel; // cmd_xbar_demux_001:src7_channel -> hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_channel
wire rsp_xbar_demux_src0_endofpacket; // rsp_xbar_demux:src0_endofpacket -> rsp_xbar_mux:sink0_endofpacket
wire rsp_xbar_demux_src0_valid; // rsp_xbar_demux:src0_valid -> rsp_xbar_mux:sink0_valid
wire rsp_xbar_demux_src0_startofpacket; // rsp_xbar_demux:src0_startofpacket -> rsp_xbar_mux:sink0_startofpacket
wire [98:0] rsp_xbar_demux_src0_data; // rsp_xbar_demux:src0_data -> rsp_xbar_mux:sink0_data
wire [7:0] rsp_xbar_demux_src0_channel; // rsp_xbar_demux:src0_channel -> rsp_xbar_mux:sink0_channel
wire rsp_xbar_demux_src0_ready; // rsp_xbar_mux:sink0_ready -> rsp_xbar_demux:src0_ready
wire rsp_xbar_demux_src1_endofpacket; // rsp_xbar_demux:src1_endofpacket -> rsp_xbar_mux_001:sink0_endofpacket
wire rsp_xbar_demux_src1_valid; // rsp_xbar_demux:src1_valid -> rsp_xbar_mux_001:sink0_valid
wire rsp_xbar_demux_src1_startofpacket; // rsp_xbar_demux:src1_startofpacket -> rsp_xbar_mux_001:sink0_startofpacket
wire [98:0] rsp_xbar_demux_src1_data; // rsp_xbar_demux:src1_data -> rsp_xbar_mux_001:sink0_data
wire [7:0] rsp_xbar_demux_src1_channel; // rsp_xbar_demux:src1_channel -> rsp_xbar_mux_001:sink0_channel
wire rsp_xbar_demux_src1_ready; // rsp_xbar_mux_001:sink0_ready -> rsp_xbar_demux:src1_ready
wire rsp_xbar_demux_001_src0_endofpacket; // rsp_xbar_demux_001:src0_endofpacket -> rsp_xbar_mux:sink1_endofpacket
wire rsp_xbar_demux_001_src0_valid; // rsp_xbar_demux_001:src0_valid -> rsp_xbar_mux:sink1_valid
wire rsp_xbar_demux_001_src0_startofpacket; // rsp_xbar_demux_001:src0_startofpacket -> rsp_xbar_mux:sink1_startofpacket
wire [98:0] rsp_xbar_demux_001_src0_data; // rsp_xbar_demux_001:src0_data -> rsp_xbar_mux:sink1_data
wire [7:0] rsp_xbar_demux_001_src0_channel; // rsp_xbar_demux_001:src0_channel -> rsp_xbar_mux:sink1_channel
wire rsp_xbar_demux_001_src0_ready; // rsp_xbar_mux:sink1_ready -> rsp_xbar_demux_001:src0_ready
wire rsp_xbar_demux_001_src1_endofpacket; // rsp_xbar_demux_001:src1_endofpacket -> rsp_xbar_mux_001:sink1_endofpacket
wire rsp_xbar_demux_001_src1_valid; // rsp_xbar_demux_001:src1_valid -> rsp_xbar_mux_001:sink1_valid
wire rsp_xbar_demux_001_src1_startofpacket; // rsp_xbar_demux_001:src1_startofpacket -> rsp_xbar_mux_001:sink1_startofpacket
wire [98:0] rsp_xbar_demux_001_src1_data; // rsp_xbar_demux_001:src1_data -> rsp_xbar_mux_001:sink1_data
wire [7:0] rsp_xbar_demux_001_src1_channel; // rsp_xbar_demux_001:src1_channel -> rsp_xbar_mux_001:sink1_channel
wire rsp_xbar_demux_001_src1_ready; // rsp_xbar_mux_001:sink1_ready -> rsp_xbar_demux_001:src1_ready
wire rsp_xbar_demux_002_src0_endofpacket; // rsp_xbar_demux_002:src0_endofpacket -> rsp_xbar_mux_001:sink2_endofpacket
wire rsp_xbar_demux_002_src0_valid; // rsp_xbar_demux_002:src0_valid -> rsp_xbar_mux_001:sink2_valid
wire rsp_xbar_demux_002_src0_startofpacket; // rsp_xbar_demux_002:src0_startofpacket -> rsp_xbar_mux_001:sink2_startofpacket
wire [98:0] rsp_xbar_demux_002_src0_data; // rsp_xbar_demux_002:src0_data -> rsp_xbar_mux_001:sink2_data
wire [7:0] rsp_xbar_demux_002_src0_channel; // rsp_xbar_demux_002:src0_channel -> rsp_xbar_mux_001:sink2_channel
wire rsp_xbar_demux_002_src0_ready; // rsp_xbar_mux_001:sink2_ready -> rsp_xbar_demux_002:src0_ready
wire rsp_xbar_demux_003_src0_endofpacket; // rsp_xbar_demux_003:src0_endofpacket -> rsp_xbar_mux_001:sink3_endofpacket
wire rsp_xbar_demux_003_src0_valid; // rsp_xbar_demux_003:src0_valid -> rsp_xbar_mux_001:sink3_valid
wire rsp_xbar_demux_003_src0_startofpacket; // rsp_xbar_demux_003:src0_startofpacket -> rsp_xbar_mux_001:sink3_startofpacket
wire [98:0] rsp_xbar_demux_003_src0_data; // rsp_xbar_demux_003:src0_data -> rsp_xbar_mux_001:sink3_data
wire [7:0] rsp_xbar_demux_003_src0_channel; // rsp_xbar_demux_003:src0_channel -> rsp_xbar_mux_001:sink3_channel
wire rsp_xbar_demux_003_src0_ready; // rsp_xbar_mux_001:sink3_ready -> rsp_xbar_demux_003:src0_ready
wire rsp_xbar_demux_004_src0_endofpacket; // rsp_xbar_demux_004:src0_endofpacket -> rsp_xbar_mux_001:sink4_endofpacket
wire rsp_xbar_demux_004_src0_valid; // rsp_xbar_demux_004:src0_valid -> rsp_xbar_mux_001:sink4_valid
wire rsp_xbar_demux_004_src0_startofpacket; // rsp_xbar_demux_004:src0_startofpacket -> rsp_xbar_mux_001:sink4_startofpacket
wire [98:0] rsp_xbar_demux_004_src0_data; // rsp_xbar_demux_004:src0_data -> rsp_xbar_mux_001:sink4_data
wire [7:0] rsp_xbar_demux_004_src0_channel; // rsp_xbar_demux_004:src0_channel -> rsp_xbar_mux_001:sink4_channel
wire rsp_xbar_demux_004_src0_ready; // rsp_xbar_mux_001:sink4_ready -> rsp_xbar_demux_004:src0_ready
wire rsp_xbar_demux_005_src0_endofpacket; // rsp_xbar_demux_005:src0_endofpacket -> rsp_xbar_mux_001:sink5_endofpacket
wire rsp_xbar_demux_005_src0_valid; // rsp_xbar_demux_005:src0_valid -> rsp_xbar_mux_001:sink5_valid
wire rsp_xbar_demux_005_src0_startofpacket; // rsp_xbar_demux_005:src0_startofpacket -> rsp_xbar_mux_001:sink5_startofpacket
wire [98:0] rsp_xbar_demux_005_src0_data; // rsp_xbar_demux_005:src0_data -> rsp_xbar_mux_001:sink5_data
wire [7:0] rsp_xbar_demux_005_src0_channel; // rsp_xbar_demux_005:src0_channel -> rsp_xbar_mux_001:sink5_channel
wire rsp_xbar_demux_005_src0_ready; // rsp_xbar_mux_001:sink5_ready -> rsp_xbar_demux_005:src0_ready
wire rsp_xbar_demux_006_src0_endofpacket; // rsp_xbar_demux_006:src0_endofpacket -> rsp_xbar_mux_001:sink6_endofpacket
wire rsp_xbar_demux_006_src0_valid; // rsp_xbar_demux_006:src0_valid -> rsp_xbar_mux_001:sink6_valid
wire rsp_xbar_demux_006_src0_startofpacket; // rsp_xbar_demux_006:src0_startofpacket -> rsp_xbar_mux_001:sink6_startofpacket
wire [98:0] rsp_xbar_demux_006_src0_data; // rsp_xbar_demux_006:src0_data -> rsp_xbar_mux_001:sink6_data
wire [7:0] rsp_xbar_demux_006_src0_channel; // rsp_xbar_demux_006:src0_channel -> rsp_xbar_mux_001:sink6_channel
wire rsp_xbar_demux_006_src0_ready; // rsp_xbar_mux_001:sink6_ready -> rsp_xbar_demux_006:src0_ready
wire rsp_xbar_demux_007_src0_endofpacket; // rsp_xbar_demux_007:src0_endofpacket -> rsp_xbar_mux_001:sink7_endofpacket
wire rsp_xbar_demux_007_src0_valid; // rsp_xbar_demux_007:src0_valid -> rsp_xbar_mux_001:sink7_valid
wire rsp_xbar_demux_007_src0_startofpacket; // rsp_xbar_demux_007:src0_startofpacket -> rsp_xbar_mux_001:sink7_startofpacket
wire [98:0] rsp_xbar_demux_007_src0_data; // rsp_xbar_demux_007:src0_data -> rsp_xbar_mux_001:sink7_data
wire [7:0] rsp_xbar_demux_007_src0_channel; // rsp_xbar_demux_007:src0_channel -> rsp_xbar_mux_001:sink7_channel
wire rsp_xbar_demux_007_src0_ready; // rsp_xbar_mux_001:sink7_ready -> rsp_xbar_demux_007:src0_ready
wire limiter_cmd_src_endofpacket; // limiter:cmd_src_endofpacket -> cmd_xbar_demux:sink_endofpacket
wire limiter_cmd_src_startofpacket; // limiter:cmd_src_startofpacket -> cmd_xbar_demux:sink_startofpacket
wire [98:0] limiter_cmd_src_data; // limiter:cmd_src_data -> cmd_xbar_demux:sink_data
wire [7:0] limiter_cmd_src_channel; // limiter:cmd_src_channel -> cmd_xbar_demux:sink_channel
wire limiter_cmd_src_ready; // cmd_xbar_demux:sink_ready -> limiter:cmd_src_ready
wire rsp_xbar_mux_src_endofpacket; // rsp_xbar_mux:src_endofpacket -> limiter:rsp_sink_endofpacket
wire rsp_xbar_mux_src_valid; // rsp_xbar_mux:src_valid -> limiter:rsp_sink_valid
wire rsp_xbar_mux_src_startofpacket; // rsp_xbar_mux:src_startofpacket -> limiter:rsp_sink_startofpacket
wire [98:0] rsp_xbar_mux_src_data; // rsp_xbar_mux:src_data -> limiter:rsp_sink_data
wire [7:0] rsp_xbar_mux_src_channel; // rsp_xbar_mux:src_channel -> limiter:rsp_sink_channel
wire rsp_xbar_mux_src_ready; // limiter:rsp_sink_ready -> rsp_xbar_mux:src_ready
wire limiter_001_cmd_src_endofpacket; // limiter_001:cmd_src_endofpacket -> cmd_xbar_demux_001:sink_endofpacket
wire limiter_001_cmd_src_startofpacket; // limiter_001:cmd_src_startofpacket -> cmd_xbar_demux_001:sink_startofpacket
wire [98:0] limiter_001_cmd_src_data; // limiter_001:cmd_src_data -> cmd_xbar_demux_001:sink_data
wire [7:0] limiter_001_cmd_src_channel; // limiter_001:cmd_src_channel -> cmd_xbar_demux_001:sink_channel
wire limiter_001_cmd_src_ready; // cmd_xbar_demux_001:sink_ready -> limiter_001:cmd_src_ready
wire rsp_xbar_mux_001_src_endofpacket; // rsp_xbar_mux_001:src_endofpacket -> limiter_001:rsp_sink_endofpacket
wire rsp_xbar_mux_001_src_valid; // rsp_xbar_mux_001:src_valid -> limiter_001:rsp_sink_valid
wire rsp_xbar_mux_001_src_startofpacket; // rsp_xbar_mux_001:src_startofpacket -> limiter_001:rsp_sink_startofpacket
wire [98:0] rsp_xbar_mux_001_src_data; // rsp_xbar_mux_001:src_data -> limiter_001:rsp_sink_data
wire [7:0] rsp_xbar_mux_001_src_channel; // rsp_xbar_mux_001:src_channel -> limiter_001:rsp_sink_channel
wire rsp_xbar_mux_001_src_ready; // limiter_001:rsp_sink_ready -> rsp_xbar_mux_001:src_ready
wire cmd_xbar_mux_src_endofpacket; // cmd_xbar_mux:src_endofpacket -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_mux_src_valid; // cmd_xbar_mux:src_valid -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_mux_src_startofpacket; // cmd_xbar_mux:src_startofpacket -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [98:0] cmd_xbar_mux_src_data; // cmd_xbar_mux:src_data -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_data
wire [7:0] cmd_xbar_mux_src_channel; // cmd_xbar_mux:src_channel -> nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_mux_src_ready; // nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux:src_ready
wire id_router_src_endofpacket; // id_router:src_endofpacket -> rsp_xbar_demux:sink_endofpacket
wire id_router_src_valid; // id_router:src_valid -> rsp_xbar_demux:sink_valid
wire id_router_src_startofpacket; // id_router:src_startofpacket -> rsp_xbar_demux:sink_startofpacket
wire [98:0] id_router_src_data; // id_router:src_data -> rsp_xbar_demux:sink_data
wire [7:0] id_router_src_channel; // id_router:src_channel -> rsp_xbar_demux:sink_channel
wire id_router_src_ready; // rsp_xbar_demux:sink_ready -> id_router:src_ready
wire cmd_xbar_demux_001_src2_ready; // jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src2_ready
wire id_router_002_src_endofpacket; // id_router_002:src_endofpacket -> rsp_xbar_demux_002:sink_endofpacket
wire id_router_002_src_valid; // id_router_002:src_valid -> rsp_xbar_demux_002:sink_valid
wire id_router_002_src_startofpacket; // id_router_002:src_startofpacket -> rsp_xbar_demux_002:sink_startofpacket
wire [98:0] id_router_002_src_data; // id_router_002:src_data -> rsp_xbar_demux_002:sink_data
wire [7:0] id_router_002_src_channel; // id_router_002:src_channel -> rsp_xbar_demux_002:sink_channel
wire id_router_002_src_ready; // rsp_xbar_demux_002:sink_ready -> id_router_002:src_ready
wire cmd_xbar_demux_001_src3_ready; // timer_1_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src3_ready
wire id_router_003_src_endofpacket; // id_router_003:src_endofpacket -> rsp_xbar_demux_003:sink_endofpacket
wire id_router_003_src_valid; // id_router_003:src_valid -> rsp_xbar_demux_003:sink_valid
wire id_router_003_src_startofpacket; // id_router_003:src_startofpacket -> rsp_xbar_demux_003:sink_startofpacket
wire [98:0] id_router_003_src_data; // id_router_003:src_data -> rsp_xbar_demux_003:sink_data
wire [7:0] id_router_003_src_channel; // id_router_003:src_channel -> rsp_xbar_demux_003:sink_channel
wire id_router_003_src_ready; // rsp_xbar_demux_003:sink_ready -> id_router_003:src_ready
wire cmd_xbar_demux_001_src4_ready; // timer_0_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src4_ready
wire id_router_004_src_endofpacket; // id_router_004:src_endofpacket -> rsp_xbar_demux_004:sink_endofpacket
wire id_router_004_src_valid; // id_router_004:src_valid -> rsp_xbar_demux_004:sink_valid
wire id_router_004_src_startofpacket; // id_router_004:src_startofpacket -> rsp_xbar_demux_004:sink_startofpacket
wire [98:0] id_router_004_src_data; // id_router_004:src_data -> rsp_xbar_demux_004:sink_data
wire [7:0] id_router_004_src_channel; // id_router_004:src_channel -> rsp_xbar_demux_004:sink_channel
wire id_router_004_src_ready; // rsp_xbar_demux_004:sink_ready -> id_router_004:src_ready
wire cmd_xbar_demux_001_src5_ready; // sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src5_ready
wire id_router_005_src_endofpacket; // id_router_005:src_endofpacket -> rsp_xbar_demux_005:sink_endofpacket
wire id_router_005_src_valid; // id_router_005:src_valid -> rsp_xbar_demux_005:sink_valid
wire id_router_005_src_startofpacket; // id_router_005:src_startofpacket -> rsp_xbar_demux_005:sink_startofpacket
wire [98:0] id_router_005_src_data; // id_router_005:src_data -> rsp_xbar_demux_005:sink_data
wire [7:0] id_router_005_src_channel; // id_router_005:src_channel -> rsp_xbar_demux_005:sink_channel
wire id_router_005_src_ready; // rsp_xbar_demux_005:sink_ready -> id_router_005:src_ready
wire cmd_xbar_demux_001_src6_ready; // onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src6_ready
wire id_router_006_src_endofpacket; // id_router_006:src_endofpacket -> rsp_xbar_demux_006:sink_endofpacket
wire id_router_006_src_valid; // id_router_006:src_valid -> rsp_xbar_demux_006:sink_valid
wire id_router_006_src_startofpacket; // id_router_006:src_startofpacket -> rsp_xbar_demux_006:sink_startofpacket
wire [98:0] id_router_006_src_data; // id_router_006:src_data -> rsp_xbar_demux_006:sink_data
wire [7:0] id_router_006_src_channel; // id_router_006:src_channel -> rsp_xbar_demux_006:sink_channel
wire id_router_006_src_ready; // rsp_xbar_demux_006:sink_ready -> id_router_006:src_ready
wire cmd_xbar_demux_001_src7_ready; // hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src7_ready
wire id_router_007_src_endofpacket; // id_router_007:src_endofpacket -> rsp_xbar_demux_007:sink_endofpacket
wire id_router_007_src_valid; // id_router_007:src_valid -> rsp_xbar_demux_007:sink_valid
wire id_router_007_src_startofpacket; // id_router_007:src_startofpacket -> rsp_xbar_demux_007:sink_startofpacket
wire [98:0] id_router_007_src_data; // id_router_007:src_data -> rsp_xbar_demux_007:sink_data
wire [7:0] id_router_007_src_channel; // id_router_007:src_channel -> rsp_xbar_demux_007:sink_channel
wire id_router_007_src_ready; // rsp_xbar_demux_007:sink_ready -> id_router_007:src_ready
wire cmd_xbar_demux_002_src0_endofpacket; // cmd_xbar_demux_002:src0_endofpacket -> cmd_xbar_mux_008:sink0_endofpacket
wire cmd_xbar_demux_002_src0_valid; // cmd_xbar_demux_002:src0_valid -> cmd_xbar_mux_008:sink0_valid
wire cmd_xbar_demux_002_src0_startofpacket; // cmd_xbar_demux_002:src0_startofpacket -> cmd_xbar_mux_008:sink0_startofpacket
wire [100:0] cmd_xbar_demux_002_src0_data; // cmd_xbar_demux_002:src0_data -> cmd_xbar_mux_008:sink0_data
wire [1:0] cmd_xbar_demux_002_src0_channel; // cmd_xbar_demux_002:src0_channel -> cmd_xbar_mux_008:sink0_channel
wire cmd_xbar_demux_002_src0_ready; // cmd_xbar_mux_008:sink0_ready -> cmd_xbar_demux_002:src0_ready
wire cmd_xbar_demux_003_src0_endofpacket; // cmd_xbar_demux_003:src0_endofpacket -> cmd_xbar_mux_008:sink1_endofpacket
wire cmd_xbar_demux_003_src0_valid; // cmd_xbar_demux_003:src0_valid -> cmd_xbar_mux_008:sink1_valid
wire cmd_xbar_demux_003_src0_startofpacket; // cmd_xbar_demux_003:src0_startofpacket -> cmd_xbar_mux_008:sink1_startofpacket
wire [100:0] cmd_xbar_demux_003_src0_data; // cmd_xbar_demux_003:src0_data -> cmd_xbar_mux_008:sink1_data
wire [1:0] cmd_xbar_demux_003_src0_channel; // cmd_xbar_demux_003:src0_channel -> cmd_xbar_mux_008:sink1_channel
wire cmd_xbar_demux_003_src0_ready; // cmd_xbar_mux_008:sink1_ready -> cmd_xbar_demux_003:src0_ready
wire rsp_xbar_demux_008_src0_endofpacket; // rsp_xbar_demux_008:src0_endofpacket -> hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:rp_endofpacket
wire rsp_xbar_demux_008_src0_valid; // rsp_xbar_demux_008:src0_valid -> hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:rp_valid
wire rsp_xbar_demux_008_src0_startofpacket; // rsp_xbar_demux_008:src0_startofpacket -> hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:rp_startofpacket
wire [100:0] rsp_xbar_demux_008_src0_data; // rsp_xbar_demux_008:src0_data -> hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:rp_data
wire [1:0] rsp_xbar_demux_008_src0_channel; // rsp_xbar_demux_008:src0_channel -> hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:rp_channel
wire rsp_xbar_demux_008_src1_endofpacket; // rsp_xbar_demux_008:src1_endofpacket -> hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:rp_endofpacket
wire rsp_xbar_demux_008_src1_valid; // rsp_xbar_demux_008:src1_valid -> hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:rp_valid
wire rsp_xbar_demux_008_src1_startofpacket; // rsp_xbar_demux_008:src1_startofpacket -> hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:rp_startofpacket
wire [100:0] rsp_xbar_demux_008_src1_data; // rsp_xbar_demux_008:src1_data -> hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:rp_data
wire [1:0] rsp_xbar_demux_008_src1_channel; // rsp_xbar_demux_008:src1_channel -> hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:rp_channel
wire addr_router_002_src_endofpacket; // addr_router_002:src_endofpacket -> cmd_xbar_demux_002:sink_endofpacket
wire addr_router_002_src_valid; // addr_router_002:src_valid -> cmd_xbar_demux_002:sink_valid
wire addr_router_002_src_startofpacket; // addr_router_002:src_startofpacket -> cmd_xbar_demux_002:sink_startofpacket
wire [100:0] addr_router_002_src_data; // addr_router_002:src_data -> cmd_xbar_demux_002:sink_data
wire [1:0] addr_router_002_src_channel; // addr_router_002:src_channel -> cmd_xbar_demux_002:sink_channel
wire addr_router_002_src_ready; // cmd_xbar_demux_002:sink_ready -> addr_router_002:src_ready
wire rsp_xbar_demux_008_src0_ready; // hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_demux_008:src0_ready
wire addr_router_003_src_endofpacket; // addr_router_003:src_endofpacket -> cmd_xbar_demux_003:sink_endofpacket
wire addr_router_003_src_valid; // addr_router_003:src_valid -> cmd_xbar_demux_003:sink_valid
wire addr_router_003_src_startofpacket; // addr_router_003:src_startofpacket -> cmd_xbar_demux_003:sink_startofpacket
wire [100:0] addr_router_003_src_data; // addr_router_003:src_data -> cmd_xbar_demux_003:sink_data
wire [1:0] addr_router_003_src_channel; // addr_router_003:src_channel -> cmd_xbar_demux_003:sink_channel
wire addr_router_003_src_ready; // cmd_xbar_demux_003:sink_ready -> addr_router_003:src_ready
wire rsp_xbar_demux_008_src1_ready; // hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_demux_008:src1_ready
wire cmd_xbar_mux_008_src_endofpacket; // cmd_xbar_mux_008:src_endofpacket -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_mux_008_src_valid; // cmd_xbar_mux_008:src_valid -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_mux_008_src_startofpacket; // cmd_xbar_mux_008:src_startofpacket -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [100:0] cmd_xbar_mux_008_src_data; // cmd_xbar_mux_008:src_data -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:cp_data
wire [1:0] cmd_xbar_mux_008_src_channel; // cmd_xbar_mux_008:src_channel -> onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_mux_008_src_ready; // onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux_008:src_ready
wire id_router_008_src_endofpacket; // id_router_008:src_endofpacket -> rsp_xbar_demux_008:sink_endofpacket
wire id_router_008_src_valid; // id_router_008:src_valid -> rsp_xbar_demux_008:sink_valid
wire id_router_008_src_startofpacket; // id_router_008:src_startofpacket -> rsp_xbar_demux_008:sink_startofpacket
wire [100:0] id_router_008_src_data; // id_router_008:src_data -> rsp_xbar_demux_008:sink_data
wire [1:0] id_router_008_src_channel; // id_router_008:src_channel -> rsp_xbar_demux_008:sink_channel
wire id_router_008_src_ready; // rsp_xbar_demux_008:sink_ready -> id_router_008:src_ready
wire cmd_xbar_mux_001_src_endofpacket; // cmd_xbar_mux_001:src_endofpacket -> width_adapter:in_endofpacket
wire cmd_xbar_mux_001_src_valid; // cmd_xbar_mux_001:src_valid -> width_adapter:in_valid
wire cmd_xbar_mux_001_src_startofpacket; // cmd_xbar_mux_001:src_startofpacket -> width_adapter:in_startofpacket
wire [98:0] cmd_xbar_mux_001_src_data; // cmd_xbar_mux_001:src_data -> width_adapter:in_data
wire [7:0] cmd_xbar_mux_001_src_channel; // cmd_xbar_mux_001:src_channel -> width_adapter:in_channel
wire cmd_xbar_mux_001_src_ready; // width_adapter:in_ready -> cmd_xbar_mux_001:src_ready
wire width_adapter_src_endofpacket; // width_adapter:out_endofpacket -> burst_adapter:sink0_endofpacket
wire width_adapter_src_valid; // width_adapter:out_valid -> burst_adapter:sink0_valid
wire width_adapter_src_startofpacket; // width_adapter:out_startofpacket -> burst_adapter:sink0_startofpacket
wire [80:0] width_adapter_src_data; // width_adapter:out_data -> burst_adapter:sink0_data
wire width_adapter_src_ready; // burst_adapter:sink0_ready -> width_adapter:out_ready
wire [7:0] width_adapter_src_channel; // width_adapter:out_channel -> burst_adapter:sink0_channel
wire id_router_001_src_endofpacket; // id_router_001:src_endofpacket -> width_adapter_001:in_endofpacket
wire id_router_001_src_valid; // id_router_001:src_valid -> width_adapter_001:in_valid
wire id_router_001_src_startofpacket; // id_router_001:src_startofpacket -> width_adapter_001:in_startofpacket
wire [80:0] id_router_001_src_data; // id_router_001:src_data -> width_adapter_001:in_data
wire [7:0] id_router_001_src_channel; // id_router_001:src_channel -> width_adapter_001:in_channel
wire id_router_001_src_ready; // width_adapter_001:in_ready -> id_router_001:src_ready
wire width_adapter_001_src_endofpacket; // width_adapter_001:out_endofpacket -> rsp_xbar_demux_001:sink_endofpacket
wire width_adapter_001_src_valid; // width_adapter_001:out_valid -> rsp_xbar_demux_001:sink_valid
wire width_adapter_001_src_startofpacket; // width_adapter_001:out_startofpacket -> rsp_xbar_demux_001:sink_startofpacket
wire [98:0] width_adapter_001_src_data; // width_adapter_001:out_data -> rsp_xbar_demux_001:sink_data
wire width_adapter_001_src_ready; // rsp_xbar_demux_001:sink_ready -> width_adapter_001:out_ready
wire [7:0] width_adapter_001_src_channel; // width_adapter_001:out_channel -> rsp_xbar_demux_001:sink_channel
wire [7:0] limiter_cmd_valid_data; // limiter:cmd_src_valid -> cmd_xbar_demux:sink_valid
wire [7:0] limiter_001_cmd_valid_data; // limiter_001:cmd_src_valid -> cmd_xbar_demux_001:sink_valid
wire irq_mapper_receiver0_irq; // jtag_uart_1:av_irq -> irq_mapper:receiver0_irq
wire irq_mapper_receiver1_irq; // timer_1:irq -> irq_mapper:receiver1_irq
wire irq_mapper_receiver2_irq; // timer_0:irq -> irq_mapper:receiver2_irq
wire irq_mapper_receiver3_irq; // hibi_pe_dma_0:rx_irq_out -> irq_mapper:receiver3_irq
wire [31:0] nios2_qsys_1_d_irq_irq; // irq_mapper:sender_irq -> nios2_qsys_1:d_irq
 
nios2_sdram_nios2_qsys_1 nios2_qsys_1 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset_n.reset_n
.d_address (nios2_qsys_1_data_master_address), // data_master.address
.d_byteenable (nios2_qsys_1_data_master_byteenable), // .byteenable
.d_read (nios2_qsys_1_data_master_read), // .read
.d_readdata (nios2_qsys_1_data_master_readdata), // .readdata
.d_waitrequest (nios2_qsys_1_data_master_waitrequest), // .waitrequest
.d_write (nios2_qsys_1_data_master_write), // .write
.d_writedata (nios2_qsys_1_data_master_writedata), // .writedata
.d_readdatavalid (nios2_qsys_1_data_master_readdatavalid), // .readdatavalid
.jtag_debug_module_debugaccess_to_roms (nios2_qsys_1_data_master_debugaccess), // .debugaccess
.i_address (nios2_qsys_1_instruction_master_address), // instruction_master.address
.i_read (nios2_qsys_1_instruction_master_read), // .read
.i_readdata (nios2_qsys_1_instruction_master_readdata), // .readdata
.i_waitrequest (nios2_qsys_1_instruction_master_waitrequest), // .waitrequest
.i_readdatavalid (nios2_qsys_1_instruction_master_readdatavalid), // .readdatavalid
.d_irq (nios2_qsys_1_d_irq_irq), // d_irq.irq
.jtag_debug_module_resetrequest (), // jtag_debug_module_reset.reset
.jtag_debug_module_address (nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_address), // jtag_debug_module.address
.jtag_debug_module_begintransfer (nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_begintransfer), // .begintransfer
.jtag_debug_module_byteenable (nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_byteenable), // .byteenable
.jtag_debug_module_debugaccess (nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess), // .debugaccess
.jtag_debug_module_readdata (nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_readdata), // .readdata
.jtag_debug_module_select (nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_chipselect), // .chipselect
.jtag_debug_module_write (nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_write), // .write
.jtag_debug_module_writedata (nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_writedata), // .writedata
.no_ci_readra () // custom_instruction_master.readra
);
 
nios2_sdram_onchip_memory2_1 onchip_memory2_1 (
.clk (clk_clk), // clk1.clk
.address (onchip_memory2_1_s1_translator_avalon_anti_slave_0_address), // s1.address
.chipselect (onchip_memory2_1_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect
.clken (onchip_memory2_1_s1_translator_avalon_anti_slave_0_clken), // .clken
.readdata (onchip_memory2_1_s1_translator_avalon_anti_slave_0_readdata), // .readdata
.write (onchip_memory2_1_s1_translator_avalon_anti_slave_0_write), // .write
.writedata (onchip_memory2_1_s1_translator_avalon_anti_slave_0_writedata), // .writedata
.byteenable (onchip_memory2_1_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable
.reset (rst_controller_reset_out_reset), // reset1.reset
.address2 (onchip_memory2_1_s2_translator_avalon_anti_slave_0_address), // s2.address
.chipselect2 (onchip_memory2_1_s2_translator_avalon_anti_slave_0_chipselect), // .chipselect
.clken2 (onchip_memory2_1_s2_translator_avalon_anti_slave_0_clken), // .clken
.readdata2 (onchip_memory2_1_s2_translator_avalon_anti_slave_0_readdata), // .readdata
.write2 (onchip_memory2_1_s2_translator_avalon_anti_slave_0_write), // .write
.writedata2 (onchip_memory2_1_s2_translator_avalon_anti_slave_0_writedata), // .writedata
.byteenable2 (onchip_memory2_1_s2_translator_avalon_anti_slave_0_byteenable), // .byteenable
.clk2 (clk_clk), // clk2.clk
.reset2 (rst_controller_reset_out_reset) // reset2.reset
);
 
nios2_sdram_jtag_uart_1 jtag_uart_1 (
.clk (clk_clk), // clk.clk
.rst_n (~rst_controller_reset_out_reset), // reset.reset_n
.av_chipselect (jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect), // avalon_jtag_slave.chipselect
.av_address (jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_address), // .address
.av_read_n (~jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_read), // .read_n
.av_readdata (jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata), // .readdata
.av_write_n (~jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_write), // .write_n
.av_writedata (jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata), // .writedata
.av_waitrequest (jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.av_irq (irq_mapper_receiver0_irq) // irq.irq
);
 
nios2_sdram_sysid_qsys_1 sysid_qsys_1 (
.clock (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.readdata (sysid_qsys_1_control_slave_translator_avalon_anti_slave_0_readdata), // control_slave.readdata
.address (sysid_qsys_1_control_slave_translator_avalon_anti_slave_0_address) // .address
);
 
nios2_sdram_timer_0 timer_0 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (timer_0_s1_translator_avalon_anti_slave_0_address), // s1.address
.writedata (timer_0_s1_translator_avalon_anti_slave_0_writedata), // .writedata
.readdata (timer_0_s1_translator_avalon_anti_slave_0_readdata), // .readdata
.chipselect (timer_0_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect
.write_n (~timer_0_s1_translator_avalon_anti_slave_0_write), // .write_n
.irq (irq_mapper_receiver2_irq) // irq.irq
);
 
nios2_sdram_timer_0 timer_1 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (timer_1_s1_translator_avalon_anti_slave_0_address), // s1.address
.writedata (timer_1_s1_translator_avalon_anti_slave_0_writedata), // .writedata
.readdata (timer_1_s1_translator_avalon_anti_slave_0_readdata), // .readdata
.chipselect (timer_1_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect
.write_n (~timer_1_s1_translator_avalon_anti_slave_0_write), // .write_n
.irq (irq_mapper_receiver1_irq) // irq.irq
);
 
nios2_sdram_sdram_0 sdram_0 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.az_addr (sdram_0_s1_translator_avalon_anti_slave_0_address), // s1.address
.az_be_n (~sdram_0_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable_n
.az_cs (sdram_0_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect
.az_data (sdram_0_s1_translator_avalon_anti_slave_0_writedata), // .writedata
.az_rd_n (~sdram_0_s1_translator_avalon_anti_slave_0_read), // .read_n
.az_wr_n (~sdram_0_s1_translator_avalon_anti_slave_0_write), // .write_n
.za_data (sdram_0_s1_translator_avalon_anti_slave_0_readdata), // .readdata
.za_valid (sdram_0_s1_translator_avalon_anti_slave_0_readdatavalid), // .readdatavalid
.za_waitrequest (sdram_0_s1_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.zs_addr (sdram_0_addr), // wire.export
.zs_ba (sdram_0_ba), // .export
.zs_cas_n (sdram_0_cas_n), // .export
.zs_cke (sdram_0_cke), // .export
.zs_cs_n (sdram_0_cs_n), // .export
.zs_dq (sdram_0_dq), // .export
.zs_dqm (sdram_0_dqm), // .export
.zs_ras_n (sdram_0_ras_n), // .export
.zs_we_n (sdram_0_we_n) // .export
);
 
hibi_pe_dma #(
.data_width_g (32),
.addr_width_g (32),
.words_width_g (16),
.n_stream_chans_g (2),
.n_packet_chans_g (2),
.n_chans_bits_g (3),
.hibi_addr_cmp_lo_g (0),
.hibi_addr_cmp_hi_g (31)
) hibi_pe_dma_0 (
.avalon_cfg_addr_in (hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_address), // avalon_slave_0.address
.avalon_cfg_we_in (hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_write), // .write
.avalon_cfg_re_in (hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_read), // .read
.avalon_cfg_cs_in (hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_chipselect), // .chipselect
.avalon_cfg_waitrequest_out (hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.avalon_cfg_writedata_in (hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_writedata), // .writedata
.avalon_cfg_readdata_out (hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata), // .readdata
.hibi_data_in (hibi_pe_dma_data_in), // conduit_end.export
.hibi_av_in (hibi_pe_dma_av_in), // .export
.hibi_empty_in (hibi_pe_dma_empty_in), // .export
.hibi_comm_in (hibi_pe_dma_comm_in), // .export
.hibi_re_out (hibi_pe_dma_re_out), // .export
.hibi_data_out (hibi_pe_dma_data_out), // .export
.hibi_av_out (hibi_pe_dma_av_out), // .export
.hibi_full_in (hibi_pe_dma_full_in), // .export
.hibi_comm_out (hibi_pe_dma_comm_out), // .export
.hibi_we_out (hibi_pe_dma_we_out), // .export
.rst_n (~rst_controller_reset_out_reset), // clock_sink_reset.reset_n
.rx_irq_out (irq_mapper_receiver3_irq), // interrupt_sender.irq
.avalon_addr_out_rx (hibi_pe_dma_0_avalon_master_address), // avalon_master.address
.avalon_we_out_rx (hibi_pe_dma_0_avalon_master_write), // .write
.avalon_be_out_rx (hibi_pe_dma_0_avalon_master_byteenable), // .byteenable
.avalon_writedata_out_rx (hibi_pe_dma_0_avalon_master_writedata), // .writedata
.avalon_waitrequest_in_rx (hibi_pe_dma_0_avalon_master_waitrequest), // .waitrequest
.avalon_readdatavalid_in_tx (hibi_pe_dma_0_avalon_master_1_readdatavalid), // avalon_master_1.readdatavalid
.avalon_waitrequest_in_tx (hibi_pe_dma_0_avalon_master_1_waitrequest), // .waitrequest
.avalon_readdata_in_tx (hibi_pe_dma_0_avalon_master_1_readdata), // .readdata
.avalon_re_out_tx (hibi_pe_dma_0_avalon_master_1_read), // .read
.avalon_addr_out_tx (hibi_pe_dma_0_avalon_master_1_address), // .address
.clk (clk_clk) // clock.clk
);
 
altera_merlin_master_translator #(
.AV_ADDRESS_W (26),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (26),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (0),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (1),
.AV_REGISTERINCOMINGSIGNALS (0)
) nios2_qsys_1_instruction_master_translator (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_read), // .read
.uav_write (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (nios2_qsys_1_instruction_master_address), // avalon_anti_master_0.address
.av_waitrequest (nios2_qsys_1_instruction_master_waitrequest), // .waitrequest
.av_read (nios2_qsys_1_instruction_master_read), // .read
.av_readdata (nios2_qsys_1_instruction_master_readdata), // .readdata
.av_readdatavalid (nios2_qsys_1_instruction_master_readdatavalid), // .readdatavalid
.av_burstcount (1'b1), // (terminated)
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_write (1'b0), // (terminated)
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1) // (terminated)
);
 
altera_merlin_master_translator #(
.AV_ADDRESS_W (26),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (26),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) nios2_qsys_1_data_master_translator (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (nios2_qsys_1_data_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (nios2_qsys_1_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (nios2_qsys_1_data_master_translator_avalon_universal_master_0_read), // .read
.uav_write (nios2_qsys_1_data_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (nios2_qsys_1_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (nios2_qsys_1_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (nios2_qsys_1_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (nios2_qsys_1_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (nios2_qsys_1_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (nios2_qsys_1_data_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (nios2_qsys_1_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (nios2_qsys_1_data_master_address), // avalon_anti_master_0.address
.av_waitrequest (nios2_qsys_1_data_master_waitrequest), // .waitrequest
.av_byteenable (nios2_qsys_1_data_master_byteenable), // .byteenable
.av_read (nios2_qsys_1_data_master_read), // .read
.av_readdata (nios2_qsys_1_data_master_readdata), // .readdata
.av_readdatavalid (nios2_qsys_1_data_master_readdatavalid), // .readdatavalid
.av_write (nios2_qsys_1_data_master_write), // .write
.av_writedata (nios2_qsys_1_data_master_writedata), // .writedata
.av_debugaccess (nios2_qsys_1_data_master_debugaccess), // .debugaccess
.av_burstcount (1'b1), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1) // (terminated)
);
 
altera_merlin_slave_translator #(
.AV_ADDRESS_W (9),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (26),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) nios2_qsys_1_jtag_debug_module_translator (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_write), // .write
.av_readdata (nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_writedata), // .writedata
.av_begintransfer (nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_begintransfer), // .begintransfer
.av_byteenable (nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_byteenable), // .byteenable
.av_chipselect (nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_chipselect), // .chipselect
.av_debugaccess (nios2_qsys_1_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess), // .debugaccess
.av_read (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable () // (terminated)
);
 
altera_merlin_slave_translator #(
.AV_ADDRESS_W (22),
.AV_DATA_W (16),
.UAV_DATA_W (16),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (2),
.UAV_BYTEENABLE_W (2),
.UAV_ADDRESS_W (26),
.UAV_BURSTCOUNT_W (2),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (2),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sdram_0_s1_translator (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (sdram_0_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (sdram_0_s1_translator_avalon_anti_slave_0_write), // .write
.av_read (sdram_0_s1_translator_avalon_anti_slave_0_read), // .read
.av_readdata (sdram_0_s1_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (sdram_0_s1_translator_avalon_anti_slave_0_writedata), // .writedata
.av_byteenable (sdram_0_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable
.av_readdatavalid (sdram_0_s1_translator_avalon_anti_slave_0_readdatavalid), // .readdatavalid
.av_waitrequest (sdram_0_s1_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.av_chipselect (sdram_0_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
 
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (26),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) jtag_uart_1_avalon_jtag_slave_translator (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_write), // .write
.av_read (jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_read), // .read
.av_readdata (jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata), // .writedata
.av_waitrequest (jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.av_chipselect (jtag_uart_1_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
 
altera_merlin_slave_translator #(
.AV_ADDRESS_W (3),
.AV_DATA_W (16),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (26),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) timer_1_s1_translator (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (timer_1_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (timer_1_s1_translator_avalon_anti_slave_0_write), // .write
.av_readdata (timer_1_s1_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (timer_1_s1_translator_avalon_anti_slave_0_writedata), // .writedata
.av_chipselect (timer_1_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
 
altera_merlin_slave_translator #(
.AV_ADDRESS_W (3),
.AV_DATA_W (16),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (26),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) timer_0_s1_translator (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (timer_0_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (timer_0_s1_translator_avalon_anti_slave_0_write), // .write
.av_readdata (timer_0_s1_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (timer_0_s1_translator_avalon_anti_slave_0_writedata), // .writedata
.av_chipselect (timer_0_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
 
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (26),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sysid_qsys_1_control_slave_translator (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (sysid_qsys_1_control_slave_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_readdata (sysid_qsys_1_control_slave_translator_avalon_anti_slave_0_readdata), // .readdata
.av_write (), // (terminated)
.av_read (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
 
altera_merlin_slave_translator #(
.AV_ADDRESS_W (11),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (26),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) onchip_memory2_1_s1_translator (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (onchip_memory2_1_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (onchip_memory2_1_s1_translator_avalon_anti_slave_0_write), // .write
.av_readdata (onchip_memory2_1_s1_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (onchip_memory2_1_s1_translator_avalon_anti_slave_0_writedata), // .writedata
.av_byteenable (onchip_memory2_1_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable
.av_chipselect (onchip_memory2_1_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect
.av_clken (onchip_memory2_1_s1_translator_avalon_anti_slave_0_clken), // .clken
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
 
altera_merlin_slave_translator #(
.AV_ADDRESS_W (7),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (26),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) hibi_pe_dma_0_avalon_slave_0_translator (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_write), // .write
.av_read (hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_read), // .read
.av_readdata (hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_writedata), // .writedata
.av_waitrequest (hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.av_chipselect (hibi_pe_dma_0_avalon_slave_0_translator_avalon_anti_slave_0_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
 
altera_merlin_master_translator #(
.AV_ADDRESS_W (32),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.USE_READ (0),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) hibi_pe_dma_0_avalon_master_translator (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_read), // .read
.uav_write (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (hibi_pe_dma_0_avalon_master_address), // avalon_anti_master_0.address
.av_waitrequest (hibi_pe_dma_0_avalon_master_waitrequest), // .waitrequest
.av_byteenable (hibi_pe_dma_0_avalon_master_byteenable), // .byteenable
.av_write (hibi_pe_dma_0_avalon_master_write), // .write
.av_writedata (hibi_pe_dma_0_avalon_master_writedata), // .writedata
.av_burstcount (1'b1), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_read (1'b0), // (terminated)
.av_readdata (), // (terminated)
.av_readdatavalid (), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1) // (terminated)
);
 
altera_merlin_master_translator #(
.AV_ADDRESS_W (32),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (0),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) hibi_pe_dma_0_avalon_master_1_translator (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_read), // .read
.uav_write (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (hibi_pe_dma_0_avalon_master_1_address), // avalon_anti_master_0.address
.av_waitrequest (hibi_pe_dma_0_avalon_master_1_waitrequest), // .waitrequest
.av_read (hibi_pe_dma_0_avalon_master_1_read), // .read
.av_readdata (hibi_pe_dma_0_avalon_master_1_readdata), // .readdata
.av_readdatavalid (hibi_pe_dma_0_avalon_master_1_readdatavalid), // .readdatavalid
.av_burstcount (1'b1), // (terminated)
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_write (1'b0), // (terminated)
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1) // (terminated)
);
 
altera_merlin_slave_translator #(
.AV_ADDRESS_W (11),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) onchip_memory2_1_s2_translator (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (onchip_memory2_1_s2_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (onchip_memory2_1_s2_translator_avalon_anti_slave_0_write), // .write
.av_readdata (onchip_memory2_1_s2_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (onchip_memory2_1_s2_translator_avalon_anti_slave_0_writedata), // .writedata
.av_byteenable (onchip_memory2_1_s2_translator_avalon_anti_slave_0_byteenable), // .byteenable
.av_chipselect (onchip_memory2_1_s2_translator_avalon_anti_slave_0_chipselect), // .chipselect
.av_clken (onchip_memory2_1_s2_translator_avalon_anti_slave_0_clken), // .clken
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
 
altera_merlin_master_agent #(
.PKT_PROTECTION_H (92),
.PKT_PROTECTION_L (90),
.PKT_BEGIN_BURST (81),
.PKT_BURSTWRAP_H (73),
.PKT_BURSTWRAP_L (71),
.PKT_BURST_SIZE_H (76),
.PKT_BURST_SIZE_L (74),
.PKT_BURST_TYPE_H (78),
.PKT_BURST_TYPE_L (77),
.PKT_BYTE_CNT_H (70),
.PKT_BYTE_CNT_L (68),
.PKT_ADDR_H (61),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (62),
.PKT_TRANS_POSTED (63),
.PKT_TRANS_WRITE (64),
.PKT_TRANS_READ (65),
.PKT_TRANS_LOCK (66),
.PKT_TRANS_EXCLUSIVE (67),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (85),
.PKT_SRC_ID_L (83),
.PKT_DEST_ID_H (88),
.PKT_DEST_ID_L (86),
.PKT_THREAD_ID_H (89),
.PKT_THREAD_ID_L (89),
.PKT_CACHE_H (96),
.PKT_CACHE_L (93),
.PKT_DATA_SIDEBAND_H (80),
.PKT_DATA_SIDEBAND_L (80),
.PKT_QOS_H (82),
.PKT_QOS_L (82),
.PKT_ADDR_SIDEBAND_H (79),
.PKT_ADDR_SIDEBAND_L (79),
.ST_DATA_W (99),
.ST_CHANNEL_W (8),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (0),
.BURSTWRAP_VALUE (3),
.CACHE_VALUE (4'b0000)
) nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.av_address (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_address), // av.address
.av_write (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_write), // .write
.av_read (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid
.cp_data (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.cp_startofpacket (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.cp_ready (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent_cp_ready), // .ready
.rp_valid (limiter_rsp_src_valid), // rp.valid
.rp_data (limiter_rsp_src_data), // .data
.rp_channel (limiter_rsp_src_channel), // .channel
.rp_startofpacket (limiter_rsp_src_startofpacket), // .startofpacket
.rp_endofpacket (limiter_rsp_src_endofpacket), // .endofpacket
.rp_ready (limiter_rsp_src_ready) // .ready
);
 
altera_merlin_master_agent #(
.PKT_PROTECTION_H (92),
.PKT_PROTECTION_L (90),
.PKT_BEGIN_BURST (81),
.PKT_BURSTWRAP_H (73),
.PKT_BURSTWRAP_L (71),
.PKT_BURST_SIZE_H (76),
.PKT_BURST_SIZE_L (74),
.PKT_BURST_TYPE_H (78),
.PKT_BURST_TYPE_L (77),
.PKT_BYTE_CNT_H (70),
.PKT_BYTE_CNT_L (68),
.PKT_ADDR_H (61),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (62),
.PKT_TRANS_POSTED (63),
.PKT_TRANS_WRITE (64),
.PKT_TRANS_READ (65),
.PKT_TRANS_LOCK (66),
.PKT_TRANS_EXCLUSIVE (67),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (85),
.PKT_SRC_ID_L (83),
.PKT_DEST_ID_H (88),
.PKT_DEST_ID_L (86),
.PKT_THREAD_ID_H (89),
.PKT_THREAD_ID_L (89),
.PKT_CACHE_H (96),
.PKT_CACHE_L (93),
.PKT_DATA_SIDEBAND_H (80),
.PKT_DATA_SIDEBAND_L (80),
.PKT_QOS_H (82),
.PKT_QOS_L (82),
.PKT_ADDR_SIDEBAND_H (79),
.PKT_ADDR_SIDEBAND_L (79),
.ST_DATA_W (99),
.ST_CHANNEL_W (8),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (1),
.BURSTWRAP_VALUE (7),
.CACHE_VALUE (4'b0000)
) nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.av_address (nios2_qsys_1_data_master_translator_avalon_universal_master_0_address), // av.address
.av_write (nios2_qsys_1_data_master_translator_avalon_universal_master_0_write), // .write
.av_read (nios2_qsys_1_data_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (nios2_qsys_1_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (nios2_qsys_1_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (nios2_qsys_1_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (nios2_qsys_1_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (nios2_qsys_1_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (nios2_qsys_1_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (nios2_qsys_1_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (nios2_qsys_1_data_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid
.cp_data (nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.cp_startofpacket (nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.cp_ready (nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent_cp_ready), // .ready
.rp_valid (limiter_001_rsp_src_valid), // rp.valid
.rp_data (limiter_001_rsp_src_data), // .data
.rp_channel (limiter_001_rsp_src_channel), // .channel
.rp_startofpacket (limiter_001_rsp_src_startofpacket), // .startofpacket
.rp_endofpacket (limiter_001_rsp_src_endofpacket), // .endofpacket
.rp_ready (limiter_001_rsp_src_ready) // .ready
);
 
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (81),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (61),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (62),
.PKT_TRANS_POSTED (63),
.PKT_TRANS_WRITE (64),
.PKT_TRANS_READ (65),
.PKT_TRANS_LOCK (66),
.PKT_SRC_ID_H (85),
.PKT_SRC_ID_L (83),
.PKT_DEST_ID_H (88),
.PKT_DEST_ID_L (86),
.PKT_BURSTWRAP_H (73),
.PKT_BURSTWRAP_L (71),
.PKT_BYTE_CNT_H (70),
.PKT_BYTE_CNT_L (68),
.PKT_PROTECTION_H (92),
.PKT_PROTECTION_L (90),
.PKT_RESPONSE_STATUS_H (98),
.PKT_RESPONSE_STATUS_L (97),
.PKT_BURST_SIZE_H (76),
.PKT_BURST_SIZE_L (74),
.ST_CHANNEL_W (8),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_mux_src_ready), // cp.ready
.cp_valid (cmd_xbar_mux_src_valid), // .valid
.cp_data (cmd_xbar_mux_src_data), // .data
.cp_startofpacket (cmd_xbar_mux_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_mux_src_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_mux_src_channel), // .channel
.rf_sink_ready (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
 
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
 
altera_merlin_slave_agent #(
.PKT_DATA_H (15),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (63),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_ADDR_H (43),
.PKT_ADDR_L (18),
.PKT_TRANS_COMPRESSED_READ (44),
.PKT_TRANS_POSTED (45),
.PKT_TRANS_WRITE (46),
.PKT_TRANS_READ (47),
.PKT_TRANS_LOCK (48),
.PKT_SRC_ID_H (67),
.PKT_SRC_ID_L (65),
.PKT_DEST_ID_H (70),
.PKT_DEST_ID_L (68),
.PKT_BURSTWRAP_H (55),
.PKT_BURSTWRAP_L (53),
.PKT_BYTE_CNT_H (52),
.PKT_BYTE_CNT_L (50),
.PKT_PROTECTION_H (74),
.PKT_PROTECTION_L (72),
.PKT_RESPONSE_STATUS_H (80),
.PKT_RESPONSE_STATUS_L (79),
.PKT_BURST_SIZE_H (58),
.PKT_BURST_SIZE_L (56),
.ST_CHANNEL_W (8),
.ST_DATA_W (81),
.AVS_BURSTCOUNT_W (2),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1)
) sdram_0_s1_translator_avalon_universal_slave_0_agent (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (burst_adapter_source0_ready), // cp.ready
.cp_valid (burst_adapter_source0_valid), // .valid
.cp_data (burst_adapter_source0_data), // .data
.cp_startofpacket (burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (burst_adapter_source0_channel), // .channel
.rf_sink_ready (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
 
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (82),
.FIFO_DEPTH (8),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
 
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (81),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (61),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (62),
.PKT_TRANS_POSTED (63),
.PKT_TRANS_WRITE (64),
.PKT_TRANS_READ (65),
.PKT_TRANS_LOCK (66),
.PKT_SRC_ID_H (85),
.PKT_SRC_ID_L (83),
.PKT_DEST_ID_H (88),
.PKT_DEST_ID_L (86),
.PKT_BURSTWRAP_H (73),
.PKT_BURSTWRAP_L (71),
.PKT_BYTE_CNT_H (70),
.PKT_BYTE_CNT_L (68),
.PKT_PROTECTION_H (92),
.PKT_PROTECTION_L (90),
.PKT_RESPONSE_STATUS_H (98),
.PKT_RESPONSE_STATUS_L (97),
.PKT_BURST_SIZE_H (76),
.PKT_BURST_SIZE_L (74),
.ST_CHANNEL_W (8),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_001_src2_ready), // cp.ready
.cp_valid (cmd_xbar_demux_001_src2_valid), // .valid
.cp_data (cmd_xbar_demux_001_src2_data), // .data
.cp_startofpacket (cmd_xbar_demux_001_src2_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_001_src2_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_001_src2_channel), // .channel
.rf_sink_ready (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
 
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
 
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (81),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (61),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (62),
.PKT_TRANS_POSTED (63),
.PKT_TRANS_WRITE (64),
.PKT_TRANS_READ (65),
.PKT_TRANS_LOCK (66),
.PKT_SRC_ID_H (85),
.PKT_SRC_ID_L (83),
.PKT_DEST_ID_H (88),
.PKT_DEST_ID_L (86),
.PKT_BURSTWRAP_H (73),
.PKT_BURSTWRAP_L (71),
.PKT_BYTE_CNT_H (70),
.PKT_BYTE_CNT_L (68),
.PKT_PROTECTION_H (92),
.PKT_PROTECTION_L (90),
.PKT_RESPONSE_STATUS_H (98),
.PKT_RESPONSE_STATUS_L (97),
.PKT_BURST_SIZE_H (76),
.PKT_BURST_SIZE_L (74),
.ST_CHANNEL_W (8),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) timer_1_s1_translator_avalon_universal_slave_0_agent (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (timer_1_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (timer_1_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (timer_1_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (timer_1_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (timer_1_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (timer_1_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_001_src3_ready), // cp.ready
.cp_valid (cmd_xbar_demux_001_src3_valid), // .valid
.cp_data (cmd_xbar_demux_001_src3_data), // .data
.cp_startofpacket (cmd_xbar_demux_001_src3_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_001_src3_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_001_src3_channel), // .channel
.rf_sink_ready (timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (timer_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (timer_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (timer_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (timer_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (timer_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (timer_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
 
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (timer_1_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (timer_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
 
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (81),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (61),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (62),
.PKT_TRANS_POSTED (63),
.PKT_TRANS_WRITE (64),
.PKT_TRANS_READ (65),
.PKT_TRANS_LOCK (66),
.PKT_SRC_ID_H (85),
.PKT_SRC_ID_L (83),
.PKT_DEST_ID_H (88),
.PKT_DEST_ID_L (86),
.PKT_BURSTWRAP_H (73),
.PKT_BURSTWRAP_L (71),
.PKT_BYTE_CNT_H (70),
.PKT_BYTE_CNT_L (68),
.PKT_PROTECTION_H (92),
.PKT_PROTECTION_L (90),
.PKT_RESPONSE_STATUS_H (98),
.PKT_RESPONSE_STATUS_L (97),
.PKT_BURST_SIZE_H (76),
.PKT_BURST_SIZE_L (74),
.ST_CHANNEL_W (8),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) timer_0_s1_translator_avalon_universal_slave_0_agent (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_001_src4_ready), // cp.ready
.cp_valid (cmd_xbar_demux_001_src4_valid), // .valid
.cp_data (cmd_xbar_demux_001_src4_data), // .data
.cp_startofpacket (cmd_xbar_demux_001_src4_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_001_src4_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_001_src4_channel), // .channel
.rf_sink_ready (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
 
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
 
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (81),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (61),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (62),
.PKT_TRANS_POSTED (63),
.PKT_TRANS_WRITE (64),
.PKT_TRANS_READ (65),
.PKT_TRANS_LOCK (66),
.PKT_SRC_ID_H (85),
.PKT_SRC_ID_L (83),
.PKT_DEST_ID_H (88),
.PKT_DEST_ID_L (86),
.PKT_BURSTWRAP_H (73),
.PKT_BURSTWRAP_L (71),
.PKT_BYTE_CNT_H (70),
.PKT_BYTE_CNT_L (68),
.PKT_PROTECTION_H (92),
.PKT_PROTECTION_L (90),
.PKT_RESPONSE_STATUS_H (98),
.PKT_RESPONSE_STATUS_L (97),
.PKT_BURST_SIZE_H (76),
.PKT_BURST_SIZE_L (74),
.ST_CHANNEL_W (8),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_001_src5_ready), // cp.ready
.cp_valid (cmd_xbar_demux_001_src5_valid), // .valid
.cp_data (cmd_xbar_demux_001_src5_data), // .data
.cp_startofpacket (cmd_xbar_demux_001_src5_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_001_src5_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_001_src5_channel), // .channel
.rf_sink_ready (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
 
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
 
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (81),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (61),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (62),
.PKT_TRANS_POSTED (63),
.PKT_TRANS_WRITE (64),
.PKT_TRANS_READ (65),
.PKT_TRANS_LOCK (66),
.PKT_SRC_ID_H (85),
.PKT_SRC_ID_L (83),
.PKT_DEST_ID_H (88),
.PKT_DEST_ID_L (86),
.PKT_BURSTWRAP_H (73),
.PKT_BURSTWRAP_L (71),
.PKT_BYTE_CNT_H (70),
.PKT_BYTE_CNT_L (68),
.PKT_PROTECTION_H (92),
.PKT_PROTECTION_L (90),
.PKT_RESPONSE_STATUS_H (98),
.PKT_RESPONSE_STATUS_L (97),
.PKT_BURST_SIZE_H (76),
.PKT_BURST_SIZE_L (74),
.ST_CHANNEL_W (8),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_001_src6_ready), // cp.ready
.cp_valid (cmd_xbar_demux_001_src6_valid), // .valid
.cp_data (cmd_xbar_demux_001_src6_data), // .data
.cp_startofpacket (cmd_xbar_demux_001_src6_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_001_src6_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_001_src6_channel), // .channel
.rf_sink_ready (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
 
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
 
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (81),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (61),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (62),
.PKT_TRANS_POSTED (63),
.PKT_TRANS_WRITE (64),
.PKT_TRANS_READ (65),
.PKT_TRANS_LOCK (66),
.PKT_SRC_ID_H (85),
.PKT_SRC_ID_L (83),
.PKT_DEST_ID_H (88),
.PKT_DEST_ID_L (86),
.PKT_BURSTWRAP_H (73),
.PKT_BURSTWRAP_L (71),
.PKT_BYTE_CNT_H (70),
.PKT_BYTE_CNT_L (68),
.PKT_PROTECTION_H (92),
.PKT_PROTECTION_L (90),
.PKT_RESPONSE_STATUS_H (98),
.PKT_RESPONSE_STATUS_L (97),
.PKT_BURST_SIZE_H (76),
.PKT_BURST_SIZE_L (74),
.ST_CHANNEL_W (8),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_001_src7_ready), // cp.ready
.cp_valid (cmd_xbar_demux_001_src7_valid), // .valid
.cp_data (cmd_xbar_demux_001_src7_data), // .data
.cp_startofpacket (cmd_xbar_demux_001_src7_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_001_src7_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_001_src7_channel), // .channel
.rf_sink_ready (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
 
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
 
altera_merlin_master_agent #(
.PKT_PROTECTION_H (94),
.PKT_PROTECTION_L (92),
.PKT_BEGIN_BURST (87),
.PKT_BURSTWRAP_H (79),
.PKT_BURSTWRAP_L (77),
.PKT_BURST_SIZE_H (82),
.PKT_BURST_SIZE_L (80),
.PKT_BURST_TYPE_H (84),
.PKT_BURST_TYPE_L (83),
.PKT_BYTE_CNT_H (76),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_TRANS_LOCK (72),
.PKT_TRANS_EXCLUSIVE (73),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (89),
.PKT_SRC_ID_L (89),
.PKT_DEST_ID_H (90),
.PKT_DEST_ID_L (90),
.PKT_THREAD_ID_H (91),
.PKT_THREAD_ID_L (91),
.PKT_CACHE_H (98),
.PKT_CACHE_L (95),
.PKT_DATA_SIDEBAND_H (86),
.PKT_DATA_SIDEBAND_L (86),
.PKT_QOS_H (88),
.PKT_QOS_L (88),
.PKT_ADDR_SIDEBAND_H (85),
.PKT_ADDR_SIDEBAND_L (85),
.ST_DATA_W (101),
.ST_CHANNEL_W (2),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (0),
.BURSTWRAP_VALUE (7),
.CACHE_VALUE (4'b0000)
) hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.av_address (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_address), // av.address
.av_write (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_write), // .write
.av_read (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid
.cp_data (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.cp_startofpacket (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.cp_ready (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_ready), // .ready
.rp_valid (rsp_xbar_demux_008_src0_valid), // rp.valid
.rp_data (rsp_xbar_demux_008_src0_data), // .data
.rp_channel (rsp_xbar_demux_008_src0_channel), // .channel
.rp_startofpacket (rsp_xbar_demux_008_src0_startofpacket), // .startofpacket
.rp_endofpacket (rsp_xbar_demux_008_src0_endofpacket), // .endofpacket
.rp_ready (rsp_xbar_demux_008_src0_ready) // .ready
);
 
altera_merlin_master_agent #(
.PKT_PROTECTION_H (94),
.PKT_PROTECTION_L (92),
.PKT_BEGIN_BURST (87),
.PKT_BURSTWRAP_H (79),
.PKT_BURSTWRAP_L (77),
.PKT_BURST_SIZE_H (82),
.PKT_BURST_SIZE_L (80),
.PKT_BURST_TYPE_H (84),
.PKT_BURST_TYPE_L (83),
.PKT_BYTE_CNT_H (76),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_TRANS_LOCK (72),
.PKT_TRANS_EXCLUSIVE (73),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (89),
.PKT_SRC_ID_L (89),
.PKT_DEST_ID_H (90),
.PKT_DEST_ID_L (90),
.PKT_THREAD_ID_H (91),
.PKT_THREAD_ID_L (91),
.PKT_CACHE_H (98),
.PKT_CACHE_L (95),
.PKT_DATA_SIDEBAND_H (86),
.PKT_DATA_SIDEBAND_L (86),
.PKT_QOS_H (88),
.PKT_QOS_L (88),
.PKT_ADDR_SIDEBAND_H (85),
.PKT_ADDR_SIDEBAND_L (85),
.ST_DATA_W (101),
.ST_CHANNEL_W (2),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (1),
.BURSTWRAP_VALUE (7),
.CACHE_VALUE (4'b0000)
) hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.av_address (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_address), // av.address
.av_write (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_write), // .write
.av_read (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_read), // .read
.av_writedata (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid
.cp_data (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_data), // .data
.cp_startofpacket (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.cp_ready (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_ready), // .ready
.rp_valid (rsp_xbar_demux_008_src1_valid), // rp.valid
.rp_data (rsp_xbar_demux_008_src1_data), // .data
.rp_channel (rsp_xbar_demux_008_src1_channel), // .channel
.rp_startofpacket (rsp_xbar_demux_008_src1_startofpacket), // .startofpacket
.rp_endofpacket (rsp_xbar_demux_008_src1_endofpacket), // .endofpacket
.rp_ready (rsp_xbar_demux_008_src1_ready) // .ready
);
 
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (87),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_TRANS_LOCK (72),
.PKT_SRC_ID_H (89),
.PKT_SRC_ID_L (89),
.PKT_DEST_ID_H (90),
.PKT_DEST_ID_L (90),
.PKT_BURSTWRAP_H (79),
.PKT_BURSTWRAP_L (77),
.PKT_BYTE_CNT_H (76),
.PKT_BYTE_CNT_L (74),
.PKT_PROTECTION_H (94),
.PKT_PROTECTION_L (92),
.PKT_RESPONSE_STATUS_H (100),
.PKT_RESPONSE_STATUS_L (99),
.PKT_BURST_SIZE_H (82),
.PKT_BURST_SIZE_L (80),
.ST_CHANNEL_W (2),
.ST_DATA_W (101),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_mux_008_src_ready), // cp.ready
.cp_valid (cmd_xbar_mux_008_src_valid), // .valid
.cp_data (cmd_xbar_mux_008_src_data), // .data
.cp_startofpacket (cmd_xbar_mux_008_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_mux_008_src_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_mux_008_src_channel), // .channel
.rf_sink_ready (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
 
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (102),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
 
nios2_sdram_addr_router addr_router (
.sink_ready (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready
.sink_valid (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent_cp_valid), // .valid
.sink_data (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.sink_startofpacket (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (nios2_qsys_1_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (addr_router_src_ready), // src.ready
.src_valid (addr_router_src_valid), // .valid
.src_data (addr_router_src_data), // .data
.src_channel (addr_router_src_channel), // .channel
.src_startofpacket (addr_router_src_startofpacket), // .startofpacket
.src_endofpacket (addr_router_src_endofpacket) // .endofpacket
);
 
nios2_sdram_addr_router_001 addr_router_001 (
.sink_ready (nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready
.sink_valid (nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent_cp_valid), // .valid
.sink_data (nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.sink_startofpacket (nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (nios2_qsys_1_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (addr_router_001_src_ready), // src.ready
.src_valid (addr_router_001_src_valid), // .valid
.src_data (addr_router_001_src_data), // .data
.src_channel (addr_router_001_src_channel), // .channel
.src_startofpacket (addr_router_001_src_startofpacket), // .startofpacket
.src_endofpacket (addr_router_001_src_endofpacket) // .endofpacket
);
 
nios2_sdram_id_router id_router (
.sink_ready (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (nios2_qsys_1_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_src_ready), // src.ready
.src_valid (id_router_src_valid), // .valid
.src_data (id_router_src_data), // .data
.src_channel (id_router_src_channel), // .channel
.src_startofpacket (id_router_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_src_endofpacket) // .endofpacket
);
 
nios2_sdram_id_router_001 id_router_001 (
.sink_ready (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_001_src_ready), // src.ready
.src_valid (id_router_001_src_valid), // .valid
.src_data (id_router_001_src_data), // .data
.src_channel (id_router_001_src_channel), // .channel
.src_startofpacket (id_router_001_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_001_src_endofpacket) // .endofpacket
);
 
nios2_sdram_id_router_002 id_router_002 (
.sink_ready (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (jtag_uart_1_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_002_src_ready), // src.ready
.src_valid (id_router_002_src_valid), // .valid
.src_data (id_router_002_src_data), // .data
.src_channel (id_router_002_src_channel), // .channel
.src_startofpacket (id_router_002_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_002_src_endofpacket) // .endofpacket
);
 
nios2_sdram_id_router_002 id_router_003 (
.sink_ready (timer_1_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (timer_1_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (timer_1_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (timer_1_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (timer_1_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_003_src_ready), // src.ready
.src_valid (id_router_003_src_valid), // .valid
.src_data (id_router_003_src_data), // .data
.src_channel (id_router_003_src_channel), // .channel
.src_startofpacket (id_router_003_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_003_src_endofpacket) // .endofpacket
);
 
nios2_sdram_id_router_002 id_router_004 (
.sink_ready (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_004_src_ready), // src.ready
.src_valid (id_router_004_src_valid), // .valid
.src_data (id_router_004_src_data), // .data
.src_channel (id_router_004_src_channel), // .channel
.src_startofpacket (id_router_004_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_004_src_endofpacket) // .endofpacket
);
 
nios2_sdram_id_router_002 id_router_005 (
.sink_ready (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sysid_qsys_1_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_005_src_ready), // src.ready
.src_valid (id_router_005_src_valid), // .valid
.src_data (id_router_005_src_data), // .data
.src_channel (id_router_005_src_channel), // .channel
.src_startofpacket (id_router_005_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_005_src_endofpacket) // .endofpacket
);
 
nios2_sdram_id_router_002 id_router_006 (
.sink_ready (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (onchip_memory2_1_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_006_src_ready), // src.ready
.src_valid (id_router_006_src_valid), // .valid
.src_data (id_router_006_src_data), // .data
.src_channel (id_router_006_src_channel), // .channel
.src_startofpacket (id_router_006_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_006_src_endofpacket) // .endofpacket
);
 
nios2_sdram_id_router_002 id_router_007 (
.sink_ready (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (hibi_pe_dma_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_007_src_ready), // src.ready
.src_valid (id_router_007_src_valid), // .valid
.src_data (id_router_007_src_data), // .data
.src_channel (id_router_007_src_channel), // .channel
.src_startofpacket (id_router_007_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_007_src_endofpacket) // .endofpacket
);
 
nios2_sdram_addr_router_002 addr_router_002 (
.sink_ready (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready
.sink_valid (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_valid), // .valid
.sink_data (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.sink_startofpacket (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (hibi_pe_dma_0_avalon_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (addr_router_002_src_ready), // src.ready
.src_valid (addr_router_002_src_valid), // .valid
.src_data (addr_router_002_src_data), // .data
.src_channel (addr_router_002_src_channel), // .channel
.src_startofpacket (addr_router_002_src_startofpacket), // .startofpacket
.src_endofpacket (addr_router_002_src_endofpacket) // .endofpacket
);
 
nios2_sdram_addr_router_002 addr_router_003 (
.sink_ready (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready
.sink_valid (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_valid), // .valid
.sink_data (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_data), // .data
.sink_startofpacket (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (hibi_pe_dma_0_avalon_master_1_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (addr_router_003_src_ready), // src.ready
.src_valid (addr_router_003_src_valid), // .valid
.src_data (addr_router_003_src_data), // .data
.src_channel (addr_router_003_src_channel), // .channel
.src_startofpacket (addr_router_003_src_startofpacket), // .startofpacket
.src_endofpacket (addr_router_003_src_endofpacket) // .endofpacket
);
 
nios2_sdram_id_router_008 id_router_008 (
.sink_ready (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (onchip_memory2_1_s2_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_008_src_ready), // src.ready
.src_valid (id_router_008_src_valid), // .valid
.src_data (id_router_008_src_data), // .data
.src_channel (id_router_008_src_channel), // .channel
.src_startofpacket (id_router_008_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_008_src_endofpacket) // .endofpacket
);
 
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (88),
.PKT_DEST_ID_L (86),
.PKT_TRANS_POSTED (63),
.PKT_TRANS_WRITE (64),
.MAX_OUTSTANDING_RESPONSES (9),
.PIPELINED (0),
.ST_DATA_W (99),
.ST_CHANNEL_W (8),
.VALID_WIDTH (8),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.PKT_BYTE_CNT_H (70),
.PKT_BYTE_CNT_L (68),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32)
) limiter (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.cmd_sink_ready (addr_router_src_ready), // cmd_sink.ready
.cmd_sink_valid (addr_router_src_valid), // .valid
.cmd_sink_data (addr_router_src_data), // .data
.cmd_sink_channel (addr_router_src_channel), // .channel
.cmd_sink_startofpacket (addr_router_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (addr_router_src_endofpacket), // .endofpacket
.cmd_src_ready (limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (limiter_cmd_src_data), // .data
.cmd_src_channel (limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_xbar_mux_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_xbar_mux_src_valid), // .valid
.rsp_sink_channel (rsp_xbar_mux_src_channel), // .channel
.rsp_sink_data (rsp_xbar_mux_src_data), // .data
.rsp_sink_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket
.rsp_src_ready (limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (limiter_rsp_src_valid), // .valid
.rsp_src_data (limiter_rsp_src_data), // .data
.rsp_src_channel (limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (limiter_cmd_valid_data) // cmd_valid.data
);
 
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (88),
.PKT_DEST_ID_L (86),
.PKT_TRANS_POSTED (63),
.PKT_TRANS_WRITE (64),
.MAX_OUTSTANDING_RESPONSES (9),
.PIPELINED (0),
.ST_DATA_W (99),
.ST_CHANNEL_W (8),
.VALID_WIDTH (8),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.PKT_BYTE_CNT_H (70),
.PKT_BYTE_CNT_L (68),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32)
) limiter_001 (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.cmd_sink_ready (addr_router_001_src_ready), // cmd_sink.ready
.cmd_sink_valid (addr_router_001_src_valid), // .valid
.cmd_sink_data (addr_router_001_src_data), // .data
.cmd_sink_channel (addr_router_001_src_channel), // .channel
.cmd_sink_startofpacket (addr_router_001_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (addr_router_001_src_endofpacket), // .endofpacket
.cmd_src_ready (limiter_001_cmd_src_ready), // cmd_src.ready
.cmd_src_data (limiter_001_cmd_src_data), // .data
.cmd_src_channel (limiter_001_cmd_src_channel), // .channel
.cmd_src_startofpacket (limiter_001_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (limiter_001_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_xbar_mux_001_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_xbar_mux_001_src_valid), // .valid
.rsp_sink_channel (rsp_xbar_mux_001_src_channel), // .channel
.rsp_sink_data (rsp_xbar_mux_001_src_data), // .data
.rsp_sink_startofpacket (rsp_xbar_mux_001_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_xbar_mux_001_src_endofpacket), // .endofpacket
.rsp_src_ready (limiter_001_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (limiter_001_rsp_src_valid), // .valid
.rsp_src_data (limiter_001_rsp_src_data), // .data
.rsp_src_channel (limiter_001_rsp_src_channel), // .channel
.rsp_src_startofpacket (limiter_001_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (limiter_001_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (limiter_001_cmd_valid_data) // cmd_valid.data
);
 
altera_merlin_burst_adapter #(
.PKT_ADDR_H (43),
.PKT_ADDR_L (18),
.PKT_BEGIN_BURST (63),
.PKT_BYTE_CNT_H (52),
.PKT_BYTE_CNT_L (50),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_BURST_SIZE_H (58),
.PKT_BURST_SIZE_L (56),
.PKT_BURST_TYPE_H (60),
.PKT_BURST_TYPE_L (59),
.PKT_BURSTWRAP_H (55),
.PKT_BURSTWRAP_L (53),
.PKT_TRANS_COMPRESSED_READ (44),
.PKT_TRANS_WRITE (46),
.PKT_TRANS_READ (47),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (0),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (81),
.ST_CHANNEL_W (8),
.OUT_BYTE_CNT_H (51),
.OUT_BURSTWRAP_H (55),
.COMPRESSED_READ_SUPPORT (0),
.BYTEENABLE_SYNTHESIS (0),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (3),
.BURSTWRAP_CONST_VALUE (3)
) burst_adapter (
.clk (clk_clk), // cr0.clk
.reset (rst_controller_reset_out_reset), // cr0_reset.reset
.sink0_valid (width_adapter_src_valid), // sink0.valid
.sink0_data (width_adapter_src_data), // .data
.sink0_channel (width_adapter_src_channel), // .channel
.sink0_startofpacket (width_adapter_src_startofpacket), // .startofpacket
.sink0_endofpacket (width_adapter_src_endofpacket), // .endofpacket
.sink0_ready (width_adapter_src_ready), // .ready
.source0_valid (burst_adapter_source0_valid), // source0.valid
.source0_data (burst_adapter_source0_data), // .data
.source0_channel (burst_adapter_source0_channel), // .channel
.source0_startofpacket (burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (burst_adapter_source0_ready) // .ready
);
 
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2)
) rst_controller (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_in15 (1'b0) // (terminated)
);
 
nios2_sdram_cmd_xbar_demux cmd_xbar_demux (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (limiter_cmd_src_ready), // sink.ready
.sink_channel (limiter_cmd_src_channel), // .channel
.sink_data (limiter_cmd_src_data), // .data
.sink_startofpacket (limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_xbar_demux_src0_ready), // src0.ready
.src0_valid (cmd_xbar_demux_src0_valid), // .valid
.src0_data (cmd_xbar_demux_src0_data), // .data
.src0_channel (cmd_xbar_demux_src0_channel), // .channel
.src0_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_xbar_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_xbar_demux_src1_ready), // src1.ready
.src1_valid (cmd_xbar_demux_src1_valid), // .valid
.src1_data (cmd_xbar_demux_src1_data), // .data
.src1_channel (cmd_xbar_demux_src1_channel), // .channel
.src1_startofpacket (cmd_xbar_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_xbar_demux_src1_endofpacket) // .endofpacket
);
 
nios2_sdram_cmd_xbar_demux_001 cmd_xbar_demux_001 (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (limiter_001_cmd_src_ready), // sink.ready
.sink_channel (limiter_001_cmd_src_channel), // .channel
.sink_data (limiter_001_cmd_src_data), // .data
.sink_startofpacket (limiter_001_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (limiter_001_cmd_src_endofpacket), // .endofpacket
.sink_valid (limiter_001_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_xbar_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_xbar_demux_001_src0_valid), // .valid
.src0_data (cmd_xbar_demux_001_src0_data), // .data
.src0_channel (cmd_xbar_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_xbar_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_xbar_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (cmd_xbar_demux_001_src1_ready), // src1.ready
.src1_valid (cmd_xbar_demux_001_src1_valid), // .valid
.src1_data (cmd_xbar_demux_001_src1_data), // .data
.src1_channel (cmd_xbar_demux_001_src1_channel), // .channel
.src1_startofpacket (cmd_xbar_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_xbar_demux_001_src1_endofpacket), // .endofpacket
.src2_ready (cmd_xbar_demux_001_src2_ready), // src2.ready
.src2_valid (cmd_xbar_demux_001_src2_valid), // .valid
.src2_data (cmd_xbar_demux_001_src2_data), // .data
.src2_channel (cmd_xbar_demux_001_src2_channel), // .channel
.src2_startofpacket (cmd_xbar_demux_001_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_xbar_demux_001_src2_endofpacket), // .endofpacket
.src3_ready (cmd_xbar_demux_001_src3_ready), // src3.ready
.src3_valid (cmd_xbar_demux_001_src3_valid), // .valid
.src3_data (cmd_xbar_demux_001_src3_data), // .data
.src3_channel (cmd_xbar_demux_001_src3_channel), // .channel
.src3_startofpacket (cmd_xbar_demux_001_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_xbar_demux_001_src3_endofpacket), // .endofpacket
.src4_ready (cmd_xbar_demux_001_src4_ready), // src4.ready
.src4_valid (cmd_xbar_demux_001_src4_valid), // .valid
.src4_data (cmd_xbar_demux_001_src4_data), // .data
.src4_channel (cmd_xbar_demux_001_src4_channel), // .channel
.src4_startofpacket (cmd_xbar_demux_001_src4_startofpacket), // .startofpacket
.src4_endofpacket (cmd_xbar_demux_001_src4_endofpacket), // .endofpacket
.src5_ready (cmd_xbar_demux_001_src5_ready), // src5.ready
.src5_valid (cmd_xbar_demux_001_src5_valid), // .valid
.src5_data (cmd_xbar_demux_001_src5_data), // .data
.src5_channel (cmd_xbar_demux_001_src5_channel), // .channel
.src5_startofpacket (cmd_xbar_demux_001_src5_startofpacket), // .startofpacket
.src5_endofpacket (cmd_xbar_demux_001_src5_endofpacket), // .endofpacket
.src6_ready (cmd_xbar_demux_001_src6_ready), // src6.ready
.src6_valid (cmd_xbar_demux_001_src6_valid), // .valid
.src6_data (cmd_xbar_demux_001_src6_data), // .data
.src6_channel (cmd_xbar_demux_001_src6_channel), // .channel
.src6_startofpacket (cmd_xbar_demux_001_src6_startofpacket), // .startofpacket
.src6_endofpacket (cmd_xbar_demux_001_src6_endofpacket), // .endofpacket
.src7_ready (cmd_xbar_demux_001_src7_ready), // src7.ready
.src7_valid (cmd_xbar_demux_001_src7_valid), // .valid
.src7_data (cmd_xbar_demux_001_src7_data), // .data
.src7_channel (cmd_xbar_demux_001_src7_channel), // .channel
.src7_startofpacket (cmd_xbar_demux_001_src7_startofpacket), // .startofpacket
.src7_endofpacket (cmd_xbar_demux_001_src7_endofpacket) // .endofpacket
);
 
nios2_sdram_cmd_xbar_mux cmd_xbar_mux (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (cmd_xbar_mux_src_ready), // src.ready
.src_valid (cmd_xbar_mux_src_valid), // .valid
.src_data (cmd_xbar_mux_src_data), // .data
.src_channel (cmd_xbar_mux_src_channel), // .channel
.src_startofpacket (cmd_xbar_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_xbar_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_xbar_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_xbar_demux_src0_valid), // .valid
.sink0_channel (cmd_xbar_demux_src0_channel), // .channel
.sink0_data (cmd_xbar_demux_src0_data), // .data
.sink0_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_xbar_demux_src0_endofpacket), // .endofpacket
.sink1_ready (cmd_xbar_demux_001_src0_ready), // sink1.ready
.sink1_valid (cmd_xbar_demux_001_src0_valid), // .valid
.sink1_channel (cmd_xbar_demux_001_src0_channel), // .channel
.sink1_data (cmd_xbar_demux_001_src0_data), // .data
.sink1_startofpacket (cmd_xbar_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_xbar_demux_001_src0_endofpacket) // .endofpacket
);
 
nios2_sdram_cmd_xbar_mux cmd_xbar_mux_001 (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (cmd_xbar_mux_001_src_ready), // src.ready
.src_valid (cmd_xbar_mux_001_src_valid), // .valid
.src_data (cmd_xbar_mux_001_src_data), // .data
.src_channel (cmd_xbar_mux_001_src_channel), // .channel
.src_startofpacket (cmd_xbar_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_xbar_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_xbar_demux_src1_ready), // sink0.ready
.sink0_valid (cmd_xbar_demux_src1_valid), // .valid
.sink0_channel (cmd_xbar_demux_src1_channel), // .channel
.sink0_data (cmd_xbar_demux_src1_data), // .data
.sink0_startofpacket (cmd_xbar_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_xbar_demux_src1_endofpacket), // .endofpacket
.sink1_ready (cmd_xbar_demux_001_src1_ready), // sink1.ready
.sink1_valid (cmd_xbar_demux_001_src1_valid), // .valid
.sink1_channel (cmd_xbar_demux_001_src1_channel), // .channel
.sink1_data (cmd_xbar_demux_001_src1_data), // .data
.sink1_startofpacket (cmd_xbar_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_xbar_demux_001_src1_endofpacket) // .endofpacket
);
 
nios2_sdram_rsp_xbar_demux rsp_xbar_demux (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_src_ready), // sink.ready
.sink_channel (id_router_src_channel), // .channel
.sink_data (id_router_src_data), // .data
.sink_startofpacket (id_router_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_src_endofpacket), // .endofpacket
.sink_valid (id_router_src_valid), // .valid
.src0_ready (rsp_xbar_demux_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_src0_valid), // .valid
.src0_data (rsp_xbar_demux_src0_data), // .data
.src0_channel (rsp_xbar_demux_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_src0_endofpacket), // .endofpacket
.src1_ready (rsp_xbar_demux_src1_ready), // src1.ready
.src1_valid (rsp_xbar_demux_src1_valid), // .valid
.src1_data (rsp_xbar_demux_src1_data), // .data
.src1_channel (rsp_xbar_demux_src1_channel), // .channel
.src1_startofpacket (rsp_xbar_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_xbar_demux_src1_endofpacket) // .endofpacket
);
 
nios2_sdram_rsp_xbar_demux rsp_xbar_demux_001 (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (width_adapter_001_src_ready), // sink.ready
.sink_channel (width_adapter_001_src_channel), // .channel
.sink_data (width_adapter_001_src_data), // .data
.sink_startofpacket (width_adapter_001_src_startofpacket), // .startofpacket
.sink_endofpacket (width_adapter_001_src_endofpacket), // .endofpacket
.sink_valid (width_adapter_001_src_valid), // .valid
.src0_ready (rsp_xbar_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_001_src0_valid), // .valid
.src0_data (rsp_xbar_demux_001_src0_data), // .data
.src0_channel (rsp_xbar_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (rsp_xbar_demux_001_src1_ready), // src1.ready
.src1_valid (rsp_xbar_demux_001_src1_valid), // .valid
.src1_data (rsp_xbar_demux_001_src1_data), // .data
.src1_channel (rsp_xbar_demux_001_src1_channel), // .channel
.src1_startofpacket (rsp_xbar_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_xbar_demux_001_src1_endofpacket) // .endofpacket
);
 
nios2_sdram_rsp_xbar_demux_002 rsp_xbar_demux_002 (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_002_src_ready), // sink.ready
.sink_channel (id_router_002_src_channel), // .channel
.sink_data (id_router_002_src_data), // .data
.sink_startofpacket (id_router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_002_src_endofpacket), // .endofpacket
.sink_valid (id_router_002_src_valid), // .valid
.src0_ready (rsp_xbar_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_002_src0_valid), // .valid
.src0_data (rsp_xbar_demux_002_src0_data), // .data
.src0_channel (rsp_xbar_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_002_src0_endofpacket) // .endofpacket
);
 
nios2_sdram_rsp_xbar_demux_002 rsp_xbar_demux_003 (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_003_src_ready), // sink.ready
.sink_channel (id_router_003_src_channel), // .channel
.sink_data (id_router_003_src_data), // .data
.sink_startofpacket (id_router_003_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_003_src_endofpacket), // .endofpacket
.sink_valid (id_router_003_src_valid), // .valid
.src0_ready (rsp_xbar_demux_003_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_003_src0_valid), // .valid
.src0_data (rsp_xbar_demux_003_src0_data), // .data
.src0_channel (rsp_xbar_demux_003_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_003_src0_endofpacket) // .endofpacket
);
 
nios2_sdram_rsp_xbar_demux_002 rsp_xbar_demux_004 (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_004_src_ready), // sink.ready
.sink_channel (id_router_004_src_channel), // .channel
.sink_data (id_router_004_src_data), // .data
.sink_startofpacket (id_router_004_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_004_src_endofpacket), // .endofpacket
.sink_valid (id_router_004_src_valid), // .valid
.src0_ready (rsp_xbar_demux_004_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_004_src0_valid), // .valid
.src0_data (rsp_xbar_demux_004_src0_data), // .data
.src0_channel (rsp_xbar_demux_004_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_004_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_004_src0_endofpacket) // .endofpacket
);
 
nios2_sdram_rsp_xbar_demux_002 rsp_xbar_demux_005 (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_005_src_ready), // sink.ready
.sink_channel (id_router_005_src_channel), // .channel
.sink_data (id_router_005_src_data), // .data
.sink_startofpacket (id_router_005_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_005_src_endofpacket), // .endofpacket
.sink_valid (id_router_005_src_valid), // .valid
.src0_ready (rsp_xbar_demux_005_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_005_src0_valid), // .valid
.src0_data (rsp_xbar_demux_005_src0_data), // .data
.src0_channel (rsp_xbar_demux_005_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_005_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_005_src0_endofpacket) // .endofpacket
);
 
nios2_sdram_rsp_xbar_demux_002 rsp_xbar_demux_006 (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_006_src_ready), // sink.ready
.sink_channel (id_router_006_src_channel), // .channel
.sink_data (id_router_006_src_data), // .data
.sink_startofpacket (id_router_006_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_006_src_endofpacket), // .endofpacket
.sink_valid (id_router_006_src_valid), // .valid
.src0_ready (rsp_xbar_demux_006_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_006_src0_valid), // .valid
.src0_data (rsp_xbar_demux_006_src0_data), // .data
.src0_channel (rsp_xbar_demux_006_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_006_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_006_src0_endofpacket) // .endofpacket
);
 
nios2_sdram_rsp_xbar_demux_002 rsp_xbar_demux_007 (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_007_src_ready), // sink.ready
.sink_channel (id_router_007_src_channel), // .channel
.sink_data (id_router_007_src_data), // .data
.sink_startofpacket (id_router_007_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_007_src_endofpacket), // .endofpacket
.sink_valid (id_router_007_src_valid), // .valid
.src0_ready (rsp_xbar_demux_007_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_007_src0_valid), // .valid
.src0_data (rsp_xbar_demux_007_src0_data), // .data
.src0_channel (rsp_xbar_demux_007_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_007_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_007_src0_endofpacket) // .endofpacket
);
 
nios2_sdram_rsp_xbar_mux rsp_xbar_mux (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (rsp_xbar_mux_src_ready), // src.ready
.src_valid (rsp_xbar_mux_src_valid), // .valid
.src_data (rsp_xbar_mux_src_data), // .data
.src_channel (rsp_xbar_mux_src_channel), // .channel
.src_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_xbar_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_xbar_demux_src0_valid), // .valid
.sink0_channel (rsp_xbar_demux_src0_channel), // .channel
.sink0_data (rsp_xbar_demux_src0_data), // .data
.sink0_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_xbar_demux_src0_endofpacket), // .endofpacket
.sink1_ready (rsp_xbar_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_xbar_demux_001_src0_valid), // .valid
.sink1_channel (rsp_xbar_demux_001_src0_channel), // .channel
.sink1_data (rsp_xbar_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_xbar_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_xbar_demux_001_src0_endofpacket) // .endofpacket
);
 
nios2_sdram_rsp_xbar_mux_001 rsp_xbar_mux_001 (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (rsp_xbar_mux_001_src_ready), // src.ready
.src_valid (rsp_xbar_mux_001_src_valid), // .valid
.src_data (rsp_xbar_mux_001_src_data), // .data
.src_channel (rsp_xbar_mux_001_src_channel), // .channel
.src_startofpacket (rsp_xbar_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_xbar_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (rsp_xbar_demux_src1_ready), // sink0.ready
.sink0_valid (rsp_xbar_demux_src1_valid), // .valid
.sink0_channel (rsp_xbar_demux_src1_channel), // .channel
.sink0_data (rsp_xbar_demux_src1_data), // .data
.sink0_startofpacket (rsp_xbar_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_xbar_demux_src1_endofpacket), // .endofpacket
.sink1_ready (rsp_xbar_demux_001_src1_ready), // sink1.ready
.sink1_valid (rsp_xbar_demux_001_src1_valid), // .valid
.sink1_channel (rsp_xbar_demux_001_src1_channel), // .channel
.sink1_data (rsp_xbar_demux_001_src1_data), // .data
.sink1_startofpacket (rsp_xbar_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_xbar_demux_001_src1_endofpacket), // .endofpacket
.sink2_ready (rsp_xbar_demux_002_src0_ready), // sink2.ready
.sink2_valid (rsp_xbar_demux_002_src0_valid), // .valid
.sink2_channel (rsp_xbar_demux_002_src0_channel), // .channel
.sink2_data (rsp_xbar_demux_002_src0_data), // .data
.sink2_startofpacket (rsp_xbar_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_xbar_demux_002_src0_endofpacket), // .endofpacket
.sink3_ready (rsp_xbar_demux_003_src0_ready), // sink3.ready
.sink3_valid (rsp_xbar_demux_003_src0_valid), // .valid
.sink3_channel (rsp_xbar_demux_003_src0_channel), // .channel
.sink3_data (rsp_xbar_demux_003_src0_data), // .data
.sink3_startofpacket (rsp_xbar_demux_003_src0_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_xbar_demux_003_src0_endofpacket), // .endofpacket
.sink4_ready (rsp_xbar_demux_004_src0_ready), // sink4.ready
.sink4_valid (rsp_xbar_demux_004_src0_valid), // .valid
.sink4_channel (rsp_xbar_demux_004_src0_channel), // .channel
.sink4_data (rsp_xbar_demux_004_src0_data), // .data
.sink4_startofpacket (rsp_xbar_demux_004_src0_startofpacket), // .startofpacket
.sink4_endofpacket (rsp_xbar_demux_004_src0_endofpacket), // .endofpacket
.sink5_ready (rsp_xbar_demux_005_src0_ready), // sink5.ready
.sink5_valid (rsp_xbar_demux_005_src0_valid), // .valid
.sink5_channel (rsp_xbar_demux_005_src0_channel), // .channel
.sink5_data (rsp_xbar_demux_005_src0_data), // .data
.sink5_startofpacket (rsp_xbar_demux_005_src0_startofpacket), // .startofpacket
.sink5_endofpacket (rsp_xbar_demux_005_src0_endofpacket), // .endofpacket
.sink6_ready (rsp_xbar_demux_006_src0_ready), // sink6.ready
.sink6_valid (rsp_xbar_demux_006_src0_valid), // .valid
.sink6_channel (rsp_xbar_demux_006_src0_channel), // .channel
.sink6_data (rsp_xbar_demux_006_src0_data), // .data
.sink6_startofpacket (rsp_xbar_demux_006_src0_startofpacket), // .startofpacket
.sink6_endofpacket (rsp_xbar_demux_006_src0_endofpacket), // .endofpacket
.sink7_ready (rsp_xbar_demux_007_src0_ready), // sink7.ready
.sink7_valid (rsp_xbar_demux_007_src0_valid), // .valid
.sink7_channel (rsp_xbar_demux_007_src0_channel), // .channel
.sink7_data (rsp_xbar_demux_007_src0_data), // .data
.sink7_startofpacket (rsp_xbar_demux_007_src0_startofpacket), // .startofpacket
.sink7_endofpacket (rsp_xbar_demux_007_src0_endofpacket) // .endofpacket
);
 
nios2_sdram_cmd_xbar_demux_002 cmd_xbar_demux_002 (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (addr_router_002_src_ready), // sink.ready
.sink_channel (addr_router_002_src_channel), // .channel
.sink_data (addr_router_002_src_data), // .data
.sink_startofpacket (addr_router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (addr_router_002_src_endofpacket), // .endofpacket
.sink_valid (addr_router_002_src_valid), // .valid
.src0_ready (cmd_xbar_demux_002_src0_ready), // src0.ready
.src0_valid (cmd_xbar_demux_002_src0_valid), // .valid
.src0_data (cmd_xbar_demux_002_src0_data), // .data
.src0_channel (cmd_xbar_demux_002_src0_channel), // .channel
.src0_startofpacket (cmd_xbar_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_xbar_demux_002_src0_endofpacket) // .endofpacket
);
 
nios2_sdram_cmd_xbar_demux_002 cmd_xbar_demux_003 (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (addr_router_003_src_ready), // sink.ready
.sink_channel (addr_router_003_src_channel), // .channel
.sink_data (addr_router_003_src_data), // .data
.sink_startofpacket (addr_router_003_src_startofpacket), // .startofpacket
.sink_endofpacket (addr_router_003_src_endofpacket), // .endofpacket
.sink_valid (addr_router_003_src_valid), // .valid
.src0_ready (cmd_xbar_demux_003_src0_ready), // src0.ready
.src0_valid (cmd_xbar_demux_003_src0_valid), // .valid
.src0_data (cmd_xbar_demux_003_src0_data), // .data
.src0_channel (cmd_xbar_demux_003_src0_channel), // .channel
.src0_startofpacket (cmd_xbar_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_xbar_demux_003_src0_endofpacket) // .endofpacket
);
 
nios2_sdram_cmd_xbar_mux_008 cmd_xbar_mux_008 (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (cmd_xbar_mux_008_src_ready), // src.ready
.src_valid (cmd_xbar_mux_008_src_valid), // .valid
.src_data (cmd_xbar_mux_008_src_data), // .data
.src_channel (cmd_xbar_mux_008_src_channel), // .channel
.src_startofpacket (cmd_xbar_mux_008_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_xbar_mux_008_src_endofpacket), // .endofpacket
.sink0_ready (cmd_xbar_demux_002_src0_ready), // sink0.ready
.sink0_valid (cmd_xbar_demux_002_src0_valid), // .valid
.sink0_channel (cmd_xbar_demux_002_src0_channel), // .channel
.sink0_data (cmd_xbar_demux_002_src0_data), // .data
.sink0_startofpacket (cmd_xbar_demux_002_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_xbar_demux_002_src0_endofpacket), // .endofpacket
.sink1_ready (cmd_xbar_demux_003_src0_ready), // sink1.ready
.sink1_valid (cmd_xbar_demux_003_src0_valid), // .valid
.sink1_channel (cmd_xbar_demux_003_src0_channel), // .channel
.sink1_data (cmd_xbar_demux_003_src0_data), // .data
.sink1_startofpacket (cmd_xbar_demux_003_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_xbar_demux_003_src0_endofpacket) // .endofpacket
);
 
nios2_sdram_rsp_xbar_demux_008 rsp_xbar_demux_008 (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_008_src_ready), // sink.ready
.sink_channel (id_router_008_src_channel), // .channel
.sink_data (id_router_008_src_data), // .data
.sink_startofpacket (id_router_008_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_008_src_endofpacket), // .endofpacket
.sink_valid (id_router_008_src_valid), // .valid
.src0_ready (rsp_xbar_demux_008_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_008_src0_valid), // .valid
.src0_data (rsp_xbar_demux_008_src0_data), // .data
.src0_channel (rsp_xbar_demux_008_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_008_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_008_src0_endofpacket), // .endofpacket
.src1_ready (rsp_xbar_demux_008_src1_ready), // src1.ready
.src1_valid (rsp_xbar_demux_008_src1_valid), // .valid
.src1_data (rsp_xbar_demux_008_src1_data), // .data
.src1_channel (rsp_xbar_demux_008_src1_channel), // .channel
.src1_startofpacket (rsp_xbar_demux_008_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_xbar_demux_008_src1_endofpacket) // .endofpacket
);
 
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (61),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (70),
.IN_PKT_BYTE_CNT_L (68),
.IN_PKT_TRANS_COMPRESSED_READ (62),
.IN_PKT_BURSTWRAP_H (73),
.IN_PKT_BURSTWRAP_L (71),
.IN_PKT_BURST_SIZE_H (76),
.IN_PKT_BURST_SIZE_L (74),
.IN_PKT_RESPONSE_STATUS_H (98),
.IN_PKT_RESPONSE_STATUS_L (97),
.IN_PKT_TRANS_EXCLUSIVE (67),
.IN_PKT_BURST_TYPE_H (78),
.IN_PKT_BURST_TYPE_L (77),
.IN_ST_DATA_W (99),
.OUT_PKT_ADDR_H (43),
.OUT_PKT_ADDR_L (18),
.OUT_PKT_DATA_H (15),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (17),
.OUT_PKT_BYTEEN_L (16),
.OUT_PKT_BYTE_CNT_H (52),
.OUT_PKT_BYTE_CNT_L (50),
.OUT_PKT_TRANS_COMPRESSED_READ (44),
.OUT_PKT_BURST_SIZE_H (58),
.OUT_PKT_BURST_SIZE_L (56),
.OUT_PKT_RESPONSE_STATUS_H (80),
.OUT_PKT_RESPONSE_STATUS_L (79),
.OUT_PKT_TRANS_EXCLUSIVE (49),
.OUT_PKT_BURST_TYPE_H (60),
.OUT_PKT_BURST_TYPE_L (59),
.OUT_ST_DATA_W (81),
.ST_CHANNEL_W (8),
.OPTIMIZE_FOR_RSP (0)
) width_adapter (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_valid (cmd_xbar_mux_001_src_valid), // sink.valid
.in_channel (cmd_xbar_mux_001_src_channel), // .channel
.in_startofpacket (cmd_xbar_mux_001_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_xbar_mux_001_src_endofpacket), // .endofpacket
.in_ready (cmd_xbar_mux_001_src_ready), // .ready
.in_data (cmd_xbar_mux_001_src_data), // .data
.out_endofpacket (width_adapter_src_endofpacket), // src.endofpacket
.out_data (width_adapter_src_data), // .data
.out_channel (width_adapter_src_channel), // .channel
.out_valid (width_adapter_src_valid), // .valid
.out_ready (width_adapter_src_ready), // .ready
.out_startofpacket (width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
 
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (43),
.IN_PKT_ADDR_L (18),
.IN_PKT_DATA_H (15),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (17),
.IN_PKT_BYTEEN_L (16),
.IN_PKT_BYTE_CNT_H (52),
.IN_PKT_BYTE_CNT_L (50),
.IN_PKT_TRANS_COMPRESSED_READ (44),
.IN_PKT_BURSTWRAP_H (55),
.IN_PKT_BURSTWRAP_L (53),
.IN_PKT_BURST_SIZE_H (58),
.IN_PKT_BURST_SIZE_L (56),
.IN_PKT_RESPONSE_STATUS_H (80),
.IN_PKT_RESPONSE_STATUS_L (79),
.IN_PKT_TRANS_EXCLUSIVE (49),
.IN_PKT_BURST_TYPE_H (60),
.IN_PKT_BURST_TYPE_L (59),
.IN_ST_DATA_W (81),
.OUT_PKT_ADDR_H (61),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (70),
.OUT_PKT_BYTE_CNT_L (68),
.OUT_PKT_TRANS_COMPRESSED_READ (62),
.OUT_PKT_BURST_SIZE_H (76),
.OUT_PKT_BURST_SIZE_L (74),
.OUT_PKT_RESPONSE_STATUS_H (98),
.OUT_PKT_RESPONSE_STATUS_L (97),
.OUT_PKT_TRANS_EXCLUSIVE (67),
.OUT_PKT_BURST_TYPE_H (78),
.OUT_PKT_BURST_TYPE_L (77),
.OUT_ST_DATA_W (99),
.ST_CHANNEL_W (8),
.OPTIMIZE_FOR_RSP (1)
) width_adapter_001 (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_valid (id_router_001_src_valid), // sink.valid
.in_channel (id_router_001_src_channel), // .channel
.in_startofpacket (id_router_001_src_startofpacket), // .startofpacket
.in_endofpacket (id_router_001_src_endofpacket), // .endofpacket
.in_ready (id_router_001_src_ready), // .ready
.in_data (id_router_001_src_data), // .data
.out_endofpacket (width_adapter_001_src_endofpacket), // src.endofpacket
.out_data (width_adapter_001_src_data), // .data
.out_channel (width_adapter_001_src_channel), // .channel
.out_valid (width_adapter_001_src_valid), // .valid
.out_ready (width_adapter_001_src_ready), // .ready
.out_startofpacket (width_adapter_001_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
 
nios2_sdram_irq_mapper irq_mapper (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq
.receiver1_irq (irq_mapper_receiver1_irq), // receiver1.irq
.receiver2_irq (irq_mapper_receiver2_irq), // receiver2.irq
.receiver3_irq (irq_mapper_receiver3_irq), // receiver3.irq
.sender_irq (nios2_qsys_1_d_irq_irq) // sender.irq
);
 
endmodule
/funbase_ip_library/trunk/Altera/ip.hwp.cpu/nios_ii_sdram/2.0/hdl/nios2_sdram/synthesis/nios2_sdram.qip
0,0 → 1,172
set_global_assignment -entity "nios2_sdram" -library "nios2_sdram" -name IP_TOOL_NAME "qsys"
set_global_assignment -entity "nios2_sdram" -library "nios2_sdram" -name IP_TOOL_VERSION "12.1"
set_global_assignment -entity "nios2_sdram" -library "nios2_sdram" -name IP_TOOL_ENV "qsys"
set_global_assignment -library "nios2_sdram" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../nios2_sdram.sopcinfo"]
set_instance_assignment -entity "nios2_sdram" -library "nios2_sdram" -name SLD_INFO "QSYS_NAME nios2_sdram HAS_SOPCINFO 1 GENERATION_ID 1370947932"
set_global_assignment -library "nios2_sdram" -name MISC_FILE [file join $::quartus(qip_path) "../../nios2_sdram.cmp"]
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
set_global_assignment -library "nios2_sdram" -name MISC_FILE [file join $::quartus(qip_path) "../../nios2_sdram.qsys"]
 
set_global_assignment -library "nios2_sdram" -name VERILOG_FILE [file join $::quartus(qip_path) "nios2_sdram.v"]
set_global_assignment -library "nios2_sdram" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/nios2_sdram_irq_mapper.sv"]
set_global_assignment -library "nios2_sdram" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_width_adapter.sv"]
set_global_assignment -library "nios2_sdram" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_burst_uncompressor.sv"]
set_global_assignment -library "nios2_sdram" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_address_alignment.sv"]
set_global_assignment -library "nios2_sdram" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/nios2_sdram_rsp_xbar_demux_008.sv"]
set_global_assignment -library "nios2_sdram" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_arbitrator.sv"]
set_global_assignment -library "nios2_sdram" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/nios2_sdram_cmd_xbar_mux_008.sv"]
set_global_assignment -library "nios2_sdram" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/nios2_sdram_cmd_xbar_demux_002.sv"]
set_global_assignment -library "nios2_sdram" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/nios2_sdram_rsp_xbar_mux_001.sv"]
set_global_assignment -library "nios2_sdram" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/nios2_sdram_rsp_xbar_mux.sv"]
set_global_assignment -library "nios2_sdram" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/nios2_sdram_rsp_xbar_demux_002.sv"]
set_global_assignment -library "nios2_sdram" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/nios2_sdram_rsp_xbar_demux.sv"]
set_global_assignment -library "nios2_sdram" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/nios2_sdram_cmd_xbar_mux.sv"]
set_global_assignment -library "nios2_sdram" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/nios2_sdram_cmd_xbar_demux_001.sv"]
set_global_assignment -library "nios2_sdram" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/nios2_sdram_cmd_xbar_demux.sv"]
set_global_assignment -library "nios2_sdram" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_reset_controller.v"]
set_global_assignment -library "nios2_sdram" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_reset_synchronizer.v"]
set_global_assignment -library "nios2_sdram" -name SDC_FILE [file join $::quartus(qip_path) "submodules/altera_reset_controller.sdc"]
set_global_assignment -library "nios2_sdram" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_burst_adapter.sv"]
set_global_assignment -library "nios2_sdram" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_traffic_limiter.sv"]
set_global_assignment -library "nios2_sdram" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_avalon_st_pipeline_base.v"]
set_global_assignment -library "nios2_sdram" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/nios2_sdram_id_router_008.sv"]
set_global_assignment -library "nios2_sdram" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/nios2_sdram_addr_router_002.sv"]
set_global_assignment -library "nios2_sdram" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/nios2_sdram_id_router_002.sv"]
set_global_assignment -library "nios2_sdram" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/nios2_sdram_id_router_001.sv"]
set_global_assignment -library "nios2_sdram" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/nios2_sdram_id_router.sv"]
set_global_assignment -library "nios2_sdram" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/nios2_sdram_addr_router_001.sv"]
set_global_assignment -library "nios2_sdram" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/nios2_sdram_addr_router.sv"]
set_global_assignment -library "nios2_sdram" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_avalon_sc_fifo.v"]
set_global_assignment -library "nios2_sdram" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_slave_agent.sv"]
set_global_assignment -library "nios2_sdram" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_master_agent.sv"]
set_global_assignment -library "nios2_sdram" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_slave_translator.sv"]
set_global_assignment -library "nios2_sdram" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_master_translator.sv"]
set_global_assignment -library "nios2_sdram" -name VHDL_FILE [file join $::quartus(qip_path) "submodules/hpd_tx_control.vhd"]
set_global_assignment -library "nios2_sdram" -name VHDL_FILE [file join $::quartus(qip_path) "submodules/hpd_rx_packet.vhd"]
set_global_assignment -library "nios2_sdram" -name VHDL_FILE [file join $::quartus(qip_path) "submodules/hpd_rx_stream.vhd"]
set_global_assignment -library "nios2_sdram" -name VHDL_FILE [file join $::quartus(qip_path) "submodules/hpd_rx_and_conf.vhd"]
set_global_assignment -library "nios2_sdram" -name VHDL_FILE [file join $::quartus(qip_path) "submodules/hibi_pe_dma.vhd"]
set_global_assignment -library "nios2_sdram" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/nios2_sdram_sdram_0.v"]
set_global_assignment -library "nios2_sdram" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/nios2_sdram_timer_0.v"]
set_global_assignment -library "nios2_sdram" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/nios2_sdram_sysid_qsys_1.v"]
set_global_assignment -library "nios2_sdram" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/nios2_sdram_jtag_uart_1.v"]
set_global_assignment -library "nios2_sdram" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/nios2_sdram_jtag_uart_1_input_mutex.dat"]
set_global_assignment -library "nios2_sdram" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/nios2_sdram_jtag_uart_1_input_stream.dat"]
set_global_assignment -library "nios2_sdram" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/nios2_sdram_jtag_uart_1_output_stream.dat"]
set_global_assignment -library "nios2_sdram" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/nios2_sdram_onchip_memory2_1.hex"]
set_global_assignment -library "nios2_sdram" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/nios2_sdram_onchip_memory2_1.v"]
set_global_assignment -library "nios2_sdram" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/nios2_sdram_nios2_qsys_1.ocp"]
set_global_assignment -library "nios2_sdram" -name SDC_FILE [file join $::quartus(qip_path) "submodules/nios2_sdram_nios2_qsys_1.sdc"]
set_global_assignment -library "nios2_sdram" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/nios2_sdram_nios2_qsys_1.v"]
set_global_assignment -library "nios2_sdram" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/nios2_sdram_nios2_qsys_1_bht_ram.mif"]
set_global_assignment -library "nios2_sdram" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/nios2_sdram_nios2_qsys_1_dc_tag_ram.mif"]
set_global_assignment -library "nios2_sdram" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/nios2_sdram_nios2_qsys_1_ic_tag_ram.mif"]
set_global_assignment -library "nios2_sdram" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/nios2_sdram_nios2_qsys_1_jtag_debug_module_sysclk.v"]
set_global_assignment -library "nios2_sdram" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/nios2_sdram_nios2_qsys_1_jtag_debug_module_tck.v"]
set_global_assignment -library "nios2_sdram" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/nios2_sdram_nios2_qsys_1_jtag_debug_module_wrapper.v"]
set_global_assignment -library "nios2_sdram" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/nios2_sdram_nios2_qsys_1_mult_cell.v"]
set_global_assignment -library "nios2_sdram" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/nios2_sdram_nios2_qsys_1_ociram_default_contents.mif"]
set_global_assignment -library "nios2_sdram" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/nios2_sdram_nios2_qsys_1_oci_test_bench.v"]
set_global_assignment -library "nios2_sdram" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/nios2_sdram_nios2_qsys_1_rf_ram_a.mif"]
set_global_assignment -library "nios2_sdram" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/nios2_sdram_nios2_qsys_1_rf_ram_b.mif"]
set_global_assignment -library "nios2_sdram" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/nios2_sdram_nios2_qsys_1_test_bench.v"]
 
set_global_assignment -entity "nios2_sdram_irq_mapper" -library "nios2_sdram" -name IP_TOOL_NAME "altera_irq_mapper"
set_global_assignment -entity "nios2_sdram_irq_mapper" -library "nios2_sdram" -name IP_TOOL_VERSION "12.1"
set_global_assignment -entity "nios2_sdram_irq_mapper" -library "nios2_sdram" -name IP_TOOL_ENV "qsys"
set_global_assignment -entity "altera_merlin_width_adapter" -library "nios2_sdram" -name IP_TOOL_NAME "altera_merlin_width_adapter"
set_global_assignment -entity "altera_merlin_width_adapter" -library "nios2_sdram" -name IP_TOOL_VERSION "12.1"
set_global_assignment -entity "altera_merlin_width_adapter" -library "nios2_sdram" -name IP_TOOL_ENV "qsys"
set_global_assignment -entity "nios2_sdram_rsp_xbar_demux_008" -library "nios2_sdram" -name IP_TOOL_NAME "altera_merlin_demultiplexer"
set_global_assignment -entity "nios2_sdram_rsp_xbar_demux_008" -library "nios2_sdram" -name IP_TOOL_VERSION "12.1"
set_global_assignment -entity "nios2_sdram_rsp_xbar_demux_008" -library "nios2_sdram" -name IP_TOOL_ENV "qsys"
set_global_assignment -entity "nios2_sdram_cmd_xbar_mux_008" -library "nios2_sdram" -name IP_TOOL_NAME "altera_merlin_multiplexer"
set_global_assignment -entity "nios2_sdram_cmd_xbar_mux_008" -library "nios2_sdram" -name IP_TOOL_VERSION "12.1"
set_global_assignment -entity "nios2_sdram_cmd_xbar_mux_008" -library "nios2_sdram" -name IP_TOOL_ENV "qsys"
set_global_assignment -entity "nios2_sdram_cmd_xbar_demux_002" -library "nios2_sdram" -name IP_TOOL_NAME "altera_merlin_demultiplexer"
set_global_assignment -entity "nios2_sdram_cmd_xbar_demux_002" -library "nios2_sdram" -name IP_TOOL_VERSION "12.1"
set_global_assignment -entity "nios2_sdram_cmd_xbar_demux_002" -library "nios2_sdram" -name IP_TOOL_ENV "qsys"
set_global_assignment -entity "nios2_sdram_rsp_xbar_mux_001" -library "nios2_sdram" -name IP_TOOL_NAME "altera_merlin_multiplexer"
set_global_assignment -entity "nios2_sdram_rsp_xbar_mux_001" -library "nios2_sdram" -name IP_TOOL_VERSION "12.1"
set_global_assignment -entity "nios2_sdram_rsp_xbar_mux_001" -library "nios2_sdram" -name IP_TOOL_ENV "qsys"
set_global_assignment -entity "nios2_sdram_rsp_xbar_mux" -library "nios2_sdram" -name IP_TOOL_NAME "altera_merlin_multiplexer"
set_global_assignment -entity "nios2_sdram_rsp_xbar_mux" -library "nios2_sdram" -name IP_TOOL_VERSION "12.1"
set_global_assignment -entity "nios2_sdram_rsp_xbar_mux" -library "nios2_sdram" -name IP_TOOL_ENV "qsys"
set_global_assignment -entity "nios2_sdram_rsp_xbar_demux_002" -library "nios2_sdram" -name IP_TOOL_NAME "altera_merlin_demultiplexer"
set_global_assignment -entity "nios2_sdram_rsp_xbar_demux_002" -library "nios2_sdram" -name IP_TOOL_VERSION "12.1"
set_global_assignment -entity "nios2_sdram_rsp_xbar_demux_002" -library "nios2_sdram" -name IP_TOOL_ENV "qsys"
set_global_assignment -entity "nios2_sdram_rsp_xbar_demux" -library "nios2_sdram" -name IP_TOOL_NAME "altera_merlin_demultiplexer"
set_global_assignment -entity "nios2_sdram_rsp_xbar_demux" -library "nios2_sdram" -name IP_TOOL_VERSION "12.1"
set_global_assignment -entity "nios2_sdram_rsp_xbar_demux" -library "nios2_sdram" -name IP_TOOL_ENV "qsys"
set_global_assignment -entity "nios2_sdram_cmd_xbar_mux" -library "nios2_sdram" -name IP_TOOL_NAME "altera_merlin_multiplexer"
set_global_assignment -entity "nios2_sdram_cmd_xbar_mux" -library "nios2_sdram" -name IP_TOOL_VERSION "12.1"
set_global_assignment -entity "nios2_sdram_cmd_xbar_mux" -library "nios2_sdram" -name IP_TOOL_ENV "qsys"
set_global_assignment -entity "nios2_sdram_cmd_xbar_demux_001" -library "nios2_sdram" -name IP_TOOL_NAME "altera_merlin_demultiplexer"
set_global_assignment -entity "nios2_sdram_cmd_xbar_demux_001" -library "nios2_sdram" -name IP_TOOL_VERSION "12.1"
set_global_assignment -entity "nios2_sdram_cmd_xbar_demux_001" -library "nios2_sdram" -name IP_TOOL_ENV "qsys"
set_global_assignment -entity "nios2_sdram_cmd_xbar_demux" -library "nios2_sdram" -name IP_TOOL_NAME "altera_merlin_demultiplexer"
set_global_assignment -entity "nios2_sdram_cmd_xbar_demux" -library "nios2_sdram" -name IP_TOOL_VERSION "12.1"
set_global_assignment -entity "nios2_sdram_cmd_xbar_demux" -library "nios2_sdram" -name IP_TOOL_ENV "qsys"
set_global_assignment -entity "altera_reset_controller" -library "nios2_sdram" -name IP_TOOL_NAME "altera_reset_controller"
set_global_assignment -entity "altera_reset_controller" -library "nios2_sdram" -name IP_TOOL_VERSION "12.1"
set_global_assignment -entity "altera_reset_controller" -library "nios2_sdram" -name IP_TOOL_ENV "qsys"
set_global_assignment -entity "altera_merlin_burst_adapter" -library "nios2_sdram" -name IP_TOOL_NAME "altera_merlin_burst_adapter"
set_global_assignment -entity "altera_merlin_burst_adapter" -library "nios2_sdram" -name IP_TOOL_VERSION "12.1"
set_global_assignment -entity "altera_merlin_burst_adapter" -library "nios2_sdram" -name IP_TOOL_ENV "qsys"
set_global_assignment -entity "altera_merlin_traffic_limiter" -library "nios2_sdram" -name IP_TOOL_NAME "altera_merlin_traffic_limiter"
set_global_assignment -entity "altera_merlin_traffic_limiter" -library "nios2_sdram" -name IP_TOOL_VERSION "12.1"
set_global_assignment -entity "altera_merlin_traffic_limiter" -library "nios2_sdram" -name IP_TOOL_ENV "qsys"
set_global_assignment -entity "nios2_sdram_id_router_008" -library "nios2_sdram" -name IP_TOOL_NAME "altera_merlin_router"
set_global_assignment -entity "nios2_sdram_id_router_008" -library "nios2_sdram" -name IP_TOOL_VERSION "12.1"
set_global_assignment -entity "nios2_sdram_id_router_008" -library "nios2_sdram" -name IP_TOOL_ENV "qsys"
set_global_assignment -entity "nios2_sdram_addr_router_002" -library "nios2_sdram" -name IP_TOOL_NAME "altera_merlin_router"
set_global_assignment -entity "nios2_sdram_addr_router_002" -library "nios2_sdram" -name IP_TOOL_VERSION "12.1"
set_global_assignment -entity "nios2_sdram_addr_router_002" -library "nios2_sdram" -name IP_TOOL_ENV "qsys"
set_global_assignment -entity "nios2_sdram_id_router_002" -library "nios2_sdram" -name IP_TOOL_NAME "altera_merlin_router"
set_global_assignment -entity "nios2_sdram_id_router_002" -library "nios2_sdram" -name IP_TOOL_VERSION "12.1"
set_global_assignment -entity "nios2_sdram_id_router_002" -library "nios2_sdram" -name IP_TOOL_ENV "qsys"
set_global_assignment -entity "nios2_sdram_id_router_001" -library "nios2_sdram" -name IP_TOOL_NAME "altera_merlin_router"
set_global_assignment -entity "nios2_sdram_id_router_001" -library "nios2_sdram" -name IP_TOOL_VERSION "12.1"
set_global_assignment -entity "nios2_sdram_id_router_001" -library "nios2_sdram" -name IP_TOOL_ENV "qsys"
set_global_assignment -entity "nios2_sdram_id_router" -library "nios2_sdram" -name IP_TOOL_NAME "altera_merlin_router"
set_global_assignment -entity "nios2_sdram_id_router" -library "nios2_sdram" -name IP_TOOL_VERSION "12.1"
set_global_assignment -entity "nios2_sdram_id_router" -library "nios2_sdram" -name IP_TOOL_ENV "qsys"
set_global_assignment -entity "nios2_sdram_addr_router_001" -library "nios2_sdram" -name IP_TOOL_NAME "altera_merlin_router"
set_global_assignment -entity "nios2_sdram_addr_router_001" -library "nios2_sdram" -name IP_TOOL_VERSION "12.1"
set_global_assignment -entity "nios2_sdram_addr_router_001" -library "nios2_sdram" -name IP_TOOL_ENV "qsys"
set_global_assignment -entity "nios2_sdram_addr_router" -library "nios2_sdram" -name IP_TOOL_NAME "altera_merlin_router"
set_global_assignment -entity "nios2_sdram_addr_router" -library "nios2_sdram" -name IP_TOOL_VERSION "12.1"
set_global_assignment -entity "nios2_sdram_addr_router" -library "nios2_sdram" -name IP_TOOL_ENV "qsys"
set_global_assignment -entity "altera_avalon_sc_fifo" -library "nios2_sdram" -name IP_TOOL_NAME "altera_avalon_sc_fifo"
set_global_assignment -entity "altera_avalon_sc_fifo" -library "nios2_sdram" -name IP_TOOL_VERSION "12.1"
set_global_assignment -entity "altera_avalon_sc_fifo" -library "nios2_sdram" -name IP_TOOL_ENV "qsys"
set_global_assignment -entity "altera_merlin_slave_agent" -library "nios2_sdram" -name IP_TOOL_NAME "altera_merlin_slave_agent"
set_global_assignment -entity "altera_merlin_slave_agent" -library "nios2_sdram" -name IP_TOOL_VERSION "12.1"
set_global_assignment -entity "altera_merlin_slave_agent" -library "nios2_sdram" -name IP_TOOL_ENV "qsys"
set_global_assignment -entity "altera_merlin_master_agent" -library "nios2_sdram" -name IP_TOOL_NAME "altera_merlin_master_agent"
set_global_assignment -entity "altera_merlin_master_agent" -library "nios2_sdram" -name IP_TOOL_VERSION "12.1"
set_global_assignment -entity "altera_merlin_master_agent" -library "nios2_sdram" -name IP_TOOL_ENV "qsys"
set_global_assignment -entity "altera_merlin_slave_translator" -library "nios2_sdram" -name IP_TOOL_NAME "altera_merlin_slave_translator"
set_global_assignment -entity "altera_merlin_slave_translator" -library "nios2_sdram" -name IP_TOOL_VERSION "12.1"
set_global_assignment -entity "altera_merlin_slave_translator" -library "nios2_sdram" -name IP_TOOL_ENV "qsys"
set_global_assignment -entity "altera_merlin_master_translator" -library "nios2_sdram" -name IP_TOOL_NAME "altera_merlin_master_translator"
set_global_assignment -entity "altera_merlin_master_translator" -library "nios2_sdram" -name IP_TOOL_VERSION "12.1"
set_global_assignment -entity "altera_merlin_master_translator" -library "nios2_sdram" -name IP_TOOL_ENV "qsys"
set_global_assignment -entity "nios2_sdram_sdram_0" -library "nios2_sdram" -name IP_TOOL_NAME "altera_avalon_new_sdram_controller"
set_global_assignment -entity "nios2_sdram_sdram_0" -library "nios2_sdram" -name IP_TOOL_VERSION "12.1"
set_global_assignment -entity "nios2_sdram_sdram_0" -library "nios2_sdram" -name IP_TOOL_ENV "qsys"
set_global_assignment -entity "nios2_sdram_timer_0" -library "nios2_sdram" -name IP_TOOL_NAME "altera_avalon_timer"
set_global_assignment -entity "nios2_sdram_timer_0" -library "nios2_sdram" -name IP_TOOL_VERSION "12.1"
set_global_assignment -entity "nios2_sdram_timer_0" -library "nios2_sdram" -name IP_TOOL_ENV "qsys"
set_global_assignment -entity "nios2_sdram_sysid_qsys_1" -library "nios2_sdram" -name IP_TOOL_NAME "altera_avalon_sysid_qsys"
set_global_assignment -entity "nios2_sdram_sysid_qsys_1" -library "nios2_sdram" -name IP_TOOL_VERSION "12.1"
set_global_assignment -entity "nios2_sdram_sysid_qsys_1" -library "nios2_sdram" -name IP_TOOL_ENV "qsys"
set_global_assignment -entity "nios2_sdram_jtag_uart_1" -library "nios2_sdram" -name IP_TOOL_NAME "altera_avalon_jtag_uart"
set_global_assignment -entity "nios2_sdram_jtag_uart_1" -library "nios2_sdram" -name IP_TOOL_VERSION "12.1"
set_global_assignment -entity "nios2_sdram_jtag_uart_1" -library "nios2_sdram" -name IP_TOOL_ENV "qsys"
set_global_assignment -entity "nios2_sdram_onchip_memory2_1" -library "nios2_sdram" -name IP_TOOL_NAME "altera_avalon_onchip_memory2"
set_global_assignment -entity "nios2_sdram_onchip_memory2_1" -library "nios2_sdram" -name IP_TOOL_VERSION "12.1"
set_global_assignment -entity "nios2_sdram_onchip_memory2_1" -library "nios2_sdram" -name IP_TOOL_ENV "qsys"
set_global_assignment -entity "nios2_sdram_nios2_qsys_1" -library "nios2_sdram" -name IP_TOOL_NAME "altera_nios2_qsys"
set_global_assignment -entity "nios2_sdram_nios2_qsys_1" -library "nios2_sdram" -name IP_TOOL_VERSION "12.1"
set_global_assignment -entity "nios2_sdram_nios2_qsys_1" -library "nios2_sdram" -name IP_TOOL_ENV "qsys"
/funbase_ip_library/trunk/Altera/ip.hwp.cpu/nios_ii_sdram/2.0/hdl/components.ipx
0,0 → 1,13
<?xml version="1.0" encoding="UTF-8"?>
<library>
<!-- date: 2013.06.06.13:16:04 -->
<!-- generated by: ip-make-ipx -->
<!-- -->
<!-- 2 in ../../../../../TUT/ip.hwp.communication/hibi_pe_dma/ip/ -->
<!-- -->
<path
path="D:/user/matilail/teaching/TKT-3541/2013_fall/TUT/ip.hwp.communication/hibi_pe_dma/ip/**/*" />
<path
path="D:/user/matilail/quartus_projects/altera_ips/altera_up_avalon_sram/**/*" />
</library>
/funbase_ip_library/trunk/Altera/ip.hwp.cpu/nios_ii_sdram/2.0/hdl/nios2_sdram.qsys
0,0 → 1,629
<?xml version="1.0" encoding="UTF-8"?>
<system name="$${FILENAME}">
<component
name="$${FILENAME}"
displayName="$${FILENAME}"
version="1.0"
description=""
tags=""
categories="System" />
<parameter name="bonusData"><![CDATA[bonusData
{
element $${FILENAME}
{
}
element jtag_uart_1.avalon_jtag_slave
{
datum baseAddress
{
value = "12872";
type = "String";
}
}
element hibi_pe_dma_0.avalon_slave_0
{
datum _lockedAddress
{
value = "0";
type = "boolean";
}
datum baseAddress
{
value = "12288";
type = "String";
}
}
element clk_0
{
datum _sortIndex
{
value = "0";
type = "int";
}
}
element sysid_qsys_1.control_slave
{
datum baseAddress
{
value = "12864";
type = "String";
}
}
element hibi_pe_dma_0
{
datum _sortIndex
{
value = "8";
type = "int";
}
}
element nios2_qsys_1.jtag_debug_module
{
datum baseAddress
{
value = "10240";
type = "String";
}
}
element jtag_uart_1
{
datum _sortIndex
{
value = "7";
type = "int";
}
}
element nios2_qsys_1
{
datum _sortIndex
{
value = "1";
type = "int";
}
}
element onchip_memory2_1
{
datum _sortIndex
{
value = "2";
type = "int";
}
}
element sdram_0.s1
{
datum baseAddress
{
value = "33554432";
type = "String";
}
}
element onchip_memory2_1.s1
{
datum _lockedAddress
{
value = "1";
type = "boolean";
}
datum baseAddress
{
value = "0";
type = "String";
}
}
element timer_0.s1
{
datum baseAddress
{
value = "12800";
type = "String";
}
}
element timer_1.s1
{
datum baseAddress
{
value = "12832";
type = "String";
}
}
element onchip_memory2_1.s2
{
datum _lockedAddress
{
value = "1";
type = "boolean";
}
datum baseAddress
{
value = "0";
type = "String";
}
}
element sdram_0
{
datum _sortIndex
{
value = "3";
type = "int";
}
datum megawizard_uipreferences
{
value = "{output_language=VERILOG, output_directory=D:\\user\\matilail\\repos\\opencores_lib\\Altera\\ip.hwp.cpu\\nios_ii_sdram\\1.2\\hdl}";
type = "String";
}
}
element sysid_qsys_1
{
datum _sortIndex
{
value = "4";
type = "int";
}
}
element timer_0
{
datum _sortIndex
{
value = "5";
type = "int";
}
}
element timer_1
{
datum _sortIndex
{
value = "6";
type = "int";
}
}
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
<parameter name="device" value="EP2C35F672C6" />
<parameter name="deviceFamily" value="Cyclone II" />
<parameter name="deviceSpeedGrade" value="6" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="1" />
<parameter name="timeStamp" value="1370947901242" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface name="clk" internal="clk_0.clk_in" type="clock" dir="end" />
<interface name="reset" internal="clk_0.clk_in_reset" type="reset" dir="end" />
<interface name="sdram_0" internal="sdram_0.wire" type="conduit" dir="end" />
<interface
name="hibi_pe_dma"
internal="hibi_pe_dma_0.conduit_end"
type="conduit"
dir="end" />
<module kind="clock_source" version="12.1" enabled="1" name="clk_0">
<parameter name="clockFrequency" value="50000000" />
<parameter name="clockFrequencyKnown" value="true" />
<parameter name="inputClockFrequency" value="0" />
<parameter name="resetSynchronousEdges" value="NONE" />
</module>
<module
kind="altera_nios2_qsys"
version="12.1"
enabled="1"
name="nios2_qsys_1">
<parameter name="setting_showUnpublishedSettings" value="false" />
<parameter name="setting_showInternalSettings" value="false" />
<parameter name="setting_preciseSlaveAccessErrorException" value="false" />
<parameter name="setting_preciseIllegalMemAccessException" value="false" />
<parameter name="setting_preciseDivisionErrorException" value="false" />
<parameter name="setting_performanceCounter" value="false" />
<parameter name="setting_illegalMemAccessDetection" value="false" />
<parameter name="setting_illegalInstructionsTrap" value="false" />
<parameter name="setting_fullWaveformSignals" value="false" />
<parameter name="setting_extraExceptionInfo" value="false" />
<parameter name="setting_exportPCB" value="false" />
<parameter name="setting_debugSimGen" value="false" />
<parameter name="setting_clearXBitsLDNonBypass" value="true" />
<parameter name="setting_bit31BypassDCache" value="true" />
<parameter name="setting_bigEndian" value="false" />
<parameter name="setting_export_large_RAMs" value="false" />
<parameter name="setting_asic_enabled" value="false" />
<parameter name="setting_asic_synopsys_translate_on_off" value="false" />
<parameter name="setting_oci_export_jtag_signals" value="false" />
<parameter name="setting_bhtIndexPcOnly" value="false" />
<parameter name="setting_avalonDebugPortPresent" value="false" />
<parameter name="setting_alwaysEncrypt" value="true" />
<parameter name="setting_allowFullAddressRange" value="false" />
<parameter name="setting_activateTrace" value="true" />
<parameter name="setting_activateTestEndChecker" value="false" />
<parameter name="setting_activateMonitors" value="true" />
<parameter name="setting_activateModelChecker" value="false" />
<parameter name="setting_HDLSimCachesCleared" value="true" />
<parameter name="setting_HBreakTest" value="false" />
<parameter name="muldiv_divider" value="false" />
<parameter name="mpu_useLimit" value="false" />
<parameter name="mpu_enabled" value="false" />
<parameter name="mmu_enabled" value="false" />
<parameter name="mmu_autoAssignTlbPtrSz" value="true" />
<parameter name="manuallyAssignCpuID" value="true" />
<parameter name="debug_triggerArming" value="true" />
<parameter name="debug_embeddedPLL" value="true" />
<parameter name="debug_debugReqSignals" value="false" />
<parameter name="debug_assignJtagInstanceID" value="false" />
<parameter name="dcache_omitDataMaster" value="false" />
<parameter name="cpuReset" value="false" />
<parameter name="is_hardcopy_compatible" value="false" />
<parameter name="setting_shadowRegisterSets" value="0" />
<parameter name="mpu_numOfInstRegion" value="8" />
<parameter name="mpu_numOfDataRegion" value="8" />
<parameter name="mmu_TLBMissExcOffset" value="0" />
<parameter name="debug_jtagInstanceID" value="0" />
<parameter name="resetOffset" value="0" />
<parameter name="exceptionOffset" value="32" />
<parameter name="cpuID" value="16777216" />
<parameter name="cpuID_stored" value="16777216" />
<parameter name="breakOffset" value="32" />
<parameter name="userDefinedSettings" value="" />
<parameter name="resetSlave" value="sdram_0.s1" />
<parameter name="mmu_TLBMissExcSlave" value="" />
<parameter name="exceptionSlave" value="sdram_0.s1" />
<parameter name="breakSlave">nios2_qsys_1.jtag_debug_module</parameter>
<parameter name="setting_perfCounterWidth" value="32" />
<parameter name="setting_interruptControllerType" value="Internal" />
<parameter name="setting_branchPredictionType" value="Automatic" />
<parameter name="setting_bhtPtrSz" value="8" />
<parameter name="muldiv_multiplierType" value="EmbeddedMulFast" />
<parameter name="mpu_minInstRegionSize" value="12" />
<parameter name="mpu_minDataRegionSize" value="12" />
<parameter name="mmu_uitlbNumEntries" value="4" />
<parameter name="mmu_udtlbNumEntries" value="6" />
<parameter name="mmu_tlbPtrSz" value="7" />
<parameter name="mmu_tlbNumWays" value="16" />
<parameter name="mmu_processIDNumBits" value="8" />
<parameter name="impl" value="Fast" />
<parameter name="icache_size" value="4096" />
<parameter name="icache_ramBlockType" value="Automatic" />
<parameter name="icache_numTCIM" value="0" />
<parameter name="icache_burstType" value="None" />
<parameter name="dcache_bursts" value="false" />
<parameter name="debug_level" value="Level1" />
<parameter name="debug_OCIOnchipTrace" value="_128" />
<parameter name="dcache_size" value="2048" />
<parameter name="dcache_ramBlockType" value="Automatic" />
<parameter name="dcache_numTCDM" value="0" />
<parameter name="dcache_lineSize" value="32" />
<parameter name="instAddrWidth" value="26" />
<parameter name="dataAddrWidth" value="26" />
<parameter name="tightlyCoupledDataMaster0AddrWidth" value="1" />
<parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
<parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
<parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
<parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="1" />
<parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
<parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
<parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
<parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='nios2_qsys_1.jtag_debug_module' start='0x2800' end='0x3000' /><slave name='sdram_0.s1' start='0x2000000' end='0x2800000' /></address-map>]]></parameter>
<parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='onchip_memory2_1.s1' start='0x0' end='0x2000' /><slave name='nios2_qsys_1.jtag_debug_module' start='0x2800' end='0x3000' /><slave name='hibi_pe_dma_0.avalon_slave_0' start='0x3000' end='0x3200' /><slave name='timer_0.s1' start='0x3200' end='0x3220' /><slave name='timer_1.s1' start='0x3220' end='0x3240' /><slave name='sysid_qsys_1.control_slave' start='0x3240' end='0x3248' /><slave name='jtag_uart_1.avalon_jtag_slave' start='0x3248' end='0x3250' /><slave name='sdram_0.s1' start='0x2000000' end='0x2800000' /></address-map>]]></parameter>
<parameter name="clockFrequency" value="50000000" />
<parameter name="deviceFamilyName" value="Cyclone II" />
<parameter name="internalIrqMaskSystemInfo" value="15" />
<parameter name="customInstSlavesSystemInfo" value="&lt;info/&gt;" />
<parameter name="deviceFeaturesSystemInfo">NOT_LISTED 0 INSTALLED 1 IS_DEFAULT_FAMILY 0 ADDRESS_STALL 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 0 HAS_ADVANCED_IO_TIMING_SUPPORT 0 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 1 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 0 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 1 HAS_JITTER_SUPPORT 0 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 1 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 0 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 0 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 1 HAS_SPLIT_IO_SUPPORT 0 HAS_SPLIT_LC_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 0 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 1 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 IS_CONFIG_ROM 0 IS_HARDCOPY_FAMILY 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 1 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 0 MRAM_MEMORY 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 1 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 0 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 1 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 1 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 0 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 0 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 0 USE_ADVANCED_IO_TIMING_BY_DEFAULT 0 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 0 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 0 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0</parameter>
<parameter name="tightlyCoupledDataMaster0MapParam" value="" />
<parameter name="tightlyCoupledDataMaster1MapParam" value="" />
<parameter name="tightlyCoupledDataMaster2MapParam" value="" />
<parameter name="tightlyCoupledDataMaster3MapParam" value="" />
<parameter name="tightlyCoupledInstructionMaster0MapParam" value="" />
<parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
<parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
<parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
</module>
<module
kind="altera_avalon_onchip_memory2"
version="12.1"
enabled="1"
name="onchip_memory2_1">
<parameter name="allowInSystemMemoryContentEditor" value="false" />
<parameter name="autoInitializationFileName">$${FILENAME}_onchip_memory2_1</parameter>
<parameter name="blockType" value="AUTO" />
<parameter name="dataWidth" value="32" />
<parameter name="deviceFamily" value="Cyclone II" />
<parameter name="dualPort" value="true" />
<parameter name="initMemContent" value="true" />
<parameter name="initializationFileName" value="onchip_memory2_1" />
<parameter name="instanceID" value="NONE" />
<parameter name="memorySize" value="8192" />
<parameter name="readDuringWriteMode" value="DONT_CARE" />
<parameter name="simAllowMRAMContentsFile" value="false" />
<parameter name="simMemInitOnlyFilename" value="0" />
<parameter name="singleClockOperation" value="false" />
<parameter name="slave1Latency" value="1" />
<parameter name="slave2Latency" value="1" />
<parameter name="useNonDefaultInitFile" value="false" />
<parameter name="useShallowMemBlocks" value="false" />
<parameter name="writable" value="true" />
</module>
<module
kind="altera_avalon_jtag_uart"
version="12.1"
enabled="1"
name="jtag_uart_1">
<parameter name="allowMultipleConnections" value="false" />
<parameter name="avalonSpec" value="2.0" />
<parameter name="hubInstanceID" value="0" />
<parameter name="readBufferDepth" value="64" />
<parameter name="readIRQThreshold" value="8" />
<parameter name="simInputCharacterStream" value="" />
<parameter name="simInteractiveOptions">INTERACTIVE_ASCII_OUTPUT</parameter>
<parameter name="useRegistersForReadBuffer" value="false" />
<parameter name="useRegistersForWriteBuffer" value="false" />
<parameter name="useRelativePathForSimFile" value="false" />
<parameter name="writeBufferDepth" value="64" />
<parameter name="writeIRQThreshold" value="8" />
</module>
<module
kind="altera_avalon_sysid_qsys"
version="12.1"
enabled="1"
name="sysid_qsys_1">
<parameter name="id" value="16777216" />
<parameter name="timestamp" value="0" />
<parameter name="AUTO_CLK_CLOCK_RATE" value="50000000" />
<parameter name="AUTO_DEVICE_FAMILY" value="Cyclone II" />
</module>
<module kind="altera_avalon_timer" version="12.1" enabled="1" name="timer_0">
<parameter name="alwaysRun" value="false" />
<parameter name="counterSize" value="32" />
<parameter name="fixedPeriod" value="false" />
<parameter name="period" value="1" />
<parameter name="periodUnits" value="MSEC" />
<parameter name="resetOutput" value="false" />
<parameter name="snapshot" value="true" />
<parameter name="systemFrequency" value="50000000" />
<parameter name="timeoutPulseOutput" value="false" />
<parameter name="timerPreset" value="CUSTOM" />
</module>
<module kind="altera_avalon_timer" version="12.1" enabled="1" name="timer_1">
<parameter name="alwaysRun" value="false" />
<parameter name="counterSize" value="32" />
<parameter name="fixedPeriod" value="false" />
<parameter name="period" value="1" />
<parameter name="periodUnits" value="MSEC" />
<parameter name="resetOutput" value="false" />
<parameter name="snapshot" value="true" />
<parameter name="systemFrequency" value="50000000" />
<parameter name="timeoutPulseOutput" value="false" />
<parameter name="timerPreset" value="CUSTOM" />
</module>
<module
kind="altera_avalon_new_sdram_controller"
version="12.1"
enabled="1"
name="sdram_0">
<parameter name="TAC" value="5.5" />
<parameter name="TMRD" value="3" />
<parameter name="TRCD" value="20.0" />
<parameter name="TRFC" value="70.0" />
<parameter name="TRP" value="20.0" />
<parameter name="TWR" value="14.0" />
<parameter name="casLatency" value="3" />
<parameter name="clockRate" value="50000000" />
<parameter name="columnWidth" value="8" />
<parameter name="dataWidth" value="16" />
<parameter name="generateSimulationModel" value="false" />
<parameter name="initNOPDelay" value="0.0" />
<parameter name="initRefreshCommands" value="2" />
<parameter name="masteredTristateBridgeSlave" value="" />
<parameter name="model" value="custom" />
<parameter name="numberOfBanks" value="4" />
<parameter name="numberOfChipSelects" value="1" />
<parameter name="pinsSharedViaTriState" value="false" />
<parameter name="powerUpDelay" value="100.0" />
<parameter name="refreshPeriod" value="15.625" />
<parameter name="registerDataIn" value="true" />
<parameter name="rowWidth" value="12" />
</module>
<module kind="hibi_pe_dma" version="1.0" enabled="1" name="hibi_pe_dma_0">
<parameter name="data_width_g" value="32" />
<parameter name="addr_width_g" value="32" />
<parameter name="words_width_g" value="16" />
<parameter name="n_stream_chans_g" value="2" />
<parameter name="n_packet_chans_g" value="2" />
<parameter name="n_chans_bits_g" value="3" />
<parameter name="hibi_addr_cmp_lo_g" value="0" />
<parameter name="hibi_addr_cmp_hi_g" value="31" />
<parameter name="AUTO_CLOCK_CLOCK_RATE" value="50000000" />
</module>
<connection
kind="avalon"
version="12.1"
start="nios2_qsys_1.instruction_master"
end="nios2_qsys_1.jtag_debug_module">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x2800" />
</connection>
<connection
kind="avalon"
version="12.1"
start="nios2_qsys_1.data_master"
end="nios2_qsys_1.jtag_debug_module">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x2800" />
</connection>
<connection kind="clock" version="12.1" start="clk_0.clk" end="sdram_0.clk" />
<connection
kind="reset"
version="12.1"
start="clk_0.clk_reset"
end="sdram_0.reset" />
<connection kind="clock" version="12.1" start="clk_0.clk" end="timer_1.clk" />
<connection
kind="reset"
version="12.1"
start="clk_0.clk_reset"
end="timer_1.reset" />
<connection kind="clock" version="12.1" start="clk_0.clk" end="timer_0.clk" />
<connection
kind="reset"
version="12.1"
start="clk_0.clk_reset"
end="timer_0.reset" />
<connection kind="clock" version="12.1" start="clk_0.clk" end="sysid_qsys_1.clk" />
<connection
kind="reset"
version="12.1"
start="clk_0.clk_reset"
end="sysid_qsys_1.reset" />
<connection kind="clock" version="12.1" start="clk_0.clk" end="jtag_uart_1.clk" />
<connection
kind="reset"
version="12.1"
start="clk_0.clk_reset"
end="jtag_uart_1.reset" />
<connection
kind="clock"
version="12.1"
start="clk_0.clk"
end="onchip_memory2_1.clk2" />
<connection
kind="reset"
version="12.1"
start="clk_0.clk_reset"
end="onchip_memory2_1.reset2" />
<connection
kind="clock"
version="12.1"
start="clk_0.clk"
end="onchip_memory2_1.clk1" />
<connection
kind="reset"
version="12.1"
start="clk_0.clk_reset"
end="onchip_memory2_1.reset1" />
<connection kind="clock" version="12.1" start="clk_0.clk" end="nios2_qsys_1.clk" />
<connection
kind="reset"
version="12.1"
start="clk_0.clk_reset"
end="nios2_qsys_1.reset_n" />
<connection
kind="interrupt"
version="12.1"
start="nios2_qsys_1.d_irq"
end="jtag_uart_1.irq">
<parameter name="irqNumber" value="0" />
</connection>
<connection
kind="interrupt"
version="12.1"
start="nios2_qsys_1.d_irq"
end="timer_1.irq">
<parameter name="irqNumber" value="1" />
</connection>
<connection
kind="interrupt"
version="12.1"
start="nios2_qsys_1.d_irq"
end="timer_0.irq">
<parameter name="irqNumber" value="2" />
</connection>
<connection
kind="avalon"
version="12.1"
start="nios2_qsys_1.data_master"
end="jtag_uart_1.avalon_jtag_slave">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x3248" />
</connection>
<connection
kind="avalon"
version="12.1"
start="nios2_qsys_1.data_master"
end="timer_1.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x3220" />
</connection>
<connection
kind="avalon"
version="12.1"
start="nios2_qsys_1.data_master"
end="timer_0.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x3200" />
</connection>
<connection
kind="avalon"
version="12.1"
start="nios2_qsys_1.data_master"
end="sysid_qsys_1.control_slave">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x3240" />
</connection>
<connection
kind="avalon"
version="12.1"
start="nios2_qsys_1.data_master"
end="sdram_0.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x02000000" />
</connection>
<connection
kind="avalon"
version="12.1"
start="nios2_qsys_1.instruction_master"
end="sdram_0.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x02000000" />
</connection>
<connection
kind="avalon"
version="12.1"
start="nios2_qsys_1.data_master"
end="onchip_memory2_1.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0000" />
</connection>
<connection
kind="clock"
version="12.1"
start="clk_0.clk"
end="hibi_pe_dma_0.clock" />
<connection
kind="reset"
version="12.1"
start="clk_0.clk_reset"
end="hibi_pe_dma_0.clock_sink_reset" />
<connection
kind="avalon"
version="12.1"
start="nios2_qsys_1.data_master"
end="hibi_pe_dma_0.avalon_slave_0">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x3000" />
</connection>
<connection
kind="interrupt"
version="12.1"
start="nios2_qsys_1.d_irq"
end="hibi_pe_dma_0.interrupt_sender">
<parameter name="irqNumber" value="3" />
</connection>
<connection
kind="avalon"
version="12.1"
start="hibi_pe_dma_0.avalon_master"
end="onchip_memory2_1.s2">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0000" />
</connection>
<connection
kind="avalon"
version="12.1"
start="hibi_pe_dma_0.avalon_master_1"
end="onchip_memory2_1.s2">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0000" />
</connection>
</system>
/funbase_ip_library/trunk/Altera/ip.hwp.cpu/nios_ii_sdram/2.0/nios_ii_sdram.2.0.xml
0,0 → 1,859
<?xml version="1.0" encoding="UTF-8"?>
<!-- Created by Kactus2 - Open source IP-Xact toolset -->
<!-- http://sourceforge.net/projects/kactus2/ -->
<!-- Date: 03.09.2012 -->
<!-- Time: 13:49:00 -->
<spirit:component xmlns:kactus2="http://funbase.cs.tut.fi/" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5 http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.5/index.xsd">
<spirit:vendor>Altera</spirit:vendor>
<spirit:library>ip.hwp.cpu</spirit:library>
<spirit:name>nios_ii_sdram</spirit:name>
<spirit:version>2.0</spirit:version>
<spirit:description>Nios2 SDRAM subsystem.</spirit:description>
<spirit:busInterfaces>
<spirit:busInterface>
<spirit:name>clk</spirit:name>
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="clock.busdef" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="clock.absDef" spirit:version="1.0"/>
<spirit:slave/>
<spirit:connectionRequired>false</spirit:connectionRequired>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CLK</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>clk_clk</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:bitsInLau>8</spirit:bitsInLau>
<spirit:endianness>little</spirit:endianness>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>hibi_master</spirit:name>
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.communication" spirit:name="hibi_ip_r4.busdef" spirit:version="3.0"/>
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.communication" spirit:name="hibi_ip_r4.absdef" spirit:version="3.0"/>
<spirit:master/>
<spirit:connectionRequired>false</spirit:connectionRequired>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AV</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>hibi_pe_dma_av_out</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>WE</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>hibi_pe_dma_we_out</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RE</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>hibi_pe_dma_re_out</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>DATA</spirit:name>
<spirit:vector>
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>hibi_pe_dma_data_out</spirit:name>
<spirit:vector>
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>COMM</spirit:name>
<spirit:vector>
<spirit:left>4</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>hibi_pe_dma_comm_out</spirit:name>
<spirit:vector>
<spirit:left>4</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:bitsInLau>8</spirit:bitsInLau>
<spirit:endianness>little</spirit:endianness>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>rst_n</spirit:name>
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="reset.busdef" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="reset.absDef" spirit:version="1.0"/>
<spirit:slave/>
<spirit:connectionRequired>false</spirit:connectionRequired>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RESETn</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>reset_reset_n</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:bitsInLau>8</spirit:bitsInLau>
<spirit:endianness>little</spirit:endianness>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>sdram_if</spirit:name>
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.storage" spirit:name="sdram_io.busdef" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.storage" spirit:name="sdram_io.absDef" spirit:version="1.0"/>
<spirit:master/>
<spirit:connectionRequired>false</spirit:connectionRequired>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>sdram_address_out</spirit:name>
<spirit:vector>
<spirit:left>11</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>sdram_0_addr</spirit:name>
<spirit:vector>
<spirit:left>11</spirit:left>
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<spirit:name>sdram_0_ba</spirit:name>
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<spirit:logicalPort>
<spirit:name>sdram_cas_n_out</spirit:name>
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<spirit:name>sdram_0_cas_n</spirit:name>
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</spirit:physicalPort>
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<spirit:portMap>
<spirit:logicalPort>
<spirit:name>sdram_cke_out</spirit:name>
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<spirit:physicalPort>
<spirit:name>sdram_0_cke</spirit:name>
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<spirit:logicalPort>
<spirit:name>sdram_cs_n_out</spirit:name>
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<spirit:physicalPort>
<spirit:name>sdram_0_cs_n</spirit:name>
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</spirit:physicalPort>
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<spirit:portMap>
<spirit:logicalPort>
<spirit:name>sdram_data_inout</spirit:name>
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<spirit:physicalPort>
<spirit:name>sdram_0_dq</spirit:name>
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</spirit:physicalPort>
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<spirit:portMap>
<spirit:logicalPort>
<spirit:name>sdram_dqm_out</spirit:name>
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<spirit:physicalPort>
<spirit:name>sdram_0_dqm</spirit:name>
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<spirit:portMap>
<spirit:logicalPort>
<spirit:name>sdram_ras_n_out</spirit:name>
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</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>sdram_0_ras_n</spirit:name>
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</spirit:physicalPort>
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<spirit:portMap>
<spirit:logicalPort>
<spirit:name>sdram_we_n_out</spirit:name>
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<spirit:name>sdram_0_we_n</spirit:name>
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</spirit:physicalPort>
</spirit:portMap>
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<spirit:bitsInLau>8</spirit:bitsInLau>
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<spirit:busInterface>
<spirit:name>hibi_slave</spirit:name>
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<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.communication" spirit:name="hibi_ip_r4.absdef" spirit:version="3.0"/>
<spirit:slave>
<spirit:memoryMapRef spirit:memoryMapRef="hibi_mem_map"/>
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<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AV</spirit:name>
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</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>hibi_pe_dma_av_in</spirit:name>
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<spirit:logicalPort>
<spirit:name>COMM</spirit:name>
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</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>hibi_pe_dma_comm_in</spirit:name>
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</spirit:physicalPort>
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<spirit:portMap>
<spirit:logicalPort>
<spirit:name>DATA</spirit:name>
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</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>hibi_pe_dma_data_in</spirit:name>
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<spirit:left>31</spirit:left>
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</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>EMPTY</spirit:name>
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</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>hibi_pe_dma_empty_in</spirit:name>
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<spirit:left>0</spirit:left>
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</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>FULL</spirit:name>
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</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>hibi_pe_dma_full_in</spirit:name>
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<spirit:left>0</spirit:left>
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</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:bitsInLau>8</spirit:bitsInLau>
<spirit:endianness>little</spirit:endianness>
</spirit:busInterface>
</spirit:busInterfaces>
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<spirit:addressSpace>
<spirit:name>avalon_addr_space</spirit:name>
<spirit:description>Avalon address space. (local)</spirit:description>
<spirit:range>4G</spirit:range>
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<spirit:segments>
<spirit:segment>
<spirit:name>.bss</spirit:name>
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<spirit:range>512</spirit:range>
</spirit:segment>
<spirit:segment>
<spirit:name>.exceptions</spirit:name>
<spirit:addressOffset>0x00800200</spirit:addressOffset>
<spirit:range>512</spirit:range>
</spirit:segment>
<spirit:segment>
<spirit:name>.entry</spirit:name>
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</spirit:segment>
<spirit:segment>
<spirit:name>.stack</spirit:name>
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<spirit:segment>
<spirit:name>.heap</spirit:name>
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<spirit:range>512</spirit:range>
</spirit:segment>
<spirit:segment>
<spirit:name>.rwdata</spirit:name>
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</spirit:segment>
<spirit:segment>
<spirit:name>.text</spirit:name>
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<spirit:range>512</spirit:range>
</spirit:segment>
<spirit:segment>
<spirit:name>.rodata</spirit:name>
<spirit:addressOffset>0x00800E00</spirit:addressOffset>
<spirit:range>512</spirit:range>
</spirit:segment>
<spirit:segment>
<spirit:name>Shared_memory</spirit:name>
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<spirit:range>4K</spirit:range>
</spirit:segment>
</spirit:segments>
<spirit:addressUnitBits>8</spirit:addressUnitBits>
<spirit:localMemoryMap>
<spirit:name>avalon_addr_space</spirit:name>
<spirit:addressBlock>
<spirit:name>HIBI_PE_DMA</spirit:name>
<spirit:baseAddress>0x0</spirit:baseAddress>
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<spirit:usage>reserved</spirit:usage>
</spirit:addressBlock>
<spirit:addressBlock>
<spirit:name>JTAG_UART</spirit:name>
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<spirit:usage>reserved</spirit:usage>
</spirit:addressBlock>
<spirit:addressBlock>
<spirit:name>TIMER</spirit:name>
<spirit:baseAddress>0x8</spirit:baseAddress>
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<spirit:usage>reserved</spirit:usage>
</spirit:addressBlock>
<spirit:addressBlock>
<spirit:name>SYSID</spirit:name>
<spirit:baseAddress>0x10</spirit:baseAddress>
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<spirit:usage>reserved</spirit:usage>
</spirit:addressBlock>
<spirit:addressBlock>
<spirit:name>ONCHIP_MEM</spirit:name>
<spirit:baseAddress>0x1000000</spirit:baseAddress>
<spirit:range>4K</spirit:range>
<spirit:width>32</spirit:width>
<spirit:usage>memory</spirit:usage>
</spirit:addressBlock>
<spirit:addressBlock>
<spirit:name>SDRAM</spirit:name>
<spirit:baseAddress>0x00800000</spirit:baseAddress>
<spirit:range>8M</spirit:range>
<spirit:width>32</spirit:width>
<spirit:usage>memory</spirit:usage>
</spirit:addressBlock>
</spirit:localMemoryMap>
</spirit:addressSpace>
<spirit:addressSpace>
<spirit:name>hibi_addr_space</spirit:name>
<spirit:description>HIBI address space</spirit:description>
<spirit:range>4G</spirit:range>
<spirit:width>32</spirit:width>
<spirit:addressUnitBits>8</spirit:addressUnitBits>
</spirit:addressSpace>
</spirit:addressSpaces>
<spirit:memoryMaps>
<spirit:memoryMap>
<spirit:name>hibi_mem_map</spirit:name>
<spirit:addressBlock>
<spirit:name>hibi_addr_block</spirit:name>
<spirit:baseAddress>0x0</spirit:baseAddress>
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<spirit:width>32</spirit:width>
<spirit:usage>register</spirit:usage>
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<spirit:addressUnitBits>32</spirit:addressUnitBits>
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</spirit:memoryMaps>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>rtl</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:modelName>nios2_sdram</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>hdlSources</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>clk_clk</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
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<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>hibi_pe_dma_av_in</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>hibi_pe_dma_av_out</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>hibi_pe_dma_comm_in</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left>4</spirit:left>
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</spirit:vector>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>hibi_pe_dma_comm_out</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>4</spirit:left>
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</spirit:vector>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>hibi_pe_dma_data_in</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>hibi_pe_dma_data_out</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>hibi_pe_dma_empty_in</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>hibi_pe_dma_full_in</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>hibi_pe_dma_re_out</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>hibi_pe_dma_we_out</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>reset_reset_n</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>in</spirit:direction>
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<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>sdram_0_addr</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>11</spirit:left>
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</spirit:vector>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>sdram_0_ba</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>1</spirit:left>
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</spirit:vector>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>sdram_0_cas_n</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>sdram_0_cke</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>sdram_0_cs_n</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>sdram_0_dq</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>inout</spirit:direction>
<spirit:vector>
<spirit:left>15</spirit:left>
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</spirit:vector>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>sdram_0_dqm</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>1</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>sdram_0_ras_n</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
<spirit:port>
<spirit:name>sdram_0_we_n</spirit:name>
<spirit:wire spirit:allLogicalDirectionsAllowed="false">
<spirit:direction>out</spirit:direction>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
</spirit:ports>
</spirit:model>
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>hdlSources</spirit:name>
<spirit:description>HDL sources</spirit:description>
<spirit:file>
<spirit:name>hdl/nios2_sdram/synthesis/nios2_sdram.qip</spirit:name>
<spirit:userFileType>quartusIPFile</spirit:userFileType>
<spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
</spirit:file>
<spirit:file>
<spirit:name>hdl/nios2_sdram.sopcinfo</spirit:name>
<spirit:userFileType>sopcInfoFile</spirit:userFileType>
<spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
</spirit:file>
<spirit:file>
<spirit:name>hdl/nios2_sdram.qsys</spirit:name>
<spirit:userFileType>qsysFile</spirit:userFileType>
<spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>nios2_sbt_files</spirit:name>
<spirit:description>NIOS II Software Build tools files</spirit:description>
<spirit:file>
<spirit:name>hdl/components.ipx</spirit:name>
<spirit:userFileType>alteraIpxFile</spirit:userFileType>
<spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
<spirit:description>Altera's IPX file to include user component and drivers</spirit:description>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>ucosii_bsp</spirit:name>
<spirit:description>Contains the BSP files generated by Altera tools for SW view ucosii</spirit:description>
<spirit:group>generatedFiles</spirit:group>
<spirit:file>
<spirit:name>BSP/.force_relink</spirit:name>
<spirit:fileType>unknown</spirit:fileType>
<spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
</spirit:file>
<spirit:file>
<spirit:name>BSP/alt_sys_init.c</spirit:name>
<spirit:fileType>cSource</spirit:fileType>
<spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
</spirit:file>
<spirit:file>
<spirit:name>BSP/linker.h</spirit:name>
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<spirit:fileType>cppSource</spirit:fileType>
<spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
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<spirit:file>
<spirit:name>BSP/linker.x</spirit:name>
<spirit:userFileType>linkerFile</spirit:userFileType>
<spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
</spirit:file>
<spirit:file>
<spirit:name>BSP/Makefile</spirit:name>
<spirit:userFileType>makefile</spirit:userFileType>
<spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
</spirit:file>
<spirit:file>
<spirit:name>BSP/mem_init.mk</spirit:name>
<spirit:userFileType>mkFile</spirit:userFileType>
<spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
</spirit:file>
<spirit:file>
<spirit:name>BSP/memory.gdb</spirit:name>
<spirit:userFileType>gdbFile</spirit:userFileType>
<spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
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<spirit:file>
<spirit:name>BSP/public.mk</spirit:name>
<spirit:userFileType>mkFile</spirit:userFileType>
<spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
</spirit:file>
<spirit:file>
<spirit:name>BSP/settings.bsp</spirit:name>
<spirit:userFileType>BSPFile</spirit:userFileType>
<spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
</spirit:file>
<spirit:file>
<spirit:name>BSP/summary.html</spirit:name>
<spirit:userFileType>htmlFile</spirit:userFileType>
<spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
</spirit:file>
<spirit:file>
<spirit:name>BSP/system.h</spirit:name>
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<spirit:fileType>cppSource</spirit:fileType>
<spirit:isIncludeFile spirit:externalDeclarations="false">false</spirit:isIncludeFile>
</spirit:file>
<spirit:dependency>BSP/drivers</spirit:dependency>
<spirit:dependency>BSP/HAL</spirit:dependency>
<spirit:dependency>BSP/UCOSII</spirit:dependency>
</spirit:fileSet>
</spirit:fileSets>
<spirit:cpus>
<spirit:cpu>
<spirit:name>nios2_qsys_1</spirit:name>
<spirit:addressSpaceRef spirit:addressSpaceRef="avalon_addr_space"/>
</spirit:cpu>
</spirit:cpus>
<spirit:vendorExtensions>
<kactus2:extensions>
<kactus2:kts_attributes>
<kactus2:kts_productHier>IP</kactus2:kts_productHier>
<kactus2:kts_implementation>HW</kactus2:kts_implementation>
<kactus2:kts_firmness>Fixed</kactus2:kts_firmness>
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<kactus2:swViews>
<kactus2:swView>
<spirit:name>ucosii</spirit:name>
<spirit:hierarchyRef spirit:vendor="TUT" spirit:library="ip.swp.stack" spirit:name="mcapi_nios.swdesigncfg" spirit:version="1.0"/>
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<spirit:command>nios2-elf-gcc</spirit:command>
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<kactus2:BSPBuildCommand>
<kactus2:fileType>sopcInfoFile</kactus2:fileType>
<spirit:command>nios2-bsp ucosii</spirit:command>
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</kactus2:BSPBuildCommand>
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</kactus2:swViews>
</kactus2:extensions>
</spirit:vendorExtensions>
</spirit:component>

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