URL
https://opencores.org/ocsvn/8051/8051/trunk
Subversion Repositories 8051
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 177 to Rev 178
- ↔ Reverse comparison
Rev 177 → Rev 178
/trunk/rtl/verilog/oc8051_alu.v
46,6 → 46,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.17 2003/06/09 16:51:16 simont |
// fix bug in DA operation. |
// |
// Revision 1.16 2003/06/03 17:15:06 simont |
// sub_result output added. |
// |
226,7 → 229,7
des2 = mulsrc2; |
desOv = mulOv; |
desCy = 1'b0; |
desAc = 1'bx; |
desAc = 1'b0; |
enable_mul = 1'b1; |
enable_div = 1'b0; |
end |
236,7 → 239,7
des1 = src1; |
des2 = divsrc2; |
desOv = divOv; |
desAc = 1'bx; |
desAc = 1'b0; |
desCy = 1'b0; |
enable_mul = 1'b0; |
enable_div = 1'b1; |
266,8 → 269,8
des1 = ~src1; |
des2 = 8'h00; |
desCy = !srcCy; |
desAc = 1'bx; |
desOv = 1'bx; |
desAc = 1'b0; |
desOv = 1'b0; |
enable_mul = 1'b0; |
enable_div = 1'b0; |
end |
278,8 → 281,8
des1 = src1 & src2; |
des2 = 8'h00; |
desCy = srcCy & bit_in; |
desAc = 1'bx; |
desOv = 1'bx; |
desAc = 1'b0; |
desOv = 1'b0; |
enable_mul = 1'b0; |
enable_div = 1'b0; |
end |
290,8 → 293,8
des1 = src1 ^ src2; |
des2 = 8'h00; |
desCy = srcCy ^ bit_in; |
desAc = 1'bx; |
desOv = 1'bx; |
desAc = 1'b0; |
desOv = 1'b0; |
enable_mul = 1'b0; |
enable_div = 1'b0; |
end |
302,8 → 305,8
des1 = src1 | src2; |
des2 = 8'h00; |
desCy = srcCy | bit_in; |
desAc = 1'bx; |
desOv = 1'bx; |
desAc = 1'b0; |
desOv = 1'b0; |
enable_mul = 1'b0; |
enable_div = 1'b0; |
end |
314,8 → 317,8
des1 = src1 ; |
des2 = 8'h00; |
desCy = srcCy | !bit_in; |
desAc = 1'bx; |
desOv = 1'bx; |
desAc = 1'b0; |
desOv = 1'b0; |
enable_mul = 1'b0; |
enable_div = 1'b0; |
end |