URL
https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk
Subversion Repositories sdhc-sc-core
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 177 to Rev 178
- ↔ Reverse comparison
Rev 177 → Rev 178
/sdhc-sc-core/trunk/src/grpSd/unitTbdSd/Files.tcl
60,6 → 60,7
Sd TestWbMaster {Rtl} |
Rs232 Rs232Tx {Rtl} |
Components Ics307Configurator {Rtl} |
Sd SdClkDomain {Rtl} |
Sd SdTop {Rtl} |
Sd TbdSd {Rtl}} |
|
/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/wave.do
1,40 → 1,15
onerror {resume} |
quietly WaveActivateNextPane {} 0 |
add wave -noupdate -format Logic /Testbed/CardInterface/Cmd |
add wave -noupdate -format Logic /Testbed/CardInterface/SClk |
add wave -noupdate -format Literal -radix hexadecimal /Testbed/CardInterface/Data |
add wave -noupdate -format Logic /Testbed/IWbBus/ERR_I |
add wave -noupdate -format Logic /Testbed/IWbBus/RTY_I |
add wave -noupdate -format Logic /Testbed/IWbBus/CLK_I |
add wave -noupdate -format Logic /Testbed/IWbBus/RST_I |
add wave -noupdate -format Logic /Testbed/IWbBus/ACK_I |
add wave -noupdate -format Literal -radix hexadecimal /Testbed/IWbBus/DAT_I |
add wave -noupdate -format Logic /Testbed/IWbBus/CYC_O |
add wave -noupdate -format Literal -radix hexadecimal /Testbed/IWbBus/ADR_O |
add wave -noupdate -format Literal -radix hexadecimal /Testbed/IWbBus/DAT_O |
add wave -noupdate -format Logic /Testbed/IWbBus/STB_O |
add wave -noupdate -format Logic /Testbed/IWbBus/WE_O |
add wave -noupdate -format Logic /Testbed/top/sddata_inst/iclk |
add wave -noupdate -format Logic /Testbed/top/sddata_inst/inresetasync |
add wave -noupdate -format Logic /Testbed/top/sddata_inst/istrobe |
add wave -noupdate -format Literal /Testbed/top/sddata_inst/isddatafromcontroller |
add wave -noupdate -format Literal /Testbed/top/sddata_inst/osddatatocontroller |
add wave -noupdate -format Literal /Testbed/top/sddata_inst/idata |
add wave -noupdate -format Literal /Testbed/top/sddata_inst/odata |
add wave -noupdate -format Literal /Testbed/top/sddata_inst/ireadwritefifo |
add wave -noupdate -format Literal /Testbed/top/sddata_inst/oreadwritefifo |
add wave -noupdate -format Literal /Testbed/top/sddata_inst/iwritereadfifo |
add wave -noupdate -format Literal /Testbed/top/sddata_inst/owritereadfifo |
add wave -noupdate -format Logic /Testbed/top/sddata_inst/odisablesdclk |
add wave -noupdate -format Literal /Testbed/top/sddata_inst/crcin |
add wave -noupdate -format Literal /Testbed/top/sddata_inst/crcout |
add wave -noupdate -format Literal /Testbed/top/sddata_inst/crcdatain |
add wave -noupdate -format Literal /Testbed/top/sddata_inst/r |
add wave -noupdate -format Literal /Testbed/top/sddata_inst/nextr |
add wave -noupdate -format Literal /Testbed/top/sddata_inst/rbitinwordc |
add wave -noupdate -format Literal /Testbed/top/sddata_inst/rwordc |
add wave -noupdate -format Literal /Testbed/top/sddata_inst/rbytec |
add wave -noupdate -format Literal /Testbed/top/sddata_inst/rbitc |
add wave -divider -noupdate CardInterface |
add wave -noupdate /Testbed/CardInterface/* |
add wave -divider -noupdate IWbBus |
add wave -noupdate /Testbed/IWbBus/* |
add wave -divider -noupdate sdcontroller_inst |
add wave -noupdate /Testbed/top/sdclkdomain_inst/sdcontroller_inst/* |
add wave -divider -noupdate sdcmd_inst |
add wave -noupdate /Testbed/top/sdclkdomain_inst/sdcmd_inst/* |
add wave -divider -noupdate sddata_inst |
add wave -noupdate /Testbed/top/sdclkdomain_inst/sddata_inst/* |
TreeUpdate [SetDefaultTree] |
WaveRestoreCursors {{Cursor 1} {2496665 ns} 0} {{Cursor 2} {6033878 ns} 0} {{Cursor 3} {18655442 ns} 0} |
configure wave -namecolwidth 150 |
/sdhc-sc-core/trunk/src/grpCrc/unitCrc/src/tbCrc-bhv-ea.vhdl
40,7 → 40,7
end entity tbCrc; |
|
architecture bhv of tbCrc is |
signal Clk, nResetAsync : std_ulogic := '0'; |
signal Clk, ResetSync : std_ulogic := '1'; |
signal CRC_7 : std_ulogic_vector(6 downto 0); |
signal CRC_16 : std_ulogic_vector(15 downto 0); |
signal DataToCrc_7, DataToCrc_16 : std_ulogic; |
99,7 → 99,7
begin |
|
Clk <= not Clk after 10 ns when EndOfSim = false else '0'; |
nResetAsync <= '1' after 100 ns; |
ResetSync <= '0' after 100 ns; |
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generate_and_test7 : process is |
procedure Test7( |
120,7 → 120,7
|
variable data : std_ulogic_vector(0 to (512*8)-1) := (others => '1'); |
begin |
wait until (nResetAsync = '1'); |
wait until (ResetSync = '0'); |
|
Test7("0100000000000000000000000000000000000000","1001010"); |
Test7("01000000000000000000000000000000000000001001010","0000000"); |
144,7 → 144,7
|
duv7: entity work.crc |
port map (iClk => Clk, |
inResetAsync => nResetAsync, |
iRstSync => ResetSync, |
iDataIn => CRCDataIn_7, |
iStrobe => '1', |
iClear => CRCClear_7, |
155,7 → 155,7
duv16: entity work.crc |
generic map (gPolynom => crc16) |
port map (iClk => Clk, |
inResetAsync => nResetAsync, |
iRstSync => ResetSync, |
iDataIn => CRCDataIn_16, |
iStrobe => '1', |
iClear => CRCClear_16, |
/sdhc-sc-core/trunk/src/grpStrobesClocks/unitTimeoutGenerator/src/tbTimeoutGenerator-Bhv-ea.vhdl
48,7 → 48,7
constant cResetTime : time := 4 * cClkPeriod; |
constant cTimeoutTime : time := 10 us; |
signal Clk : std_ulogic := '1'; |
signal nResetAsync : std_ulogic := cnActivated; |
signal ResetSync : std_ulogic := cActivated; |
signal Done : std_ulogic := cInactivated; |
signal Timeout : std_ulogic; |
signal Enable : std_ulogic := cInactivated; |
55,8 → 55,8
|
begin |
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Clk <= not Clk after (cClkPeriod / 2) when Done = cInactivated else '0'; |
nResetAsync <= cnInactivated after cResetTime; |
Clk <= not Clk after (cClkPeriod / 2) when Done = cInactivated else '0'; |
ResetSync <= cInactivated after cResetTime; |
|
DUT : entity work.TimeoutGenerator |
generic map ( |
64,11 → 64,11
gTimeoutTime => cTimeoutTime |
) |
port map ( |
iClk => Clk, |
inResetAsync => nResetAsync, |
iDisable => cInactivated, |
iEnable => Enable, |
oTimeout => Timeout |
iClk => Clk, |
iRstSync => ResetSync, |
iDisable => cInactivated, |
iEnable => Enable, |
oTimeout => Timeout |
); |
|
Stimuli : process |
/sdhc-sc-core/trunk/src/grpStrobesClocks/unitTimeoutGenerator/sim/wave.do
1,7 → 1,7
onerror {resume} |
quietly WaveActivateNextPane {} 0 |
add wave -noupdate -format Logic /tbtimeoutgenerator/clk |
add wave -noupdate -format Logic /tbtimeoutgenerator/nresetasync |
add wave -noupdate -format Logic /tbtimeoutgenerator/resetsync |
add wave -noupdate -format Logic /tbtimeoutgenerator/done |
add wave -noupdate -format Logic /tbtimeoutgenerator/timeout |
add wave -noupdate -format Logic /tbtimeoutgenerator/enable |
/sdhc-sc-core/trunk/Makefile
4,6 → 4,8
SYSVSIMS = grpSd/unitSdVerificationTestbench |
SYNS = grpSd/unitTbdSd |
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all: clean sim svsim syn |
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sim: |
for i in $(SIMS); do make -C src/$$i/sim; done |
|