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https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
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- This comparison shows the changes necessary to convert path
/
- from Rev 179 to Rev 180
- ↔ Reverse comparison
Rev 179 → Rev 180
/openmsp430/trunk/core/rtl/verilog/omsp_register_file.v
209,7 → 209,7
wire mclk_r2 = mclk; |
`endif |
|
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
`ifdef CPUOFF_EN |
wire [15:0] cpuoff_mask = 16'h0010; |
`else |
/openmsp430/trunk/core/rtl/verilog/omsp_sfr.v
299,7 → 299,7
// Pulse capture and synchronization |
//----------------------------------- |
`ifdef SYNC_NMI |
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
// Glitch free reset for the event capture |
reg nmi_capture_rst; |
always @(posedge mclk or posedge puc_rst) |
351,7 → 351,7
wire nmi_pnd = nmiifg & nmie; |
|
// NMI wakeup |
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
wire nmi_wkup; |
omsp_and_gate and_nmi_wkup (.y(nmi_wkup), .a(nmi_capture ^ nmi_dly), .b(nmie)); |
`else |
/openmsp430/trunk/core/rtl/verilog/omsp_clock_module.v
194,7 → 194,7
wire bcsctl1_wr = BCSCTL1[0] ? reg_hi_wr[BCSCTL1] : reg_lo_wr[BCSCTL1]; |
wire [7:0] bcsctl1_nxt = BCSCTL1[0] ? per_din[15:8] : per_din[7:0]; |
|
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
`ifdef ACLK_DIVIDER |
wire [7:0] divax_mask = 8'h30; |
`else |
225,7 → 225,7
`else |
wire [7:0] divmx_mask = 8'h00; |
`endif |
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
`ifdef SMCLK_MUX |
wire [7:0] sels_mask = 8'h08; |
`else |
263,7 → 263,7
// 5) DCO_CLK / LFXT_CLK INTERFACES (WAKEUP, ENABLE, ...) |
//============================================================================= |
|
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
wire cpuoff_and_mclk_enable; |
omsp_and_gate and_cpuoff_mclk_en (.y(cpuoff_and_mclk_enable), .a(cpuoff), .b(mclk_enable)); |
`endif |
376,7 → 376,7
// Note: unlike the original MSP430 specification, |
// we allow to switch off the LFXT even |
// if it is selected by MCLK or SMCLK. |
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
|
`ifdef OSCOFF_EN |
|
526,7 → 526,7
// Synchronize CPU_EN signal to the SMCLK domain |
//---------------------------------------------- |
// Note: the synchronizer is only required if there is a SMCLK_MUX |
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
`ifdef SMCLK_MUX |
wire cpu_en_sm_s; |
omsp_sync_cell sync_cell_cpu_sm_en ( |
625,7 → 625,7
|
// ASIC MODE |
//---------------------------- |
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
|
`ifdef ACLK_DIVIDER |
`ifdef LFXT_DOMAIN |
758,7 → 758,7
|
// ASIC MODE |
//---------------------------- |
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
`ifdef SMCLK_MUX |
|
// Synchronizers |
916,7 → 916,7
// Serial Debug Interface Clock gate |
//------------------------------------------------ |
`ifdef DBG_EN |
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
omsp_clock_gate clock_gate_dbg_clk ( |
.gclk (dbg_clk), |
.clk (mclk), |
/openmsp430/trunk/core/rtl/verilog/omsp_watchdog.v
176,7 → 176,7
parameter [7:0] WDTNMIES_MASK = 8'h00; |
`endif |
|
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
`ifdef WATCHDOG_MUX |
parameter [7:0] WDTSSEL_MASK = 8'h04; |
`else |
229,7 → 229,7
//============================================================================= |
// 5) WATCHDOG TIMER (ASIC IMPLEMENTATION) |
//============================================================================= |
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
|
// Watchdog clock source selection |
//--------------------------------- |
/openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v
132,7 → 132,7
`define WATCHDOG |
|
|
///------------------------------------------------------- |
//------------------------------------------------------- |
// Include/Exclude Non-Maskable-Interrupt support |
//------------------------------------------------------- |
`define NMI |
315,6 → 315,20
|
|
//=============================================================== |
// ASIC CLOCKING |
//=============================================================== |
|
//------------------------------------------------------- |
// When uncommented, this define will enable the ASIC |
// architectural clock gating as well as the advanced low |
// power modes support (most common). |
// Comment this out in order to get FPGA-like clocking. |
//------------------------------------------------------- |
`define ASIC_CLOCKING |
|
|
`ifdef ASIC_CLOCKING |
//=============================================================== |
// LFXT CLOCK DOMAIN |
//=============================================================== |
|
437,8 → 451,8
`define OSCOFF_EN |
|
|
|
`endif |
`endif |
|
//==========================================================================// |
//==========================================================================// |
/openmsp430/trunk/core/rtl/verilog/openMSP430_undefines.v
263,6 → 263,11
// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! ) |
//---------------------------------------------------------------------------- |
|
// ASIC/FPGA-like clocking |
`ifdef ASIC_CLOCKING |
`undef ASIC_CLOCKING |
`endif |
|
// Fine grained clock gating |
`ifdef CLOCK_GATING |
`undef CLOCK_GATING |
/openmsp430/trunk/core/sim/rtl_sim/src/wdt_watchdog.v
67,7 → 67,7
if (mem208 !== 16'h6924) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6924 (CONFIG 2) ====="); |
`else |
if (mem200 !== 16'h6920) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6920 (CONFIG 3) ====="); |
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
if (mem202 !== 16'h69f3) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x69f3 (CONFIG 3-ASIC) ====="); |
if (mem204 !== 16'h6971) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6971 (CONFIG 3-ASIC) ====="); |
if (mem206 !== 16'h69a2) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x69a2 (CONFIG 3-ASIC) ====="); |
95,7 → 95,7
if (mem208 !== 16'h6904) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6904 (CONFIG 5) ====="); |
`else |
if (mem200 !== 16'h6900) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6900 (CONFIG 6) ====="); |
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
if (mem202 !== 16'h6993) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6993 (CONFIG 6-ASIC) ====="); |
if (mem204 !== 16'h6911) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6911 (CONFIG 6-ASIC) ====="); |
if (mem206 !== 16'h6982) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6982 (CONFIG 6-ASIC) ====="); |
109,7 → 109,7
`endif |
`endif |
|
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
`ifdef WATCHDOG_MUX |
`else |
`ifdef WATCHDOG_NOMUX_ACLK |
123,7 → 123,7
//-------------------------------------------------------- |
|
@(mem250===16'h2000); |
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
if (mem200 !== 16'h000B) tb_error("====== WATCHDOG MODE /64: @0x200 != 0x000B ====="); |
`else |
if (mem200 !== 16'h000A) tb_error("====== WATCHDOG MODE /64: @0x200 != 0x000A ====="); |
136,7 → 136,7
//-------------------------------------------------------- |
|
@(mem250===16'h3000); |
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
if (mem202 !== 16'h0056) tb_error("====== WATCHDOG MODE /512: @0x202 != 0x0056 ====="); |
`else |
if (mem202 !== 16'h0055) tb_error("====== WATCHDOG MODE /512: @0x202 != 0x0055 ====="); |
149,7 → 149,7
//-------------------------------------------------------- |
|
@(mem250===16'h4000); |
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
if (mem204 !== 16'h0556) tb_error("====== WATCHDOG MODE /8192: @0x204 != 0x0556 ====="); |
`else |
if (mem204 !== 16'h0555) tb_error("====== WATCHDOG MODE /8192: @0x204 != 0x0555 ====="); |
162,7 → 162,7
//-------------------------------------------------------- |
|
@(mem250===16'h5000); |
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
if (mem206 !== 16'h1556) tb_error("====== WATCHDOG MODE /32768: @0x206 != 0x1556 ====="); |
`else |
if (mem206 !== 16'h1555) tb_error("====== WATCHDOG MODE /32768: @0x206 != 0x1555 ====="); |
/openmsp430/trunk/core/sim/rtl_sim/src/tA_clkmux.v
73,7 → 73,7
stimulus_done = 0; |
|
|
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
$display(" ==============================================="); |
$display("| SIMULATION SKIPPED |"); |
$display("| (this test is not supported in ASIC mode) |"); |
/openmsp430/trunk/core/sim/rtl_sim/src/wdt_interval.v
67,7 → 67,7
if (r8 !== 16'h6924) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6924 (CONFIG 2) ====="); |
`else |
if (r4 !== 16'h6920) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6920 (CONFIG 3) ====="); |
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
if (r5 !== 16'h69f3) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x69f3 (CONFIG 3-ASIC) ====="); |
if (r6 !== 16'h6971) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6971 (CONFIG 3-ASIC) ====="); |
if (r7 !== 16'h69a2) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x69a2 (CONFIG 3-ASIC) ====="); |
95,7 → 95,7
if (r8 !== 16'h6904) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6904 (CONFIG 5) ====="); |
`else |
if (r4 !== 16'h6900) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6900 (CONFIG 6) ====="); |
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
if (r5 !== 16'h6993) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6993 (CONFIG 6-ASIC) ====="); |
if (r6 !== 16'h6911) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6911 (CONFIG 6-ASIC) ====="); |
if (r7 !== 16'h6982) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6982 (CONFIG 6-ASIC) ====="); |
121,7 → 121,7
@(r15==16'h2000); |
if (r5 !== 16'h3401) tb_error("====== WATCHDOG INTERVAL MODE /64: R5 != 0x3401 ====="); |
if (r6 !== 16'h0000) tb_error("====== WATCHDOG INTERVAL MODE /64: R6 != 0x0000 ====="); |
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
`ifdef WATCHDOG_MUX |
if (r7 !== 16'h000E) tb_error("====== WATCHDOG INTERVAL MODE /64: R7 != 0x000E (CONFIG 1) ====="); |
`else |
145,7 → 145,7
if (r7 !== 16'h0000) tb_error("====== WATCHDOG INTERVAL MODE /64 NO IRQ: R7 != 0x0000 ====="); |
if (r8 !== 16'h0000) tb_error("====== WATCHDOG INTERVAL MODE /64 NO IRQ: R8 != 0x0000 ====="); |
|
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
`ifdef WATCHDOG_MUX |
`else |
`ifdef WATCHDOG_NOMUX_ACLK |
175,7 → 175,7
@(r15==16'h3000); |
if (r5 !== 16'h3403) tb_error("====== WATCHDOG INTERVAL MODE /512: R5 != 0x3403 ====="); |
if (r6 !== 16'h0000) tb_error("====== WATCHDOG INTERVAL MODE /512: R6 != 0x0000 ====="); |
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
if (r7 !== 16'h0068) tb_error("====== WATCHDOG INTERVAL MODE /512: R7 != 0x0068 ====="); |
`else |
if (r7 !== 16'h0066) tb_error("====== WATCHDOG INTERVAL MODE /512: R7 != 0x0066 ====="); |
190,7 → 190,7
@(r15==16'h4000); |
if (r5 !== 16'h3404) tb_error("====== WATCHDOG INTERVAL MODE /8192: R5 != 0x3404 ====="); |
if (r6 !== 16'h0000) tb_error("====== WATCHDOG INTERVAL MODE /8192: R6 != 0x0000 ====="); |
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
if (r7 !== 16'h0668) tb_error("====== WATCHDOG INTERVAL MODE /8192: R7 != 0x0668 ====="); |
`else |
if (r7 !== 16'h0667) tb_error("====== WATCHDOG INTERVAL MODE /8192: R7 != 0x0667 ====="); |
205,7 → 205,7
@(r15==16'h5000); |
if (r5 !== 16'h3405) tb_error("====== WATCHDOG INTERVAL MODE /32768: R5 != 0x3405 ====="); |
if (r6 !== 16'h0000) tb_error("====== WATCHDOG INTERVAL MODE /32768: R6 != 0x0000 ====="); |
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
if (r7 !== 16'h199B) tb_error("====== WATCHDOG INTERVAL MODE /32768: R7 != 0x199B ====="); |
`else |
if (r7 !== 16'h199A) tb_error("====== WATCHDOG INTERVAL MODE /32768: R7 != 0x199A ====="); |
/openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_smclk.v
59,7 → 59,7
repeat(5) @(posedge smclk); |
stimulus_done = 0; |
|
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
|
//-------------------------------------------------------- |
// SMCLK GENERATION - LFXT_CLK INPUT |
/openmsp430/trunk/core/sim/rtl_sim/src/wdt_wkup.v
50,7 → 50,7
smclk_cnt <= smclk_cnt+1; |
|
integer aclk_cnt; |
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
always @(negedge aclk) |
aclk_cnt <= aclk_cnt+1; |
`else |
63,7 → 63,7
inst_cnt <= inst_cnt+1; |
|
reg watchdog_clock; |
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
`ifdef WATCHDOG_MUX |
always @(posedge lfxt_clk or negedge lfxt_clk) watchdog_clock <= lfxt_clk; |
`else |
106,7 → 106,7
|
@(r15==16'h1000); |
|
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
`ifdef WATCHDOG_MUX |
`ifdef ACLK_DIVIDER |
repeat(5) @(posedge watchdog_clock); |
135,7 → 135,7
smclk_cnt = 0; |
aclk_cnt = 0; |
inst_cnt = 0; |
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
`ifdef WATCHDOG_MUX |
repeat(62) @(posedge watchdog_clock); |
jj = 2; |
/openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_lfxt.v
55,7 → 55,7
repeat(5) @(posedge mclk); |
stimulus_done = 0; |
|
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
`ifdef OSCOFF_EN |
`ifdef MCLK_MUX |
|
/openmsp430/trunk/core/sim/rtl_sim/src/clock_module.v
59,7 → 59,7
repeat(5) @(posedge mclk); |
stimulus_done = 0; |
|
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
$display(" ==============================================="); |
$display("| SIMULATION SKIPPED |"); |
$display("| (this test is not supported in ASIC mode) |"); |
/openmsp430/trunk/core/sim/rtl_sim/src/tA_compare.v
48,7 → 48,7
repeat(5) @(posedge mclk); |
stimulus_done = 0; |
|
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
$display(" ==============================================="); |
$display("| SIMULATION SKIPPED |"); |
$display("| (this test is not supported in ASIC mode) |"); |
/openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic.v
76,7 → 76,7
|
force tb_openMSP430.dut.wdt_reset = 1'b0; |
|
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
|
// MCLK GENERATION: SELECTING DCO_CLK |
//-------------------------------------------------------- |
533,7 → 533,7
bcsctl1_mask = 16'h0000; |
bcsctl2_mask = 16'h0000; |
|
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
`ifdef ACLK_DIVIDER |
bcsctl1_mask = bcsctl1_mask | 16'h0030; |
`endif |
547,7 → 547,7
`ifdef MCLK_DIVIDER |
bcsctl2_mask = bcsctl2_mask | 16'h0030; |
`endif |
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
`ifdef SMCLK_MUX |
bcsctl2_mask = bcsctl2_mask | 16'h0008; |
`endif |
/openmsp430/trunk/core/sim/rtl_sim/src/lp_modes_asic.v
99,7 → 99,7
wkup[3] = 0; |
|
|
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
|
// ACTIVE |
//-------------------------------------------------------- |
/openmsp430/trunk/core/sim/rtl_sim/src/op_modes.v
57,7 → 57,7
repeat(5) @(posedge mclk); |
stimulus_done = 0; |
|
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
$display(" ==============================================="); |
$display("| SIMULATION SKIPPED |"); |
$display("| (this test is not supported in ASIC mode) |"); |
/openmsp430/trunk/core/sim/rtl_sim/src/tA_output.v
49,7 → 49,7
repeat(5) @(posedge mclk); |
stimulus_done = 0; |
|
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
$display(" ==============================================="); |
$display("| SIMULATION SKIPPED |"); |
$display("| (this test is not supported in ASIC mode) |"); |
/openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_mclk.v
61,7 → 61,7
|
force tb_openMSP430.dut.wdt_reset = 1'b0; |
|
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
|
//-------------------------------------------------------- |
// MCLK GENERATION - LFXT_CLK INPUT |
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_onoff_asic.v
55,7 → 55,7
$display(" ==============================================="); |
`ifdef DBG_EN |
`ifdef DBG_UART |
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
test_nr = 0; |
#1 dbg_en = 0; |
repeat(30) @(posedge dco_clk); |
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_onoff.v
47,7 → 47,7
$display(" ==============================================="); |
`ifdef DBG_EN |
`ifdef DBG_I2C |
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
$display(" ==============================================="); |
$display("| SIMULATION SKIPPED |"); |
$display("| (this test is not supported in ASIC mode) |"); |
/openmsp430/trunk/core/sim/rtl_sim/src/wdt_clkmux.v
65,7 → 65,7
r5_counter = 0; |
repeat(1024) @(negedge mclk); |
if (mclk_counter !== 1024) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK - TEST 1 ====="); |
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
`ifdef WATCHDOG_MUX |
`ifdef SMCLK_DIVIDER |
if (r5_counter !== 7) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK - TEST 2 ====="); |
102,7 → 102,7
r5_counter = 0; |
repeat(7815) @(negedge mclk); |
if (mclk_counter !== 7815) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - ACLK - TEST 1 ====="); |
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
`ifdef WATCHDOG_MUX |
if (r5_counter !== 4) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - ACLK - TEST 2 ====="); |
`else |
/openmsp430/trunk/core/sim/rtl_sim/src/op_modes_asic.v
92,7 → 92,7
wkup[3] = 0; |
|
|
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
|
// SCG1 (<=> R2[7]): turn off SMCLK |
//-------------------------------------------------------- |
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_onoff.v
47,7 → 47,7
$display(" ==============================================="); |
`ifdef DBG_EN |
`ifdef DBG_UART |
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
$display(" ==============================================="); |
$display("| SIMULATION SKIPPED |"); |
$display("| (this test is not supported in ASIC mode) |"); |
/openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_onoff_asic.v
55,7 → 55,7
$display(" ==============================================="); |
`ifdef DBG_EN |
`ifdef DBG_I2C |
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
test_nr = 0; |
#1 dbg_en = 0; |
repeat(30) @(posedge dco_clk); |
/openmsp430/trunk/core/sim/rtl_sim/src/cpu_startup_asic.v
69,7 → 69,7
repeat(5) @(posedge mclk); |
stimulus_done = 0; |
|
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
// #### CPU_EN=0 #### DBG_EN=0 #### RESET_N=0 #### // |
test_nr = 0; |
|
/openmsp430/trunk/core/sim/rtl_sim/src/lp_modes_dbg_asic.v
104,7 → 104,7
|
//$display("dco_clk_cnt: %d / mclk_cnt: %d / smclk_cnt: %d / aclk_cnt: %d / inst_cnt: %d ", dco_clk_cnt, mclk_cnt, smclk_cnt, aclk_cnt, inst_cnt); |
|
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
|
// ACTIVE |
//-------------------------------------------------------- |
/openmsp430/trunk/core/sim/rtl_sim/src/tA_capture.v
49,7 → 49,7
repeat(5) @(posedge mclk); |
stimulus_done = 0; |
|
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
$display(" ==============================================="); |
$display("| SIMULATION SKIPPED |"); |
$display("| (this test is not supported in ASIC mode) |"); |
/openmsp430/trunk/core/sim/rtl_sim/src/tA_modes.v
52,7 → 52,7
stimulus_done = 0; |
test_step = 0; |
|
`ifdef ASIC |
`ifdef ASIC_CLOCKING |
$display(" ==============================================="); |
$display("| SIMULATION SKIPPED |"); |
$display("| (this test is not supported in ASIC mode) |"); |