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URL https://opencores.org/ocsvn/uart_fpga_slow_control_migrated/uart_fpga_slow_control_migrated/trunk

Subversion Repositories uart_fpga_slow_control_migrated

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    from Rev 18 to Rev 19
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Rev 18 → Rev 19

/uart_fpga_slow_control/trunk/code/ab_top.vhd
75,16 → 75,15
component uart_16550_wrapper
port(
-- general purpose
sys_clk_i : in std_logic; -- system clock
-- general purpose
sys_clk_i : in std_logic; -- system clock
sys_rst_i : in std_logic; -- system reset
-- TX/RX process command line
echo_en_i : in std_logic; -- Echo enable (byte by byte) enable/disable = 1/0
tx_addr_wwo_i : in std_logic; -- control of TX process With or WithOut address W/WO=(1/0)
-- serial I/O side
lantronix_output_i : in std_logic; -- Lantronix Serial data OUTPUT signal
lantronix_input_o : out std_logic; -- Lantronix Serial data INPUT signal
cp_b : inout std_logic_vector(2 downto 0); -- general purpose IO pins
uart_din_i : in std_logic; -- Serial data INPUT signal (from the FPGA)
uart_dout_o : out std_logic; -- Serial data OUTPUT signal (to the FPGA)
-- parallel I/O side
s_br_clk_uart_o : out std_logic; -- br_clk clock probe signal
-- RX part/control
110,7 → 109,6
signal s_clk_uart : std_logic; -- slow (29 MHz) clock
-- uart control signals
signal s_uart_cp : std_logic_vector (2 downto 0); -- unused
signal s_uart_br_clk : std_logic; -- unused clock monitor
signal s_uart_rx_add : std_logic_vector (15 downto 0);
signal s_uart_rx_data : std_logic_vector (31 downto 0);
286,9 → 284,8
sys_rst_i => s_rst,
echo_en_i => r_config_addr_uart(0),
tx_addr_wwo_i => r_config_addr_uart(1),
lantronix_output_i => uart_dout_i,
lantronix_input_o => uart_din_o,
cp_b => s_uart_cp,
uart_dout_i => uart_dout_i,
uart_din_o => uart_din_o,
s_br_clk_uart_o => s_uart_br_clk,
v_rx_add_o => s_uart_rx_add,
v_rx_data_o => s_uart_rx_data,
/uart_fpga_slow_control/trunk/code/gh_uart_16550.vhd
55,13 → 55,13
ADD : in std_logic_vector(2 downto 0); -- Address bus
D : in std_logic_vector(7 downto 0); -- Input DATA BUS
sRX : in std_logic; -- Lantronix's OUTPUT
sRX : in std_logic; -- uart's INPUT
CTSn : in std_logic := '1';
DSRn : in std_logic := '1';
RIn : in std_logic := '1';
DCDn : in std_logic := '1';
sTX : out std_logic; -- Lantronix's INPUT
sTX : out std_logic; -- uart's OUTPUT
DTRn : out std_logic; -- not used
RTSn : out std_logic; -- not used
OUT1n : out std_logic; -- not used
/uart_fpga_slow_control/trunk/code/ab_register_rx_handler.vhd
32,7 → 32,7
-- data word lenght: 32 bits
--
--
-- dependencies: Lantronix_wrapper
-- dependencies: uart_wrapper
-- uart_lbus_slave
-- gh_uart_16550
--
/uart_fpga_slow_control/trunk/code/ab_uart_lbus_slave.vhd
17,7 → 17,7
-- description: <file content, behaviour, purpose, special usage notes...>
-- <further description>
--
-- dependencies: Lantronix_wrapper
-- dependencies: uart_wrapper
-- gh_uart_16550
-- register_rx_handler
-- register_tx_handler
/uart_fpga_slow_control/trunk/code/ab_uart_16550_wrapper.vhd
75,9 → 75,8
echo_en_i : in std_logic; -- Echo enable (byte by byte) enable/disable = 1/0
tx_addr_wwo_i : in std_logic; -- control of TX process With or WithOut address W/WO=(1/0)
-- serial I/O side
lantronix_output_i : in std_logic; -- Lantronix Serial data OUTPUT signal
lantronix_input_o : out std_logic; -- Lantronix Serial data INPUT signal
cp_b : inout std_logic_vector(2 downto 0); -- general purpose IO pins
uart_din_i : in std_logic; -- Serial data INPUT signal (from the FPGA)
uart_dout_o : out std_logic; -- Serial data OUTPUT signal (to the FPGA)
-- parallel I/O side
s_br_clk_uart_o : out std_logic; -- br_clk clock probe signal
-- RX part/control
115,13 → 114,13
ADD : in std_logic_vector(2 downto 0); -- ADDRESS BUS
D : in std_logic_vector(7 downto 0); -- Input DATA BUS and CONTROL BUS
sRX : in std_logic; -- Lantronix's OUTPUT
sRX : in std_logic; -- uart's INPUT
CTSn : in std_logic := '1';
DSRn : in std_logic := '1';
RIn : in std_logic := '1';
DCDn : in std_logic := '1';
sTX : out std_logic; -- Lantronix's INPUT
sTX : out std_logic; -- uart's OUTPUT
DTRn : out std_logic;
RTSn : out std_logic;
OUT1n : out std_logic;
341,8 → 340,8
begin
 
s_clk <= sys_clk_i; -- 14,xxx MHz main clock single ended buffer and division by one
-- and 1 Mbit/s with Lantronix
s_clk <= sys_clk_i; -- 29,xxx MHz main clock single ended buffer
 
s_clk_n <= not s_clk;
s_rst <= sys_rst_i;
s_br_clk <= s_clk;
492,13 → 491,13
WR => s_wr, -- WRITE when HIGH with CS high | READ when LOW with CS high
ADD => uart_add_bus, -- ADDRESS BUS
D => uart_data_bus, -- Input DATA BUS and CONTROL BUS
sRX => lantronix_output_i, -- Lantronix's OUTPUT
sRX => uart_din_i, -- uart' INPUT
CTSn => '1', -- not used
DSRn => '1', -- not used
RIn => '1', -- not used
DCDn => '1', -- not used
sTX => lantronix_input_o, -- Lantronix's INPUT
sTX => uart_dout_o, -- uart's OUTPUT
DTRn => open, -- not used
RTSn => open, -- not used
OUT1n => open, -- not used
/uart_fpga_slow_control/trunk/code/ab_register_tx_handler.vhd
42,7 → 42,7
-- data word lenght: 32 bits
--
--
-- dependencies: Lantronix_wrapper
-- dependencies: uart_wrapper
-- uart_lbus_slave
-- gh_uart_16550
--

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