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Rev 18 → Rev 19

/trunk/rtl/verilog/vga_vga_and_clut_top.v File deleted
/trunk/rtl/verilog/vga_vtim.v
31,6 → 31,7
 
wire Dsync, Dgdel, Dgate, Dlen;
reg go, drst;
reg hDlen, hDgate;
 
//
// module body
45,7 → 46,7
end
else if (ena)
begin
go <= Dlen | (!rst & drst);
go <= Dlen | hDlen | (!rst & drst);
drst <= rst;
end
 
58,21 → 59,43
// hookup gate counter
ro_cnt #(16) gate_cnt (.clk(clk), .rst(rst), .nReset(1'b1), .cnt_en(ena), .go(Dgdel), .d(Tgate), .id(Tgate), .q(), .done(Dgate));
 
// hookup gate counter
// hookup length counter
ro_cnt #(16) len_cnt (.clk(clk), .rst(rst), .nReset(1'b1), .cnt_en(ena), .go(go), .d(Tlen), .id(Tlen), .q(), .done(Dlen));
 
// hold dgate signal
always@(posedge clk)
if (rst)
hDgate <= 1'b0;
else
hDgate <= (Dgate | hDgate) & Gate;
 
// hold dlen signal
always@(posedge clk)
if (rst)
hDlen <= 1'b0;
else
hDlen <= (Dlen | hDlen) & !go;
 
// generate output signals
always@(posedge clk)
if (rst)
Sync <= 1'b0;
else
Sync <= (go | Sync) & !Dsync;
Sync <= (go | Sync) & !Dsync;
 
always@(posedge clk)
if (rst)
Gate <= 1'b0;
else
Gate <= (Dgdel | Gate) & !Dgate;
Gate <= (Dgdel | Gate) & !( (Dgate | hDgate) & ena);
 
assign Done = Dlen;
endmodule
 
 
 
 
 
 
 
 
/trunk/rtl/verilog/vga_fifo.v
68,17 → 68,7
wptr <= #1 wptr + 1;
 
// memory array operations
/*
always@(posedge clk)
begin
if (wreq)
mem[wptr] <= #1 d;
 
q <= #1 mem[rptr];
end
*/
always@(posedge clk)
if (wreq)
mem[wptr] <= #1 d;
 
103,5 → 93,3
assign hfull = fifo_cnt[AWIDTH -1];
assign full = fifo_cnt[AWIDTH];
endmodule
 
 
/trunk/rtl/verilog/vga_wb_master.v
2,38 → 2,41
// File wb_master.v, WISHBONE MASTER interface (video-memory/clut memory)
// Project: VGA
// Author : Richard Herveille
// rev.: 0.1 August 2nd, 2001. Initial Verilog release
// rev.: 0.2 August 29th, 2001. Changed some sections, try to get core up to speed.
// rev.: 0.1 August 2nd, 2001. Initial Verilog release
// rev.: 0.2 August 29th, 2001. Changed some sections, try to get core up to speed.
// rev.: 1.0 October 2nd, 2001. Revised core. Moved clut-memory into color-processor. Removed all references to clut-accesses from wishbone master.
// Changed video memory address generation.
//
 
`include "timescale.v"
 
module vga_wb_master (CLK_I, RST_I, nRESET, CYC_O, STB_O, CAB_O, WE_O, ADR_O, SEL_O, ACK_I, ERR_I, DAT_I, SINT,
ctrl_ven, ctrl_cd, ctrl_pc, ctrl_vbl, ctrl_vbsw, ctrl_cbsw, VBAa, VBAb, CBA, Thgate, Tvgate,
stat_avmp, stat_acmp, bs_req, line_fifo_wreq, line_fifo_d, line_fifo_full);
module vga_wb_master (clk_i, rst_i, nrst_i, cyc_o, stb_o, cab_o, we_o, adr_o, sel_o, ack_i, err_i, dat_i, sint,
ctrl_ven, ctrl_cd, ctrl_pc, ctrl_vbl, ctrl_vbsw, ctrl_cbsw, VBAa, VBAb, Thgate, Tvgate,
stat_avmp, stat_acmp, vmem_switch, clut_switch, line_fifo_wreq, line_fifo_d, line_fifo_full,
clut_req, clut_ack, clut_adr, clut_q);
 
// inputs & outputs
 
// wishbone signals
input CLK_I; // master clock input
input RST_I; // synchronous active high reset
input nRESET; // asynchronous low reset
output CYC_O; // cycle output
reg CYC_O;
output STB_O; // strobe ouput
reg STB_O;
output CAB_O; // consecutive address burst output
reg CAB_O;
output WE_O; // write enable output
reg WE_O;
output [31:2] ADR_O; // address output
output [ 3:0] SEL_O; // byte select outputs (only 32bits accesses are supported)
reg [3:0] SEL_O;
input ACK_I; // wishbone cycle acknowledge
input ERR_I; // wishbone cycle error
input [31:0] DAT_I; // wishbone data in
input clk_i; // master clock input
input rst_i; // synchronous active high reset
input nrst_i; // asynchronous low reset
output cyc_o; // cycle output
reg cyc_o;
output stb_o; // strobe ouput
reg stb_o;
output cab_o; // consecutive address burst output
reg cab_o;
output we_o; // write enable output
reg we_o;
output [31:0] adr_o; // address output
output [ 3:0] sel_o; // byte select outputs (only 32bits accesses are supported)
reg [3:0] sel_o;
input ack_i; // wishbone cycle acknowledge
input err_i; // wishbone cycle error
input [31:0] dat_i; // wishbone data in
 
output SINT; // non recoverable error, interrupt host
output sint; // non recoverable error, interrupt host
 
// control register settings
input ctrl_ven; // video enable bit
46,7 → 49,6
// video memory addresses
input [31: 2] VBAa; // video memory base address A
input [31: 2] VBAb; // video memory base address B
input [31:11] CBA; // CLUT base address
 
input [15:0] Thgate; // horizontal visible area (in pixels)
input [15:0] Tvgate; // vertical visible area (in horizontal lines)
53,7 → 55,9
 
output stat_avmp; // active video memory page
output stat_acmp; // active CLUT memory page
output bs_req; // bank-switch request: memory page switched (when enabled). bs_req is always generated
reg stat_acmp;
output vmem_switch; // video memory bank-switch request: memory page switched (when enabled)
output clut_switch; // clut memory bank-switch request: clut page switched (when enabled)
 
// to/from line-fifo
output line_fifo_wreq;
60,87 → 64,132
output [23:0] line_fifo_d;
input line_fifo_full;
 
// to/from color lookup-table
output clut_req; // clut access request
input clut_ack; // clut access acknowledge
output [ 8:0] clut_adr; // clut access address
input [23:0] clut_q; // clut access data in
 
//
// variable declarations
//
reg vmem_acc, clut_acc; // video memory access // clut access
wire clut_req, clut_ack; // clut access request // clut access acknowledge
wire [7:0] clut_offs; // clut memory offset
 
reg vmem_acc; // video memory access
wire nvmem_req, vmem_ack; // NOT video memory access request // video memory access acknowledge
wire ImDoneStrb; // image done (strobe signal)
reg dImDoneStrb;
wire pixelbuf_rreq, pixelbuf_empty, pixelbuf_hfull;
wire [31:0] pixelbuf_q;
wire RGBbuf_wreq, RGBbuf_empty, RGBbuf_full, RGB_fifo_full;
// reg RGBbuf_rreq, fill_RGBfifo;
reg fill_RGBfifo;
wire RGBbuf_rreq;
wire [23:0] RGBbuf_d;
reg dvmem_ack; // delayed video memory acknowledge
 
// wire ImDone; // Done reading image from video mem
reg ImDone; // Done reading image from video mem
reg dImDone; // delayed ImDone
wire ImDoneStrb; // image done (strobe signal)
reg dImDoneStrb; // delayed ImDoneStrb
 
wire data_fifo_rreq, data_fifo_empty, data_fifo_hfull;
wire [31:0] data_fifo_q;
wire rgb_fifo_wreq, rgb_fifo_empty, rgb_fifo_full, rgb_ffull, rgb_fifo_rreq;
reg fill_rgb_fifo;
wire [23:0] rgb_fifo_d;
wire ImDoneFifoQ;
reg dImDoneFifoQ;
reg [2:0] ImDoneCpQ;
reg dImDoneCpQ;
 
reg sclr; // synchronous clear
 
wire [7:0] clut_offs; // color lookup table offset
 
//
// module body
//
 
// generate synchronous clear
always@(posedge clk_i)
sclr <= #1 ~ctrl_ven;
//
// WISHBONE block
//
reg [ 2:0] burst_cnt; // video memory burst access counter
wire ImDone; // Done reading image from video mem
reg dImDone; // delayed ImDone
reg hImDone;
wire burst_done; // completed burst access to video mem
reg sel_VBA, sel_CBA; // select video memory base address // select clut base address
reg sel_VBA; // select video memory base address
reg [31:2] vmemA; // video memory address
wire [31:2] clutA; // clut address
reg [15:0] hgate_cnt, vgate_cnt; // horizontal / vertical pixel counters
wire hdone, vdone; // horizontal count done / vertical count done
 
// wishbone access controller, video memory access request has highest priority (try to keep fifo full)
always@(posedge CLK_I)
if (~ctrl_ven)
begin
vmem_acc <= #1 1'b0;
clut_acc <= #1 1'b0;
end
always@(posedge clk_i)
if (sclr)
vmem_acc <= #1 1'b0;
else
begin
clut_acc <= #1 clut_req & ( (nvmem_req & !vmem_acc) | clut_acc);
vmem_acc <= #1 (!nvmem_req | (vmem_acc & !(burst_done & vmem_ack) )) & !clut_acc;
end
vmem_acc <= #1 (!nvmem_req | (vmem_acc & !(burst_done & vmem_ack) ) ) & !ImDone;
 
assign vmem_ack = ACK_I & vmem_acc;
assign clut_ack = ACK_I & clut_acc;
assign vmem_ack = ack_i;
assign sint = err_i; // Non recoverable error, interrupt host system
 
assign SINT = (vmem_acc | clut_acc) & ERR_I; // Non recoverable error, interrupt host system
// select active memory page
assign vmem_switch = ImDoneStrb;
 
// select active memory page
always@(posedge CLK_I)
if (~ctrl_ven)
always@(posedge clk_i)
if (sclr)
sel_VBA <= #1 1'b0;
else if (ctrl_vbsw)
sel_VBA <= #1 sel_VBA ^ ImDoneStrb; // select next video memory bank when finished reading current bank (and bank switch enabled)
sel_VBA <= #1 sel_VBA ^ vmem_switch; // select next video memory bank when finished reading current bank (and bank switch enabled)
 
assign stat_avmp = sel_VBA; // assign output
 
// select active clut page
always@(posedge CLK_I)
if (~ctrl_ven)
sel_CBA <= #1 1'b0;
 
// clut bank switch delay1; push ImDoneStrb into fifo. Account for data_fifo delay
always@(posedge clk_i)
dvmem_ack <= #1 vmem_ack;
 
vga_fifo #(4, 1) clut_sw_fifo (
.clk(clk_i),
.aclr(1'b1),
.sclr(sclr),
.d(ImDone),
.wreq(dvmem_ack),
.q(ImDoneFifoQ),
.rreq(data_fifo_rreq),
.empty(),
.hfull(),
.full()
);
 
// clut bank switch delay2: Account for ColorProcessor DataBuffer delay
always@(posedge clk_i)
if (data_fifo_rreq)
dImDoneFifoQ <= #1 ImDoneFifoQ;
 
// clut bank switch delay3; Account for ColorProcessor internal delay
always@(posedge clk_i)
if (sclr)
begin
ImDoneCpQ <= #1 4'h0;
dImDoneCpQ <= #1 1'b0;
end
else
begin
dImDoneCpQ <= #1 ImDoneCpQ[2];
if (rgb_fifo_wreq)
ImDoneCpQ <= #1 { ImDoneCpQ[2:0], dImDoneFifoQ };
end
 
assign clut_switch = ImDoneCpQ[2] & !dImDoneCpQ;
 
always@(posedge clk_i)
if (sclr)
stat_acmp <= #1 1'b0;
else if (ctrl_cbsw)
sel_CBA <= #1 sel_CBA ^ ImDoneStrb; // select next clut when finished reading current video bank
stat_acmp <= #1 stat_acmp ^ clut_switch; // select next clut when finished reading clut for current video bank (and bank switch enabled)
 
assign stat_acmp = sel_CBA; // assign output
// generate clut-address
assign clut_adr = {stat_acmp, clut_offs};
 
// assign bank_switch_request (status register) output
assign bs_req = ImDoneStrb & ctrl_ven; // bank switch request
 
// generate burst counter
wire [3:0] burst_cnt_val;
assign burst_cnt_val = {1'b0, burst_cnt} -4'h1;
assign burst_done = burst_cnt_val[3];
 
always@(posedge CLK_I)
always@(posedge clk_i)
if ( (burst_done & vmem_ack) | !vmem_acc)
case (ctrl_vbl) // synopsis full_case parallel_case
2'b00: burst_cnt <= #1 3'b000; // burst length 1
156,59 → 205,98
//
 
// hgate counter
wire [16:0] hgate_cnt_val;
assign hgate_cnt_val = {1'b0, hgate_cnt} -17'h1;
assign hdone = hgate_cnt_val[16];
reg [15:0] hgate_cnt;
reg [16:0] hgate_cnt_val;
reg [1:0] hgate_div_cnt;
reg [2:0] hgate_div_val;
 
always@(posedge CLK_I)
if (~ctrl_ven)
hgate_cnt <= #1 Thgate;
else if (RGBbuf_wreq)
if (hdone)
hgate_cnt <= #1 Thgate;
wire hdone = hgate_cnt_val[16] & vmem_ack; // ????
 
always@(hgate_cnt or hgate_div_cnt or ctrl_cd)
begin
hgate_div_val = {1'b0, hgate_div_cnt} - 3'h1;
if (ctrl_cd != 2'b10)
hgate_cnt_val = {1'b0, hgate_cnt} - 17'h1;
else if ( hgate_div_val[2] )
hgate_cnt_val = {1'b0, hgate_cnt} - 17'h1;
else
hgate_cnt <= #1 hgate_cnt_val[15:0];
hgate_cnt_val = {1'b0, hgate_cnt};
end
 
always@(posedge clk_i)
if (sclr)
begin
case(ctrl_cd) // synopsys full_case parallel_case
2'b00: // 8bpp
hgate_cnt <= #1 Thgate >> 2; // 4 pixels per cycle
2'b01: //16bpp
hgate_cnt <= #1 Thgate >> 1; // 2 pixels per cycle
2'b10: //24bpp
hgate_cnt <= #1 Thgate >> 2; // 4/3 pixels per cycle
2'b11: //reserved
;
endcase
 
hgate_div_cnt <= 2'b10;
end
else if (vmem_ack)
if (hdone)
begin
case(ctrl_cd) // synopsys full_case parallel_case
2'b00: // 8bpp
hgate_cnt <= #1 Thgate >> 2; // 4 pixels per cycle
2'b01: //16bpp
hgate_cnt <= #1 Thgate >> 1; // 2 pixels per cycle
2'b10: //24bpp
hgate_cnt <= #1 Thgate >> 2; // 4/3 pixels per cycle
2'b11: //reserved
;
endcase
hgate_div_cnt <= #1 2'b10;
end
else //if (vmem_ack)
begin
hgate_cnt <= #1 hgate_cnt_val[15:0];
 
if ( hgate_div_val[2] )
hgate_div_cnt <= #1 2'b10;
else
hgate_div_cnt <= #1 hgate_div_val[1:0];
end
 
// vgate counter
wire [16:0] vgate_cnt_val;
assign vgate_cnt_val = {1'b0, vgate_cnt} -17'h1;
assign vdone = vgate_cnt_val[16];
reg [15:0] vgate_cnt;
wire [16:0] vgate_cnt_val = {1'b0, vgate_cnt} -17'h1;
wire vdone = vgate_cnt_val[16];
 
always@(posedge CLK_I)
if (~ctrl_ven)
always@(posedge clk_i)
if (sclr)
vgate_cnt <= #1 Tvgate;
else if (hdone & RGBbuf_wreq)
if (ImDone)
vgate_cnt <= #1 Tvgate;
else
vgate_cnt <= #1 vgate_cnt_val[15:0];
else if (ImDoneStrb)
vgate_cnt <= #1 Tvgate;
else if (hdone)
vgate_cnt <= #1 vgate_cnt_val[15:0];
 
assign ImDone = hdone & vdone;
always@(posedge clk_i)
ImDone <= #1 hdone & vdone;
 
// assign ImDone = hdone & vdone;
assign ImDoneStrb = ImDone & !dImDone;
 
always@(posedge CLK_I)
begin
if (~ctrl_ven)
dImDone <= #1 1'b0;
else
always@(posedge clk_i)
begin
dImDone <= #1 ImDone;
dImDoneStrb <= #1 ImDoneStrb;
end
 
dImDoneStrb <= #1 ImDoneStrb;
end
 
always@(posedge CLK_I)
if (!ctrl_ven)
hImDone <= #1 1'b0;
else
hImDone <= #1 (ImDone || hImDone) && vmem_acc && !(burst_done && vmem_ack);
 
//
// generate addresses
//
 
// select video memory base address
always@(posedge CLK_I)
if (dImDoneStrb | !ctrl_ven)
always@(posedge clk_i)
if (dImDoneStrb | sclr)
if (!sel_VBA)
vmemA <= #1 VBAa;
else
216,117 → 304,98
else if (vmem_ack)
vmemA <= #1 vmemA +30'h1;
 
// calculate CLUT address
assign clutA = {CBA, sel_CBA, clut_offs};
 
// generate wishbone signals
assign ADR_O = vmem_acc ? vmemA : clutA;
assign adr_o = {vmemA, 2'b00};
wire wb_cycle = vmem_acc & !(burst_done & vmem_ack & nvmem_req) & !ImDone;
 
always@(posedge CLK_I or negedge nRESET)
if (!nRESET)
always@(posedge clk_i or negedge nrst_i)
if (!nrst_i)
begin
CYC_O <= #1 1'b0;
STB_O <= #1 1'b0;
SEL_O <= #1 4'b1111;
CAB_O <= #1 1'b0;
WE_O <= #1 1'b0;
cyc_o <= #1 1'b0;
stb_o <= #1 1'b0;
sel_o <= #1 4'b1111;
cab_o <= #1 1'b0;
we_o <= #1 1'b0;
end
else
if (RST_I)
if (rst_i)
begin
CYC_O <= #1 1'b0;
STB_O <= #1 1'b0;
SEL_O <= #1 4'b1111;
CAB_O <= #1 1'b0;
WE_O <= #1 1'b0;
cyc_o <= #1 1'b0;
stb_o <= #1 1'b0;
sel_o <= #1 4'b1111;
cab_o <= #1 1'b0;
we_o <= #1 1'b0;
end
else
begin
CYC_O <= #1 (clut_acc & clut_req & !ACK_I) | (vmem_acc & !(burst_done & vmem_ack & nvmem_req) );
STB_O <= #1 (clut_acc & clut_req & !ACK_I) | (vmem_acc & !(burst_done & vmem_ack & nvmem_req) );
SEL_O <= #1 4'b1111; // only 32bit accesses are supported
CAB_O <= #1 vmem_acc & !(burst_done & vmem_ack & nvmem_req);
WE_O <= #1 1'b0; // read only
cyc_o <= #1 wb_cycle;
stb_o <= #1 wb_cycle;
sel_o <= #1 4'b1111; // only 32bit accesses are supported
cab_o <= #1 wb_cycle;
we_o <= #1 1'b0; // read only
end
 
// pixel buffer (temporary store data read from video memory)
vga_fifo #(4, 32) pixel_buf (
.clk(CLK_I),
vga_fifo #(4, 32) data_fifo (
.clk(clk_i),
.aclr(1'b1),
.sclr(!ctrl_ven || hImDone || ImDoneStrb),
.d(DAT_I),
.sclr(sclr),
.d(dat_i),
.wreq(vmem_ack),
.q(pixelbuf_q),
.rreq(pixelbuf_rreq),
.empty(pixelbuf_empty),
.hfull(pixelbuf_hfull),
.q(data_fifo_q),
.rreq(data_fifo_rreq),
.empty(data_fifo_empty),
.hfull(data_fifo_hfull),
.full()
);
 
assign nvmem_req = !(!pixelbuf_hfull && !(ImDoneStrb || hImDone) );
assign nvmem_req = data_fifo_hfull;
 
always@(posedge CLK_I)
if (!ctrl_ven)
fill_RGBfifo <= #1 1'b0;
always@(posedge clk_i)
if (sclr)
fill_rgb_fifo <= #1 1'b0;
else
fill_RGBfifo <= #1 (RGBbuf_empty | fill_RGBfifo) & !RGBbuf_full;
fill_rgb_fifo <= #1 (rgb_fifo_empty | fill_rgb_fifo) & !rgb_fifo_full;
 
assign RGB_fifo_full = !(fill_RGBfifo & !RGBbuf_full);
assign rgb_ffull = !(fill_rgb_fifo & !rgb_fifo_full);
 
// hookup color processor
vga_colproc color_proc (
.clk(CLK_I),
.srst(!ctrl_ven || (ImDoneStrb && !clut_acc) ),
.pixel_buffer_di(pixelbuf_q),
.wb_di(DAT_I),
.clk(clk_i),
.srst(sclr),
.pixel_buffer_di(data_fifo_q),
.ColorDepth(ctrl_cd),
.PseudoColor(ctrl_pc),
.pixel_buffer_empty(pixelbuf_empty),
.pixel_buffer_rreq(pixelbuf_rreq),
.RGB_fifo_full(RGB_fifo_full),
.RGB_fifo_wreq(RGBbuf_wreq),
.R(RGBbuf_d[23:16]),
.G(RGBbuf_d[15:8]),
.B(RGBbuf_d[7:0]),
.pixel_buffer_empty(data_fifo_empty),
.pixel_buffer_rreq(data_fifo_rreq),
.RGB_fifo_full(rgb_ffull),
.RGB_fifo_wreq(rgb_fifo_wreq),
.R(rgb_fifo_d[23:16]),
.G(rgb_fifo_d[15:8]),
.B(rgb_fifo_d[7:0]),
.clut_req(clut_req),
.clut_ack(clut_ack),
.clut_offs(clut_offs),
.clut_ack(clut_ack)
.clut_q(clut_q)
);
 
// hookup RGB buffer (temporary station between WISHBONE-clock-domain and pixel-clock-domain)
vga_fifo #(3, 24) RGB_buf (
.clk(CLK_I),
vga_fifo #(3, 24) rgb_fifo (
.clk(clk_i),
.aclr(1'b1),
.sclr(!ctrl_ven),
.d(RGBbuf_d),
.wreq(RGBbuf_wreq),
.sclr(sclr),
.d(rgb_fifo_d),
.wreq(rgb_fifo_wreq),
.q(line_fifo_d),
.rreq(RGBbuf_rreq),
.empty(RGBbuf_empty),
.hfull(RGBbuf_full),
.rreq(rgb_fifo_rreq),
.empty(rgb_fifo_empty),
.hfull(rgb_fifo_full),
.full()
);
 
// generate signals for line-fifo
/*
always@(posedge CLK_I)
if (!ctrl_ven)
RGBbuf_rreq <= #1 1'b0;
else
RGBbuf_rreq <= #1 !line_fifo_full & !RGBbuf_empty & !RGBbuf_rreq;
*/
assign rgb_fifo_rreq = !line_fifo_full && !rgb_fifo_empty;
assign line_fifo_wreq = rgb_fifo_rreq;
 
assign RGBbuf_rreq = !line_fifo_full && !RGBbuf_empty;
assign line_fifo_wreq = RGBbuf_rreq;
 
endmodule
 
 
 
 
 
 
 
 
 
 
/trunk/rtl/verilog/ro_cnt.v
40,7 → 40,7
rci <= #1 1'b0;
else if (rst)
rci <= #1 1'b0;
else if (cnt_en)
else //if (cnt_en)
rci <= #1 (go | rci) & !rco;
 
assign nld = !go;
52,3 → 52,6
// assign outputs
assign done = rco;
endmodule
 
 
 
/trunk/rtl/verilog/vga_colproc.v
2,25 → 2,28
// File colproc.vhd, Color Processor
// Project: VGA
// Author : Richard Herveille. Ideas and thoughts: Sherif Taher Eid
// rev. 1.0 August 2nd, 2001. Initial Verilog release
// rev. 1.1 August 29th, 2001. Changed statemachine to increase bandwidth.
//
// rev. 1.0 August 2nd, 2001. Initial Verilog release
// rev. 1.1 August 29th, 2001. Changed statemachine to increase bandwidth.
// rev. 2.0 October 2nd, 2001. Revised core. Included color lookup table in Color Processor
 
`include "timescale.v"
 
module vga_colproc(clk, srst, pixel_buffer_di, wb_di, ColorDepth, PseudoColor,
module vga_colproc(clk, srst, pixel_buffer_di, ColorDepth, PseudoColor,
pixel_buffer_empty, pixel_buffer_rreq, RGB_fifo_full,
RGB_fifo_wreq, R, G, B, clut_req, clut_offs, clut_ack);
RGB_fifo_wreq, R, G, B,
clut_req, clut_ack, clut_offs, clut_q);
 
//
// inputs & outputs
//
input clk; // master clock
input srst; // synchronous reset
 
input [31:0] pixel_buffer_di; // Pixel Buffer data input
input [31:0] wb_di; // wishbone data input
 
input [1:0] ColorDepth; // color depth (8bpp, 16bpp, 24bpp)
input PseudoColor; // pseudo color enabled (only for 8bpp color depth)
input PseudoColor; // pseudo color enabled (only for 8bpp color depth)
 
input pixel_buffer_empty;
output pixel_buffer_rreq; // pixel buffer read request
32,13 → 35,16
output [7:0] R, G, B; // pixel color information
reg [7:0] R, G, B;
 
output clut_req; // Color lookup table access request
reg clut_req;
output [7:0] clut_offs; // offset into color lookup table
reg [7:0] clut_offs;
input clut_ack; // Color lookup table data acknowledge
output clut_req; // clut request
reg clut_req;
input clut_ack; // clut acknowledge
output [ 7:0] clut_offs; // clut offset
reg [7:0] clut_offs;
input [23:0] clut_q; // clut data in
 
//
// variable declarations
//
reg [31:0] DataBuffer;
 
reg [7:0] Ra, Ga, Ba;
45,7 → 51,6
reg [1:0] colcnt;
reg RGBbuf_wreq;
 
 
//
// Module body
//
154,18 → 159,18
c_state <= #1 nxt_state;
 
 
reg clut_acc;
reg iclut_req;
reg pixelbuf_rreq;
reg [7:0] iR, iG, iB, iRa, iGa, iBa;
 
// output decoder
always@(c_state or pixel_buffer_empty or colcnt or DataBuffer or RGB_fifo_full or clut_ack or wb_di or Ba or Ga or Ra)
always@(c_state or pixel_buffer_empty or colcnt or DataBuffer or RGB_fifo_full or clut_ack or clut_q or Ba or Ga or Ra)
begin : output_decoder
 
// initial values
pixelbuf_rreq = 1'b0;
RGBbuf_wreq = 1'b0;
clut_acc = 1'b0;
iclut_req = 1'b0;
iR = 'h0;
iG = 'h0;
233,14 → 238,14
pixelbuf_rreq = 1'b1;
end
 
iR = wb_di[23:16];
iG = wb_di[15: 8];
iB = wb_di[ 7: 0];
iR = clut_q[23:16];
iG = clut_q[15: 8];
iB = clut_q[ 7: 0];
 
clut_acc = ~RGB_fifo_full;
iclut_req = ~RGB_fifo_full;
 
if ( !(|colcnt) && clut_ack)
clut_acc =1'b0;
iclut_req =1'b0;
end
 
//
349,7 → 354,7
begin
pixel_buffer_rreq <= #1 pixelbuf_rreq;
RGB_fifo_wreq <= #1 RGBbuf_wreq;
clut_req <= #1 clut_acc;
clut_req <= #1 iclut_req;
end
end
 
371,18 → 376,4
colcnt <= #1 2'b11;
else if (RGBbuf_wreq)
colcnt <= #1 colcnt -2'h1;
 
endmodule
 
 
 
 
 
 
 
 
 
 
 
 
 
/trunk/rtl/verilog/vga_top.v
1,22 → 1,28
//
// file: vga.v
// file: vga_top.v
// project: VGA/LCD controller
// author: Richard Herveille
//
// rev 1.0 August 6th, 2001. Initial Verilog release
// rev. 1.0 August 6th, 2001. Initial Verilog release
// rev. 2.0 October 2nd, 2001. Revised core. Moved color lookup table to color-processor.
// Changed wb-master address generation
// Changed status & control registers
// Changed port names to new naming convention
//
 
`include "timescale.v"
`include "vga_defines.v"
 
module vga_top (wb_clk_i, wb_rst_i, rst_nreset_i, wb_inta_o,
wb_adr_i, wb_sdat_i, wb_sdat_o, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_err_o,
wb_adr_o, wb_mdat_i, wb_cab_o, wb_sel_o, wb_we_o, wb_stb_o, wb_cyc_o, wb_ack_i, wb_err_i,
clk_pclk_i, vga_hsync_pad_o, vga_vsync_pad_o, vga_csync_pad_o, vga_blank_pad_o,
vga_r_pad_o, vga_g_pad_o, vga_b_pad_o);
module vga_top (wb_clk_i, wb_rst_i, rst_i, wb_inta_o,
wbs_adr_i, wbs_dat_i, wbs_dat_o, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, wbs_ack_o, wbs_err_o,
wbm_adr_o, wbm_dat_i, wbm_cab_o, wbm_sel_o, wbm_we_o, wbm_stb_o, wbm_cyc_o, wbm_ack_i, wbm_err_i,
clk_p_i, hsync_pad_o, vsync_pad_o, csync_pad_o, blank_pad_o, r_pad_o, g_pad_o, b_pad_o);
 
//
// parameters
//
parameter LINE_FIFO_AWIDTH = 7;
parameter ARST_LVL = 1'b0;
 
//
// inputs & outputs
23,49 → 29,52
//
 
// syscon interface
input wb_clk_i; // wishbone clock input
input wb_rst_i; // synchronous active high reset
input rst_nreset_i; // asynchronous active low reset
output wb_inta_o; // interrupt request output
input wb_clk_i; // wishbone clock input
input wb_rst_i; // synchronous active high reset
input rst_i; // asynchronous reset
output wb_inta_o; // interrupt request output
 
// slave signals
input [ 4:2] wb_adr_i; // addressbus input (only 32bit databus accesses supported)
input [31:0] wb_sdat_i; // Slave databus output
output [31:0] wb_sdat_o; // Slave databus input
input [ 3:0] wb_sel_i; // byte select inputs
input wb_we_i; // write enabel input
input wb_stb_i; // strobe/select input
input wb_cyc_i; // valid bus cycle input
output wb_ack_o; // bus cycle acknowledge output
output wb_err_o; // bus cycle error output
input [11:0] wbs_adr_i; // addressbus input (only 32bit databus accesses supported)
input [31:0] wbs_dat_i; // Slave databus output
output [31:0] wbs_dat_o; // Slave databus input
input [ 3:0] wbs_sel_i; // byte select inputs
input wbs_we_i; // write enabel input
input wbs_stb_i; // strobe/select input
input wbs_cyc_i; // valid bus cycle input
output wbs_ack_o; // bus cycle acknowledge output
output wbs_err_o; // bus cycle error output
// master signals
output [31:2] wb_adr_o; // addressbus output
input [31:0] wb_mdat_i; // Master databus input
output [ 3:0] wb_sel_o; // byte select outputs
output wb_we_o; // write enable output
output wb_stb_o; // strobe output
output wb_cyc_o; // valid bus cycle output
output wb_cab_o; // continuos address burst output
input wb_ack_i; // bus cycle acknowledge input
input wb_err_i; // bus cycle error input
output [31:0] wbm_adr_o; // addressbus output
input [31:0] wbm_dat_i; // Master databus input
output [ 3:0] wbm_sel_o; // byte select outputs
output wbm_we_o; // write enable output
output wbm_stb_o; // strobe output
output wbm_cyc_o; // valid bus cycle output
output wbm_cab_o; // continuos address burst output
input wbm_ack_i; // bus cycle acknowledge input
input wbm_err_i; // bus cycle error input
 
// VGA signals
input clk_pclk_i; // pixel clock
output vga_hsync_pad_o; // horizontal sync
reg vga_hsync_pad_o;
output vga_vsync_pad_o; // vertical sync
reg vga_vsync_pad_o;
output vga_csync_pad_o; // composite sync
reg vga_csync_pad_o;
output vga_blank_pad_o; // blanking signal
reg vga_blank_pad_o;
output [ 7:0] vga_r_pad_o, vga_g_pad_o, vga_b_pad_o; // RGB color signals
input clk_p_i; // pixel clock
output hsync_pad_o; // horizontal sync
reg hsync_pad_o;
output vsync_pad_o; // vertical sync
reg vsync_pad_o;
output csync_pad_o; // composite sync
reg csync_pad_o;
output blank_pad_o; // blanking signal
reg blank_pad_o;
output [ 7:0] r_pad_o, g_pad_o, b_pad_o; // RGB color signals
 
//
// variable declarations
//
 
// programable asynchronous reset
wire arst = rst_i ^ ARST_LVL;
 
// from wb_slave
wire ctrl_bl, ctrl_csl, ctrl_vsl, ctrl_hsl, ctrl_pc, ctrl_cbsw, ctrl_vbsw, ctrl_ven;
wire [ 1: 0] ctrl_cd, ctrl_vbl;
72,10 → 81,9
wire [ 7: 0] Thsync, Thgdel, Tvsync, Tvgdel;
wire [15: 0] Thgate, Thlen, Tvgate, Tvlen;
wire [31: 2] VBARa, VBARb;
wire [31:11] CBAR;
 
// to wb_slave
wire stat_avmp, stat_acmp, bsint, hint, vint, sint;
wire stat_avmp, stat_acmp, vmem_swint, clut_swint, hint, vint, sint;
reg luint;
 
// from pixel generator
85,6 → 93,14
// line fifo connections
wire line_fifo_dpm_wreq;
wire [23:0] line_fifo_dpm_d, line_fifo_dpm_q;
 
// clut connections
wire clut_req, clut_ack;
wire [23:0] clut_q;
wire cp_clut_req, cp_clut_ack;
wire [ 8:0] cp_clut_adr;
wire [23:0] cp_clut_q;
 
//
// Module body
//
94,16 → 110,16
// wishbone interface
.CLK_I(wb_clk_i),
.RST_I(wb_rst_i),
.nRESET(rst_nreset_i),
.ADR_I(wb_adr_i),
.DAT_I(wb_sdat_i),
.DAT_O(wb_sdat_o),
.SEL_I(wb_sel_i),
.WE_I(wb_we_i),
.STB_I(wb_stb_i),
.CYC_I(wb_cyc_i),
.ACK_O(wb_ack_o),
.ERR_O(wb_err_o),
.nRESET(arst),
.ADR_I(wbs_adr_i[11:2]),
.DAT_I(wbs_dat_i),
.DAT_O(wbs_dat_o),
.SEL_I(wbs_sel_i),
.WE_I(wbs_we_i),
.STB_I(wbs_stb_i),
.CYC_I(wbs_cyc_i),
.ACK_O(wbs_ack_o),
.ERR_O(wbs_err_o),
.INTA_O(wb_inta_o),
 
// internal connections
119,11 → 135,12
.ven(ctrl_ven),
.acmp(stat_acmp),
.avmp(stat_avmp),
.bsint_in(bsint),
.hint_in(hint),
.vint_in(vint),
.luint_in(luint),
.sint_in(sint),
.vbsint_in(vmem_swint), // video memory bank switch interrupt
.cbsint_in(clut_swint), // clut memory bank switch interrupt
.hint_in(hint), // horizontal interrupt
.vint_in(vint), // vertical interrupt
.luint_in(luint), // line fifo underrun interrupt
.sint_in(sint), // system-error interrupt
.Thsync(Thsync),
.Thgdel(Thgdel),
.Thgate(Thgate),
134,27 → 151,29
.Tvlen(Tvlen),
.VBARa(VBARa),
.VBARb(VBARb),
.CBAR(CBAR)
.clut_acc(clut_req),
.clut_ack(clut_ack),
.clut_q(clut_q)
);
 
// hookup wishbone master
vga_wb_master u2 (
// wishbone interface
.CLK_I(wb_clk_i),
.RST_I(wb_rst_i),
.nRESET(rst_nreset_i),
.CYC_O(wb_cyc_o),
.STB_O(wb_stb_o),
.CAB_O(wb_cab_o),
.WE_O(wb_we_o),
.ADR_O(wb_adr_o),
.SEL_O(wb_sel_o),
.ACK_I(wb_ack_i),
.ERR_I(wb_err_i),
.DAT_I(wb_mdat_i),
.clk_i(wb_clk_i),
.rst_i(wb_rst_i),
.nrst_i(arst),
.cyc_o(wbm_cyc_o),
.stb_o(wbm_stb_o),
.cab_o(wbm_cab_o),
.we_o(wbm_we_o),
.adr_o(wbm_adr_o),
.sel_o(wbm_sel_o),
.ack_i(wbm_ack_i),
.err_i(wbm_err_i),
.dat_i(wbm_dat_i),
 
// internal connections
.SINT(sint),
.sint(sint),
.ctrl_ven(ctrl_ven),
.ctrl_cd(ctrl_cd),
.ctrl_pc(ctrl_pc),
163,24 → 182,50
.ctrl_vbsw(ctrl_vbsw),
.VBAa(VBARa),
.VBAb(VBARb),
.CBA(CBAR),
.Thgate(Thgate),
.Tvgate(Tvgate),
.stat_acmp(stat_acmp),
.stat_avmp(stat_avmp),
.bs_req(bsint),
.vmem_switch(vmem_swint),
.clut_switch(clut_swint),
 
// line fifo memory signals
.line_fifo_wreq(line_fifo_dpm_wreq),
.line_fifo_d(line_fifo_dpm_d),
.line_fifo_full(line_fifo_full_wr)
.line_fifo_full(line_fifo_full_wr),
 
// clut memory signals
.clut_req(cp_clut_req),
.clut_ack(cp_clut_ack),
.clut_adr(cp_clut_adr),
.clut_q(cp_clut_q)
);
 
// hookup CLUT <cycle shared memory>
vga_csm_pb #(24, 9) clut_mem(
.clk_i(wb_clk_i),
 
// color processor access
.req0_i(cp_clut_req),
.ack0_o(cp_clut_ack),
.adr0_i(cp_clut_adr),
.dat0_i(24'h0),
.dat0_o(cp_clut_q),
.we0_i(1'b0), // no writes
 
// external access
.req1_i(clut_req),
.ack1_o(clut_ack),
.adr1_i(wbs_adr_i[10:2]),
.dat1_i(wbs_dat_i[23:0]),
.dat1_o(clut_q),
.we1_i(wbs_we_i)
);
 
// hookup pixel and video timing generator
vga_pgen u3 (
.mclk(wb_clk_i),
.pclk(clk_pclk_i),
.pclk(clk_p_i),
.ctrl_ven(ctrl_ven),
.ctrl_HSyncL(ctrl_hsl),
.Thsync(Thsync),
205,17 → 250,17
 
 
// delay video control signals 1 clock cycle (dual clock fifo synchronizes output)
always@(posedge clk_pclk_i)
always@(posedge clk_p_i)
begin
vga_hsync_pad_o <= #1 ihsync;
vga_vsync_pad_o <= #1 ivsync;
vga_csync_pad_o <= #1 icsync;
vga_blank_pad_o <= #1 iblank;
hsync_pad_o <= #1 ihsync;
vsync_pad_o <= #1 ivsync;
csync_pad_o <= #1 icsync;
blank_pad_o <= #1 iblank;
end
 
// hookup line-fifo
vga_fifo_dc #(LINE_FIFO_AWIDTH, 24) u4 (
.rclk(clk_pclk_i),
.rclk(clk_p_i),
.wclk(wb_clk_i),
.aclr(ctrl_ven),
.wreq(line_fifo_dpm_wreq),
228,18 → 273,18
.wr_full(line_fifo_full_wr)
);
 
assign vga_r_pad_o = line_fifo_dpm_q[23:16];
assign vga_g_pad_o = line_fifo_dpm_q[15: 8];
assign vga_b_pad_o = line_fifo_dpm_q[ 7: 0];
assign r_pad_o = line_fifo_dpm_q[23:16];
assign g_pad_o = line_fifo_dpm_q[15: 8];
assign b_pad_o = line_fifo_dpm_q[ 7: 0];
 
// generate interrupt signal when reading line-fifo while it is empty (line-fifo under-run interrupt)
reg luint_pclk, sluint;
 
always@(posedge clk_pclk_i)
always@(posedge clk_p_i)
luint_pclk <= #1 cgate & line_fifo_empty_rd;
 
always@(posedge wb_clk_i or negedge rst_nreset_i)
if (!rst_nreset_i)
always@(posedge wb_clk_i or negedge arst)
if (!arst)
begin
sluint <= #1 1'b0;
luint <= #1 1'b0;
262,3 → 307,6
 
endmodule
 
 
 
 
/trunk/rtl/verilog/vga_wb_slave.v
2,14 → 2,15
// file: wb_slave.v
// project: VGA/LCD controller
// author: Richard Herveille
// rev 1.0 August 6th, 2001. Initial verilog release
// rev. 1.0 August 6th, 2001. Initial verilog release
// rev. 2.0 October 2nd, 2001. Revised core. Moved color lookup-table to color processor. Changed wishbone slave to access clut, made outputs registered.
//
 
`include "timescale.v"
 
module vga_wb_slave(CLK_I, RST_I, nRESET, ADR_I, DAT_I, DAT_O, SEL_I, WE_I, STB_I, CYC_I, ACK_O, ERR_O, INTA_O,
bl, csl, vsl, hsl, pc, cd, vbl, cbsw, vbsw, ven, avmp, acmp, bsint_in, hint_in, vint_in, luint_in, sint_in,
Thsync, Thgdel, Thgate, Thlen, Tvsync, Tvgdel, Tvgate, Tvlen, VBARa, VBARb, CBAR);
bl, csl, vsl, hsl, pc, cd, vbl, cbsw, vbsw, ven, avmp, acmp, vbsint_in, cbsint_in, hint_in, vint_in, luint_in, sint_in,
Thsync, Thgdel, Thgate, Thlen, Tvsync, Tvgdel, Tvgate, Tvlen, VBARa, VBARb, clut_acc, clut_ack, clut_q);
 
//
// inputs & outputs
19,7 → 20,7
input CLK_I;
input RST_I;
input nRESET;
input [ 4:2] ADR_I;
input [11:2] ADR_I;
input [31:0] DAT_I;
output [31:0] DAT_O;
reg [31:0] DAT_O;
28,8 → 29,11
input STB_I;
input CYC_I;
output ACK_O;
reg ACK_O;
output ERR_O;
reg ERR_O;
output INTA_O;
reg INTA_O;
 
// control register settings
output bl; // blanking level
44,13 → 48,14
output ven; // vdeio system enable
 
// status register inputs
input avmp; // active video memory page
input acmp; // active clut memory page
input bsint_in; // bank switch interrupt request
input hint_in; // hsync interrupt request
input vint_in; // vsync interrupt request
input luint_in; // line fifo underrun interrupt request
input sint_in; // system error interrupt request
input avmp; // active video memory page
input acmp; // active clut memory page
input vbsint_in; // bank switch interrupt request
input cbsint_in; // clut switch interrupt request
input hint_in; // hsync interrupt request
input vint_in; // vsync interrupt request
input luint_in; // line fifo underrun interrupt request
input sint_in; // system error interrupt request
 
// Horizontal Timing Register
output [ 7:0] Thsync;
64,16 → 69,24
output [15:0] Tvgate;
output [15:0] Tvlen;
 
// video base addresses
output [31: 2] VBARa;
reg [31: 2] VBARa;
output [31: 2] VBARb;
reg [31: 2] VBARb;
output [31:11] CBAR;
reg [31:11] CBAR;
 
// color lookup table signals
output clut_acc;
input clut_ack;
input [23:0] clut_q;
 
 
//
// variable declarations
//
wire [2:0] REG_ADR = ADR_I[4:2];
wire CLUT_ADR = ADR_I[11];
 
parameter [2:0] CTRL_ADR = 3'b000;
parameter [2:0] STAT_ADR = 3'b001;
parameter [2:0] HTIM_ADR = 3'b010;
81,25 → 94,33
parameter [2:0] HVLEN_ADR = 3'b100;
parameter [2:0] VBARA_ADR = 3'b101;
parameter [2:0] VBARB_ADR = 3'b110;
parameter [2:0] CBAR_ADR = 3'b111;
 
 
reg [31:0] ctrl, stat, htim, vtim, hvlen;
wire HINT, VINT, BSINT, LUINT, SINT;
wire hie, vie, bsie;
wire acc, acc32, reg_acc;
wire hint, vint, vbsint, cbsint, luint, sint;
wire hie, vie, vbsie, cbsie;
wire acc, acc32, reg_acc, reg_wacc;
 
 
reg [31:0] reg_dato; // data output from registers
 
//
// Module body
//
 
assign acc = CYC_I & STB_I;
assign acc32 = (SEL_I == 4'b1111);
assign reg_acc = acc & acc32 & WE_I;
assign ACK_O = acc & acc32;
assign ERR_O = acc & !acc32;
assign acc = CYC_I & STB_I;
assign acc32 = (SEL_I == 4'b1111);
assign clut_acc = CLUT_ADR & acc & acc32;
assign reg_acc = !CLUT_ADR & acc & acc32;
assign reg_wacc = reg_acc & WE_I;
 
always@(posedge CLK_I)
ACK_O <= #1 ((reg_acc & acc32) | clut_ack) & !ACK_O;
 
always@(posedge CLK_I)
ERR_O <= #1 acc & !acc32;
 
 
// generate registers
always@(posedge CLK_I or negedge nRESET)
begin : gen_regs
110,7 → 131,6
hvlen <= #1 0;
VBARa <= #1 0;
VBARb <= #1 0;
CBAR <= #1 0;
end
else if (RST_I)
begin
119,9 → 139,8
hvlen <= #1 0;
VBARa <= #1 0;
VBARb <= #1 0;
CBAR <= #1 0;
end
else if (reg_acc)
else if (reg_wacc)
case (ADR_I) // synopsis full_case parallel_case
HTIM_ADR : htim <= #1 DAT_I;
VTIM_ADR : vtim <= #1 DAT_I;
128,7 → 147,6
HVLEN_ADR : hvlen <= #1 DAT_I;
VBARA_ADR : VBARa <= #1 DAT_I[31: 2];
VBARB_ADR : VBARb <= #1 DAT_I[31: 2];
CBAR_ADR : CBAR <= #1 DAT_I[31:11];
endcase
end
 
139,12 → 157,12
ctrl <= #1 0;
else if (RST_I)
ctrl <= #1 0;
else if (reg_acc & (ADR_I == CTRL_ADR) )
else if (reg_wacc & (REG_ADR == CTRL_ADR) )
ctrl <= #1 DAT_I;
else
begin
ctrl[5] <= #1 ctrl[5] & !bsint_in;
ctrl[4] <= #1 ctrl[4] & !bsint_in;
ctrl[6] <= #1 ctrl[6] & !cbsint_in;
ctrl[5] <= #1 ctrl[5] & !vbsint_in;
end
 
 
158,17 → 176,19
begin
stat[17] <= #1 acmp;
stat[16] <= #1 avmp;
if (reg_acc & (ADR_I == STAT_ADR) )
if (reg_wacc & (REG_ADR == STAT_ADR) )
begin
stat[6] <= #1 bsint_in | (stat[6] & !DAT_I[6]);
stat[5] <= #1 hint_in | (stat[5] & !DAT_I[5]);
stat[4] <= #1 vint_in | (stat[4] & !DAT_I[4]);
stat[1] <= #1 luint_in | (stat[3] & !DAT_I[1]);
stat[0] <= #1 sint_in | (stat[0] & !DAT_I[0]);
stat[7] <= #1 cbsint_in | (stat[7] & !DAT_I[7]);
stat[6] <= #1 vbsint_in | (stat[6] & !DAT_I[6]);
stat[5] <= #1 hint_in | (stat[5] & !DAT_I[5]);
stat[4] <= #1 vint_in | (stat[4] & !DAT_I[4]);
stat[1] <= #1 luint_in | (stat[3] & !DAT_I[1]);
stat[0] <= #1 sint_in | (stat[0] & !DAT_I[0]);
end
else
begin
stat[6] <= #1 stat[6] | bsint_in;
stat[7] <= #1 stat[7] | cbsint_in;
stat[6] <= #1 stat[6] | vbsint_in;
stat[5] <= #1 stat[5] | hint_in;
stat[4] <= #1 stat[4] | vint_in;
stat[1] <= #1 stat[1] | luint_in;
178,26 → 198,28
 
 
// decode control register
assign bl = ctrl[15];
assign csl = ctrl[14];
assign vsl = ctrl[13];
assign hsl = ctrl[12];
assign pc = ctrl[11];
assign cd = ctrl[10:9];
assign vbl = ctrl[8:7];
assign cbsw = ctrl[5];
assign vbsw = ctrl[4];
assign bsie = ctrl[3];
assign hie = ctrl[2];
assign vie = ctrl[1];
assign ven = ctrl[0];
assign bl = ctrl[15];
assign csl = ctrl[14];
assign vsl = ctrl[13];
assign hsl = ctrl[12];
assign pc = ctrl[11];
assign cd = ctrl[10:9];
assign vbl = ctrl[8:7];
assign cbsw = ctrl[6];
assign vbsw = ctrl[5];
assign cbsie = ctrl[4];
assign vbsie = ctrl[3];
assign hie = ctrl[2];
assign vie = ctrl[1];
assign ven = ctrl[0];
 
// decode status register
assign BSINT = stat[6];
assign HINT = stat[5];
assign VINT = stat[4];
assign LUINT = stat[1];
assign SINT = stat[0];
assign cbsint = stat[7];
assign vbsint = stat[6];
assign hint = stat[5];
assign vint = stat[4];
assign luint = stat[1];
assign sint = stat[0];
 
// decode Horizontal Timing Register
assign Thsync = htim[31:24];
213,18 → 235,23
 
// assign output
always@(ADR_I or ctrl or stat or htim or vtim or hvlen or VBARa or VBARb or CBAR or acmp)
case (ADR_I) // synopsis full_case parallel_case
CTRL_ADR : DAT_O = ctrl;
STAT_ADR : DAT_O = stat;
HTIM_ADR : DAT_O = htim;
VTIM_ADR : DAT_O = vtim;
HVLEN_ADR : DAT_O = hvlen;
VBARA_ADR : DAT_O = {VBARa, 2'b0};
VBARB_ADR : DAT_O = {VBARb, 2'b0};
CBAR_ADR : DAT_O = {CBAR, acmp, 10'b0};
always@(REG_ADR or ctrl or stat or htim or vtim or hvlen or VBARa or VBARb or acmp)
case (REG_ADR) // synopsis full_case parallel_case
CTRL_ADR : reg_dato = ctrl;
STAT_ADR : reg_dato = stat;
HTIM_ADR : reg_dato = htim;
VTIM_ADR : reg_dato = vtim;
HVLEN_ADR : reg_dato = hvlen;
VBARA_ADR : reg_dato = {VBARa, 2'b0};
VBARB_ADR : reg_dato = {VBARb, 2'b0};
default : reg_dato = 32'h0000_0000;
endcase
 
always@(posedge CLK_I)
DAT_O <= #1 reg_acc ? reg_dato : {8'h0, clut_q};
 
// generate interrupt request signal
assign INTA_O = (HINT & hie) | (VINT & vie) | (BSINT & bsie) | LUINT | SINT;
always@(posedge CLK_I)
INTA_O <= #1 (hint & hie) | (vint & vie) | (vbsint & vbsie) | (cbsint & cbsie) | luint | sint;
endmodule
 
/trunk/rtl/verilog/vga_csm_pb.v
1,16 → 1,14
//
// Wishbone compliant cycle shared memory, priority based selection
// Cycle shared memory, priority based selection (port0 has higher priority than port1)
// author: Richard Herveille
//
// rev.: 1.0 August 13th, 2001. Initial Verilog release
//
// rev.: 1.0 August 13th, 2001. Initial Verilog release
// rev.: 1.1 October 2nd, 2001. Removed wishbone interface
//
 
`include "timescale.v"
 
module vga_csm_pb (wb_clk_i, wb_rst_i, rst_nreset_i,
wb_adr0_i, wb_dat0_i, wb_dat0_o, wb_sel0_i, wb_we0_i, wb_stb0_i, wb_cyc0_i, wb_ack0_o, wb_err0_o,
wb_adr1_i, wb_dat1_i, wb_dat1_o, wb_sel1_i, wb_we1_i, wb_stb1_i, wb_cyc1_i, wb_ack1_o, wb_err1_o );
module vga_csm_pb (clk_i, req0_i, ack0_o, adr0_i, dat0_i, dat0_o, we0_i, req1_i, ack1_o, adr1_i, dat1_i, dat1_o, we1_i);
//
// parameters
22,32 → 20,23
// inputs & outputs
//
// syscon signals
input wb_clk_i; // wishbone clock input
input wb_rst_i; // wishbone active high synchronous reset input
input rst_nreset_i; // active low asynchronous input
input clk_i; // clock input
 
// wishbone slave0 connections
input [ AWIDTH -1:0] wb_adr0_i; // address input
input [ DWIDTH -1:0] wb_dat0_i; // data input
output [ DWIDTH -1:0] wb_dat0_o; // data output
input [(DWIDTH/8)-1:0] wb_sel0_i; // byte select input
input wb_we0_i; // write enable input
input wb_stb0_i; // strobe/select input
input wb_cyc0_i; // valid bus cycle input
output wb_ack0_o; // acknowledge output
output wb_err0_o; // error output
input [ AWIDTH -1:0] adr0_i; // address input
input [ DWIDTH -1:0] dat0_i; // data input
output [ DWIDTH -1:0] dat0_o; // data output
input we0_i; // write enable input
input req0_i; // access request input
output ack0_o; // access acknowledge output
 
// wishbone slave1 connections
input [ AWIDTH -1:0] wb_adr1_i; // address input
input [ DWIDTH -1:0] wb_dat1_i; // data input
output [ DWIDTH -1:0] wb_dat1_o; // data output
input [(DWIDTH/8)-1:0] wb_sel1_i; // byte select input
input wb_we1_i; // write enable input
input wb_stb1_i; // strobe/select input
input wb_cyc1_i; // valid bus cycle input
output wb_ack1_o; // acknowledge output
output wb_err1_o; // error output
input [ AWIDTH -1:0] adr1_i; // address input
input [ DWIDTH -1:0] dat1_i; // data input
output [ DWIDTH -1:0] dat1_o; // data output
input we1_i; // write enable input
input req1_i; // access request input
output ack1_o; // access acknowledge output
 
//
// variable declarations
54,14 → 43,11
//
 
// multiplexor select signal
wire wb0_acc, wb1_acc;
reg dwb0_acc, dwb1_acc;
wire sel_wb0, sel_wb1;
wire acc0, acc1;
reg dacc0, dacc1;
wire sel0, sel1;
reg ack0, ack1;
// acknowledge generation
wire wb0_ack, wb1_ack;
 
// memory data output
wire [DWIDTH -1:0] mem_q;
 
71,42 → 57,31
//
 
// generate multiplexor select signal
assign wb0_acc = wb_cyc0_i && wb_stb0_i;
assign wb1_acc = wb_cyc1_i && wb_stb1_i && !sel_wb0;
assign acc0 = req0_i;
assign acc1 = req1_i && !sel0;
 
always@(posedge wb_clk_i)
always@(posedge clk_i)
begin
dwb0_acc <= #1 wb0_acc & !wb0_ack;
dwb1_acc <= #1 wb1_acc & !wb1_ack;
dacc0 <= #1 acc0 & !ack0_o;
dacc1 <= #1 acc1 & !ack1_o;
end
 
assign sel_wb0 = wb0_acc && !dwb0_acc;
assign sel_wb1 = wb1_acc && !dwb1_acc;
assign sel0 = acc0 && !dacc0;
assign sel1 = acc1 && !dacc1;
 
always@(posedge wb_clk_i or negedge rst_nreset_i)
if (!rst_nreset_i)
begin
ack0 <= #1 0;
ack1 <= #1 0;
end
else if (wb_rst_i)
begin
ack0 <= #1 0;
ack1 <= #1 0;
end
else
begin
ack0 <= #1 sel_wb0 && !wb0_ack;
ack1 <= #1 sel_wb1 && !wb1_ack;
end
always@(posedge clk_i)
begin
ack0 <= #1 sel0 && !ack0_o;
ack1 <= #1 sel1 && !ack1_o;
end
 
wire [AWIDTH -1:0] mem_adr = sel_wb0 ? wb_adr0_i : wb_adr1_i;
wire [DWIDTH -1:0] mem_d = sel_wb0 ? wb_dat0_i : wb_dat1_i;
wire mem_we = sel_wb0 ? wb_we0_i && wb_cyc0_i && wb_stb0_i : wb_we1_i && wb_cyc1_i && wb_stb1_i;
wire [AWIDTH -1:0] mem_adr = sel0 ? adr0_i : adr1_i;
wire [DWIDTH -1:0] mem_d = sel0 ? dat0_i : dat1_i;
wire mem_we = sel0 ? req0_i && we0_i : req1_i && we1_i;
 
// hookup generic synchronous single port memory
generic_spram #(AWIDTH, DWIDTH) clut_mem(
.clk(wb_clk_i),
.clk(clk_i),
.rst(1'b0), // no reset
.ce(1'b1), // always enable memory
.we(mem_we),
117,19 → 92,12
);
 
// assign DAT_O outputs
assign wb_dat0_o = mem_q;
assign wb_dat1_o = mem_q;
assign dat0_o = mem_q;
assign dat1_o = mem_q;
 
// generate ack signals
assign wb0_ack = ( (sel_wb0 && wb_we0_i) || ack0 );
assign wb1_ack = ( (sel_wb1 && wb_we1_i) || ack1 );
// generate ack outputs
assign ack0_o = ( (sel0 && we0_i) || ack0 );
assign ack1_o = ( (sel1 && we1_i) || ack1 );
endmodule
 
// ACK outputs
assign wb_ack0_o = wb0_ack;
assign wb_ack1_o = wb1_ack;
 
// ERR outputs
assign wb_err0_o = !(&wb_sel0_i) && wb_cyc0_i && wb_stb0_i;
assign wb_err1_o = !(&wb_sel1_i) && wb_cyc1_i && wb_stb1_i;
 
endmodule
/trunk/rtl/verilog/vga_defines.v
0,0 → 1,5
//
// define memory vendor
//
 
`define VENDOR_FPGA

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