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URL https://opencores.org/ocsvn/video_systems/video_systems/trunk

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Rev 18 → Rev 19

/trunk/common/h264/rtl/vhdl/h264components.vhd
102,12 → 102,16
);
end component h264intra8x8cc;
--
component h264predp is
component h264interz is
generic (
MVB : integer := 2 --bits to encode MV
);
port (
CLK : in std_logic; --pixel clock
--
-- in interface:
FIRST : in std_logic; --indication this is the first on a line
NEWSLICE : in std_logic; --indication this is the first in a slice
NEWLINE : in std_logic; --indication this is the first on a line
STROBEI : in std_logic; --data here
PREVI : in std_logic; --1=previous frame, 0=new data to encode
DATAI : in std_logic_vector(31 downto 0);
114,9 → 118,10
READYI : out std_logic := '0';
--
-- top interface:
TOPV : in std_logic; --set if TVEC* valid (not first)
TVECXI : in std_logic_vector(3 downto 0); --top blocks prediction X vector
TVECYI : in std_logic_vector(3 downto 0); --top blocks prediction Y vector
TVECXI : in std_logic_vector(MVB-1 downto 0) := (others=>'0'); --top block's X vector
TVECYI : in std_logic_vector(MVB-1 downto 0) := (others=>'0'); --top block's Y vector
SVECXI : in std_logic_vector(MVB-1 downto 0) := (others=>'0'); --suggested X vector
SVECYI : in std_logic_vector(MVB-1 downto 0) := (others=>'0'); --suggested Y vector
XXINC : out std_logic := '0'; --when to increment XX macroblock
--
-- out interface:
123,8 → 128,8
STROBEO : out std_logic := '0'; --data here
DATAO : out std_logic_vector(35 downto 0) := (others => '0');
READYO : in std_logic;
VECXO : out std_logic_vector(3 downto 0) := (others => '0');--vector X, signed
VECYO : out std_logic_vector(3 downto 0) := (others => '0') --vector Y, signed
VECXO : out std_logic_vector(MVB-1 downto 0) := (others => '0');--vector X, signed
VECYO : out std_logic_vector(MVB-1 downto 0) := (others => '0') --vector Y, signed
);
end component;
--
144,15 → 149,14
CLK : in std_logic; --fast io clock
ENABLE : in std_logic; --values input only when this is 1
WIN : in std_logic_vector(15 downto 0); --input (reverse zigzag order)
LAST : out std_logic := '0'; --set when last coeff (C00) about to be input
VALID : out std_logic := '0'; --values output only when this is 1
XOUT : out std_logic_vector(35 downto 0) --4 x 9bit, first px is lsbs
XOUT : out std_logic_vector(39 downto 0) --4 x 10bit, first px is lsbs
);
end component;
--
component h264dctransform is
generic (
TOGETHER : boolean := false --true if output kept together as one block
TOGETHER : integer := 0 --1 if output kept together as one block
);
port (
CLK2 : in std_logic; --fast io clock
187,7 → 191,7
CLK : in std_logic; --pixel clock
ENABLE : in std_logic; --values transfered only when this is 1
QP : in std_logic_vector(5 downto 0); --0..51 as specified in standard
ZIN : in std_logic_vector(11 downto 0);
ZIN : in std_logic_vector(15 downto 0);
DCCI : in std_logic; --2x2 DC chroma in
LAST : out std_logic := '0'; --set when last coeff about to be input
WOUT : out std_logic_vector(15 downto 0) := (others=>'0');
203,7 → 207,7
-- in interface:
NEWSLICE : in std_logic; --reset
STROBEI : in std_logic; --data here
DATAI : in std_logic_vector(35 downto 0);
DATAI : in std_logic_vector(39 downto 0);
BSTROBEI : in std_logic; --base data here
BCHROMAI : in std_logic; --chroma
BASEI : in std_logic_vector(31 downto 0);
/trunk/common/h264/rtl/vhdl/h264topskeleton.vhd
105,6 → 105,7
end h264topskeleton;
 
architecture hw of h264topskeleton is
--
signal intra4x4_TOPI : std_logic_vector(31 downto 0) := (others => '0');
signal intra4x4_TOPMI : std_logic_vector(3 downto 0) := (others => '0');
signal intra4x4_STROBEO : std_logic := '0'; --values transfered out when this is 1
153,7 → 154,7
signal quantise_dcco : std_logic := '0';
--
signal dequantise_enable : std_logic := '0';
signal dequantise_zin : std_logic_vector(11 downto 0);
signal dequantise_zin : std_logic_vector(15 downto 0);
signal dequantise_last : std_logic := '0';
signal dequantise_valid : std_logic := '0';
signal dequantise_dcco : std_logic := '0';
165,11 → 166,8
signal invdctransform_yyout : std_logic_vector(15 downto 0);
signal invdctransform_ready : std_logic := '0';
--
--signal invtransform_enable : std_logic := '0';
--signal invtransform_win : std_logic_vector(15 downto 0);
--signal invtransform_last : std_logic := '0';
signal invtransform_valid : std_logic := '0';
signal invtransform_xout : std_logic_vector(35 downto 0);
signal invtransform_xout : std_logic_vector(39 downto 0);
--
signal recon_BSTROBEI : std_logic := '0'; --values transfered only when this is 1
signal recon_basei : std_logic_vector(31 downto 0) := (others => '0');
183,7 → 181,6
signal xbuffer_NV : std_logic_vector(1 downto 0); --valid flags for NIN/NOUT (1=left, 2=top, 3=avg)
signal xbuffer_NXINC : std_logic := '0'; --increment for X macroblock counter
signal xbuffer_READYI : std_logic := '0';
--signal xbuffer_DCREADYI : std_logic := '0';
signal xbuffer_CCIN : std_logic := '0';
--
signal cavlc_ENABLE : std_logic := '0'; --values transfered only when this is 1
331,10 → 328,10
recon_basei <= intra4x4_baseo when intra4x4_strobeo='1' else intra8x8cc_baseo;
--
dctransform : h264dctransform
generic map ( TOGETHER => true )
generic map ( TOGETHER => 1 )
port map (
CLK2 => clk2,
RESET => NEWslice,
RESET => newslice,
--READYI =>
ENABLE => intra8x8cc_dcstrobeo,
XXIN => intra8x8cc_dcdatao,
361,7 → 358,7
invdctransform : h264dctransform
port map (
CLK2 => clk2,
RESET => NEWslice,
RESET => newslice,
--READYI =>
ENABLE => invdctransform_enable,
XXIN => invdctransform_zin,
387,7 → 384,7
VALID => dequantise_valid
);
dequantise_enable <= quantise_valid and not quantise_dcco;
dequantise_zin <= quantise_zout when invdctransform_valid='0' else invdctransform_yyout(11 downto 0); --WIDTH!!
dequantise_zin <= sxt(quantise_zout,16) when invdctransform_valid='0' else invdctransform_yyout;
--
invtransform : h264invtransform
port map (
394,12 → 391,9
CLK => clk2,
ENABLE => dequantise_valid,
WIN => dequantise_wout,
--LAST => invtransform_last,
VALID => invtransform_valid,
XOUT => invtransform_xout
);
--invtransform_enable <= dequantise_valid and not dequantise_dcco;
--invtransform_win <= dequantise_wout when invdctransform_valid='0' else invdctransform_yyout;
--
recon : h264recon
port map (
533,3 → 527,4
end process;
--
end hw;
 

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