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  • This comparison shows the changes necessary to convert path 
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    from Rev 180 to Rev 181
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Rev 180 → Rev 181

/raytrac/branches/fp/im.vhd
33,10 → 33,9
);
port (
clk,rst: in std_logic;
rfull_events: in std_logic_vector(num_events-1 downto 0); --! full results queue events
eoi_events: in std_logic_vector(num_events-1 downto 0); --! end of instruction related events
eoi_int: out std_logic_vector(num_events-1 downto 0);--! end of instruction related interruptions
rfull_int: out std_logic_vector(num_events-1downto 0); --! full results queue related interruptions
rfull_event: in std_logic;
eoi_event: in std_logic; --! end of instruction related events
int: out std_logic; --! interruption
state: out iCtrlState
);
47,55 → 46,37
signal s_state : iCtrlState;
signal s_event_polling_chain : std_logic_vector(num_events-1 downto 0);
signal s_eoi_events : std_logic_vector(num_events-1 downto 0);
begin
state <= s_state;
--! Existen 2 estados para disparar la se&ntilde;al de interrupci&oacute;n : WAITING_FOR_A_RFULL_EVENT y INHIBIT_RFULL_INT. Siempre que haya el final de una instrucci&oacute;n en cualquiera de los dos estados se notificar&aacute; el evento sin importar el estado en que se encuentre la m&aacute;quina.
--! Si cualquiera de las se&ntilde;ales de cola llena se encuentra activa, el evento ser&aacute; notificado en el estado WAITING_FOR_A_RFULL_EVENT, inmediatamente se cambia al estado INHIBIT_RFULL_INT, donde durante un n&uacte;mero de ciclos (parametrizado) se ignora la se&ntilde;al de full de las colas de resultados.
--! Despues que han transcurrido los ciclos mencionados, se vuelve al estado WAITING_FOR_A_RFULL_EVENT.
sm_proc:
process (clk,rst,s_event_polling_chain,rfull_events,eoi_events)
process (clk,rst)
variable tempo : integer range 0 to cycles_to_wait:=cycles_to_wait;
begin
if rst=rstMasterValue then
tempo := cycles_to_wait;
s_state <= WAITING_FOR_AN_EVENT;
s_event_polling_chain <= (others => '0');
s_eoi_events <= (others => '0');
rfull_int <= (others => '0');
eoi_int <= (others => '0');
int <= '0';
elsif clk'event and clk='1' then
for i in num_events-1 downto 0 loop
if s_eoi_events(i)='0' then --! Hooking events
s_eoi_events(i) <= eoi_events(i);
else --! Event Hooked
s_eoi_events(i) <= not(s_event_polling_chain(i));
end if;
rfull_int(i) <= s_event_polling_chain(i) and rfull_events(i);
eoi_int(i) <= s_event_polling_chain(i) and s_eoi_events(i);
case s_state is
when WAITING_FOR_A_RFULL_EVENT =>
end loop;
case s_state is
when WAITING_FOR_AN_EVENT =>
for i in num_events-1 downto 0 loop
if rfull_events(i)='1' then
s_state <= FIRING_INTERRUPTIONS;
s_event_polling_chain(0) <= '1';
end if;
end loop;
when FIRING_INTERRUPTIONS =>
if s_event_polling_chain(num_events-1)='1' then
s_state <= SUSPEND;
tempo := cycles_to_wait;
int <= rfull_event or eoi_event;
if rfull_event='1' then
s_state <= INHIBIT_RFULL_INT;
end if;
for i in num_events-1 downto 1 loop
s_event_polling_chain(i) <= s_event_polling_chain(i-1);
end loop;
s_event_polling_chain(0) <= '0';
when SUSPEND =>
when INHIBIT_RFULL_INT =>
int <= eoi_event;
if tempo=0 then
s_state <= WAITING_FOR_AN_EVENT;
s_state <= WAITING_FOR_A_RFULL_EVENT;
tempo := cycles_to_wait;
else
tempo:=tempo-1;
end if;
/raytrac/branches/fp/raytrac.vhd
45,7 → 45,7
d : in std_logic_vector (31 downto 0);
--! Interrupciones
int07,int06,int05,int04,int03,int02,int01,int00 : out std_logic;
int : out std_logic;
--! Salidas
q : out std_logic_vector (31 downto 0)
127,19 → 127,12
--!TBXSTART:IM
--! Se&ntilde;ales de Interruption Machine al testbench
signal s_iCtrlState : iCtrlState;
signal s_int : std_logic_vector (7 downto 0);
signal s_int : std_logic;
--!TBXEND
begin
 
--! Sacar las interrupciones
int07 <= s_int(7);
int06 <= s_int(6);
int05 <= s_int(5);
int04 <= s_int(4);
int03 <= s_int(3);
int02 <= s_int(2);
int01 <= s_int(1);
int00 <= s_int(0);
int <= s_int;
--! Signo de los bloques de suma
s_sign <= not(s_dpc_uca(2)) and s_dpc_uca(1);
148,11 → 141,6
s_int_rd_add <= s_addb&s_adda;
--!TBXINSTANCESTART
MemoryBlock : memblock
generic map (
blocksize => 512,
external_readable_widthad => 3,
external_writeable_widthad => 4
)
port map (
clk => clk,
rst => rst,
166,10 → 154,11
ext_rd => rd,
ext_wr => wr,
ext_wr_add => add,
ext_rd_add => add(12 downto 10),
ext_rd_add => add(12 downto 9),
ext_d => d,
resultfifo_full => s_rfull_events,
int_d => s_results_d,
status_register => s_eoi_events,
ext_q => q,
instrfifo_q => s_iq,
int_q => s_q,
263,10 → 252,9
port map (
clk => clk,
rst => rst,
rfull_events => s_rfull_events,
eoi_events => s_eoi_events,
eoi_int => s_int(3 downto 0),
rfull_int => s_int(7 downto 4),
rfull_event => s_full_r,
eoi_event => s_eoi,
int => s_int,
state => s_iCtrlState
);
/raytrac/branches/fp/arithpack.vhd
20,7 → 20,7
--! Estados para la maquina de estados.
type macState is (LOAD_INSTRUCTION,FLUSH_ARITH_PIPELINE,EXECUTE_INSTRUCTION);
--! Estados para el controlador de interrupciones.
type iCtrlState is (WAITING_FOR_AN_EVENT,FIRING_INTERRUPTIONS,SUSPEND);
type iCtrlState is (WAITING_FOR_A_RFULL_EVENT,INHIBIT_RFULL_INT);
--! Float data blocks
constant floatwidth : integer := 32;
70,7 → 70,7
d : in std_logic_vector (31 downto 0);
--! Interrupciones
int : out std_logic_vector (7 downto 0);
int : out std_logic;
--! Salidas
q : out std_logic_vector (31 downto 0)
235,20 → 235,14
);
port (
clk,rst: in std_logic;
rfull_events: in std_logic_vector(num_events-1 downto 0); --! full results queue events
eoi_events: in std_logic_vector(num_events-1 downto 0); --! end of instruction related events
eoi_int: out std_logic_vector(num_events-1 downto 0);--! end of instruction related interruptions
rfull_int: out std_logic_vector(num_events-1downto 0); --! full results queue related interruptions
rfull_event: in std_logic; --! full results queue events
eoi_event: in std_logic; --! end of instruction related events
int: out std_logic;
state: out iCtrlState
);
end component;
--! Bloque de memorias
component memblock
generic (
blocksize : integer;
external_readable_widthad : integer;
external_writeable_widthad : integer
);
port (
256,10 → 250,13
instrfifo_rd : in std_logic;
resultfifo_wr: in std_logic_vector(8-1 downto 0);
instrfifo_empty: out std_logic; ext_rd,ext_wr: in std_logic;
ext_wr_add : in std_logic_vector(external_writeable_widthad+widthadmemblock-1 downto 0);
ext_rd_add : in std_logic_vector(external_readable_widthad-1 downto 0);
ext_wr_add : in std_logic_vector(4+widthadmemblock-1 downto 0);
ext_rd_add : in std_logic_vector(3 downto 0);
ext_d: in std_logic_vector(floatwidth-1 downto 0);
int_d : in vectorblock08;
status_register : in std_logic_vector(3 downto 0);
resultfifo_full : out std_logic_vector(3 downto 0);
ext_q,instrfifo_q : out std_logic_vector(floatwidth-1 downto 0);
int_q : out vectorblock12;
549,12 → 546,10
write(l,string'("<< "));
case i is
when WAITING_FOR_AN_EVENT =>
tmp:="WAIT_EVNT";
when FIRING_INTERRUPTIONS =>
tmp:="FIRE_INTx";
when SUSPEND =>
tmp:="SUSPENDED";
when WAITING_FOR_A_RFULL_EVENT =>
tmp:="WAIT_RF_EVNT";
when INHIBIT_RFULL_INT =>
tmp:="INHB_RF_INT";
when others =>
tmp:="ILGL__VAL";
end case;
/raytrac/branches/fp/rt_tb.vhd
21,7 → 21,7
signal sd,sq : xfloat32;
--!TBXEND
--!TXBXSTART:INT_BUS
signal sint : std_logic_vector(7 downto 0);
signal sint : std_logic;
--!TBXEND
begin
/raytrac/branches/fp/memblock.vhd
40,12 → 40,13
instrfifo_empty: out std_logic;
ext_rd,ext_wr: in std_logic;
ext_wr_add : in std_logic_vector(4+widthadmemblock-1 downto 0);
ext_rd_add : in std_logic_vector(2 downto 0);
ext_rd_add : in std_logic_vector(3 downto 0);
ext_d: in std_logic_vector(floatwidth-1 downto 0);
resultfifo_full : out std_logic_vector(3 downto 0);
int_d : in vectorblock08;
--!Python
status_register : in std_logic_vector(3 downto 0);
ext_q,instrfifo_q : out std_logic_vector(floatwidth-1 downto 0);
int_q : out vectorblock12;
int_rd_add : in std_logic_vector(2*widthadmemblock-1 downto 0);
60,8 → 61,8
 
 
--!TXBXSTART:MEMBLOCK_EXTERNAL_WRITE
signal s0ext_wr_add_one_hot : std_logic_vector(12-1+1 downto 0); --! La se&ntilde;al extra es para la escritura de la cola de instrucciones.
signal s0ext_wr_add : std_logic_vector(4+widthadmemblock-1 downto 0);
72,13 → 73,12
signal s0ext_wr_add_choice : std_logic_vector(3 downto 0);
--!TXBXSTART:MEMBLOCK_EXTERNAL_READ
signal s0ext_rd_add : std_logic_vector(2 downto 0);
signal s0status_register : std_logic_vector(7 downto 0);
signal s0ext_rd_add : std_logic_vector(3 downto 0);
signal s0ext_rd : std_logic;
signal s0ext_rd_ack : std_logic_vector(8-1 downto 0);
signal s0ext_q : vectorblock08;
--!TBXEND
--! Se&ntilde;al de soporte
signal s0ext_rd_add_choice : std_logic_vector(3 downto 0);
--!TBXSTART:MEMBLOCK_INTERNAL_READ
92,7 → 92,11
--!TBXEND
 
begin
 
 
--! Colas internas de producto punto, ubicada en el pipe line aritm&eacute;co. Paralelo a los sumadores a0 y a2.
q0q1 : scfifo --! Debe ir registrada la salida.
generic map (
312,7 → 316,7
end process;
--! Decodificaci&oacute;n para seleccionar que cola de resultados se conectar&acute; a la salida del RayTrac.
s0ext_rd_add_choice <= '0'&s0ext_rd_add;
results_block_proc: process(clk,rst)
begin
if rst=rstMasterValue then
323,7 → 327,7
s0ext_rd_add <= ext_rd_add;
s0ext_rd <= ext_rd;
--!Etapa 0: Decodificar la cola que se va a mover (rdack! fifo showahead mode) y por ende leer ese dato.
case s0ext_rd_add_choice is
case s0ext_rd_add is
when x"0" => ext_q <= s0ext_q(0);
when x"1" => ext_q <= s0ext_q(1);
when x"2" => ext_q <= s0ext_q(2);
331,15 → 335,16
when x"4" => ext_q <= s0ext_q(4);
when x"5" => ext_q <= s0ext_q(5);
when x"6" => ext_q <= s0ext_q(6);
when others => ext_q <= s0ext_q(7);
when x"7" => ext_q <= s0ext_q(7);
when others => ext_q <= x"000000"&s0status_register;
end case;
end if;
end process;
--! rdack decoder para las colas de resultados de salida.
results_block_proc_combinatorial_stage: process(s0ext_rd,s0ext_rd_add_choice)
results_block_proc_combinatorial_stage: process(s0ext_rd,s0ext_rd_add)
begin
case s0ext_rd_add_choice is
case s0ext_rd_add(3 downto 0) is
when x"0" => s0ext_rd_ack <= x"0"&"000"&s0ext_rd;
when x"1" => s0ext_rd_ack <= x"0"&"00"&s0ext_rd&'0';
when x"2" => s0ext_rd_ack <= x"0"&"0"&s0ext_rd&"00";
347,8 → 352,44
when x"4" => s0ext_rd_ack <= "000"&s0ext_rd&x"0";
when x"5" => s0ext_rd_ack <= "00"&s0ext_rd&'0'&x"0";
when x"6" => s0ext_rd_ack <= "0"&s0ext_rd&"00"&x"0";
when others => s0ext_rd_ack <= s0ext_rd&"000"&x"0";
when x"7" => s0ext_rd_ack <= s0ext_rd&"000"&x"0";
when others => s0ext_rd_ack <= (others => '0');
end case;
end process;
--!Proceso para escribir el status register.
--!Independiente del valor rfull(i) o si se lee o no, los bits correspondientes a los eventos de cola de resultados llena, se escriben reloj a reloj.
--!Final de Instrucci&oacute;n: Si ocurre un evento de final de instrucci&oacute;n se escribe el bit de registro correspondiente.
--!Si no hay un evento de final de instrucci&oacute;n entonces se verifica si hay un evento de lectura del status register, si es asi todos los bits correspondientes dentro del registro al evento de fin de instrucci&oacute;n se borran y quedan en cero.
--!Si no hay un evento de final de instrucci&oacite;n y tampoco de lectura del status register entonces se deja el mismo valor del estatus register.
sreg_proc: process (clk,rst,s0ext_rd_add,status_register(3 downto 0))
begin
if rst=rstMasterValue then
s0status_register(7 downto 0) <= (others => '0');
elsif clk'event and clk='1' then
 
--!Sin importar el valor de las se&ntilde;ales de cola de resultados llena, escribir el registro.
s0status_register(7) <= sresultfifo_full(7) or sresultfifo_full(6) or sresultfifo_full(5);
s0status_register(6) <= sresultfifo_full(4) or sresultfifo_full(2);
s0status_register(5) <= sresultfifo_full(3) or sresultfifo_full(2) or sresultfifo_full(1);
s0status_register(4) <= sresultfifo_full(0);
for i in 3 downto 0 loop
--! Si hay evento de fin de instrucci&oacute;n entonces escribir en el bit correspondiente un uno.
if status_register(i)='1' then
s0status_register(i) <= '1';
--! Como no hubo final de instrucci&oacute;n revisar si hay lectura de Status Register y borrarlo.
elsif s0ext_rd_add(3)='1' then
s0status_register(i) <= '0';
--! No ocurrio nada de lo anterior, dejar entonces en el mismo valor el Status Register.
else
s0status_register(i) <= s0status_register(i);
end if;
end loop;
end if;
end process;
end architecture;
 

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