OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 188 to Rev 189
    ↔ Reverse comparison
  •

Rev 188 → Rev 189

/open8_urisc/trunk/VHDL/Open8_pkg.vhd
35,6 → 35,8
-- signals in the ALU and PC records.
-- Seth Henry 03/17/20 Added new subtype and constants for external
-- GP flags.
-- Seth Henry 03/18/20 Added the ceil_log2 function, since it is used in
-- memory sizing calculations.
 
library ieee;
use ieee.std_logic_1164.all;
96,6 → 98,10
Wr_Enable : out std_logic );
end component;
 
-- This function is used to calculate RAM parameters, but is generally
-- useful for making things more generic.
function ceil_log2 (x : in natural) return natural;
 
-------------------------------------------------------------------------------
-- Internal constants and type declarations.
--
268,4 → 274,17
end Open8_pkg;
 
package body Open8_pkg is
 
-- The ceil_log2 function returns the minimum register width required to
-- hold the supplied integer.
function ceil_log2 (x : in natural) return natural is
variable retval : natural;
begin
retval := 1;
while ((2**retval) - 1) < x loop
retval := retval + 1;
end loop;
return retval;
end ceil_log2;
 
end package body;
/open8_urisc/trunk/VHDL/o8_btn_int.vhd
23,8 → 23,7
--
-- VHDL Units : o8_btn_int
-- Description: Detects and reports when a user pushbutton is pressed with an
-- interrupt. Software must clear the flag for additional
-- interrupts to avoid inundating the processor.
-- interrupt.
 
library ieee;
use ieee.std_logic_1164.all;
/open8_urisc/trunk/VHDL/o8_epoch_timer.vhd
1,4 → 1,4
-- Copyright (c)2013 Jeremy Seth Henry
-- Copyright (c)2011, 2019 Jeremy Seth Henry
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
33,11 → 33,16
-- 0x0 AAAAAAAA B0 of Setpoint (W) or Buffered Time(R)
-- 0x1 AAAAAAAA B1 of Setpoint (W) or Buffered Time(R)
-- 0x2 AAAAAAAA B2 of Setpoint (W) or Buffered Time(R)
-- 0x3 DC----BA Control/Status register (RW)
-- 0x3 C-----BA Control/Status register (RW)
-- A = Update Buffered Time from internal timer (W)
-- B = Reset Internal Epoch Time (W)
-- C = Interrupt Enable (RW)
-- D = Alarm State Flag (RW) (write a 1 to clear)
-- C = Alarm State Flag (RW) (write a 1 to clear)
--
-- Revision History
-- Author Date Change
------------------ -------- ---------------------------------------------------
-- Seth Henry 07/28/11 Design Start
-- Seth Henry 12/19/19 Renamed to "o8_epoch_timer" to fit "theme"
 
library ieee;
use ieee.std_logic_1164.all;
88,8 → 93,6
signal epoch_alarm : std_logic;
signal epoch_alarm_q : std_logic;
 
signal epoch_gie : std_logic;
 
begin
 
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
107,14 → 110,13
Wr_En <= '0';
Rd_En <= '0';
Rd_Data <= (others => '0');
epoch_gie <= '0';
Interrupt <= '0';
elsif( rising_edge( Clock ) )then
epoch_tmr <= epoch_tmr + uSec_Tick;
-- Force the lower bits of the setpoint to "11" so that the offset is
-- reduced to 1uS (reproducing the original behavior). Software should
-- always subtract 4uS (-1) from the desired time to compensate
epoch_setpt(1 downto 0) <= "11";
-- Force the lower bits of the setpoint to "11" so that the offset is
-- reduced to 1uS (reproducing the original behavior). Software should
-- always subtract 4uS (-1) from the desired time to compensate
epoch_setpt(1 downto 0) <= "11";
Reg_Addr_q <= Reg_Addr;
Wr_Data_q <= Wr_Data;
 
138,7 → 140,6
if( Wr_Data_q(1) = '1' )then
epoch_tmr <= (others => '0');
end if;
epoch_gie <= Wr_Data_q(6);
if( Wr_Data_q(7) = '1' )then
epoch_alarm <= '0';
end if;
148,14 → 149,13
end if;
 
-- Set and hold on alarm condition
if( (epoch_tmr > epoch_setpt) and (epoch_alarm = '0') )then
if( epoch_tmr > epoch_setpt )then
epoch_alarm <= '1';
end if;
 
epoch_alarm_q <= epoch_alarm;
-- Fire on rising edge of epoch_alarm
Interrupt <= epoch_gie and
(epoch_alarm and not epoch_alarm_q);
Interrupt <= epoch_alarm and not epoch_alarm_q;
 
Rd_Data <= (others => '0');
Rd_En <= Addr_Match and Rd_Enable;
168,8 → 168,7
when "10" =>
Rd_Data <= epoch_buffer(23 downto 16);
when "11" =>
Rd_Data <= epoch_alarm & epoch_gie &
"000000";
Rd_Data <= epoch_alarm & "0000000";
when others => null;
end case;
end if;
/open8_urisc/trunk/VHDL/o8_gpin.vhd
1,4 → 1,4
-- Copyright (c)2013 Jeremy Seth Henry
-- Copyright (c)2006, 2016, 2019 Jeremy Seth Henry
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
23,6 → 23,15
--
-- VHDL Units : o8_gpin
-- Description: Provides a single 8-bit input register
--
-- Note: Cut the path between GPIN and GPIN_q1 for timing analysis
--
-- Revision History
-- Author Date Change
------------------ -------- ---------------------------------------------------
-- Seth Henry 07/28/11 Design Start
-- Seth Henry 12/19/19 Renamed to "o8_gpin" to fit "theme"
-- Seth Henry 12/20/19 Added metastability registers
 
library ieee;
use ieee.std_logic_1164.all;
53,6 → 62,9
alias Comp_Addr is Bus_Address(15 downto 0);
signal Addr_Match : std_logic;
signal Rd_En : std_logic;
signal GPIN_q1 : DATA_TYPE;
signal GPIN_q2 : DATA_TYPE;
signal User_In : DATA_TYPE;
 
begin
64,8 → 76,13
if( Reset = Reset_Level )then
Rd_En <= '0';
Rd_Data <= x"00";
GPIN_q1 <= x"00";
GPIN_q2 <= x"00";
User_In <= x"00";
elsif( rising_edge( Clock ) )then
User_In <= GPIN; -- first stage of double buffer
GPIN_q1 <= GPIN;
GPIN_q2 <= GPIN_q1;
User_In <= GPIN_q2;
 
Rd_Data <= (others => '0');
Rd_En <= Addr_Match;
/open8_urisc/trunk/VHDL/o8_hd44780_4b.vhd
50,18 → 50,6
 
architecture behave of o8_hd44780_4b is
 
-- The ceil_log2 function returns the minimum register width required to
-- hold the supplied integer.
function ceil_log2 (x : in natural) return natural is
variable retval : natural;
begin
retval := 1;
while ((2**retval) - 1) < x loop
retval := retval + 1;
end loop;
return retval;
end ceil_log2;
 
constant User_Addr : std_logic_vector(15 downto 2)
:= Address(15 downto 2);
alias Comp_Addr is Bus_Address(15 downto 2);
/open8_urisc/trunk/VHDL/o8_hd44780_8b.vhd
49,18 → 49,6
 
architecture behave of o8_hd44780_8b is
 
-- The ceil_log2 function returns the minimum register width required to
-- hold the supplied integer.
function ceil_log2 (x : in natural) return natural is
variable retval : natural;
begin
retval := 1;
while ((2**retval) - 1) < x loop
retval := retval + 1;
end loop;
return retval;
end ceil_log2;
 
constant User_Addr : std_logic_vector(15 downto 2)
:= Address(15 downto 2);
alias Comp_Addr is Bus_Address(15 downto 2);
/open8_urisc/trunk/VHDL/o8_rtc.vhd
5,22 → 5,19
-- : to ensure time consistency during accesses. Also provides
-- : a programmable periodic interrupt timer, as well as a uSec
-- : tick for external use.
--
--
-- Register Map:
-- Offset Bitfield Description Read/Write
-- 0x0 AAAAAAAA Periodic Interval Timer in uS (RW)
-- 0x1 -AAAAAAA Tenths (0x00 - 0x99) (RW)
-- 0x2 --AAAAAA Seconds (0x00 - 0x59) (RW)
-- 0x3 --AAAAAA Minutes (0x00 - 0x59) (RW)
-- 0x4 ---AAAAA Hours (0x00 - 0x23) (RW)
-- 0x1 -AAAAAAA Tenths (0x00 - 0x63) (RW)
-- 0x2 --AAAAAA Seconds (0x00 - 0x3B) (RW)
-- 0x3 --AAAAAA Minutes (0x00 - 0x3B) (RW)
-- 0x4 ---AAAAA Hours (0x00 - 0x17) (RW)
-- 0x5 -----AAA Day of Week (0x00 - 0x06) (RW)
-- 0x6 -------- Update RTC regs from Shadow Regs (WO)
-- 0x7 A------- Update Shadow Regs from RTC regs (RW)
-- A = Update is Busy
--
-- Note that values are stored in packed BCD, not hex
 
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
32,9 → 29,9
 
entity o8_rtc is
generic(
Address : ADDRESS_TYPE;
Sys_Freq : real;
Reset_Level : std_logic;
Sys_Freq : real
Address : ADDRESS_TYPE
);
port(
Clock : in std_logic;
54,18 → 51,6
 
architecture behave of o8_rtc is
 
-- The ceil_log2 function returns the minimum register width required to
-- hold the supplied integer.
function ceil_log2 (x : in natural) return natural is
variable retval : natural;
begin
retval := 1;
while ((2**retval) - 1) < x loop
retval := retval + 1;
end loop;
return retval;
end ceil_log2;
 
constant User_Addr : std_logic_vector(15 downto 3)
:= Address(15 downto 3);
alias Comp_Addr is Bus_Address(15 downto 3);
212,7 → 197,7
uSec_Tick_i <= '0';
if( uSec_Cntr = 0 )then
uSec_Cntr <= DLY_1USEC;
uSec_Tick_i <= '1';
uSec_Tick_i <= or_reduce(Interval);
end if;
 
pit.timer_ro <= '0';
/open8_urisc/trunk/VHDL/o8_status_led.vhd
70,16 → 70,6
 
architecture behave of o8_status_led is
 
function ceil_log2 (x : in natural) return natural is
variable retval : natural;
begin
retval := 1;
while ((2**retval) - 1) < x loop
retval := retval + 1;
end loop;
return retval;
end function;
 
constant User_Addr : std_logic_vector(15 downto 0)
:= Address(15 downto 0);
alias Comp_Addr is Bus_Address(15 downto 0);
/open8_urisc/trunk/VHDL/o8_sys_timer.vhd
78,18 → 78,6
signal Interval : DATA_TYPE;
signal Timer_Cnt : DATA_TYPE;
 
-- The ceil_log2 function returns the minimum register width required to
-- hold the supplied integer.
function ceil_log2 (x : in natural) return natural is
variable retval : natural;
begin
retval := 1;
while ((2**retval) - 1) < x loop
retval := retval + 1;
end loop;
return retval;
end ceil_log2;
 
constant DLY_1USEC_VAL: integer := integer(Sys_Freq / 1000000.0);
constant DLY_1USEC_WDT: integer := ceil_log2(DLY_1USEC_VAL - 1);
constant DLY_1USEC : std_logic_vector :=
/open8_urisc/trunk/VHDL/o8_vdsm12.vhd
65,16 → 65,6
 
architecture behave of o8_vdsm12 is
 
function ceil_log2 (x : in natural) return natural is
variable retval : natural;
begin
retval := 1;
while ((2**retval) - 1) < x loop
retval := retval + 1;
end loop;
return retval;
end function;
 
constant User_Addr : std_logic_vector(15 downto 2)
:= Address(15 downto 2);
alias Comp_Addr is Bus_Address(15 downto 2);
/open8_urisc/trunk/VHDL/o8_vdsm8.vhd
53,16 → 53,6
 
architecture behave of o8_vdsm8 is
 
function ceil_log2 (x : in natural) return natural is
variable retval : natural;
begin
retval := 1;
while ((2**retval) - 1) < x loop
retval := retval + 1;
end loop;
return retval;
end function;
 
constant User_Addr : std_logic_vector(15 downto 0) := Address;
alias Comp_Addr is Bus_Address(15 downto 0);
signal Addr_Match : std_logic;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.