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URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

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  • This comparison shows the changes necessary to convert path
    /
    from Rev 189 to Rev 190
    Reverse comparison

Rev 189 → Rev 190

/open8_urisc/trunk/VHDL/o8_cpu.vhd
442,6 → 442,7
 
when SOP_RTS | SOP_RTI =>
CPU_Next_State <= RTS_C1;
Cache_Ctrl <= CACHE_IDLE;
SP_Ctrl.Oper <= SP_POP;
 
when SOP_BRK =>
/open8_urisc/trunk/VHDL/o8_rtc.vhd
197,23 → 197,12
uSec_Tick_i <= '0';
if( uSec_Cntr = 0 )then
uSec_Cntr <= DLY_1USEC;
uSec_Tick_i <= or_reduce(Interval);
uSec_Tick_i <= '1';
end if;
 
pit.timer_ro <= '0';
 
rtc.frac_ro <= '0';
rtc.tens_l_ro <= '0';
rtc.tens_u_ro <= '0';
rtc.secs_l_ro <= '0';
rtc.secs_u_ro <= '0';
rtc.mins_l_ro <= '0';
rtc.mins_u_ro <= '0';
rtc.hours_l_ro <= '0';
rtc.hours_u_ro <= '0';
 
-- Periodic Interval Timer
pit.timer_cnt <= pit.timer_cnt - uSec_Tick_i;
pit.timer_ro <= '0';
if( or_reduce(pit.timer_cnt) = '0' )then
pit.timer_cnt <= interval;
pit.timer_ro <= or_reduce(interval); -- Only issue output on Int > 0
221,6 → 210,7
 
-- Fractional decisecond counter - cycles every 10k microseconds
rtc.frac <= rtc.frac - uSec_Tick_i;
rtc.frac_ro <= '0';
if( or_reduce(rtc.frac) = '0' or update_rtc = '1' )then
rtc.frac <= DECISEC;
rtc.frac_ro <= not update_rtc;
228,6 → 218,7
 
-- Decisecond counter (lower)
rtc.tens_l <= rtc.tens_l + rtc.frac_ro;
rtc.tens_l_ro <= '0';
if( update_rtc = '1' )then
rtc.tens_l <= shd_tens(3 downto 0);
elsif( rtc.tens_l > x"9")then
237,6 → 228,7
 
-- Decisecond counter (upper)
rtc.tens_u <= rtc.tens_u + rtc.tens_l_ro;
rtc.tens_u_ro <= '0';
if( update_rtc = '1' )then
rtc.tens_u <= shd_tens(7 downto 4);
elsif( rtc.tens_u > x"9")then
246,6 → 238,7
 
-- Second counter (lower)
rtc.secs_l <= rtc.secs_l + rtc.tens_u_ro;
rtc.secs_l_ro <= '0';
if( update_rtc = '1' )then
rtc.secs_l <= shd_secs(3 downto 0);
elsif( rtc.secs_l > x"9")then
255,6 → 248,7
 
-- Second counter (upper)
rtc.secs_u <= rtc.secs_u + rtc.secs_l_ro;
rtc.secs_u_ro <= '0';
if( update_rtc = '1' )then
rtc.secs_u <= shd_secs(7 downto 4);
elsif( rtc.secs_u > x"5")then
264,6 → 258,7
 
-- Minutes counter (lower)
rtc.mins_l <= rtc.mins_l + rtc.secs_u_ro;
rtc.mins_l_ro <= '0';
if( update_rtc = '1' )then
rtc.mins_l <= shd_mins(3 downto 0);
elsif( rtc.mins_l > x"9")then
273,6 → 268,7
 
-- Minutes counter (upper)
rtc.mins_u <= rtc.mins_u + rtc.mins_l_ro;
rtc.mins_u_ro <= '0';
if( update_rtc = '1' )then
rtc.mins_u <= shd_mins(7 downto 4);
elsif( rtc.mins_u > x"5")then
282,6 → 278,7
 
-- Hour counter (lower)
rtc.hours_l <= rtc.hours_l + rtc.mins_u_ro;
rtc.hours_l_ro <= '0';
if( update_rtc = '1' )then
rtc.hours_l <= shd_hours(3 downto 0);
elsif( rtc.hours_l > x"9")then
295,6 → 292,7
rtc.hours_u <= shd_hours(7 downto 4);
end if;
 
rtc.hours_u_ro <= '0';
if( rtc.hours_u >= x"2" and rtc.hours_l > x"3" )then
rtc.hours_l <= (others => '0');
rtc.hours_u <= (others => '0');

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