URL
https://opencores.org/ocsvn/t48/t48/trunk
Subversion Repositories t48
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- from Rev 189 to Rev 190
- ↔ Reverse comparison
Rev 189 → Rev 190
/trunk/CHANGELOG
1,9 → 1,12
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Change log for the T48 uController core |
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Version: $Date: 2005-05-08 15:51:47 $ |
Version: $Date: 2005-10-14 23:25:41 $ |
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Release 0.6 BETA |
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* Bugfix for "Wrong clock applied to T0" |
Applied in clock_ctrl.vhd 1.7 |
t48_core.vhd 1.8 |
18,7 → 21,26
* New system toplevel: t8050_wb.vhd |
Contains the Wishbone master. |
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* Prefixed all design units with 't48_'. |
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* Updates for running the core with full xtal clock. Should work now. |
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* Move latching of BUS to MSTATE2 in decoder.vhd |
-> sample BUS at the end of RD' |
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* Fix a glitch on PCH when an interrupt occurs during external |
program memory fetch in decoder.vhd |
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* Bugfix for "Target address of JMP to Program Memory Bank 1 corrupted |
by interrupt" |
and "Return address of CALL to Program Memory Bank 1 corrupted |
by interrupt" |
Applied in int.vhd 1.5 |
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* Bugfix for "MSB of Program Counter changed upon PC increment" |
Applied in pmem_ctrl.vhd 1.4 |
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Release 0.5 BETA |
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