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URL https://opencores.org/ocsvn/apbi2c/apbi2c/trunk

Subversion Repositories apbi2c

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    from Rev 19 to Rev 20
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Rev 19 → Rev 20

/apbi2c/trunk/rtl/i2c.v
91,6 → 91,8
output INT_TX,
output [31:0] PRDATA,
//I2C OUTPUT
output SDA_ENABLE,
output SCL_ENABLE,
inout SDA,
inout SCL
 
118,9 → 120,12
 
 
wire [13:0] REGISTER_CONFIG;
wire [13:0] TIMEOUT_CONFIG;
 
 
wire error;
 
 
wire tx_empty;
wire rx_empty;
 
176,6 → 181,7
.PSLVERR(PSLVERR),
.READ_DATA_ON_RX(RX_DATA_OUT),
.INTERNAL_I2C_REGISTER_CONFIG(REGISTER_CONFIG),
.INTERNAL_I2C_REGISTER_TIMEOUT(TIMEOUT_CONFIG),
.INT_RX(INT_RX),
.WR_ENA(TX_WRITE_ENA),
.WRITE_DATA_ON_TX(TX_DATA_IN),
188,22 → 194,26
);
 
//I2C CORE BLOCK WITH ALL ANOTHER BLOCKS
module_i2c DUT_I2C_INTERNAL (
module_i2c DUT_I2C_INTERNAL_RX_TX (
.PCLK(PCLK),
.PRESETn(PRESETn),
.fifo_tx_rd_en(TX_RD_EN),
.fifo_tx_f_full(TX_F_FULL),
.fifo_tx_f_empty(TX_F_EMPTY),
.fifo_tx_data_out(TX_DATA_OUT),
.fifo_rx_wr_en(RX_WRITE_ENA),
.fifo_rx_f_empty(RX_F_EMPTY),
.fifo_rx_data_in(RX_DATA_IN),
.fifo_rx_f_full(RX_F_FULL),
.fifo_tx_f_full(TX_F_FULL),
.fifo_tx_f_empty(TX_F_EMPTY),
.fifo_tx_rd_en(TX_RD_EN),
.fifo_tx_data_out(TX_DATA_OUT),
.DATA_CONFIG_REG(REGISTER_CONFIG),
.TX_EMPTY(tx_empty),
.TIMEOUT_TX(TIMEOUT_CONFIG),
.RX_EMPTY(rx_empty),
.TX_EMPTY(tx_empty),
.ERROR(error),
.ENABLE_SDA(SDA_ENABLE),
.ENABLE_SCL(SCL_ENABLE),
.SDA(SDA),
.SCL(SCL)
);
 
endmodule
/apbi2c/trunk/rtl/module_i2c.v
100,12 → 100,15
 
//INTERFACE WITH REGISTER CONFIGURATION
input [AWIDTH-1:0] DATA_CONFIG_REG,
input [AWIDTH-1:0] TIMEOUT_TX,
//INTERFACE TO APB AND READ FOR FIFO TX
//INTERFACE TO APB AND READ FOR FIFO
output reg fifo_tx_rd_en,
output TX_EMPTY,
output RX_EMPTY,
output TX_EMPTY,
output RX_EMPTY,
output ERROR,
output ENABLE_SDA,
output ENABLE_SCL,
 
//I2C BI DIRETIONAL PORTS
inout SDA,
120,71 → 123,77
 
//THIS COUNT IS USED TO CONTROL DATA ACCROSS FSM
reg [1:0] count_tx;
reg [1:0] count_rx;
//CONTROL CLOCK AND COUNTER
reg [11:0] count_send_data;
reg [11:0] count_receive_data;
reg [11:0] count_timeout;
reg BR_CLK_O;
reg SDA_OUT;
 
reg BR_CLK_O_RX;
reg SDA_OUT_RX;
 
//RESPONSE USED TO HOLD SIGNAL TO ACK OR NACK
reg RESPONSE;
 
// TX PARAMETERS USED TO STATE MACHINE
// PARAMETERS USED TO STATE MACHINE
 
localparam [5:0] RX_TX_IDLE = 6'd0, //IDLE
localparam [5:0] IDLE = 6'd0, //IDLE
 
RX_TX_START = 6'd1,//START BIT
START = 6'd1,//START BIT
 
RX_TX_CONTROLIN_1 = 6'd2, //START BYTE
RX_TX_CONTROLIN_2 = 6'd3,
RX_TX_CONTROLIN_3 = 6'd4,
RX_TX_CONTROLIN_4 = 6'd5,
RX_TX_CONTROLIN_5 = 6'd6,
RX_TX_CONTROLIN_6 = 6'd7,
RX_TX_CONTROLIN_7 = 6'd8,
RX_TX_CONTROLIN_8 = 6'd9, //END FIRST BYTE
CONTROLIN_1 = 6'd2, //START BYTE
CONTROLIN_2 = 6'd3,
CONTROLIN_3 = 6'd4,
CONTROLIN_4 = 6'd5,
CONTROLIN_5 = 6'd6,
CONTROLIN_6 = 6'd7,
CONTROLIN_7 = 6'd8,
CONTROLIN_8 = 6'd9, //END FIRST BYTE
 
RX_TX_RESPONSE_CIN =6'd10, //RESPONSE
RESPONSE_CIN =6'd10, //RESPONSE
 
RX_TX_ADRESS_1 = 6'd11,//START BYTE
RX_TX_ADRESS_2 = 6'd12,
RX_TX_ADRESS_3 = 6'd13,
RX_TX_ADRESS_4 = 6'd14,
RX_TX_ADRESS_5 = 6'd15,
RX_TX_ADRESS_6 = 6'd16,
RX_TX_ADRESS_7 = 6'd17,
RX_TX_ADRESS_8 = 6'd18,//END FIRST BYTE
ADDRESS_1 = 6'd11,//START BYTE
ADDRESS_2 = 6'd12,
ADDRESS_3 = 6'd13,
ADDRESS_4 = 6'd14,
ADDRESS_5 = 6'd15,
ADDRESS_6 = 6'd16,
ADDRESS_7 = 6'd17,
ADDRESS_8 = 6'd18,//END FIRST BYTE
 
RX_TX_RESPONSE_ADRESS =6'd19, //RESPONSE
RESPONSE_ADDRESS =6'd19, //RESPONSE
 
RX_TX_DATA0_1 = 6'd20,//START BYTE
RX_TX_DATA0_2 = 6'd21,
RX_TX_DATA0_3 = 6'd22,
RX_TX_DATA0_4 = 6'd23,
RX_TX_DATA0_5 = 6'd24,
RX_TX_DATA0_6 = 6'd25,
RX_TX_DATA0_7 = 6'd26,
RX_TX_DATA0_8 = 6'd27,//END FIRST BYTE
DATA0_1 = 6'd20,//START BYTE
DATA0_2 = 6'd21,
DATA0_3 = 6'd22,
DATA0_4 = 6'd23,
DATA0_5 = 6'd24,
DATA0_6 = 6'd25,
DATA0_7 = 6'd26,
DATA0_8 = 6'd27,//END FIRST BYTE
 
RX_TX_RESPONSE_DATA0_1 = 6'd28, //RESPONSE
RESPONSE_DATA0_1 = 6'd28, //RESPONSE
RX_TX_DATA1_1 = 6'd29,//START BYTE
RX_TX_DATA1_2 = 6'd30,
RX_TX_DATA1_3 = 6'd31,
RX_TX_DATA1_4 = 6'd32,
RX_TX_DATA1_5 = 6'd33,
RX_TX_DATA1_6 = 6'd34,
RX_TX_DATA1_7 = 6'd35,
RX_TX_DATA1_8 = 6'd36,//END FIRST BYTE
DATA1_1 = 6'd29,//START BYTE
DATA1_2 = 6'd30,
DATA1_3 = 6'd31,
DATA1_4 = 6'd32,
DATA1_5 = 6'd33,
DATA1_6 = 6'd34,
DATA1_7 = 6'd35,
DATA1_8 = 6'd36,//END FIRST BYTE
 
RX_TX_RESPONSE_DATA1_1 = 6'd37,//RESPONSE
RESPONSE_DATA1_1 = 6'd37,//RESPONSE
 
RX_TX_DELAY_BYTES = 6'd38,//USED ONLY IN ACK TO DELAY BETWEEN
RX_TX_NACK = 6'd39,//USED ONLY IN ACK TO DELAY BETWEEN BYTES
RX_TX_STOP = 6'd40;//USED TO SEND STOP BIT
DELAY_BYTES = 6'd38,//USED ONLY IN ACK TO DELAY BETWEEN
NACK = 6'd39,//USED ONLY IN ACK TO DELAY BETWEEN BYTES
STOP = 6'd40;//USED TO SEND STOP BIT
 
//STATE CONTROL
reg [5:0] state_tx_rx;
reg [5:0] next_state_tx_rx;
reg [5:0] state_tx;
reg [5:0] next_state_tx;
 
//ASSIGN REGISTERS TO BIDIRETIONAL PORTS
assign SDA = (DATA_CONFIG_REG[0] == 1'b1 & DATA_CONFIG_REG[1] == 1'b0)?SDA_OUT:1'b0;
193,481 → 202,482
//STANDARD ERROR
assign ERROR = (DATA_CONFIG_REG[0] == 1'b1 & DATA_CONFIG_REG[1] == 1'b1)?1'b1:1'b0;
 
//COMBINATIONAL BLOCK TO TX
 
//COMBINATIONAL BLOCK TO
always@(*)
begin
 
//THE FUN START HERE :-)
//COMBINATIONAL UPDATE STATE BE CAREFUL WITH WHAT YOU MAKE HERE
next_state_tx_rx = state_tx_rx;
next_state_tx=state_tx;
 
case(state_tx_rx)//state_tx_rx IS MORE SECURE CHANGE ONLY IF YOU KNOW WHAT ARE YOU DOING
RX_TX_IDLE:
case(state_tx)//state_ IS MORE SECURE CHANGE ONLY IF YOU KNOW WHAT ARE YOU DOING
IDLE:
begin
//OBEYING SPEC
if(DATA_CONFIG_REG[0] == 1'b0 && (fifo_tx_f_full == 1'b1 || fifo_tx_f_empty == 1'b0) && DATA_CONFIG_REG[1] == 1'b0)
begin
next_state_tx_rx = RX_TX_IDLE;
next_state_tx = IDLE;
end
else if(DATA_CONFIG_REG[0] == 1'b1 && (fifo_tx_f_full == 1'b1 || fifo_tx_f_empty == 1'b0) && DATA_CONFIG_REG[1] == 1'b1)
begin
next_state_tx_rx = RX_TX_IDLE;
next_state_tx = IDLE;
end
else if(DATA_CONFIG_REG[0] == 1'b1 && (fifo_tx_f_full == 1'b1 || fifo_tx_f_empty == 1'b0) && DATA_CONFIG_REG[1] == 1'b0)
else if(DATA_CONFIG_REG[0] == 1'b1 && (fifo_tx_f_full == 1'b1 || fifo_tx_f_empty == 1'b0) && DATA_CONFIG_REG[1] == 1'b0 && count_timeout < TIMEOUT_TX)
begin
next_state_tx_rx = RX_TX_START;
next_state_tx = START;
end
 
 
end
RX_TX_START://THIS IS USED TOO ALL STATE MACHINES THE COUNTER_SEND_DATA
START://THIS IS USED TOO ALL STATE MACHINES THE COUNTER_SEND_DATA
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx_rx = RX_TX_START;
next_state_tx = START;
end
else
begin
next_state_tx_rx = RX_TX_CONTROLIN_1;
next_state_tx = CONTROLIN_1;
end
end
RX_TX_CONTROLIN_1:
CONTROLIN_1:
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx_rx = RX_TX_CONTROLIN_1;
next_state_tx = CONTROLIN_1;
end
else
begin
next_state_tx_rx = RX_TX_CONTROLIN_2;
next_state_tx = CONTROLIN_2;
end
 
end
RX_TX_CONTROLIN_2:
CONTROLIN_2:
begin
 
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx_rx = RX_TX_CONTROLIN_2;
next_state_tx = CONTROLIN_2;
end
else
begin
next_state_tx_rx = RX_TX_CONTROLIN_3;
next_state_tx = CONTROLIN_3;
end
 
end
RX_TX_CONTROLIN_3:
CONTROLIN_3:
begin
 
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx_rx = RX_TX_CONTROLIN_3;
next_state_tx = CONTROLIN_3;
end
else
begin
next_state_tx_rx = RX_TX_CONTROLIN_4;
next_state_tx = CONTROLIN_4;
end
end
RX_TX_CONTROLIN_4:
CONTROLIN_4:
begin
 
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx_rx = RX_TX_CONTROLIN_4;
next_state_tx = CONTROLIN_4;
end
else
begin
next_state_tx_rx = RX_TX_CONTROLIN_5;
next_state_tx = CONTROLIN_5;
end
end
RX_TX_CONTROLIN_5:
CONTROLIN_5:
begin
 
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx_rx = RX_TX_CONTROLIN_5;
next_state_tx = CONTROLIN_5;
end
else
begin
next_state_tx_rx = RX_TX_CONTROLIN_6;
next_state_tx = CONTROLIN_6;
end
end
RX_TX_CONTROLIN_6:
CONTROLIN_6:
begin
 
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx_rx = RX_TX_CONTROLIN_6;
next_state_tx = CONTROLIN_6;
end
else
begin
next_state_tx_rx = RX_TX_CONTROLIN_7;
next_state_tx = CONTROLIN_7;
end
end
RX_TX_CONTROLIN_7:
CONTROLIN_7:
begin
 
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx_rx = RX_TX_CONTROLIN_7;
next_state_tx = CONTROLIN_7;
end
else
begin
next_state_tx_rx = RX_TX_CONTROLIN_8;
next_state_tx = CONTROLIN_8;
end
end
RX_TX_CONTROLIN_8:
CONTROLIN_8:
begin
 
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx_rx = RX_TX_CONTROLIN_8;
next_state_tx = CONTROLIN_8;
end
else
begin
next_state_tx_rx = RX_TX_RESPONSE_CIN;
next_state_tx = RESPONSE_CIN;
end
end
RX_TX_RESPONSE_CIN:
RESPONSE_CIN:
begin
 
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx_rx = RX_TX_RESPONSE_CIN;
next_state_tx = RESPONSE_CIN;
end
else if(RESPONSE == 1'b0)//ACK
begin
next_state_tx_rx = RX_TX_DELAY_BYTES;
next_state_tx = DELAY_BYTES;
end
else if(RESPONSE == 1'b1)//NACK
begin
next_state_tx_rx = RX_TX_NACK;
next_state_tx = NACK;
end
end
 
//NOW SENDING ADDRESS
RX_TX_ADRESS_1:
ADDRESS_1:
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx_rx = RX_TX_ADRESS_1;
next_state_tx = ADDRESS_1;
end
else
begin
next_state_tx_rx = RX_TX_ADRESS_2;
next_state_tx = ADDRESS_2;
end
end
RX_TX_ADRESS_2:
ADDRESS_2:
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx_rx = RX_TX_ADRESS_2;
next_state_tx = ADDRESS_2;
end
else
begin
next_state_tx_rx = RX_TX_ADRESS_3;
next_state_tx = ADDRESS_3;
end
end
RX_TX_ADRESS_3:
ADDRESS_3:
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx_rx = RX_TX_ADRESS_3;
next_state_tx = ADDRESS_3;
end
else
begin
next_state_tx_rx = RX_TX_ADRESS_4;
next_state_tx = ADDRESS_4;
end
end
RX_TX_ADRESS_4:
ADDRESS_4:
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx_rx = RX_TX_ADRESS_4;
next_state_tx = ADDRESS_4;
end
else
begin
next_state_tx_rx = RX_TX_ADRESS_5;
next_state_tx = ADDRESS_5;
end
end
RX_TX_ADRESS_5:
ADDRESS_5:
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx_rx = RX_TX_ADRESS_5;
next_state_tx = ADDRESS_5;
end
else
begin
next_state_tx_rx = RX_TX_ADRESS_6;
next_state_tx = ADDRESS_6;
end
end
RX_TX_ADRESS_6:
ADDRESS_6:
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx_rx = RX_TX_ADRESS_6;
next_state_tx = ADDRESS_6;
end
else
begin
next_state_tx_rx = RX_TX_ADRESS_7;
next_state_tx = ADDRESS_7;
end
end
RX_TX_ADRESS_7:
ADDRESS_7:
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx_rx = RX_TX_ADRESS_7;
next_state_tx = ADDRESS_7;
end
else
begin
next_state_tx_rx = RX_TX_ADRESS_8;
next_state_tx = ADDRESS_8;
end
end
RX_TX_ADRESS_8:
ADDRESS_8:
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx_rx = RX_TX_ADRESS_8;
next_state_tx = ADDRESS_8;
end
else
begin
next_state_tx_rx = RX_TX_RESPONSE_ADRESS;
next_state_tx = RESPONSE_ADDRESS;
end
end
RX_TX_RESPONSE_ADRESS:
RESPONSE_ADDRESS:
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx_rx = RX_TX_RESPONSE_ADRESS;
next_state_tx = RESPONSE_ADDRESS;
end
else if(RESPONSE == 1'b0)//ACK
begin
next_state_tx_rx = RX_TX_DELAY_BYTES;
next_state_tx = DELAY_BYTES;
end
else if(RESPONSE == 1'b1)//NACK --> RESTART CONDITION AND BACK TO START BYTE AGAIN
begin
next_state_tx_rx = RX_TX_NACK;
next_state_tx = NACK;
end
end
//data in
RX_TX_DATA0_1:
DATA0_1:
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx_rx = RX_TX_DATA0_1;
next_state_tx = DATA0_1;
end
else
begin
next_state_tx_rx = RX_TX_DATA0_2;
next_state_tx = DATA0_2;
end
end
RX_TX_DATA0_2:
DATA0_2:
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx_rx = RX_TX_DATA0_2;
next_state_tx = DATA0_2;
end
else
begin
next_state_tx_rx = RX_TX_DATA0_3;
next_state_tx = DATA0_3;
end
end
RX_TX_DATA0_3:
DATA0_3:
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx_rx = RX_TX_DATA0_3;
next_state_tx = DATA0_3;
end
else
begin
next_state_tx_rx = RX_TX_DATA0_4;
next_state_tx = DATA0_4;
end
end
RX_TX_DATA0_4:
DATA0_4:
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx_rx = RX_TX_DATA0_4;
next_state_tx = DATA0_4;
end
else
begin
next_state_tx_rx = RX_TX_DATA0_5;
next_state_tx = DATA0_5;
end
end
RX_TX_DATA0_5:
DATA0_5:
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx_rx = RX_TX_DATA0_5;
next_state_tx = DATA0_5;
end
else
begin
next_state_tx_rx = RX_TX_DATA0_6;
next_state_tx = DATA0_6;
end
end
RX_TX_DATA0_6:
DATA0_6:
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx_rx = RX_TX_DATA0_6;
next_state_tx = DATA0_6;
end
else
begin
next_state_tx_rx = RX_TX_DATA0_7;
next_state_tx = DATA0_7;
end
end
RX_TX_DATA0_7:
DATA0_7:
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx_rx = RX_TX_DATA0_7;
next_state_tx = DATA0_7;
end
else
begin
next_state_tx_rx = RX_TX_DATA0_8;
next_state_tx = DATA0_8;
end
end
RX_TX_DATA0_8:
DATA0_8:
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx_rx = RX_TX_DATA0_8;
next_state_tx = DATA0_8;
end
else
begin
next_state_tx_rx = RX_TX_RESPONSE_DATA0_1;
next_state_tx = RESPONSE_DATA0_1;
end
end
RX_TX_RESPONSE_DATA0_1:
RESPONSE_DATA0_1:
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx_rx = RX_TX_RESPONSE_DATA0_1;
next_state_tx = RESPONSE_DATA0_1;
end
else if(RESPONSE == 1'b0)//ACK
begin
next_state_tx_rx = RX_TX_DELAY_BYTES;
next_state_tx = DELAY_BYTES;
end
else if(RESPONSE == 1'b1)//NACK
begin
next_state_tx_rx = RX_TX_NACK;
next_state_tx = NACK;
end
end
 
//second byte
RX_TX_DATA1_1:
DATA1_1:
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx_rx = RX_TX_DATA1_1;
next_state_tx = DATA1_1;
end
else
begin
next_state_tx_rx = RX_TX_DATA1_2;
next_state_tx = DATA1_2;
end
end
RX_TX_DATA1_2:
DATA1_2:
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx_rx = RX_TX_DATA1_2;
next_state_tx = DATA1_2;
end
else
begin
next_state_tx_rx = RX_TX_DATA1_3;
next_state_tx = DATA1_3;
end
end
RX_TX_DATA1_3:
DATA1_3:
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx_rx = RX_TX_DATA1_3;
next_state_tx = DATA1_3;
end
else
begin
next_state_tx_rx = RX_TX_DATA1_4;
next_state_tx = DATA1_4;
end
end
RX_TX_DATA1_4:
DATA1_4:
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx_rx = RX_TX_DATA1_4;
next_state_tx = DATA1_4;
end
else
begin
next_state_tx_rx = RX_TX_DATA1_5;
next_state_tx = DATA1_5;
end
end
RX_TX_DATA1_5:
DATA1_5:
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx_rx = RX_TX_DATA1_5;
next_state_tx = DATA1_5;
end
else
begin
next_state_tx_rx = RX_TX_DATA1_6;
next_state_tx = DATA1_6;
end
end
RX_TX_DATA1_6:
DATA1_6:
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx_rx = RX_TX_DATA1_6;
next_state_tx = DATA1_6;
end
else
begin
next_state_tx_rx = RX_TX_DATA1_7;
next_state_tx = DATA1_7;
end
end
RX_TX_DATA1_7:
DATA1_7:
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx_rx = RX_TX_DATA1_7;
next_state_tx = DATA1_7;
end
else
begin
next_state_tx_rx = RX_TX_DATA1_8;
next_state_tx = DATA1_8;
end
end
RX_TX_DATA1_8:
DATA1_8:
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx_rx = RX_TX_DATA1_8;
next_state_tx = DATA1_8;
end
else
begin
next_state_tx_rx = RX_TX_RESPONSE_DATA1_1;
next_state_tx = RESPONSE_DATA1_1;
end
end
RX_TX_RESPONSE_DATA1_1:
RESPONSE_DATA1_1:
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx_rx = RX_TX_RESPONSE_DATA1_1;
next_state_tx = RESPONSE_DATA1_1;
end
else if(RESPONSE == 1'b0)//ACK
begin
next_state_tx_rx = RX_TX_DELAY_BYTES;
next_state_tx = DELAY_BYTES;
end
else if(RESPONSE == 1'b1)//NACK
begin
next_state_tx_rx = RX_TX_NACK;
next_state_tx = NACK;
end
end
RX_TX_DELAY_BYTES://THIS FORM WORKS
DELAY_BYTES://THIS FORM WORKS
begin
 
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx_rx = RX_TX_DELAY_BYTES;
next_state_tx = DELAY_BYTES;
end
else
begin
674,64 → 684,64
 
if(count_tx == 2'd0)
begin
next_state_tx_rx = RX_TX_ADRESS_1;
next_state_tx = ADDRESS_1;
end
else if(count_tx == 2'd1)
else if(count_tx == 2'd1)
begin
next_state_tx_rx = RX_TX_DATA0_1;
next_state_tx = DATA0_1;
end
else if(count_tx == 2'd2)
else if(count_tx == 2'd2)
begin
next_state_tx_rx = RX_TX_DATA1_1;
next_state_tx = DATA1_1;
end
else if(count_tx == 2'd3)
else if(count_tx == 2'd3)
begin
next_state_tx_rx = RX_TX_STOP;
next_state_tx = STOP;
end
end
 
end
RX_TX_NACK://NOT TESTED YET !!!!
NACK://NOT TESTED YET !!!!
begin
if(count_send_data != DATA_CONFIG_REG[13:2]*2'd2)
begin
next_state_tx_rx = RX_TX_NACK;
next_state_tx = NACK;
end
else
begin
if(count_tx == 2'd0)
begin
next_state_tx_rx = RX_TX_CONTROLIN_1;
next_state_tx = CONTROLIN_1;
end
else if(count_tx == 2'd1)
begin
next_state_tx_rx = RX_TX_ADRESS_1;
next_state_tx = ADDRESS_1;
end
else if(count_tx == 2'd2)
else if(count_tx == 2'd2)
begin
next_state_tx_rx = RX_TX_DATA0_1;
next_state_tx = DATA0_1;
end
else if(count_tx == 2'd3)
begin
next_state_tx_rx = RX_TX_DATA1_1;
next_state_tx = DATA1_1;
end
end
end
RX_TX_STOP://THIS WORK
STOP://THIS WORK
begin
if(count_send_data != DATA_CONFIG_REG[13:2])
begin
next_state_tx_rx = RX_TX_STOP;
next_state_tx = STOP;
end
else
begin
next_state_tx_rx = RX_TX_IDLE;
next_state_tx = IDLE;
end
end
default:
begin
next_state_tx_rx = RX_TX_IDLE;
next_state_tx = IDLE;
end
endcase
 
740,7 → 750,7
 
 
 
//SEQUENTIAL TX
//SEQUENTIAL
always@(posedge PCLK)
begin
 
749,10 → 759,10
begin
//SIGNALS MUST BE RESETED
count_send_data <= 12'd0;
state_tx_rx <= RX_TX_IDLE;
state_tx <= IDLE;
SDA_OUT<= 1'b1;
fifo_tx_rd_en <= 1'b0;
count_tx <= 2'd0;
count_tx <= 2'd0;
BR_CLK_O <= 1'b1;
RESPONSE<= 1'b0;
end
760,10 → 770,10
begin
// SEQUENTIAL FUN START
state_tx_rx <= next_state_tx_rx;
state_tx <= next_state_tx;
 
case(state_tx_rx)
RX_TX_IDLE:
case(state_tx)
IDLE:
begin
 
fifo_tx_rd_en <= 1'b0;
788,7 → 798,7
end
 
end
RX_TX_START:
START:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
804,11 → 814,11
if(count_send_data == DATA_CONFIG_REG[13:2]- 12'd1)
begin
SDA_OUT<=fifo_tx_data_out[0:0];
count_tx <= 2'd0;
count_tx <= 2'd0;
end
 
end
RX_TX_CONTROLIN_1:
CONTROLIN_1:
begin
 
842,7 → 852,7
end
RX_TX_CONTROLIN_2:
CONTROLIN_2:
begin
 
873,7 → 883,7
end
 
RX_TX_CONTROLIN_3:
CONTROLIN_3:
begin
 
905,7 → 915,7
 
end
RX_TX_CONTROLIN_4:
CONTROLIN_4:
begin
 
915,7 → 925,7
count_send_data <= count_send_data + 12'd1;
SDA_OUT<=fifo_tx_data_out[3:3];
 
if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
if(count_receive_data < DATA_CONFIG_REG[13:2]/12'd4)
begin
BR_CLK_O <= 1'b0;
end
936,7 → 946,7
end
 
RX_TX_CONTROLIN_5:
CONTROLIN_5:
begin
 
946,7 → 956,7
count_send_data <= count_send_data + 12'd1;
SDA_OUT<=fifo_tx_data_out[4:4];
 
if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
if(count_receive_data < DATA_CONFIG_REG[13:2]/12'd4)
begin
BR_CLK_O <= 1'b0;
end
968,7 → 978,7
end
 
 
RX_TX_CONTROLIN_6:
CONTROLIN_6:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
998,7 → 1008,7
end
 
RX_TX_CONTROLIN_7:
CONTROLIN_7:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
1027,7 → 1037,7
 
end
RX_TX_CONTROLIN_8:
CONTROLIN_8:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
1056,7 → 1066,7
 
end
RX_TX_RESPONSE_CIN:
RESPONSE_CIN:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
1066,7 → 1076,7
//LETS TRY USE THIS BUT I DONT THINK IF WORKS
RESPONSE<= SDA;
 
if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
if(count_receive_data < DATA_CONFIG_REG[13:2]/12'd4)
begin
BR_CLK_O <= 1'b0;
end
1086,7 → 1096,7
 
 
end
RX_TX_ADRESS_1:
ADDRESS_1:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
1114,7 → 1124,7
end
end
RX_TX_ADRESS_2:
ADDRESS_2:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
1122,7 → 1132,7
count_send_data <= count_send_data + 12'd1;
SDA_OUT<=fifo_tx_data_out[9:9];
 
if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
if(count_receive_data < DATA_CONFIG_REG[13:2]/12'd4)
begin
BR_CLK_O <= 1'b0;
end
1142,7 → 1152,7
end
 
end
RX_TX_ADRESS_3:
ADDRESS_3:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
1170,7 → 1180,7
end
 
end
RX_TX_ADRESS_4:
ADDRESS_4:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
1197,12 → 1207,12
SDA_OUT<=fifo_tx_data_out[12:12];
end
end
RX_TX_ADRESS_5:
ADDRESS_5:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
begin
count_send_data <= count_send_data + 12'd1;
count_send_data <= count_receive_data + 12'd1;
SDA_OUT<=fifo_tx_data_out[12:12];
 
if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
1226,7 → 1236,7
 
end
RX_TX_ADRESS_6:
ADDRESS_6:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
1254,7 → 1264,7
end
end
RX_TX_ADRESS_7:
ADDRESS_7:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
1283,7 → 1293,7
 
end
RX_TX_ADRESS_8:
ADDRESS_8:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
1311,7 → 1321,7
end
end
RX_TX_RESPONSE_ADRESS:
RESPONSE_ADDRESS:
begin
if(count_send_data < DATA_CONFIG_REG[13:2])
begin
1339,7 → 1349,7
end
 
end
RX_TX_DATA0_1:
DATA0_1:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
1368,12 → 1378,12
 
end
RX_TX_DATA0_2:
DATA0_2:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
begin
count_send_data <= count_send_data + 12'd1;
count_send_data <= count_receive_data + 12'd1;
SDA_OUT<=fifo_tx_data_out[17:17];
 
if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
1397,7 → 1407,7
 
end
RX_TX_DATA0_3:
DATA0_3:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
1425,7 → 1435,7
end
end
RX_TX_DATA0_4:
DATA0_4:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
1453,7 → 1463,7
end
end
RX_TX_DATA0_5:
DATA0_5:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
1481,7 → 1491,7
end
 
end
RX_TX_DATA0_6:
DATA0_6:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
1509,7 → 1519,7
end
end
RX_TX_DATA0_7:
DATA0_7:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
1537,7 → 1547,7
end
end
RX_TX_DATA0_8:
DATA0_8:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
1566,7 → 1576,7
end
end
RX_TX_RESPONSE_DATA0_1:
RESPONSE_DATA0_1:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
1595,7 → 1605,7
end
 
end
RX_TX_DATA1_1:
DATA1_1:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
1625,7 → 1635,7
 
end
RX_TX_DATA1_2:
DATA1_2:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
1653,7 → 1663,7
end
 
end
RX_TX_DATA1_3:
DATA1_3:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
1661,7 → 1671,7
count_send_data <= count_send_data + 12'd1;
SDA_OUT<=fifo_tx_data_out[26:26];
 
if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
if(count_receive_data < DATA_CONFIG_REG[13:2]/12'd4)
begin
BR_CLK_O <= 1'b0;
end
1682,7 → 1692,7
end
end
RX_TX_DATA1_4:
DATA1_4:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
1711,7 → 1721,7
end
end
RX_TX_DATA1_5:
DATA1_5:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
1740,7 → 1750,7
end
end
RX_TX_DATA1_6:
DATA1_6:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
1769,7 → 1779,7
end
end
RX_TX_DATA1_7:
DATA1_7:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
1799,7 → 1809,7
 
end
RX_TX_DATA1_8:
DATA1_8:
begin
 
if(count_send_data < DATA_CONFIG_REG[13:2])
1828,9 → 1838,9
end
end
RX_TX_RESPONSE_DATA1_1:
RESPONSE_DATA1_1:
begin
//fifo_tx_rd_en <= 1'b1;
//fifo_ _rd_en <= 1'b1;
 
if(count_send_data < DATA_CONFIG_REG[13:2])
begin
1859,7 → 1869,7
end
 
end
RX_TX_DELAY_BYTES:
DELAY_BYTES:
begin
fifo_tx_rd_en <= 1'b0;
1880,7 → 1890,7
count_tx <= count_tx + 2'd1;
SDA_OUT<=fifo_tx_data_out[8:8];
end
else if(count_tx == 2'd1)
else if(count_tx == 2'd1)
begin
count_tx <= count_tx + 2'd1;
SDA_OUT<=fifo_tx_data_out[16:16];
1901,7 → 1911,7
 
end
//THIS BLOCK MUST BE CHECKED WITH CARE
RX_TX_NACK:// MORE A RESTART
NACK:// MORE A RESTART
begin
fifo_tx_rd_en <= 1'b0;
1909,7 → 1919,7
begin
count_send_data <= count_send_data + 12'd1;
if(count_send_data < DATA_CONFIG_REG[13:2]/12'd2)
if(count_receive_data < DATA_CONFIG_REG[13:2]/12'd2)
begin
SDA_OUT<=1'b0;
end
1964,7 → 1974,7
end
end
RX_TX_STOP:
STOP:
begin
 
BR_CLK_O <= 1'b1;
1971,7 → 1981,7
 
if(count_send_data < DATA_CONFIG_REG[13:2])
begin
count_send_data <= count_send_data + 12'd1;
count_send_data <= count_receive_data + 12'd1;
 
if(count_send_data < DATA_CONFIG_REG[13:2]/12'd2-12'd2)
begin
1999,5 → 2009,1336
 
end
 
 
//STATE CONTROL
reg [5:0] state_rx;
reg [5:0] next_state_rx;
 
assign ENABLE_SDA = (state_rx == RESPONSE_CIN||
state_rx == RESPONSE_ADDRESS||
state_rx == RESPONSE_DATA0_1||
state_rx == RESPONSE_DATA1_1)?1'b1:
(state_tx == RESPONSE_CIN||
state_tx == RESPONSE_ADDRESS||
state_tx == RESPONSE_DATA0_1||
state_tx == RESPONSE_DATA1_1)?1'b0:1'b1;
 
 
assign ENABLE_SCL = (state_rx == RESPONSE_CIN||
state_rx == RESPONSE_ADDRESS||
state_rx == RESPONSE_DATA0_1||
state_rx == RESPONSE_DATA1_1)?1'b1:
(state_tx == RESPONSE_CIN||
state_tx == RESPONSE_ADDRESS||
state_tx == RESPONSE_DATA0_1||
state_tx == RESPONSE_DATA1_1)?1'b1:1'b0;
 
 
//COMBINATIONAL BLOCK TO RX
always@(*)
begin
 
//THE FUN START HERE :-)
//COMBINATIONAL UPDATE STATE BE CAREFUL WITH WHAT YOU MAKE HERE
next_state_rx = state_rx;
 
case(state_rx)//state_rx IS MORE SECURE CHANGE ONLY IF YOU KNOW WHAT ARE YOU DOING
IDLE:
begin
//OBEYING SPEC
if(DATA_CONFIG_REG[0] == 1'b0 && DATA_CONFIG_REG[1] == 1'b0)
begin
next_state_rx = IDLE;
end
else if(DATA_CONFIG_REG[0] == 1'b1 && DATA_CONFIG_REG[1] == 1'b1)
begin
next_state_rx = IDLE;
end
else if(DATA_CONFIG_REG[0] == 1'b0 && DATA_CONFIG_REG[1] == 1'b1 && SDA_OUT_RX == 1'b0 && BR_CLK_O_RX == 1'b0)
begin
next_state_rx = START;
end
 
 
end
START://THIS IS USED TOO ALL STATE MACHINES THE COUNTER_SEND_DATA
begin
 
if( count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = START;
end
else if(fifo_rx_data_in[0] == 1'b0 && fifo_rx_data_in[1] == 1'b0)
begin
next_state_rx = CONTROLIN_1;
end
else
begin
next_state_rx = IDLE;
end
end
CONTROLIN_1:
begin
if( count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = CONTROLIN_1;
end
else
begin
next_state_rx = CONTROLIN_2;
end
 
end
CONTROLIN_2:
begin
 
if( count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = CONTROLIN_2;
end
else
begin
next_state_rx = CONTROLIN_3;
end
 
end
CONTROLIN_3:
begin
 
if( count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = CONTROLIN_3;
end
else
begin
next_state_rx = CONTROLIN_4;
end
end
CONTROLIN_4:
begin
 
if( count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = CONTROLIN_4;
end
else
begin
next_state_rx = CONTROLIN_5;
end
end
CONTROLIN_5:
begin
 
if( count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = CONTROLIN_5;
end
else
begin
next_state_rx = CONTROLIN_6;
end
end
CONTROLIN_6:
begin
 
if( count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = CONTROLIN_6;
end
else
begin
next_state_rx = CONTROLIN_7;
end
end
CONTROLIN_7:
begin
 
if( count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = CONTROLIN_7;
end
else
begin
next_state_rx = CONTROLIN_8;
end
end
CONTROLIN_8:
begin
 
if( count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = CONTROLIN_8;
end
else
begin
next_state_rx = RESPONSE_CIN;
end
end
RESPONSE_CIN:
begin
 
if( count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RESPONSE_CIN;
end
else
begin
next_state_rx = ADDRESS_1;
end
end
//NOW SENDING ADDRESS
ADDRESS_1:
begin
if( count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = ADDRESS_1;
end
else
begin
next_state_rx = ADDRESS_2;
end
end
ADDRESS_2:
begin
if( count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = ADDRESS_2;
end
else
begin
next_state_rx = ADDRESS_3;
end
end
ADDRESS_3:
begin
if( count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = ADDRESS_3;
end
else
begin
next_state_rx = ADDRESS_4;
end
end
ADDRESS_4:
begin
if( count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = ADDRESS_4;
end
else
begin
next_state_rx = ADDRESS_5;
end
end
ADDRESS_5:
begin
if( count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = ADDRESS_5;
end
else
begin
next_state_rx = ADDRESS_6;
end
end
ADDRESS_6:
begin
if( count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = ADDRESS_6;
end
else
begin
next_state_rx = ADDRESS_7;
end
end
ADDRESS_7:
begin
if( count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = ADDRESS_7;
end
else
begin
next_state_rx = ADDRESS_8;
end
end
ADDRESS_8:
begin
if( count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = ADDRESS_8;
end
else
begin
next_state_rx = RESPONSE_ADDRESS;
end
end
RESPONSE_ADDRESS:
begin
if( count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RESPONSE_ADDRESS;
end
else
begin
next_state_rx = DATA0_1;
end
end
//data in
DATA0_1:
begin
if( count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = DATA0_1;
end
else
begin
next_state_rx = DATA0_2;
end
end
DATA0_2:
begin
if( count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = DATA0_2;
end
else
begin
next_state_rx = DATA0_3;
end
end
DATA0_3:
begin
if( count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = DATA0_3;
end
else
begin
next_state_rx = DATA0_4;
end
end
DATA0_4:
begin
if( count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = DATA0_4;
end
else
begin
next_state_rx = DATA0_5;
end
end
DATA0_5:
begin
if( count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = DATA0_5;
end
else
begin
next_state_rx = DATA0_6;
end
end
DATA0_6:
begin
if( count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = DATA0_6;
end
else
begin
next_state_rx = DATA0_7;
end
end
DATA0_7:
begin
if( count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = DATA0_7;
end
else
begin
next_state_rx = DATA0_8;
end
end
DATA0_8:
begin
if( count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = DATA0_8;
end
else
begin
next_state_rx = RESPONSE_DATA0_1;
end
end
RESPONSE_DATA0_1:
begin
if( count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RESPONSE_DATA0_1;
end
else
begin
next_state_rx = DATA1_1;
end
end
 
//second byte
DATA1_1:
begin
if( count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = DATA1_1;
end
else
begin
next_state_rx = DATA1_2;
end
end
DATA1_2:
begin
if( count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = DATA1_2;
end
else
begin
next_state_rx = DATA1_3;
end
end
DATA1_3:
begin
if( count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = DATA1_3;
end
else
begin
next_state_rx = DATA1_4;
end
end
DATA1_4:
begin
if( count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = DATA1_4;
end
else
begin
next_state_rx = DATA1_5;
end
end
DATA1_5:
begin
if( count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = DATA1_5;
end
else
begin
next_state_rx = DATA1_6;
end
end
DATA1_6:
begin
if( count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = DATA1_6;
end
else
begin
next_state_rx = DATA1_7;
end
end
DATA1_7:
begin
if( count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = DATA1_7;
end
else
begin
next_state_rx = DATA1_8;
end
end
DATA1_8:
begin
if( count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = DATA1_8;
end
else
begin
next_state_rx = RESPONSE_DATA1_1;
end
end
RESPONSE_DATA1_1:
begin
if( count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = RESPONSE_DATA1_1;
end
else
begin
next_state_rx = DELAY_BYTES;
end
end
DELAY_BYTES://THIS FORM WORKS
begin
 
if( count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = DELAY_BYTES;
end
else
begin
 
if(count_rx == 2'd0)
begin
next_state_rx = ADDRESS_1;
end
else if(count_rx == 2'd1)
begin
next_state_rx = DATA0_1;
end
else if(count_rx == 2'd2)
begin
next_state_rx = DATA1_1;
end
else if(count_rx == 2'd3)
begin
next_state_rx = STOP;
end
end
 
end
STOP://THIS WORK
begin
if( count_receive_data != DATA_CONFIG_REG[13:2])
begin
next_state_rx = STOP;
end
else
begin
next_state_rx = IDLE;
end
end
default:
begin
next_state_rx = IDLE;
end
endcase
 
 
end
 
 
 
//SEQUENTIAL
always@(posedge PCLK)
begin
 
//RESET SYNC
if(!PRESETn)
begin
//SIGNALS MUST BE RESETED
count_receive_data <= 12'd0;
state_rx <= IDLE;
SDA_OUT_RX<= 1'b0;
fifo_rx_wr_en <= 1'b0;
count_rx <= 2'd0;
BR_CLK_O_RX <= 1'b0;
end
else
begin
// SEQUENTIAL FUN START
state_rx <= next_state_rx;
 
case(state_rx)
IDLE:
begin
 
SDA_OUT_RX<= SDA;
BR_CLK_O_RX<=SCL;
 
if(((fifo_rx_f_full == 1'b0 && fifo_rx_f_empty == 1'b0) || (fifo_rx_f_full == 1'b0 && fifo_rx_f_empty == 1'b1)) && DATA_CONFIG_REG[1] == 1'b1)
begin
 
count_receive_data <= count_receive_data + 12'd1;
end
else
begin
count_receive_data <= count_receive_data;
end
end
START:
begin
 
if( count_receive_data < DATA_CONFIG_REG[13:2])
begin
count_receive_data <= count_receive_data + 12'd1;
end
else
begin
count_receive_data <= 12'd0;
end
 
if( count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
begin
fifo_rx_data_in[0]<= SDA;
fifo_rx_data_in[1]<= SCL;
end
 
end
CONTROLIN_1:
begin
 
if( count_receive_data < DATA_CONFIG_REG[13:2])
begin
count_receive_data <= count_receive_data + 12'd1;
end
else
begin
count_receive_data <= 12'd0;
end
 
if(SCL == 1'b1 && count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
begin
fifo_rx_data_in[0]<= SDA;
end
 
end
CONTROLIN_2:
begin
if( count_receive_data < DATA_CONFIG_REG[13:2])
begin
count_receive_data <= count_receive_data + 12'd1;
end
else
begin
count_receive_data <= 12'd0;
end
 
if(SCL == 1'b1 && count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
begin
fifo_rx_data_in[1]<= SDA;
end
end
CONTROLIN_3:
begin
 
if( count_receive_data < DATA_CONFIG_REG[13:2])
begin
count_receive_data <= count_receive_data + 12'd1;
end
else
begin
count_receive_data <= 12'd0;
end
 
 
if(SCL == 1'b1 && count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
begin
fifo_rx_data_in[2]<= SDA;
end
 
end
CONTROLIN_4:
begin
if( count_receive_data < DATA_CONFIG_REG[13:2])
begin
count_receive_data <= count_receive_data + 12'd1;
end
else
begin
count_receive_data <= 12'd0;
end
 
if(SCL == 1'b1 && count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
begin
fifo_rx_data_in[3]<= SDA;
end
end
CONTROLIN_5:
begin
 
if( count_receive_data < DATA_CONFIG_REG[13:2])
begin
count_receive_data <= count_receive_data + 12'd1;
end
else
begin
count_receive_data <= 12'd0;
end
 
if(SCL == 1'b1 && count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
begin
fifo_rx_data_in[4]<= SDA;
end
 
end
CONTROLIN_6:
begin
if( count_receive_data < DATA_CONFIG_REG[13:2])
begin
count_receive_data <= count_receive_data + 12'd1;
end
else
begin
count_receive_data <= 12'd0;
end
 
if(SCL == 1'b1 && count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
begin
fifo_rx_data_in[5]<= SDA;
end
end
 
CONTROLIN_7:
begin
 
if( count_receive_data < DATA_CONFIG_REG[13:2])
begin
count_receive_data <= count_receive_data + 12'd1;
end
else
begin
count_receive_data <= 12'd0;
end
 
if(SCL == 1'b1 && count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
begin
fifo_rx_data_in[6]<= SDA;
end
end
CONTROLIN_8:
begin
 
 
if( count_receive_data < DATA_CONFIG_REG[13:2])
begin
count_receive_data <= count_receive_data + 12'd1;
end
else
begin
count_receive_data <= 12'd0;
end
 
if(SCL == 1'b1 && count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
begin
fifo_rx_data_in[7]<= SDA;
end
 
end
RESPONSE_CIN:
begin
 
if( count_receive_data < DATA_CONFIG_REG[13:2])
begin
count_receive_data <= count_receive_data + 12'd1;
end
else
begin
count_receive_data <= 12'd0;
end
 
end
ADDRESS_1:
begin
 
 
if( count_receive_data < DATA_CONFIG_REG[13:2])
begin
count_receive_data <= count_receive_data + 12'd1;
end
else
begin
count_receive_data <= 12'd0;
end
 
if(SCL == 1'b1 && count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
begin
fifo_rx_data_in[8]<= SDA;
end
end
ADDRESS_2:
begin
 
 
if( count_receive_data < DATA_CONFIG_REG[13:2])
begin
count_receive_data <= count_receive_data + 12'd1;
end
else
begin
count_receive_data <= 12'd0;
end
 
if(SCL == 1'b1 && count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
begin
fifo_rx_data_in[9]<= SDA;
end
 
end
ADDRESS_3:
begin
 
 
if( count_receive_data < DATA_CONFIG_REG[13:2])
begin
count_receive_data <= count_receive_data + 12'd1;
end
else
begin
count_receive_data <= 12'd0;
end
 
if(SCL == 1'b1 && count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
begin
fifo_rx_data_in[10]<= SDA;
end
 
end
ADDRESS_4:
begin
 
 
if( count_receive_data < DATA_CONFIG_REG[13:2])
begin
count_receive_data <= count_receive_data + 12'd1;
end
else
begin
count_receive_data <= 12'd0;
end
 
if(SCL == 1'b1 && count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
begin
fifo_rx_data_in[11]<= SDA;
end
end
ADDRESS_5:
begin
 
 
if( count_receive_data < DATA_CONFIG_REG[13:2])
begin
count_receive_data <= count_receive_data + 12'd1;
end
else
begin
count_receive_data <= 12'd0;
end
 
if(SCL == 1'b1 && count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
begin
fifo_rx_data_in[12]<= SDA;
end
 
end
ADDRESS_6:
begin
 
if( count_receive_data < DATA_CONFIG_REG[13:2])
begin
count_receive_data <= count_receive_data + 12'd1;
end
else
begin
count_receive_data <= 12'd0;
end
 
if(SCL == 1'b1 && count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
begin
fifo_rx_data_in[13]<= SDA;
end
end
ADDRESS_7:
begin
 
 
if( count_receive_data < DATA_CONFIG_REG[13:2])
begin
count_receive_data <= count_receive_data + 12'd1;
end
else
begin
count_receive_data <= 12'd0;
end
 
if(SCL == 1'b1 && count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
begin
fifo_rx_data_in[14]<= SDA;
end
end
ADDRESS_8:
begin
 
 
if( count_receive_data < DATA_CONFIG_REG[13:2])
begin
count_receive_data <= count_receive_data + 12'd1;
end
else
begin
count_receive_data <= 12'd0;
end
 
if(SCL == 1'b1 && count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
begin
fifo_rx_data_in[15]<= SDA;
end
 
end
RESPONSE_ADDRESS:
begin
 
if( count_receive_data < DATA_CONFIG_REG[13:2])
begin
count_receive_data <= count_receive_data + 12'd1;
end
else
begin
count_receive_data <= 12'd0;
end
 
 
end
DATA0_1:
begin
 
 
if( count_receive_data < DATA_CONFIG_REG[13:2])
begin
count_receive_data <= count_receive_data + 12'd1;
end
else
begin
count_receive_data <= 12'd0;
end
 
if(SCL == 1'b1 && count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
begin
fifo_rx_data_in[16]<= SDA;
end
 
end
DATA0_2:
begin
 
 
if( count_receive_data < DATA_CONFIG_REG[13:2])
begin
count_receive_data <= count_receive_data + 12'd1;
end
else
begin
count_receive_data <= 12'd0;
end
 
if(SCL == 1'b1 && count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
begin
fifo_rx_data_in[17]<= SDA;
end
end
DATA0_3:
begin
 
if( count_receive_data < DATA_CONFIG_REG[13:2])
begin
count_receive_data <= count_receive_data + 12'd1;
end
else
begin
count_receive_data <= 12'd0;
end
 
if(SCL == 1'b1 && count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
begin
fifo_rx_data_in[18]<= SDA;
end
end
DATA0_4:
begin
 
 
 
if( count_receive_data < DATA_CONFIG_REG[13:2])
begin
count_receive_data <= count_receive_data + 12'd1;
end
else
begin
count_receive_data <= 12'd0;
end
 
if(SCL == 1'b1 && count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
begin
fifo_rx_data_in[19]<= SDA;
end
end
DATA0_5:
begin
 
 
if( count_receive_data < DATA_CONFIG_REG[13:2])
begin
count_receive_data <= count_receive_data + 12'd1;
end
else
begin
count_receive_data <= 12'd0;
end
 
if(SCL == 1'b1 && count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
begin
fifo_rx_data_in[20]<= SDA;
end
 
 
end
DATA0_6:
begin
 
if( count_receive_data < DATA_CONFIG_REG[13:2])
begin
count_receive_data <= count_receive_data + 12'd1;
end
else
begin
count_receive_data <= 12'd0;
end
 
if(SCL == 1'b1 && count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
begin
fifo_rx_data_in[21]<= SDA;
end
end
DATA0_7:
begin
 
if( count_receive_data < DATA_CONFIG_REG[13:2])
begin
count_receive_data <= count_receive_data + 12'd1;
end
else
begin
count_receive_data <= 12'd0;
end
 
if(SCL == 1'b1 && count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
begin
fifo_rx_data_in[22]<= SDA;
end
end
DATA0_8:
begin
 
if( count_receive_data < DATA_CONFIG_REG[13:2])
begin
count_receive_data <= count_receive_data + 12'd1;
end
else
begin
count_receive_data <= 12'd0;
end
 
if(SCL == 1'b1 && count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
begin
fifo_rx_data_in[23]<= SDA;
end
end
RESPONSE_DATA0_1:
begin
 
if( count_receive_data < DATA_CONFIG_REG[13:2])
begin
count_receive_data <= count_receive_data + 12'd1;
end
else
begin
count_receive_data <= 12'd0;
end
 
end
DATA1_1:
begin
 
 
if( count_receive_data < DATA_CONFIG_REG[13:2])
begin
count_receive_data <= count_receive_data + 12'd1;
end
else
begin
count_receive_data <= 12'd0;
end
 
if(SCL == 1'b1 && count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
begin
fifo_rx_data_in[24]<= SDA;
end
end
DATA1_2:
begin
 
if( count_receive_data < DATA_CONFIG_REG[13:2])
begin
count_receive_data <= count_receive_data + 12'd1;
end
else
begin
count_receive_data <= 12'd0;
end
 
if(SCL == 1'b1 && count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
begin
fifo_rx_data_in[25]<= SDA;
end
 
 
end
DATA1_3:
begin
 
 
if( count_receive_data < DATA_CONFIG_REG[13:2])
begin
count_receive_data <= count_receive_data + 12'd1;
end
else
begin
count_receive_data <= 12'd0;
end
 
if(SCL == 1'b1 && count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
begin
fifo_rx_data_in[26]<= SDA;
end
 
end
DATA1_4:
begin
 
 
if( count_receive_data < DATA_CONFIG_REG[13:2])
begin
count_receive_data <= count_receive_data + 12'd1;
end
else
begin
count_receive_data <= 12'd0;
end
 
if(SCL == 1'b1 && count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
begin
fifo_rx_data_in[27]<= SDA;
end
end
DATA1_5:
begin
 
 
 
if( count_receive_data < DATA_CONFIG_REG[13:2])
begin
count_receive_data <= count_receive_data + 12'd1;
end
else
begin
count_receive_data <= 12'd0;
end
 
if(SCL == 1'b1 && count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
begin
fifo_rx_data_in[28]<= SDA;
end
end
DATA1_6:
begin
 
 
if( count_receive_data < DATA_CONFIG_REG[13:2])
begin
count_receive_data <= count_receive_data + 12'd1;
end
else
begin
count_receive_data <= 12'd0;
end
 
if(SCL == 1'b1 && count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
begin
fifo_rx_data_in[29]<= SDA;
end
 
 
end
DATA1_7:
begin
 
 
if( count_receive_data < DATA_CONFIG_REG[13:2])
begin
count_receive_data <= count_receive_data + 12'd1;
end
else
begin
count_receive_data <= 12'd0;
end
 
if(SCL == 1'b1 && count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
begin
fifo_rx_data_in[30]<= SDA;
end
 
 
end
DATA1_8:
begin
 
 
if( count_receive_data < DATA_CONFIG_REG[13:2])
begin
count_receive_data <= count_receive_data + 12'd1;
end
else
begin
count_receive_data <= 12'd0;
end
 
if(SCL == 1'b1 && count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
begin
fifo_rx_data_in[31]<= SDA;
end
end
RESPONSE_DATA1_1:
begin
 
if( count_receive_data < DATA_CONFIG_REG[13:2])
begin
count_receive_data <= count_receive_data + 12'd1;
end
else
begin
count_receive_data <= 12'd0;
end
//fifo_ _rd_en <= 1'b1;
 
end
DELAY_BYTES:
begin
 
if( count_receive_data < DATA_CONFIG_REG[13:2])
begin
count_receive_data <= count_receive_data + 12'd1;
end
else
begin
count_receive_data <= 12'd0;
fifo_rx_wr_en <= 1'b1;
end
 
 
end
STOP:
begin
if( count_receive_data < DATA_CONFIG_REG[13:2])
begin
count_receive_data <= count_receive_data + 12'd1;
end
else
begin
count_receive_data <= 12'd0;
end
fifo_rx_wr_en <= 1'b0;
end
default:
begin
fifo_rx_wr_en <= 1'b0;
count_receive_data <= 12'd4095;
end
endcase
end
 
 
end
 
//USED ONLY TO COUNTER TIME
always@(posedge PCLK)
begin
 
//RESET SYNC
if(!PRESETn)
begin
count_timeout <= 12'd0;
end
else
begin
if(count_timeout <= TIMEOUT_TX)
begin
if(SDA == 1'b0 && SCL == 1'b0)
count_timeout <= count_timeout + 12'd1;
end
else
begin
count_timeout <= 12'd0;
end
 
end
 
end
 
 
endmodule
 

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